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22f579c6 DA |
1 | /* via_irq.c |
2 | * | |
3 | * Copyright 2004 BEAM Ltd. | |
4 | * Copyright 2002 Tungsten Graphics, Inc. | |
5 | * Copyright 2005 Thomas Hellstrom. | |
6 | * All Rights Reserved. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the next | |
16 | * paragraph) shall be included in all copies or substantial portions of the | |
17 | * Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * BEAM LTD, TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
23 | * DAMAGES OR | |
24 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
25 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
26 | * DEALINGS IN THE SOFTWARE. | |
27 | * | |
28 | * Authors: | |
29 | * Terry Barnaby <terry1@beam.ltd.uk> | |
30 | * Keith Whitwell <keith@tungstengraphics.com> | |
31 | * Thomas Hellstrom <unichrome@shipmail.org> | |
32 | * | |
33 | * This code provides standard DRM access to the Via Unichrome / Pro Vertical blank | |
34 | * interrupt, as well as an infrastructure to handle other interrupts of the chip. | |
35 | * The refresh rate is also calculated for video playback sync purposes. | |
36 | */ | |
37 | ||
38 | #include "drmP.h" | |
39 | #include "drm.h" | |
40 | #include "via_drm.h" | |
41 | #include "via_drv.h" | |
42 | ||
43 | #define VIA_REG_INTERRUPT 0x200 | |
44 | ||
45 | /* VIA_REG_INTERRUPT */ | |
0a3e67a4 | 46 | #define VIA_IRQ_GLOBAL (1 << 31) |
22f579c6 DA |
47 | #define VIA_IRQ_VBLANK_ENABLE (1 << 19) |
48 | #define VIA_IRQ_VBLANK_PENDING (1 << 3) | |
49 | #define VIA_IRQ_HQV0_ENABLE (1 << 11) | |
50 | #define VIA_IRQ_HQV1_ENABLE (1 << 25) | |
51 | #define VIA_IRQ_HQV0_PENDING (1 << 9) | |
52 | #define VIA_IRQ_HQV1_PENDING (1 << 10) | |
92514243 DA |
53 | #define VIA_IRQ_DMA0_DD_ENABLE (1 << 20) |
54 | #define VIA_IRQ_DMA0_TD_ENABLE (1 << 21) | |
55 | #define VIA_IRQ_DMA1_DD_ENABLE (1 << 22) | |
56 | #define VIA_IRQ_DMA1_TD_ENABLE (1 << 23) | |
57 | #define VIA_IRQ_DMA0_DD_PENDING (1 << 4) | |
58 | #define VIA_IRQ_DMA0_TD_PENDING (1 << 5) | |
59 | #define VIA_IRQ_DMA1_DD_PENDING (1 << 6) | |
60 | #define VIA_IRQ_DMA1_TD_PENDING (1 << 7) | |
61 | ||
22f579c6 DA |
62 | |
63 | /* | |
64 | * Device-specific IRQs go here. This type might need to be extended with | |
65 | * the register if there are multiple IRQ control registers. | |
b5e89ed5 | 66 | * Currently we activate the HQV interrupts of Unichrome Pro group A. |
22f579c6 DA |
67 | */ |
68 | ||
69 | static maskarray_t via_pro_group_a_irqs[] = { | |
b5e89ed5 | 70 | {VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x000003D0, 0x00008010, |
0a3e67a4 | 71 | 0x00000000 }, |
b5e89ed5 | 72 | {VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010, |
0a3e67a4 | 73 | 0x00000000 }, |
92514243 DA |
74 | {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0, |
75 | VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}, | |
76 | {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1, | |
77 | VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}, | |
b5e89ed5 | 78 | }; |
0a3e67a4 | 79 | static int via_num_pro_group_a = ARRAY_SIZE(via_pro_group_a_irqs); |
92514243 | 80 | static int via_irqmap_pro_group_a[] = {0, 1, -1, 2, -1, 3}; |
b5e89ed5 | 81 | |
92514243 DA |
82 | static maskarray_t via_unichrome_irqs[] = { |
83 | {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0, | |
84 | VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}, | |
85 | {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1, | |
86 | VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008} | |
87 | }; | |
0a3e67a4 | 88 | static int via_num_unichrome = ARRAY_SIZE(via_unichrome_irqs); |
92514243 | 89 | static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1}; |
b5e89ed5 | 90 | |
0a3e67a4 | 91 | |
b5e89ed5 | 92 | static unsigned time_diff(struct timeval *now, struct timeval *then) |
22f579c6 | 93 | { |
b5e89ed5 | 94 | return (now->tv_usec >= then->tv_usec) ? |
0a3e67a4 JB |
95 | now->tv_usec - then->tv_usec : |
96 | 1000000 - (then->tv_usec - now->tv_usec); | |
97 | } | |
98 | ||
99 | u32 via_get_vblank_counter(struct drm_device *dev, int crtc) | |
100 | { | |
101 | drm_via_private_t *dev_priv = dev->dev_private; | |
102 | if (crtc != 0) | |
103 | return 0; | |
104 | ||
105 | return atomic_read(&dev_priv->vbl_received); | |
22f579c6 DA |
106 | } |
107 | ||
108 | irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS) | |
109 | { | |
84b1fd10 | 110 | struct drm_device *dev = (struct drm_device *) arg; |
22f579c6 DA |
111 | drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; |
112 | u32 status; | |
113 | int handled = 0; | |
114 | struct timeval cur_vblank; | |
115 | drm_via_irq_t *cur_irq = dev_priv->via_irqs; | |
116 | int i; | |
117 | ||
118 | status = VIA_READ(VIA_REG_INTERRUPT); | |
119 | if (status & VIA_IRQ_VBLANK_PENDING) { | |
0a3e67a4 JB |
120 | atomic_inc(&dev_priv->vbl_received); |
121 | if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) { | |
22f579c6 | 122 | do_gettimeofday(&cur_vblank); |
b5e89ed5 DA |
123 | if (dev_priv->last_vblank_valid) { |
124 | dev_priv->usec_per_vblank = | |
0a3e67a4 JB |
125 | time_diff(&cur_vblank, |
126 | &dev_priv->last_vblank) >> 4; | |
22f579c6 DA |
127 | } |
128 | dev_priv->last_vblank = cur_vblank; | |
129 | dev_priv->last_vblank_valid = 1; | |
b5e89ed5 | 130 | } |
0a3e67a4 | 131 | if (!(atomic_read(&dev_priv->vbl_received) & 0xFF)) { |
22f579c6 | 132 | DRM_DEBUG("US per vblank is: %u\n", |
b5e89ed5 | 133 | dev_priv->usec_per_vblank); |
22f579c6 | 134 | } |
0a3e67a4 | 135 | drm_handle_vblank(dev, 0); |
22f579c6 DA |
136 | handled = 1; |
137 | } | |
22f579c6 | 138 | |
b5e89ed5 | 139 | for (i = 0; i < dev_priv->num_irqs; ++i) { |
22f579c6 | 140 | if (status & cur_irq->pending_mask) { |
b5e89ed5 DA |
141 | atomic_inc(&cur_irq->irq_received); |
142 | DRM_WAKEUP(&cur_irq->irq_queue); | |
22f579c6 | 143 | handled = 1; |
92514243 DA |
144 | if (dev_priv->irq_map[drm_via_irq_dma0_td] == i) { |
145 | via_dmablit_handler(dev, 0, 1); | |
146 | } else if (dev_priv->irq_map[drm_via_irq_dma1_td] == i) { | |
147 | via_dmablit_handler(dev, 1, 1); | |
148 | } | |
22f579c6 DA |
149 | } |
150 | cur_irq++; | |
151 | } | |
b5e89ed5 | 152 | |
3ad2f3fb | 153 | /* Acknowledge interrupts */ |
22f579c6 DA |
154 | VIA_WRITE(VIA_REG_INTERRUPT, status); |
155 | ||
0a3e67a4 | 156 | |
22f579c6 DA |
157 | if (handled) |
158 | return IRQ_HANDLED; | |
159 | else | |
160 | return IRQ_NONE; | |
161 | } | |
162 | ||
163 | static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t * dev_priv) | |
164 | { | |
165 | u32 status; | |
166 | ||
167 | if (dev_priv) { | |
3ad2f3fb | 168 | /* Acknowledge interrupts */ |
22f579c6 | 169 | status = VIA_READ(VIA_REG_INTERRUPT); |
b5e89ed5 | 170 | VIA_WRITE(VIA_REG_INTERRUPT, status | |
22f579c6 DA |
171 | dev_priv->irq_pending_mask); |
172 | } | |
173 | } | |
174 | ||
0a3e67a4 | 175 | int via_enable_vblank(struct drm_device *dev, int crtc) |
22f579c6 | 176 | { |
0a3e67a4 JB |
177 | drm_via_private_t *dev_priv = dev->dev_private; |
178 | u32 status; | |
22f579c6 | 179 | |
0a3e67a4 JB |
180 | if (crtc != 0) { |
181 | DRM_ERROR("%s: bad crtc %d\n", __func__, crtc); | |
22f579c6 DA |
182 | return -EINVAL; |
183 | } | |
184 | ||
0a3e67a4 | 185 | status = VIA_READ(VIA_REG_INTERRUPT); |
42dd8619 | 186 | VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_VBLANK_ENABLE); |
0a3e67a4 JB |
187 | |
188 | VIA_WRITE8(0x83d4, 0x11); | |
189 | VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30); | |
22f579c6 | 190 | |
0a3e67a4 JB |
191 | return 0; |
192 | } | |
22f579c6 | 193 | |
0a3e67a4 JB |
194 | void via_disable_vblank(struct drm_device *dev, int crtc) |
195 | { | |
196 | drm_via_private_t *dev_priv = dev->dev_private; | |
42dd8619 SF |
197 | u32 status; |
198 | ||
199 | status = VIA_READ(VIA_REG_INTERRUPT); | |
200 | VIA_WRITE(VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBLANK_ENABLE); | |
b5e89ed5 | 201 | |
0a3e67a4 JB |
202 | VIA_WRITE8(0x83d4, 0x11); |
203 | VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30); | |
204 | ||
205 | if (crtc != 0) | |
206 | DRM_ERROR("%s: bad crtc %d\n", __func__, crtc); | |
22f579c6 DA |
207 | } |
208 | ||
ce60fe02 | 209 | static int |
84b1fd10 | 210 | via_driver_irq_wait(struct drm_device * dev, unsigned int irq, int force_sequence, |
22f579c6 DA |
211 | unsigned int *sequence) |
212 | { | |
213 | drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; | |
214 | unsigned int cur_irq_sequence; | |
d253258c | 215 | drm_via_irq_t *cur_irq; |
22f579c6 | 216 | int ret = 0; |
86678dfd | 217 | maskarray_t *masks; |
92514243 | 218 | int real_irq; |
22f579c6 | 219 | |
3e684eae | 220 | DRM_DEBUG("\n"); |
22f579c6 DA |
221 | |
222 | if (!dev_priv) { | |
3e684eae | 223 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 224 | return -EINVAL; |
22f579c6 DA |
225 | } |
226 | ||
92514243 | 227 | if (irq >= drm_via_irq_num) { |
3e684eae | 228 | DRM_ERROR("Trying to wait on unknown irq %d\n", irq); |
20caafa6 | 229 | return -EINVAL; |
22f579c6 | 230 | } |
b5e89ed5 | 231 | |
92514243 DA |
232 | real_irq = dev_priv->irq_map[irq]; |
233 | ||
234 | if (real_irq < 0) { | |
3e684eae MN |
235 | DRM_ERROR("Video IRQ %d not available on this hardware.\n", |
236 | irq); | |
20caafa6 | 237 | return -EINVAL; |
92514243 | 238 | } |
86678dfd DA |
239 | |
240 | masks = dev_priv->irq_masks; | |
d253258c | 241 | cur_irq = dev_priv->via_irqs + real_irq; |
22f579c6 | 242 | |
92514243 | 243 | if (masks[real_irq][2] && !force_sequence) { |
22f579c6 | 244 | DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ, |
b5e89ed5 DA |
245 | ((VIA_READ(masks[irq][2]) & masks[irq][3]) == |
246 | masks[irq][4])); | |
22f579c6 DA |
247 | cur_irq_sequence = atomic_read(&cur_irq->irq_received); |
248 | } else { | |
249 | DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ, | |
b5e89ed5 DA |
250 | (((cur_irq_sequence = |
251 | atomic_read(&cur_irq->irq_received)) - | |
252 | *sequence) <= (1 << 23))); | |
22f579c6 DA |
253 | } |
254 | *sequence = cur_irq_sequence; | |
255 | return ret; | |
256 | } | |
257 | ||
0a3e67a4 | 258 | |
22f579c6 DA |
259 | /* |
260 | * drm_dma.h hooks | |
261 | */ | |
262 | ||
84b1fd10 | 263 | void via_driver_irq_preinstall(struct drm_device * dev) |
22f579c6 DA |
264 | { |
265 | drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; | |
266 | u32 status; | |
d253258c | 267 | drm_via_irq_t *cur_irq; |
22f579c6 DA |
268 | int i; |
269 | ||
3e684eae | 270 | DRM_DEBUG("dev_priv: %p\n", dev_priv); |
22f579c6 | 271 | if (dev_priv) { |
d253258c | 272 | cur_irq = dev_priv->via_irqs; |
22f579c6 DA |
273 | |
274 | dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE; | |
275 | dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING; | |
276 | ||
689692e7 TH |
277 | if (dev_priv->chipset == VIA_PRO_GROUP_A || |
278 | dev_priv->chipset == VIA_DX9_0) { | |
279 | dev_priv->irq_masks = via_pro_group_a_irqs; | |
280 | dev_priv->num_irqs = via_num_pro_group_a; | |
281 | dev_priv->irq_map = via_irqmap_pro_group_a; | |
282 | } else { | |
283 | dev_priv->irq_masks = via_unichrome_irqs; | |
284 | dev_priv->num_irqs = via_num_unichrome; | |
285 | dev_priv->irq_map = via_irqmap_unichrome; | |
286 | } | |
b5e89ed5 DA |
287 | |
288 | for (i = 0; i < dev_priv->num_irqs; ++i) { | |
22f579c6 | 289 | atomic_set(&cur_irq->irq_received, 0); |
b5e89ed5 | 290 | cur_irq->enable_mask = dev_priv->irq_masks[i][0]; |
22f579c6 | 291 | cur_irq->pending_mask = dev_priv->irq_masks[i][1]; |
b5e89ed5 | 292 | DRM_INIT_WAITQUEUE(&cur_irq->irq_queue); |
22f579c6 DA |
293 | dev_priv->irq_enable_mask |= cur_irq->enable_mask; |
294 | dev_priv->irq_pending_mask |= cur_irq->pending_mask; | |
295 | cur_irq++; | |
b5e89ed5 | 296 | |
22f579c6 DA |
297 | DRM_DEBUG("Initializing IRQ %d\n", i); |
298 | } | |
b5e89ed5 DA |
299 | |
300 | dev_priv->last_vblank_valid = 0; | |
22f579c6 | 301 | |
92514243 | 302 | /* Clear VSync interrupt regs */ |
22f579c6 | 303 | status = VIA_READ(VIA_REG_INTERRUPT); |
b5e89ed5 | 304 | VIA_WRITE(VIA_REG_INTERRUPT, status & |
22f579c6 | 305 | ~(dev_priv->irq_enable_mask)); |
b5e89ed5 | 306 | |
22f579c6 DA |
307 | /* Clear bits if they're already high */ |
308 | viadrv_acknowledge_irqs(dev_priv); | |
309 | } | |
310 | } | |
311 | ||
0a3e67a4 | 312 | int via_driver_irq_postinstall(struct drm_device *dev) |
22f579c6 DA |
313 | { |
314 | drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; | |
315 | u32 status; | |
316 | ||
0a3e67a4 JB |
317 | DRM_DEBUG("via_driver_irq_postinstall\n"); |
318 | if (!dev_priv) | |
319 | return -EINVAL; | |
22f579c6 | 320 | |
0a3e67a4 JB |
321 | status = VIA_READ(VIA_REG_INTERRUPT); |
322 | VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL | |
323 | | dev_priv->irq_enable_mask); | |
22f579c6 | 324 | |
0a3e67a4 JB |
325 | /* Some magic, oh for some data sheets ! */ |
326 | VIA_WRITE8(0x83d4, 0x11); | |
327 | VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30); | |
b5e89ed5 | 328 | |
0a3e67a4 | 329 | return 0; |
22f579c6 DA |
330 | } |
331 | ||
84b1fd10 | 332 | void via_driver_irq_uninstall(struct drm_device * dev) |
22f579c6 DA |
333 | { |
334 | drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; | |
335 | u32 status; | |
336 | ||
3e684eae | 337 | DRM_DEBUG("\n"); |
22f579c6 DA |
338 | if (dev_priv) { |
339 | ||
340 | /* Some more magic, oh for some data sheets ! */ | |
341 | ||
342 | VIA_WRITE8(0x83d4, 0x11); | |
343 | VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30); | |
344 | ||
345 | status = VIA_READ(VIA_REG_INTERRUPT); | |
b5e89ed5 | 346 | VIA_WRITE(VIA_REG_INTERRUPT, status & |
22f579c6 DA |
347 | ~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask)); |
348 | } | |
349 | } | |
350 | ||
c153f45f | 351 | int via_wait_irq(struct drm_device *dev, void *data, struct drm_file *file_priv) |
22f579c6 | 352 | { |
c153f45f | 353 | drm_via_irqwait_t *irqwait = data; |
22f579c6 DA |
354 | struct timeval now; |
355 | int ret = 0; | |
356 | drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; | |
357 | drm_via_irq_t *cur_irq = dev_priv->via_irqs; | |
358 | int force_sequence; | |
359 | ||
c153f45f | 360 | if (irqwait->request.irq >= dev_priv->num_irqs) { |
3e684eae | 361 | DRM_ERROR("Trying to wait on unknown irq %d\n", |
c153f45f | 362 | irqwait->request.irq); |
20caafa6 | 363 | return -EINVAL; |
22f579c6 DA |
364 | } |
365 | ||
c153f45f | 366 | cur_irq += irqwait->request.irq; |
22f579c6 | 367 | |
c153f45f | 368 | switch (irqwait->request.type & ~VIA_IRQ_FLAGS_MASK) { |
22f579c6 | 369 | case VIA_IRQ_RELATIVE: |
0a3e67a4 JB |
370 | irqwait->request.sequence += |
371 | atomic_read(&cur_irq->irq_received); | |
c153f45f | 372 | irqwait->request.type &= ~_DRM_VBLANK_RELATIVE; |
22f579c6 DA |
373 | case VIA_IRQ_ABSOLUTE: |
374 | break; | |
375 | default: | |
20caafa6 | 376 | return -EINVAL; |
22f579c6 DA |
377 | } |
378 | ||
c153f45f | 379 | if (irqwait->request.type & VIA_IRQ_SIGNAL) { |
3e684eae | 380 | DRM_ERROR("Signals on Via IRQs not implemented yet.\n"); |
20caafa6 | 381 | return -EINVAL; |
22f579c6 DA |
382 | } |
383 | ||
c153f45f | 384 | force_sequence = (irqwait->request.type & VIA_IRQ_FORCE_SEQUENCE); |
22f579c6 | 385 | |
c153f45f EA |
386 | ret = via_driver_irq_wait(dev, irqwait->request.irq, force_sequence, |
387 | &irqwait->request.sequence); | |
22f579c6 | 388 | do_gettimeofday(&now); |
c153f45f EA |
389 | irqwait->reply.tval_sec = now.tv_sec; |
390 | irqwait->reply.tval_usec = now.tv_usec; | |
22f579c6 DA |
391 | |
392 | return ret; | |
393 | } |