[deliverable/linux.git] / drivers / gpu / drm / via / via_irq.c

/* via_irq.c
 *
 * Copyright 2004 BEAM Ltd.
 * Copyright 2002 Tungsten Graphics, Inc.
 * Copyright 2005 Thomas Hellstrom.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * BEAM LTD, TUNGSTEN GRAPHICS  AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Terry Barnaby <terry1@beam.ltd.uk>
 *    Keith Whitwell <keith@tungstengraphics.com>
 *    Thomas Hellstrom <unichrome@shipmail.org>
 *
 * This code provides standard DRM access to the Via Unichrome / Pro Vertical blank
 * interrupt, as well as an infrastructure to handle other interrupts of the chip.
 * The refresh rate is also calculated for video playback sync purposes.
 */

#include <drm/drmP.h>
#include <drm/via_drm.h>
#include "via_drv.h"

#define VIA_REG_INTERRUPT       0x200

/* VIA_REG_INTERRUPT */
#define VIA_IRQ_GLOBAL	  (1 << 31)
#define VIA_IRQ_VBLANK_ENABLE   (1 << 19)
#define VIA_IRQ_VBLANK_PENDING  (1 << 3)
#define VIA_IRQ_HQV0_ENABLE     (1 << 11)
#define VIA_IRQ_HQV1_ENABLE     (1 << 25)
#define VIA_IRQ_HQV0_PENDING    (1 << 9)
#define VIA_IRQ_HQV1_PENDING    (1 << 10)
#define VIA_IRQ_DMA0_DD_ENABLE  (1 << 20)
#define VIA_IRQ_DMA0_TD_ENABLE  (1 << 21)
#define VIA_IRQ_DMA1_DD_ENABLE  (1 << 22)
#define VIA_IRQ_DMA1_TD_ENABLE  (1 << 23)
#define VIA_IRQ_DMA0_DD_PENDING (1 << 4)
#define VIA_IRQ_DMA0_TD_PENDING (1 << 5)
#define VIA_IRQ_DMA1_DD_PENDING (1 << 6)
#define VIA_IRQ_DMA1_TD_PENDING (1 << 7)


/*
 * Device-specific IRQs go here. This type might need to be extended with
 * the register if there are multiple IRQ control registers.
 * Currently we activate the HQV interrupts of  Unichrome Pro group A.
 */

static maskarray_t via_pro_group_a_irqs[] = {
	{VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x000003D0, 0x00008010,
	 0x00000000 },
	{VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010,
	 0x00000000 },
	{VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
	 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
	{VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
	 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
};
static int via_num_pro_group_a = ARRAY_SIZE(via_pro_group_a_irqs);
static int via_irqmap_pro_group_a[] = {0, 1, -1, 2, -1, 3};

static maskarray_t via_unichrome_irqs[] = {
	{VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
	 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
	{VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
	 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}
};
static int via_num_unichrome = ARRAY_SIZE(via_unichrome_irqs);
static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1};


static unsigned time_diff(struct timeval *now, struct timeval *then)
{
	return (now->tv_usec >= then->tv_usec) ?
		now->tv_usec - then->tv_usec :
		1000000 - (then->tv_usec - now->tv_usec);
}

u32 via_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
{
	drm_via_private_t *dev_priv = dev->dev_private;

	if (pipe != 0)
		return 0;

	return atomic_read(&dev_priv->vbl_received);
}

irqreturn_t via_driver_irq_handler(int irq, void *arg)
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
	u32 status;
	int handled = 0;
	struct timeval cur_vblank;
	drm_via_irq_t *cur_irq = dev_priv->via_irqs;
	int i;

	status = VIA_READ(VIA_REG_INTERRUPT);
	if (status & VIA_IRQ_VBLANK_PENDING) {
		atomic_inc(&dev_priv->vbl_received);
		if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) {
			do_gettimeofday(&cur_vblank);
			if (dev_priv->last_vblank_valid) {
				dev_priv->usec_per_vblank =
					time_diff(&cur_vblank,
						  &dev_priv->last_vblank) >> 4;
			}
			dev_priv->last_vblank = cur_vblank;
			dev_priv->last_vblank_valid = 1;
		}
		if (!(atomic_read(&dev_priv->vbl_received) & 0xFF)) {
			DRM_DEBUG("US per vblank is: %u\n",
				  dev_priv->usec_per_vblank);
		}
		drm_handle_vblank(dev, 0);
		handled = 1;
	}

	for (i = 0; i < dev_priv->num_irqs; ++i) {
		if (status & cur_irq->pending_mask) {
			atomic_inc(&cur_irq->irq_received);
			wake_up(&cur_irq->irq_queue);
			handled = 1;
			if (dev_priv->irq_map[drm_via_irq_dma0_td] == i)
				via_dmablit_handler(dev, 0, 1);
			else if (dev_priv->irq_map[drm_via_irq_dma1_td] == i)
				via_dmablit_handler(dev, 1, 1);
		}
		cur_irq++;
	}

	/* Acknowledge interrupts */
	VIA_WRITE(VIA_REG_INTERRUPT, status);


	if (handled)
		return IRQ_HANDLED;
	else
		return IRQ_NONE;
}

static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t *dev_priv)
{
	u32 status;

	if (dev_priv) {
		/* Acknowledge interrupts */
		status = VIA_READ(VIA_REG_INTERRUPT);
		VIA_WRITE(VIA_REG_INTERRUPT, status |
			  dev_priv->irq_pending_mask);
	}
}

int via_enable_vblank(struct drm_device *dev, unsigned int pipe)
{
	drm_via_private_t *dev_priv = dev->dev_private;
	u32 status;

	if (pipe != 0) {
		DRM_ERROR("%s:  bad crtc %u\n", __func__, pipe);
		return -EINVAL;
	}

	status = VIA_READ(VIA_REG_INTERRUPT);
	VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_VBLANK_ENABLE);

	VIA_WRITE8(0x83d4, 0x11);
	VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);

	return 0;
}

void via_disable_vblank(struct drm_device *dev, unsigned int pipe)
{
	drm_via_private_t *dev_priv = dev->dev_private;
	u32 status;

	status = VIA_READ(VIA_REG_INTERRUPT);
	VIA_WRITE(VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBLANK_ENABLE);

	VIA_WRITE8(0x83d4, 0x11);
	VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);

	if (pipe != 0)
		DRM_ERROR("%s:  bad crtc %u\n", __func__, pipe);
}

static int
via_driver_irq_wait(struct drm_device *dev, unsigned int irq, int force_sequence,
		    unsigned int *sequence)
{
	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
	unsigned int cur_irq_sequence;
	drm_via_irq_t *cur_irq;
	int ret = 0;
	maskarray_t *masks;
	int real_irq;

	DRM_DEBUG("\n");

	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}

	if (irq >= drm_via_irq_num) {
		DRM_ERROR("Trying to wait on unknown irq %d\n", irq);
		return -EINVAL;
	}

	real_irq = dev_priv->irq_map[irq];

	if (real_irq < 0) {
		DRM_ERROR("Video IRQ %d not available on this hardware.\n",
			  irq);
		return -EINVAL;
	}

	masks = dev_priv->irq_masks;
	cur_irq = dev_priv->via_irqs + real_irq;

	if (masks[real_irq][2] && !force_sequence) {
		DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ,
			    ((VIA_READ(masks[irq][2]) & masks[irq][3]) ==
			     masks[irq][4]));
		cur_irq_sequence = atomic_read(&cur_irq->irq_received);
	} else {
		DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ,
			    (((cur_irq_sequence =
			       atomic_read(&cur_irq->irq_received)) -
			      *sequence) <= (1 << 23)));
	}
	*sequence = cur_irq_sequence;
	return ret;
}


/*
 * drm_dma.h hooks
 */

void via_driver_irq_preinstall(struct drm_device *dev)
{
	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
	u32 status;
	drm_via_irq_t *cur_irq;
	int i;

	DRM_DEBUG("dev_priv: %p\n", dev_priv);
	if (dev_priv) {
		cur_irq = dev_priv->via_irqs;

		dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE;
		dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING;

		if (dev_priv->chipset == VIA_PRO_GROUP_A ||
		    dev_priv->chipset == VIA_DX9_0) {
			dev_priv->irq_masks = via_pro_group_a_irqs;
			dev_priv->num_irqs = via_num_pro_group_a;
			dev_priv->irq_map = via_irqmap_pro_group_a;
		} else {
			dev_priv->irq_masks = via_unichrome_irqs;
			dev_priv->num_irqs = via_num_unichrome;
			dev_priv->irq_map = via_irqmap_unichrome;
		}

		for (i = 0; i < dev_priv->num_irqs; ++i) {
			atomic_set(&cur_irq->irq_received, 0);
			cur_irq->enable_mask = dev_priv->irq_masks[i][0];
			cur_irq->pending_mask = dev_priv->irq_masks[i][1];
			init_waitqueue_head(&cur_irq->irq_queue);
			dev_priv->irq_enable_mask |= cur_irq->enable_mask;
			dev_priv->irq_pending_mask |= cur_irq->pending_mask;
			cur_irq++;

			DRM_DEBUG("Initializing IRQ %d\n", i);
		}

		dev_priv->last_vblank_valid = 0;

		/* Clear VSync interrupt regs */
		status = VIA_READ(VIA_REG_INTERRUPT);
		VIA_WRITE(VIA_REG_INTERRUPT, status &
			  ~(dev_priv->irq_enable_mask));

		/* Clear bits if they're already high */
		viadrv_acknowledge_irqs(dev_priv);
	}
}

int via_driver_irq_postinstall(struct drm_device *dev)
{
	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
	u32 status;

	DRM_DEBUG("via_driver_irq_postinstall\n");
	if (!dev_priv)
		return -EINVAL;

	status = VIA_READ(VIA_REG_INTERRUPT);
	VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL
		  | dev_priv->irq_enable_mask);

	/* Some magic, oh for some data sheets ! */
	VIA_WRITE8(0x83d4, 0x11);
	VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);

	return 0;
}

void via_driver_irq_uninstall(struct drm_device *dev)
{
	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
	u32 status;

	DRM_DEBUG("\n");
	if (dev_priv) {

		/* Some more magic, oh for some data sheets ! */

		VIA_WRITE8(0x83d4, 0x11);
		VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);

		status = VIA_READ(VIA_REG_INTERRUPT);
		VIA_WRITE(VIA_REG_INTERRUPT, status &
			  ~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask));
	}
}

int via_wait_irq(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
	drm_via_irqwait_t *irqwait = data;
	struct timeval now;
	int ret = 0;
	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
	drm_via_irq_t *cur_irq = dev_priv->via_irqs;
	int force_sequence;

	if (irqwait->request.irq >= dev_priv->num_irqs) {
		DRM_ERROR("Trying to wait on unknown irq %d\n",
			  irqwait->request.irq);
		return -EINVAL;
	}

	cur_irq += irqwait->request.irq;

	switch (irqwait->request.type & ~VIA_IRQ_FLAGS_MASK) {
	case VIA_IRQ_RELATIVE:
		irqwait->request.sequence +=
			atomic_read(&cur_irq->irq_received);
		irqwait->request.type &= ~_DRM_VBLANK_RELATIVE;
	case VIA_IRQ_ABSOLUTE:
		break;
	default:
		return -EINVAL;
	}

	if (irqwait->request.type & VIA_IRQ_SIGNAL) {
		DRM_ERROR("Signals on Via IRQs not implemented yet.\n");
		return -EINVAL;
	}

	force_sequence = (irqwait->request.type & VIA_IRQ_FORCE_SEQUENCE);

	ret = via_driver_irq_wait(dev, irqwait->request.irq, force_sequence,
				  &irqwait->request.sequence);
	do_gettimeofday(&now);
	irqwait->reply.tval_sec = now.tv_sec;
	irqwait->reply.tval_usec = now.tv_usec;

	return ret;
}
Commit	Line	Data
22f579c6 DA	1	/* via_irq.c
	2	*
	3	* Copyright 2004 BEAM Ltd.
	4	* Copyright 2002 Tungsten Graphics, Inc.
	5	* Copyright 2005 Thomas Hellstrom.
	6	* All Rights Reserved.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a
	9	* copy of this software and associated documentation files (the "Software"),
	10	* to deal in the Software without restriction, including without limitation
	11	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	12	* and/or sell copies of the Software, and to permit persons to whom the
	13	* Software is furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice (including the next
	16	* paragraph) shall be included in all copies or substantial portions of the
	17	* Software.
	18	*
	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	20	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	21	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	22	* BEAM LTD, TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	23	* DAMAGES OR
	24	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	25	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	26	* DEALINGS IN THE SOFTWARE.
	27	*
	28	* Authors:
	29	* Terry Barnaby <terry1@beam.ltd.uk>
	30	* Keith Whitwell <keith@tungstengraphics.com>
	31	* Thomas Hellstrom <unichrome@shipmail.org>
	32	*
	33	* This code provides standard DRM access to the Via Unichrome / Pro Vertical blank
	34	* interrupt, as well as an infrastructure to handle other interrupts of the chip.
	35	* The refresh rate is also calculated for video playback sync purposes.
	36	*/
	37
760285e7 DH	38	#include <drm/drmP.h>
760285e7 DH	39	#include <drm/via_drm.h>
22f579c6 DA	40	#include "via_drv.h"
	41
	42	#define VIA_REG_INTERRUPT 0x200
	43
	44	/* VIA_REG_INTERRUPT */
0a3e67a4	45	#define VIA_IRQ_GLOBAL (1 << 31)
22f579c6 DA	46	#define VIA_IRQ_VBLANK_ENABLE (1 << 19)
	47	#define VIA_IRQ_VBLANK_PENDING (1 << 3)
	48	#define VIA_IRQ_HQV0_ENABLE (1 << 11)
	49	#define VIA_IRQ_HQV1_ENABLE (1 << 25)
	50	#define VIA_IRQ_HQV0_PENDING (1 << 9)
	51	#define VIA_IRQ_HQV1_PENDING (1 << 10)
92514243 DA	52	#define VIA_IRQ_DMA0_DD_ENABLE (1 << 20)
	53	#define VIA_IRQ_DMA0_TD_ENABLE (1 << 21)
	54	#define VIA_IRQ_DMA1_DD_ENABLE (1 << 22)
	55	#define VIA_IRQ_DMA1_TD_ENABLE (1 << 23)
	56	#define VIA_IRQ_DMA0_DD_PENDING (1 << 4)
	57	#define VIA_IRQ_DMA0_TD_PENDING (1 << 5)
	58	#define VIA_IRQ_DMA1_DD_PENDING (1 << 6)
	59	#define VIA_IRQ_DMA1_TD_PENDING (1 << 7)
	60
22f579c6 DA	61
	62	/*
	63	* Device-specific IRQs go here. This type might need to be extended with
	64	* the register if there are multiple IRQ control registers.
b5e89ed5	65	* Currently we activate the HQV interrupts of Unichrome Pro group A.
22f579c6 DA	66	*/
	67
	68	static maskarray_t via_pro_group_a_irqs[] = {
b5e89ed5	69	{VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x000003D0, 0x00008010,
0a3e67a4	70	0x00000000 },
b5e89ed5	71	{VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010,
0a3e67a4	72	0x00000000 },
92514243 DA	73	{VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
	74	VIA_DMA_CSR_TA \| VIA_DMA_CSR_TD, 0x00000008},
	75	{VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
	76	VIA_DMA_CSR_TA \| VIA_DMA_CSR_TD, 0x00000008},
b5e89ed5	77	};
0a3e67a4	78	static int via_num_pro_group_a = ARRAY_SIZE(via_pro_group_a_irqs);
92514243	79	static int via_irqmap_pro_group_a[] = {0, 1, -1, 2, -1, 3};
b5e89ed5	80
92514243 DA	81	static maskarray_t via_unichrome_irqs[] = {
	82	{VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
	83	VIA_DMA_CSR_TA \| VIA_DMA_CSR_TD, 0x00000008},
	84	{VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
	85	VIA_DMA_CSR_TA \| VIA_DMA_CSR_TD, 0x00000008}
	86	};
0a3e67a4	87	static int via_num_unichrome = ARRAY_SIZE(via_unichrome_irqs);
92514243	88	static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1};
b5e89ed5	89
0a3e67a4	90
b5e89ed5	91	static unsigned time_diff(struct timeval now, struct timeval then)
22f579c6	92	{
b5e89ed5	93	return (now->tv_usec >= then->tv_usec) ?
0a3e67a4 JB	94	now->tv_usec - then->tv_usec :
	95	1000000 - (then->tv_usec - now->tv_usec);
	96	}
	97
88e72717	98	u32 via_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
0a3e67a4 JB	99	{
0a3e67a4 JB	100	drm_via_private_t *dev_priv = dev->dev_private;
88e72717 TR	101
88e72717 TR	102	if (pipe != 0)
0a3e67a4 JB	103	return 0;
	104
	105	return atomic_read(&dev_priv->vbl_received);
22f579c6 DA	106	}
22f579c6 DA	107
e9f0d76f	108	irqreturn_t via_driver_irq_handler(int irq, void *arg)
22f579c6	109	{
84b1fd10	110	struct drm_device dev = (struct drm_device ) arg;
22f579c6 DA	111	drm_via_private_t dev_priv = (drm_via_private_t ) dev->dev_private;
	112	u32 status;
	113	int handled = 0;
	114	struct timeval cur_vblank;
	115	drm_via_irq_t *cur_irq = dev_priv->via_irqs;
	116	int i;
	117
	118	status = VIA_READ(VIA_REG_INTERRUPT);
	119	if (status & VIA_IRQ_VBLANK_PENDING) {
0a3e67a4 JB	120	atomic_inc(&dev_priv->vbl_received);
0a3e67a4 JB	121	if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) {
22f579c6	122	do_gettimeofday(&cur_vblank);
b5e89ed5 DA	123	if (dev_priv->last_vblank_valid) {
b5e89ed5 DA	124	dev_priv->usec_per_vblank =
0a3e67a4 JB	125	time_diff(&cur_vblank,
0a3e67a4 JB	126	&dev_priv->last_vblank) >> 4;
22f579c6 DA	127	}
	128	dev_priv->last_vblank = cur_vblank;
	129	dev_priv->last_vblank_valid = 1;
b5e89ed5	130	}
0a3e67a4	131	if (!(atomic_read(&dev_priv->vbl_received) & 0xFF)) {
22f579c6	132	DRM_DEBUG("US per vblank is: %u\n",
b5e89ed5	133	dev_priv->usec_per_vblank);
22f579c6	134	}
0a3e67a4	135	drm_handle_vblank(dev, 0);
22f579c6 DA	136	handled = 1;
22f579c6 DA	137	}
22f579c6	138
b5e89ed5	139	for (i = 0; i < dev_priv->num_irqs; ++i) {
22f579c6	140	if (status & cur_irq->pending_mask) {
b5e89ed5	141	atomic_inc(&cur_irq->irq_received);
57ed0f7b	142	wake_up(&cur_irq->irq_queue);
22f579c6	143	handled = 1;
58c1e85a	144	if (dev_priv->irq_map[drm_via_irq_dma0_td] == i)
92514243	145	via_dmablit_handler(dev, 0, 1);
58c1e85a	146	else if (dev_priv->irq_map[drm_via_irq_dma1_td] == i)
92514243	147	via_dmablit_handler(dev, 1, 1);
22f579c6 DA	148	}
	149	cur_irq++;
	150	}
b5e89ed5	151
3ad2f3fb	152	/* Acknowledge interrupts */
22f579c6 DA	153	VIA_WRITE(VIA_REG_INTERRUPT, status);
22f579c6 DA	154
0a3e67a4	155
22f579c6 DA	156	if (handled)
	157	return IRQ_HANDLED;
	158	else
	159	return IRQ_NONE;
	160	}
	161
58c1e85a	162	static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t *dev_priv)
22f579c6 DA	163	{
	164	u32 status;
	165
	166	if (dev_priv) {
3ad2f3fb	167	/* Acknowledge interrupts */
22f579c6	168	status = VIA_READ(VIA_REG_INTERRUPT);
b5e89ed5	169	VIA_WRITE(VIA_REG_INTERRUPT, status \|
22f579c6 DA	170	dev_priv->irq_pending_mask);
	171	}
	172	}
	173
88e72717	174	int via_enable_vblank(struct drm_device *dev, unsigned int pipe)
22f579c6	175	{
0a3e67a4 JB	176	drm_via_private_t *dev_priv = dev->dev_private;
0a3e67a4 JB	177	u32 status;
22f579c6	178
88e72717 TR	179	if (pipe != 0) {
88e72717 TR	180	DRM_ERROR("%s: bad crtc %u\n", __func__, pipe);
22f579c6 DA	181	return -EINVAL;
	182	}
	183
0a3e67a4	184	status = VIA_READ(VIA_REG_INTERRUPT);
42dd8619	185	VIA_WRITE(VIA_REG_INTERRUPT, status \| VIA_IRQ_VBLANK_ENABLE);
0a3e67a4 JB	186
	187	VIA_WRITE8(0x83d4, 0x11);
	188	VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) \| 0x30);
22f579c6	189
0a3e67a4 JB	190	return 0;
0a3e67a4 JB	191	}
22f579c6	192
88e72717	193	void via_disable_vblank(struct drm_device *dev, unsigned int pipe)
0a3e67a4 JB	194	{
0a3e67a4 JB	195	drm_via_private_t *dev_priv = dev->dev_private;
42dd8619 SF	196	u32 status;
	197
	198	status = VIA_READ(VIA_REG_INTERRUPT);
	199	VIA_WRITE(VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBLANK_ENABLE);
b5e89ed5	200
0a3e67a4 JB	201	VIA_WRITE8(0x83d4, 0x11);
	202	VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
	203
88e72717 TR	204	if (pipe != 0)
88e72717 TR	205	DRM_ERROR("%s: bad crtc %u\n", __func__, pipe);
22f579c6 DA	206	}
22f579c6 DA	207
ce60fe02	208	static int
58c1e85a	209	via_driver_irq_wait(struct drm_device *dev, unsigned int irq, int force_sequence,
22f579c6 DA	210	unsigned int *sequence)
	211	{
	212	drm_via_private_t dev_priv = (drm_via_private_t ) dev->dev_private;
	213	unsigned int cur_irq_sequence;
d253258c	214	drm_via_irq_t *cur_irq;
22f579c6	215	int ret = 0;
86678dfd	216	maskarray_t *masks;
92514243	217	int real_irq;
22f579c6	218
3e684eae	219	DRM_DEBUG("\n");
22f579c6 DA	220
22f579c6 DA	221	if (!dev_priv) {
3e684eae	222	DRM_ERROR("called with no initialization\n");
20caafa6	223	return -EINVAL;
22f579c6 DA	224	}
22f579c6 DA	225
92514243	226	if (irq >= drm_via_irq_num) {
3e684eae	227	DRM_ERROR("Trying to wait on unknown irq %d\n", irq);
20caafa6	228	return -EINVAL;
22f579c6	229	}
b5e89ed5	230
92514243 DA	231	real_irq = dev_priv->irq_map[irq];
	232
	233	if (real_irq < 0) {
3e684eae MN	234	DRM_ERROR("Video IRQ %d not available on this hardware.\n",
3e684eae MN	235	irq);
20caafa6	236	return -EINVAL;
92514243	237	}
86678dfd DA	238
86678dfd DA	239	masks = dev_priv->irq_masks;
d253258c	240	cur_irq = dev_priv->via_irqs + real_irq;
22f579c6	241
92514243	242	if (masks[real_irq][2] && !force_sequence) {
bfd8303a	243	DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ,
b5e89ed5 DA	244	((VIA_READ(masks[irq][2]) & masks[irq][3]) ==
b5e89ed5 DA	245	masks[irq][4]));
22f579c6 DA	246	cur_irq_sequence = atomic_read(&cur_irq->irq_received);
22f579c6 DA	247	} else {
bfd8303a	248	DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ,
b5e89ed5 DA	249	(((cur_irq_sequence =
	250	atomic_read(&cur_irq->irq_received)) -
	251	*sequence) <= (1 << 23)));
22f579c6 DA	252	}
	253	*sequence = cur_irq_sequence;
	254	return ret;
	255	}
	256
0a3e67a4	257
22f579c6 DA	258	/*
	259	* drm_dma.h hooks
	260	*/
	261
58c1e85a	262	void via_driver_irq_preinstall(struct drm_device *dev)
22f579c6 DA	263	{
	264	drm_via_private_t dev_priv = (drm_via_private_t ) dev->dev_private;
	265	u32 status;
d253258c	266	drm_via_irq_t *cur_irq;
22f579c6 DA	267	int i;
22f579c6 DA	268
3e684eae	269	DRM_DEBUG("dev_priv: %p\n", dev_priv);
22f579c6	270	if (dev_priv) {
d253258c	271	cur_irq = dev_priv->via_irqs;
22f579c6 DA	272
	273	dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE;
	274	dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING;
	275
689692e7 TH	276	if (dev_priv->chipset == VIA_PRO_GROUP_A \|\|
	277	dev_priv->chipset == VIA_DX9_0) {
	278	dev_priv->irq_masks = via_pro_group_a_irqs;
	279	dev_priv->num_irqs = via_num_pro_group_a;
	280	dev_priv->irq_map = via_irqmap_pro_group_a;
	281	} else {
	282	dev_priv->irq_masks = via_unichrome_irqs;
	283	dev_priv->num_irqs = via_num_unichrome;
	284	dev_priv->irq_map = via_irqmap_unichrome;
	285	}
b5e89ed5 DA	286
b5e89ed5 DA	287	for (i = 0; i < dev_priv->num_irqs; ++i) {
22f579c6	288	atomic_set(&cur_irq->irq_received, 0);
b5e89ed5	289	cur_irq->enable_mask = dev_priv->irq_masks[i][0];
22f579c6	290	cur_irq->pending_mask = dev_priv->irq_masks[i][1];
57ed0f7b	291	init_waitqueue_head(&cur_irq->irq_queue);
22f579c6 DA	292	dev_priv->irq_enable_mask \|= cur_irq->enable_mask;
	293	dev_priv->irq_pending_mask \|= cur_irq->pending_mask;
	294	cur_irq++;
b5e89ed5	295
22f579c6 DA	296	DRM_DEBUG("Initializing IRQ %d\n", i);
22f579c6 DA	297	}
b5e89ed5 DA	298
b5e89ed5 DA	299	dev_priv->last_vblank_valid = 0;
22f579c6	300
92514243	301	/* Clear VSync interrupt regs */
22f579c6	302	status = VIA_READ(VIA_REG_INTERRUPT);
b5e89ed5	303	VIA_WRITE(VIA_REG_INTERRUPT, status &
22f579c6	304	~(dev_priv->irq_enable_mask));
b5e89ed5	305
22f579c6 DA	306	/* Clear bits if they're already high */
	307	viadrv_acknowledge_irqs(dev_priv);
	308	}
	309	}
	310
0a3e67a4	311	int via_driver_irq_postinstall(struct drm_device *dev)
22f579c6 DA	312	{
	313	drm_via_private_t dev_priv = (drm_via_private_t ) dev->dev_private;
	314	u32 status;
	315
0a3e67a4 JB	316	DRM_DEBUG("via_driver_irq_postinstall\n");
	317	if (!dev_priv)
	318	return -EINVAL;
22f579c6	319
0a3e67a4 JB	320	status = VIA_READ(VIA_REG_INTERRUPT);
	321	VIA_WRITE(VIA_REG_INTERRUPT, status \| VIA_IRQ_GLOBAL
	322	\| dev_priv->irq_enable_mask);
22f579c6	323
0a3e67a4 JB	324	/* Some magic, oh for some data sheets ! */
	325	VIA_WRITE8(0x83d4, 0x11);
	326	VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) \| 0x30);
b5e89ed5	327
0a3e67a4	328	return 0;
22f579c6 DA	329	}
22f579c6 DA	330
58c1e85a	331	void via_driver_irq_uninstall(struct drm_device *dev)
22f579c6 DA	332	{
	333	drm_via_private_t dev_priv = (drm_via_private_t ) dev->dev_private;
	334	u32 status;
	335
3e684eae	336	DRM_DEBUG("\n");
22f579c6 DA	337	if (dev_priv) {
	338
	339	/* Some more magic, oh for some data sheets ! */
	340
	341	VIA_WRITE8(0x83d4, 0x11);
	342	VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
	343
	344	status = VIA_READ(VIA_REG_INTERRUPT);
b5e89ed5	345	VIA_WRITE(VIA_REG_INTERRUPT, status &
22f579c6 DA	346	~(VIA_IRQ_VBLANK_ENABLE \| dev_priv->irq_enable_mask));
	347	}
	348	}
	349
c153f45f	350	int via_wait_irq(struct drm_device dev, void data, struct drm_file *file_priv)
22f579c6	351	{
c153f45f	352	drm_via_irqwait_t *irqwait = data;
22f579c6 DA	353	struct timeval now;
	354	int ret = 0;
	355	drm_via_private_t dev_priv = (drm_via_private_t ) dev->dev_private;
	356	drm_via_irq_t *cur_irq = dev_priv->via_irqs;
	357	int force_sequence;
	358
c153f45f	359	if (irqwait->request.irq >= dev_priv->num_irqs) {
3e684eae	360	DRM_ERROR("Trying to wait on unknown irq %d\n",
c153f45f	361	irqwait->request.irq);
20caafa6	362	return -EINVAL;
22f579c6 DA	363	}
22f579c6 DA	364
c153f45f	365	cur_irq += irqwait->request.irq;
22f579c6	366
c153f45f	367	switch (irqwait->request.type & ~VIA_IRQ_FLAGS_MASK) {
22f579c6	368	case VIA_IRQ_RELATIVE:
0a3e67a4 JB	369	irqwait->request.sequence +=
0a3e67a4 JB	370	atomic_read(&cur_irq->irq_received);
c153f45f	371	irqwait->request.type &= ~_DRM_VBLANK_RELATIVE;
22f579c6 DA	372	case VIA_IRQ_ABSOLUTE:
	373	break;
	374	default:
20caafa6	375	return -EINVAL;
22f579c6 DA	376	}
22f579c6 DA	377
c153f45f	378	if (irqwait->request.type & VIA_IRQ_SIGNAL) {
3e684eae	379	DRM_ERROR("Signals on Via IRQs not implemented yet.\n");
20caafa6	380	return -EINVAL;
22f579c6 DA	381	}
22f579c6 DA	382
c153f45f	383	force_sequence = (irqwait->request.type & VIA_IRQ_FORCE_SEQUENCE);
22f579c6	384
c153f45f EA	385	ret = via_driver_irq_wait(dev, irqwait->request.irq, force_sequence,
c153f45f EA	386	&irqwait->request.sequence);
22f579c6	387	do_gettimeofday(&now);
c153f45f EA	388	irqwait->reply.tval_sec = now.tv_sec;
c153f45f EA	389	irqwait->reply.tval_usec = now.tv_usec;
22f579c6 DA	390
	391	return ret;
	392	}