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Merge tag 'topic/core-stuff-2014-08-15' of git://anongit.freedesktop.org/drm-intel...
[deliverable/linux.git] / drivers / gpu / drm / vmwgfx / svga3d_reg.h
CommitLineData
632f6117
JB		 1/**********************************************************
2 * Copyright 1998-2009 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26/*
27 * svga3d_reg.h --
28 *
29 * SVGA 3D hardware definitions
30 */
31
32#ifndef _SVGA3D_REG_H_
33#define _SVGA3D_REG_H_
34
35#include "svga_reg.h"
36
d9019498 37typedef uint32 PPN;
f2a0dcb1 38typedef __le64 PPN64;
632f6117
JB		 39
40/*
41 * 3D Hardware Version
42 *
43 * The hardware version is stored in the SVGA_FIFO_3D_HWVERSION fifo
44 * register. Is set by the host and read by the guest. This lets
45 * us make new guest drivers which are backwards-compatible with old
46 * SVGA hardware revisions. It does not let us support old guest
47 * drivers. Good enough for now.
48 *
49 */
50
51#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
52#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16)
53#define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF)
54
55typedef enum {
56 SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1),
57 SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2),
58 SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3),
59 SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1),
60 SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4),
61 SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0),
8d3713ea
JB		 62 SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1),
63 SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1,
632f6117
JB		 64} SVGA3dHardwareVersion;
65
66/*
67 * Generic Types
68 */
69
70typedef uint32 SVGA3dBool; /* 32-bit Bool definition */
71#define SVGA3D_NUM_CLIPPLANES 6
72#define SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS 8
8d3713ea
JB		 73#define SVGA3D_MAX_CONTEXT_IDS 256
74#define SVGA3D_MAX_SURFACE_IDS (32 * 1024)
632f6117 75
d9019498
TH		 76#define SVGA3D_NUM_TEXTURE_UNITS 32
77#define SVGA3D_NUM_LIGHTS 8
78
632f6117
JB		 79/*
80 * Surface formats.
81 *
82 * If you modify this list, be sure to keep GLUtil.c in sync. It
83 * includes the internal format definition of each surface in
84 * GLUtil_ConvertSurfaceFormat, and it contains a table of
85 * human-readable names in GLUtil_GetFormatName.
86 */
87
88typedef enum SVGA3dSurfaceFormat {
d9019498 89 SVGA3D_FORMAT_MIN = 0,
8d3713ea 90 SVGA3D_FORMAT_INVALID = 0,
632f6117 91
8d3713ea
JB		 92 SVGA3D_X8R8G8B8 = 1,
93 SVGA3D_A8R8G8B8 = 2,
632f6117 94
8d3713ea
JB		 95 SVGA3D_R5G6B5 = 3,
96 SVGA3D_X1R5G5B5 = 4,
97 SVGA3D_A1R5G5B5 = 5,
98 SVGA3D_A4R4G4B4 = 6,
632f6117 99
8d3713ea
JB		 100 SVGA3D_Z_D32 = 7,
101 SVGA3D_Z_D16 = 8,
102 SVGA3D_Z_D24S8 = 9,
103 SVGA3D_Z_D15S1 = 10,
632f6117 104
8d3713ea
JB		 105 SVGA3D_LUMINANCE8 = 11,
106 SVGA3D_LUMINANCE4_ALPHA4 = 12,
107 SVGA3D_LUMINANCE16 = 13,
108 SVGA3D_LUMINANCE8_ALPHA8 = 14,
632f6117 109
8d3713ea
JB		 110 SVGA3D_DXT1 = 15,
111 SVGA3D_DXT2 = 16,
112 SVGA3D_DXT3 = 17,
113 SVGA3D_DXT4 = 18,
114 SVGA3D_DXT5 = 19,
632f6117 115
8d3713ea
JB		 116 SVGA3D_BUMPU8V8 = 20,
117 SVGA3D_BUMPL6V5U5 = 21,
118 SVGA3D_BUMPX8L8V8U8 = 22,
119 SVGA3D_BUMPL8V8U8 = 23,
632f6117 120
8d3713ea
JB		 121 SVGA3D_ARGB_S10E5 = 24, /* 16-bit floating-point ARGB */
122 SVGA3D_ARGB_S23E8 = 25, /* 32-bit floating-point ARGB */
632f6117 123
8d3713ea 124 SVGA3D_A2R10G10B10 = 26,
632f6117
JB		 125
126 /* signed formats */
8d3713ea
JB		 127 SVGA3D_V8U8 = 27,
128 SVGA3D_Q8W8V8U8 = 28,
129 SVGA3D_CxV8U8 = 29,
632f6117
JB		 130
131 /* mixed formats */
8d3713ea
JB		 132 SVGA3D_X8L8V8U8 = 30,
133 SVGA3D_A2W10V10U10 = 31,
632f6117 134
8d3713ea 135 SVGA3D_ALPHA8 = 32,
632f6117
JB		 136
137 /* Single- and dual-component floating point formats */
8d3713ea
JB		 138 SVGA3D_R_S10E5 = 33,
139 SVGA3D_R_S23E8 = 34,
140 SVGA3D_RG_S10E5 = 35,
141 SVGA3D_RG_S23E8 = 36,
632f6117 142
8d3713ea
JB		 143 SVGA3D_BUFFER = 37,
144
145 SVGA3D_Z_D24X8 = 38,
632f6117 146
8d3713ea 147 SVGA3D_V16U16 = 39,
632f6117 148
8d3713ea
JB		 149 SVGA3D_G16R16 = 40,
150 SVGA3D_A16B16G16R16 = 41,
632f6117
JB		 151
152 /* Packed Video formats */
8d3713ea
JB		 153 SVGA3D_UYVY = 42,
154 SVGA3D_YUY2 = 43,
155
156 /* Planar video formats */
157 SVGA3D_NV12 = 44,
158
159 /* Video format with alpha */
160 SVGA3D_AYUV = 45,
161
d9019498
TH		 162 SVGA3D_R32G32B32A32_TYPELESS = 46,
163 SVGA3D_R32G32B32A32_FLOAT = 25,
164 SVGA3D_R32G32B32A32_UINT = 47,
165 SVGA3D_R32G32B32A32_SINT = 48,
166 SVGA3D_R32G32B32_TYPELESS = 49,
167 SVGA3D_R32G32B32_FLOAT = 50,
168 SVGA3D_R32G32B32_UINT = 51,
169 SVGA3D_R32G32B32_SINT = 52,
170 SVGA3D_R16G16B16A16_TYPELESS = 53,
171 SVGA3D_R16G16B16A16_FLOAT = 24,
172 SVGA3D_R16G16B16A16_UNORM = 41,
173 SVGA3D_R16G16B16A16_UINT = 54,
174 SVGA3D_R16G16B16A16_SNORM = 55,
175 SVGA3D_R16G16B16A16_SINT = 56,
176 SVGA3D_R32G32_TYPELESS = 57,
177 SVGA3D_R32G32_FLOAT = 36,
178 SVGA3D_R32G32_UINT = 58,
179 SVGA3D_R32G32_SINT = 59,
180 SVGA3D_R32G8X24_TYPELESS = 60,
181 SVGA3D_D32_FLOAT_S8X24_UINT = 61,
182 SVGA3D_R32_FLOAT_X8X24_TYPELESS = 62,
183 SVGA3D_X32_TYPELESS_G8X24_UINT = 63,
184 SVGA3D_R10G10B10A2_TYPELESS = 64,
185 SVGA3D_R10G10B10A2_UNORM = 26,
186 SVGA3D_R10G10B10A2_UINT = 65,
187 SVGA3D_R11G11B10_FLOAT = 66,
188 SVGA3D_R8G8B8A8_TYPELESS = 67,
189 SVGA3D_R8G8B8A8_UNORM = 68,
190 SVGA3D_R8G8B8A8_UNORM_SRGB = 69,
191 SVGA3D_R8G8B8A8_UINT = 70,
192 SVGA3D_R8G8B8A8_SNORM = 28,
193 SVGA3D_R8G8B8A8_SINT = 71,
194 SVGA3D_R16G16_TYPELESS = 72,
195 SVGA3D_R16G16_FLOAT = 35,
196 SVGA3D_R16G16_UNORM = 40,
197 SVGA3D_R16G16_UINT = 73,
198 SVGA3D_R16G16_SNORM = 39,
199 SVGA3D_R16G16_SINT = 74,
200 SVGA3D_R32_TYPELESS = 75,
201 SVGA3D_D32_FLOAT = 76,
202 SVGA3D_R32_FLOAT = 34,
203 SVGA3D_R32_UINT = 77,
204 SVGA3D_R32_SINT = 78,
205 SVGA3D_R24G8_TYPELESS = 79,
206 SVGA3D_D24_UNORM_S8_UINT = 80,
207 SVGA3D_R24_UNORM_X8_TYPELESS = 81,
208 SVGA3D_X24_TYPELESS_G8_UINT = 82,
209 SVGA3D_R8G8_TYPELESS = 83,
210 SVGA3D_R8G8_UNORM = 84,
211 SVGA3D_R8G8_UINT = 85,
212 SVGA3D_R8G8_SNORM = 27,
213 SVGA3D_R8G8_SINT = 86,
214 SVGA3D_R16_TYPELESS = 87,
215 SVGA3D_R16_FLOAT = 33,
216 SVGA3D_D16_UNORM = 8,
217 SVGA3D_R16_UNORM = 88,
218 SVGA3D_R16_UINT = 89,
219 SVGA3D_R16_SNORM = 90,
220 SVGA3D_R16_SINT = 91,
221 SVGA3D_R8_TYPELESS = 92,
222 SVGA3D_R8_UNORM = 93,
223 SVGA3D_R8_UINT = 94,
224 SVGA3D_R8_SNORM = 95,
225 SVGA3D_R8_SINT = 96,
226 SVGA3D_A8_UNORM = 32,
227 SVGA3D_R1_UNORM = 97,
228 SVGA3D_R9G9B9E5_SHAREDEXP = 98,
229 SVGA3D_R8G8_B8G8_UNORM = 99,
230 SVGA3D_G8R8_G8B8_UNORM = 100,
231 SVGA3D_BC1_TYPELESS = 101,
232 SVGA3D_BC1_UNORM = 15,
233 SVGA3D_BC1_UNORM_SRGB = 102,
234 SVGA3D_BC2_TYPELESS = 103,
235 SVGA3D_BC2_UNORM = 17,
236 SVGA3D_BC2_UNORM_SRGB = 104,
237 SVGA3D_BC3_TYPELESS = 105,
238 SVGA3D_BC3_UNORM = 19,
239 SVGA3D_BC3_UNORM_SRGB = 106,
240 SVGA3D_BC4_TYPELESS = 107,
8d3713ea 241 SVGA3D_BC4_UNORM = 108,
d9019498
TH		 242 SVGA3D_BC4_SNORM = 109,
243 SVGA3D_BC5_TYPELESS = 110,
8d3713ea 244 SVGA3D_BC5_UNORM = 111,
d9019498
TH		 245 SVGA3D_BC5_SNORM = 112,
246 SVGA3D_B5G6R5_UNORM = 3,
247 SVGA3D_B5G5R5A1_UNORM = 5,
248 SVGA3D_B8G8R8A8_UNORM = 2,
249 SVGA3D_B8G8R8X8_UNORM = 1,
250 SVGA3D_R10G10B10_XR_BIAS_A2_UNORM = 113,
251 SVGA3D_B8G8R8A8_TYPELESS = 114,
252 SVGA3D_B8G8R8A8_UNORM_SRGB = 115,
253 SVGA3D_B8G8R8X8_TYPELESS = 116,
254 SVGA3D_B8G8R8X8_UNORM_SRGB = 117,
8d3713ea
JB		 255
256 /* Advanced D3D9 depth formats. */
257 SVGA3D_Z_DF16 = 118,
258 SVGA3D_Z_DF24 = 119,
259 SVGA3D_Z_D24S8_INT = 120,
632f6117 260
d9019498
TH		 261 /* Planar video formats. */
262 SVGA3D_YV12 = 121,
263
ae204569 264 SVGA3D_FORMAT_MAX = 122,
632f6117
JB		 265} SVGA3dSurfaceFormat;
266
267typedef uint32 SVGA3dColor; /* a, r, g, b */
268
269/*
270 * These match the D3DFORMAT_OP definitions used by Direct3D. We need
271 * them so that we can query the host for what the supported surface
272 * operations are (when we're using the D3D backend, in particular),
273 * and so we can send those operations to the guest.
274 */
275typedef enum {
276 SVGA3DFORMAT_OP_TEXTURE = 0x00000001,
277 SVGA3DFORMAT_OP_VOLUMETEXTURE = 0x00000002,
278 SVGA3DFORMAT_OP_CUBETEXTURE = 0x00000004,
279 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET = 0x00000008,
280 SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET = 0x00000010,
281 SVGA3DFORMAT_OP_ZSTENCIL = 0x00000040,
282 SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH = 0x00000080,
283
284/*
285 * This format can be used as a render target if the current display mode
286 * is the same depth if the alpha channel is ignored. e.g. if the device
287 * can render to A8R8G8B8 when the display mode is X8R8G8B8, then the
288 * format op list entry for A8R8G8B8 should have this cap.
289 */
290 SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET = 0x00000100,
291
292/*
293 * This format contains DirectDraw support (including Flip). This flag
294 * should not to be set on alpha formats.
295 */
296 SVGA3DFORMAT_OP_DISPLAYMODE = 0x00000400,
297
298/*
299 * The rasterizer can support some level of Direct3D support in this format
300 * and implies that the driver can create a Context in this mode (for some
301 * render target format). When this flag is set, the SVGA3DFORMAT_OP_DISPLAYMODE
302 * flag must also be set.
303 */
304 SVGA3DFORMAT_OP_3DACCELERATION = 0x00000800,
305
306/*
307 * This is set for a private format when the driver has put the bpp in
308 * the structure.
309 */
310 SVGA3DFORMAT_OP_PIXELSIZE = 0x00001000,
311
312/*
313 * Indicates that this format can be converted to any RGB format for which
314 * SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB is specified
315 */
316 SVGA3DFORMAT_OP_CONVERT_TO_ARGB = 0x00002000,
317
318/*
319 * Indicates that this format can be used to create offscreen plain surfaces.
320 */
321 SVGA3DFORMAT_OP_OFFSCREENPLAIN = 0x00004000,
322
323/*
324 * Indicated that this format can be read as an SRGB texture (meaning that the
325 * sampler will linearize the looked up data)
326 */
327 SVGA3DFORMAT_OP_SRGBREAD = 0x00008000,
328
329/*
330 * Indicates that this format can be used in the bumpmap instructions
331 */
332 SVGA3DFORMAT_OP_BUMPMAP = 0x00010000,
333
334/*
335 * Indicates that this format can be sampled by the displacement map sampler
336 */
337 SVGA3DFORMAT_OP_DMAP = 0x00020000,
338
339/*
340 * Indicates that this format cannot be used with texture filtering
341 */
342 SVGA3DFORMAT_OP_NOFILTER = 0x00040000,
343
344/*
345 * Indicates that format conversions are supported to this RGB format if
346 * SVGA3DFORMAT_OP_CONVERT_TO_ARGB is specified in the source format.
347 */
348 SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB = 0x00080000,
349
350/*
351 * Indicated that this format can be written as an SRGB target (meaning that the
352 * pixel pipe will DE-linearize data on output to format)
353 */
354 SVGA3DFORMAT_OP_SRGBWRITE = 0x00100000,
355
356/*
357 * Indicates that this format cannot be used with alpha blending
358 */
359 SVGA3DFORMAT_OP_NOALPHABLEND = 0x00200000,
360
361/*
362 * Indicates that the device can auto-generated sublevels for resources
363 * of this format
364 */
365 SVGA3DFORMAT_OP_AUTOGENMIPMAP = 0x00400000,
366
367/*
368 * Indicates that this format can be used by vertex texture sampler
369 */
370 SVGA3DFORMAT_OP_VERTEXTEXTURE = 0x00800000,
371
372/*
373 * Indicates that this format supports neither texture coordinate wrap
374 * modes, nor mipmapping
375 */
376 SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP = 0x01000000
377} SVGA3dFormatOp;
378
379/*
380 * This structure is a conversion of SVGA3DFORMAT_OP_*.
381 * Entries must be located at the same position.
382 */
383typedef union {
384 uint32 value;
385 struct {
386 uint32 texture : 1;
387 uint32 volumeTexture : 1;
388 uint32 cubeTexture : 1;
389 uint32 offscreenRenderTarget : 1;
390 uint32 sameFormatRenderTarget : 1;
391 uint32 unknown1 : 1;
392 uint32 zStencil : 1;
393 uint32 zStencilArbitraryDepth : 1;
394 uint32 sameFormatUpToAlpha : 1;
395 uint32 unknown2 : 1;
396 uint32 displayMode : 1;
397 uint32 acceleration3d : 1;
398 uint32 pixelSize : 1;
399 uint32 convertToARGB : 1;
400 uint32 offscreenPlain : 1;
401 uint32 sRGBRead : 1;
402 uint32 bumpMap : 1;
403 uint32 dmap : 1;
404 uint32 noFilter : 1;
405 uint32 memberOfGroupARGB : 1;
406 uint32 sRGBWrite : 1;
407 uint32 noAlphaBlend : 1;
408 uint32 autoGenMipMap : 1;
409 uint32 vertexTexture : 1;
410 uint32 noTexCoordWrapNorMip : 1;
411 };
412} SVGA3dSurfaceFormatCaps;
413
414/*
415 * SVGA_3D_CMD_SETRENDERSTATE Types. All value types
416 * must fit in a uint32.
417 */
418
419typedef enum {
420 SVGA3D_RS_INVALID = 0,
421 SVGA3D_RS_ZENABLE = 1, /* SVGA3dBool */
422 SVGA3D_RS_ZWRITEENABLE = 2, /* SVGA3dBool */
423 SVGA3D_RS_ALPHATESTENABLE = 3, /* SVGA3dBool */
424 SVGA3D_RS_DITHERENABLE = 4, /* SVGA3dBool */
425 SVGA3D_RS_BLENDENABLE = 5, /* SVGA3dBool */
426 SVGA3D_RS_FOGENABLE = 6, /* SVGA3dBool */
427 SVGA3D_RS_SPECULARENABLE = 7, /* SVGA3dBool */
428 SVGA3D_RS_STENCILENABLE = 8, /* SVGA3dBool */
429 SVGA3D_RS_LIGHTINGENABLE = 9, /* SVGA3dBool */
430 SVGA3D_RS_NORMALIZENORMALS = 10, /* SVGA3dBool */
431 SVGA3D_RS_POINTSPRITEENABLE = 11, /* SVGA3dBool */
432 SVGA3D_RS_POINTSCALEENABLE = 12, /* SVGA3dBool */
433 SVGA3D_RS_STENCILREF = 13, /* uint32 */
434 SVGA3D_RS_STENCILMASK = 14, /* uint32 */
435 SVGA3D_RS_STENCILWRITEMASK = 15, /* uint32 */
436 SVGA3D_RS_FOGSTART = 16, /* float */
437 SVGA3D_RS_FOGEND = 17, /* float */
438 SVGA3D_RS_FOGDENSITY = 18, /* float */
439 SVGA3D_RS_POINTSIZE = 19, /* float */
440 SVGA3D_RS_POINTSIZEMIN = 20, /* float */
441 SVGA3D_RS_POINTSIZEMAX = 21, /* float */
442 SVGA3D_RS_POINTSCALE_A = 22, /* float */
443 SVGA3D_RS_POINTSCALE_B = 23, /* float */
444 SVGA3D_RS_POINTSCALE_C = 24, /* float */
445 SVGA3D_RS_FOGCOLOR = 25, /* SVGA3dColor */
446 SVGA3D_RS_AMBIENT = 26, /* SVGA3dColor */
447 SVGA3D_RS_CLIPPLANEENABLE = 27, /* SVGA3dClipPlanes */
448 SVGA3D_RS_FOGMODE = 28, /* SVGA3dFogMode */
449 SVGA3D_RS_FILLMODE = 29, /* SVGA3dFillMode */
450 SVGA3D_RS_SHADEMODE = 30, /* SVGA3dShadeMode */
451 SVGA3D_RS_LINEPATTERN = 31, /* SVGA3dLinePattern */
452 SVGA3D_RS_SRCBLEND = 32, /* SVGA3dBlendOp */
453 SVGA3D_RS_DSTBLEND = 33, /* SVGA3dBlendOp */
454 SVGA3D_RS_BLENDEQUATION = 34, /* SVGA3dBlendEquation */
455 SVGA3D_RS_CULLMODE = 35, /* SVGA3dFace */
456 SVGA3D_RS_ZFUNC = 36, /* SVGA3dCmpFunc */
457 SVGA3D_RS_ALPHAFUNC = 37, /* SVGA3dCmpFunc */
458 SVGA3D_RS_STENCILFUNC = 38, /* SVGA3dCmpFunc */
459 SVGA3D_RS_STENCILFAIL = 39, /* SVGA3dStencilOp */
460 SVGA3D_RS_STENCILZFAIL = 40, /* SVGA3dStencilOp */
461 SVGA3D_RS_STENCILPASS = 41, /* SVGA3dStencilOp */
462 SVGA3D_RS_ALPHAREF = 42, /* float (0.0 .. 1.0) */
463 SVGA3D_RS_FRONTWINDING = 43, /* SVGA3dFrontWinding */
464 SVGA3D_RS_COORDINATETYPE = 44, /* SVGA3dCoordinateType */
465 SVGA3D_RS_ZBIAS = 45, /* float */
466 SVGA3D_RS_RANGEFOGENABLE = 46, /* SVGA3dBool */
467 SVGA3D_RS_COLORWRITEENABLE = 47, /* SVGA3dColorMask */
468 SVGA3D_RS_VERTEXMATERIALENABLE = 48, /* SVGA3dBool */
469 SVGA3D_RS_DIFFUSEMATERIALSOURCE = 49, /* SVGA3dVertexMaterial */
470 SVGA3D_RS_SPECULARMATERIALSOURCE = 50, /* SVGA3dVertexMaterial */
471 SVGA3D_RS_AMBIENTMATERIALSOURCE = 51, /* SVGA3dVertexMaterial */
472 SVGA3D_RS_EMISSIVEMATERIALSOURCE = 52, /* SVGA3dVertexMaterial */
473 SVGA3D_RS_TEXTUREFACTOR = 53, /* SVGA3dColor */
474 SVGA3D_RS_LOCALVIEWER = 54, /* SVGA3dBool */
475 SVGA3D_RS_SCISSORTESTENABLE = 55, /* SVGA3dBool */
476 SVGA3D_RS_BLENDCOLOR = 56, /* SVGA3dColor */
477 SVGA3D_RS_STENCILENABLE2SIDED = 57, /* SVGA3dBool */
478 SVGA3D_RS_CCWSTENCILFUNC = 58, /* SVGA3dCmpFunc */
479 SVGA3D_RS_CCWSTENCILFAIL = 59, /* SVGA3dStencilOp */
480 SVGA3D_RS_CCWSTENCILZFAIL = 60, /* SVGA3dStencilOp */
481 SVGA3D_RS_CCWSTENCILPASS = 61, /* SVGA3dStencilOp */
482 SVGA3D_RS_VERTEXBLEND = 62, /* SVGA3dVertexBlendFlags */
483 SVGA3D_RS_SLOPESCALEDEPTHBIAS = 63, /* float */
484 SVGA3D_RS_DEPTHBIAS = 64, /* float */
485
486
487 /*
488 * Output Gamma Level
489 *
490 * Output gamma effects the gamma curve of colors that are output from the
491 * rendering pipeline. A value of 1.0 specifies a linear color space. If the
492 * value is <= 0.0, gamma correction is ignored and linear color space is
493 * used.
494 */
495
496 SVGA3D_RS_OUTPUTGAMMA = 65, /* float */
497 SVGA3D_RS_ZVISIBLE = 66, /* SVGA3dBool */
498 SVGA3D_RS_LASTPIXEL = 67, /* SVGA3dBool */
499 SVGA3D_RS_CLIPPING = 68, /* SVGA3dBool */
500 SVGA3D_RS_WRAP0 = 69, /* SVGA3dWrapFlags */
501 SVGA3D_RS_WRAP1 = 70, /* SVGA3dWrapFlags */
502 SVGA3D_RS_WRAP2 = 71, /* SVGA3dWrapFlags */
503 SVGA3D_RS_WRAP3 = 72, /* SVGA3dWrapFlags */
504 SVGA3D_RS_WRAP4 = 73, /* SVGA3dWrapFlags */
505 SVGA3D_RS_WRAP5 = 74, /* SVGA3dWrapFlags */
506 SVGA3D_RS_WRAP6 = 75, /* SVGA3dWrapFlags */
507 SVGA3D_RS_WRAP7 = 76, /* SVGA3dWrapFlags */
508 SVGA3D_RS_WRAP8 = 77, /* SVGA3dWrapFlags */
509 SVGA3D_RS_WRAP9 = 78, /* SVGA3dWrapFlags */
510 SVGA3D_RS_WRAP10 = 79, /* SVGA3dWrapFlags */
511 SVGA3D_RS_WRAP11 = 80, /* SVGA3dWrapFlags */
512 SVGA3D_RS_WRAP12 = 81, /* SVGA3dWrapFlags */
513 SVGA3D_RS_WRAP13 = 82, /* SVGA3dWrapFlags */
514 SVGA3D_RS_WRAP14 = 83, /* SVGA3dWrapFlags */
515 SVGA3D_RS_WRAP15 = 84, /* SVGA3dWrapFlags */
516 SVGA3D_RS_MULTISAMPLEANTIALIAS = 85, /* SVGA3dBool */
517 SVGA3D_RS_MULTISAMPLEMASK = 86, /* uint32 */
518 SVGA3D_RS_INDEXEDVERTEXBLENDENABLE = 87, /* SVGA3dBool */
519 SVGA3D_RS_TWEENFACTOR = 88, /* float */
520 SVGA3D_RS_ANTIALIASEDLINEENABLE = 89, /* SVGA3dBool */
521 SVGA3D_RS_COLORWRITEENABLE1 = 90, /* SVGA3dColorMask */
522 SVGA3D_RS_COLORWRITEENABLE2 = 91, /* SVGA3dColorMask */
523 SVGA3D_RS_COLORWRITEENABLE3 = 92, /* SVGA3dColorMask */
524 SVGA3D_RS_SEPARATEALPHABLENDENABLE = 93, /* SVGA3dBool */
525 SVGA3D_RS_SRCBLENDALPHA = 94, /* SVGA3dBlendOp */
526 SVGA3D_RS_DSTBLENDALPHA = 95, /* SVGA3dBlendOp */
527 SVGA3D_RS_BLENDEQUATIONALPHA = 96, /* SVGA3dBlendEquation */
8d3713ea
JB		 528 SVGA3D_RS_TRANSPARENCYANTIALIAS = 97, /* SVGA3dTransparencyAntialiasType */
529 SVGA3D_RS_LINEAA = 98, /* SVGA3dBool */
530 SVGA3D_RS_LINEWIDTH = 99, /* float */
632f6117
JB		 531 SVGA3D_RS_MAX
532} SVGA3dRenderStateName;
533
8d3713ea
JB		 534typedef enum {
535 SVGA3D_TRANSPARENCYANTIALIAS_NORMAL = 0,
536 SVGA3D_TRANSPARENCYANTIALIAS_ALPHATOCOVERAGE = 1,
537 SVGA3D_TRANSPARENCYANTIALIAS_SUPERSAMPLE = 2,
538 SVGA3D_TRANSPARENCYANTIALIAS_MAX
539} SVGA3dTransparencyAntialiasType;
540
632f6117
JB		 541typedef enum {
542 SVGA3D_VERTEXMATERIAL_NONE = 0, /* Use the value in the current material */
543 SVGA3D_VERTEXMATERIAL_DIFFUSE = 1, /* Use the value in the diffuse component */
544 SVGA3D_VERTEXMATERIAL_SPECULAR = 2, /* Use the value in the specular component */
545} SVGA3dVertexMaterial;
546
547typedef enum {
548 SVGA3D_FILLMODE_INVALID = 0,
549 SVGA3D_FILLMODE_POINT = 1,
550 SVGA3D_FILLMODE_LINE = 2,
551 SVGA3D_FILLMODE_FILL = 3,
552 SVGA3D_FILLMODE_MAX
553} SVGA3dFillModeType;
554
555
556typedef
557union {
558 struct {
559 uint16 mode; /* SVGA3dFillModeType */
560 uint16 face; /* SVGA3dFace */
561 };
562 uint32 uintValue;
563} SVGA3dFillMode;
564
565typedef enum {
566 SVGA3D_SHADEMODE_INVALID = 0,
567 SVGA3D_SHADEMODE_FLAT = 1,
568 SVGA3D_SHADEMODE_SMOOTH = 2,
569 SVGA3D_SHADEMODE_PHONG = 3, /* Not supported */
570 SVGA3D_SHADEMODE_MAX
571} SVGA3dShadeMode;
572
573typedef
574union {
575 struct {
576 uint16 repeat;
577 uint16 pattern;
578 };
579 uint32 uintValue;
580} SVGA3dLinePattern;
581
582typedef enum {
583 SVGA3D_BLENDOP_INVALID = 0,
584 SVGA3D_BLENDOP_ZERO = 1,
585 SVGA3D_BLENDOP_ONE = 2,
586 SVGA3D_BLENDOP_SRCCOLOR = 3,
587 SVGA3D_BLENDOP_INVSRCCOLOR = 4,
588 SVGA3D_BLENDOP_SRCALPHA = 5,
589 SVGA3D_BLENDOP_INVSRCALPHA = 6,
590 SVGA3D_BLENDOP_DESTALPHA = 7,
591 SVGA3D_BLENDOP_INVDESTALPHA = 8,
592 SVGA3D_BLENDOP_DESTCOLOR = 9,
593 SVGA3D_BLENDOP_INVDESTCOLOR = 10,
594 SVGA3D_BLENDOP_SRCALPHASAT = 11,
595 SVGA3D_BLENDOP_BLENDFACTOR = 12,
596 SVGA3D_BLENDOP_INVBLENDFACTOR = 13,
597 SVGA3D_BLENDOP_MAX
598} SVGA3dBlendOp;
599
600typedef enum {
601 SVGA3D_BLENDEQ_INVALID = 0,
602 SVGA3D_BLENDEQ_ADD = 1,
603 SVGA3D_BLENDEQ_SUBTRACT = 2,
604 SVGA3D_BLENDEQ_REVSUBTRACT = 3,
605 SVGA3D_BLENDEQ_MINIMUM = 4,
606 SVGA3D_BLENDEQ_MAXIMUM = 5,
607 SVGA3D_BLENDEQ_MAX
608} SVGA3dBlendEquation;
609
610typedef enum {
611 SVGA3D_FRONTWINDING_INVALID = 0,
612 SVGA3D_FRONTWINDING_CW = 1,
613 SVGA3D_FRONTWINDING_CCW = 2,
614 SVGA3D_FRONTWINDING_MAX
615} SVGA3dFrontWinding;
616
617typedef enum {
618 SVGA3D_FACE_INVALID = 0,
619 SVGA3D_FACE_NONE = 1,
620 SVGA3D_FACE_FRONT = 2,
621 SVGA3D_FACE_BACK = 3,
622 SVGA3D_FACE_FRONT_BACK = 4,
623 SVGA3D_FACE_MAX
624} SVGA3dFace;
625
626/*
627 * The order and the values should not be changed
628 */
629
630typedef enum {
631 SVGA3D_CMP_INVALID = 0,
632 SVGA3D_CMP_NEVER = 1,
633 SVGA3D_CMP_LESS = 2,
634 SVGA3D_CMP_EQUAL = 3,
635 SVGA3D_CMP_LESSEQUAL = 4,
636 SVGA3D_CMP_GREATER = 5,
637 SVGA3D_CMP_NOTEQUAL = 6,
638 SVGA3D_CMP_GREATEREQUAL = 7,
639 SVGA3D_CMP_ALWAYS = 8,
640 SVGA3D_CMP_MAX
641} SVGA3dCmpFunc;
642
643/*
644 * SVGA3D_FOGFUNC_* specifies the fog equation, or PER_VERTEX which allows
645 * the fog factor to be specified in the alpha component of the specular
646 * (a.k.a. secondary) vertex color.
647 */
648typedef enum {
649 SVGA3D_FOGFUNC_INVALID = 0,
650 SVGA3D_FOGFUNC_EXP = 1,
651 SVGA3D_FOGFUNC_EXP2 = 2,
652 SVGA3D_FOGFUNC_LINEAR = 3,
653 SVGA3D_FOGFUNC_PER_VERTEX = 4
654} SVGA3dFogFunction;
655
656/*
657 * SVGA3D_FOGTYPE_* specifies if fog factors are computed on a per-vertex
658 * or per-pixel basis.
659 */
660typedef enum {
661 SVGA3D_FOGTYPE_INVALID = 0,
662 SVGA3D_FOGTYPE_VERTEX = 1,
663 SVGA3D_FOGTYPE_PIXEL = 2,
664 SVGA3D_FOGTYPE_MAX = 3
665} SVGA3dFogType;
666
667/*
668 * SVGA3D_FOGBASE_* selects depth or range-based fog. Depth-based fog is
669 * computed using the eye Z value of each pixel (or vertex), whereas range-
670 * based fog is computed using the actual distance (range) to the eye.
671 */
672typedef enum {
673 SVGA3D_FOGBASE_INVALID = 0,
674 SVGA3D_FOGBASE_DEPTHBASED = 1,
675 SVGA3D_FOGBASE_RANGEBASED = 2,
676 SVGA3D_FOGBASE_MAX = 3
677} SVGA3dFogBase;
678
679typedef enum {
680 SVGA3D_STENCILOP_INVALID = 0,
681 SVGA3D_STENCILOP_KEEP = 1,
682 SVGA3D_STENCILOP_ZERO = 2,
683 SVGA3D_STENCILOP_REPLACE = 3,
684 SVGA3D_STENCILOP_INCRSAT = 4,
685 SVGA3D_STENCILOP_DECRSAT = 5,
686 SVGA3D_STENCILOP_INVERT = 6,
687 SVGA3D_STENCILOP_INCR = 7,
688 SVGA3D_STENCILOP_DECR = 8,
689 SVGA3D_STENCILOP_MAX
690} SVGA3dStencilOp;
691
692typedef enum {
693 SVGA3D_CLIPPLANE_0 = (1 << 0),
694 SVGA3D_CLIPPLANE_1 = (1 << 1),
695 SVGA3D_CLIPPLANE_2 = (1 << 2),
696 SVGA3D_CLIPPLANE_3 = (1 << 3),
697 SVGA3D_CLIPPLANE_4 = (1 << 4),
698 SVGA3D_CLIPPLANE_5 = (1 << 5),
699} SVGA3dClipPlanes;
700
701typedef enum {
702 SVGA3D_CLEAR_COLOR = 0x1,
703 SVGA3D_CLEAR_DEPTH = 0x2,
704 SVGA3D_CLEAR_STENCIL = 0x4
705} SVGA3dClearFlag;
706
707typedef enum {
708 SVGA3D_RT_DEPTH = 0,
709 SVGA3D_RT_STENCIL = 1,
710 SVGA3D_RT_COLOR0 = 2,
711 SVGA3D_RT_COLOR1 = 3,
712 SVGA3D_RT_COLOR2 = 4,
713 SVGA3D_RT_COLOR3 = 5,
714 SVGA3D_RT_COLOR4 = 6,
715 SVGA3D_RT_COLOR5 = 7,
716 SVGA3D_RT_COLOR6 = 8,
717 SVGA3D_RT_COLOR7 = 9,
718 SVGA3D_RT_MAX,
719 SVGA3D_RT_INVALID = ((uint32)-1),
720} SVGA3dRenderTargetType;
721
722#define SVGA3D_MAX_RT_COLOR (SVGA3D_RT_COLOR7 - SVGA3D_RT_COLOR0 + 1)
723
724typedef
725union {
726 struct {
727 uint32 red : 1;
728 uint32 green : 1;
729 uint32 blue : 1;
730 uint32 alpha : 1;
731 };
732 uint32 uintValue;
733} SVGA3dColorMask;
734
735typedef enum {
736 SVGA3D_VBLEND_DISABLE = 0,
737 SVGA3D_VBLEND_1WEIGHT = 1,
738 SVGA3D_VBLEND_2WEIGHT = 2,
739 SVGA3D_VBLEND_3WEIGHT = 3,
740} SVGA3dVertexBlendFlags;
741
742typedef enum {
743 SVGA3D_WRAPCOORD_0 = 1 << 0,
744 SVGA3D_WRAPCOORD_1 = 1 << 1,
745 SVGA3D_WRAPCOORD_2 = 1 << 2,
746 SVGA3D_WRAPCOORD_3 = 1 << 3,
747 SVGA3D_WRAPCOORD_ALL = 0xF,
748} SVGA3dWrapFlags;
749
750/*
751 * SVGA_3D_CMD_TEXTURESTATE Types. All value types
752 * must fit in a uint32.
753 */
754
755typedef enum {
756 SVGA3D_TS_INVALID = 0,
757 SVGA3D_TS_BIND_TEXTURE = 1, /* SVGA3dSurfaceId */
758 SVGA3D_TS_COLOROP = 2, /* SVGA3dTextureCombiner */
759 SVGA3D_TS_COLORARG1 = 3, /* SVGA3dTextureArgData */
760 SVGA3D_TS_COLORARG2 = 4, /* SVGA3dTextureArgData */
761 SVGA3D_TS_ALPHAOP = 5, /* SVGA3dTextureCombiner */
762 SVGA3D_TS_ALPHAARG1 = 6, /* SVGA3dTextureArgData */
763 SVGA3D_TS_ALPHAARG2 = 7, /* SVGA3dTextureArgData */
764 SVGA3D_TS_ADDRESSU = 8, /* SVGA3dTextureAddress */
765 SVGA3D_TS_ADDRESSV = 9, /* SVGA3dTextureAddress */
766 SVGA3D_TS_MIPFILTER = 10, /* SVGA3dTextureFilter */
767 SVGA3D_TS_MAGFILTER = 11, /* SVGA3dTextureFilter */
768 SVGA3D_TS_MINFILTER = 12, /* SVGA3dTextureFilter */
769 SVGA3D_TS_BORDERCOLOR = 13, /* SVGA3dColor */
770 SVGA3D_TS_TEXCOORDINDEX = 14, /* uint32 */
771 SVGA3D_TS_TEXTURETRANSFORMFLAGS = 15, /* SVGA3dTexTransformFlags */
772 SVGA3D_TS_TEXCOORDGEN = 16, /* SVGA3dTextureCoordGen */
773 SVGA3D_TS_BUMPENVMAT00 = 17, /* float */
774 SVGA3D_TS_BUMPENVMAT01 = 18, /* float */
775 SVGA3D_TS_BUMPENVMAT10 = 19, /* float */
776 SVGA3D_TS_BUMPENVMAT11 = 20, /* float */
777 SVGA3D_TS_TEXTURE_MIPMAP_LEVEL = 21, /* uint32 */
778 SVGA3D_TS_TEXTURE_LOD_BIAS = 22, /* float */
779 SVGA3D_TS_TEXTURE_ANISOTROPIC_LEVEL = 23, /* uint32 */
780 SVGA3D_TS_ADDRESSW = 24, /* SVGA3dTextureAddress */
781
782
783 /*
784 * Sampler Gamma Level
785 *
786 * Sampler gamma effects the color of samples taken from the sampler. A
787 * value of 1.0 will produce linear samples. If the value is <= 0.0 the
788 * gamma value is ignored and a linear space is used.
789 */
790
791 SVGA3D_TS_GAMMA = 25, /* float */
792 SVGA3D_TS_BUMPENVLSCALE = 26, /* float */
793 SVGA3D_TS_BUMPENVLOFFSET = 27, /* float */
794 SVGA3D_TS_COLORARG0 = 28, /* SVGA3dTextureArgData */
795 SVGA3D_TS_ALPHAARG0 = 29, /* SVGA3dTextureArgData */
796 SVGA3D_TS_MAX
797} SVGA3dTextureStateName;
798
799typedef enum {
800 SVGA3D_TC_INVALID = 0,
801 SVGA3D_TC_DISABLE = 1,
802 SVGA3D_TC_SELECTARG1 = 2,
803 SVGA3D_TC_SELECTARG2 = 3,
804 SVGA3D_TC_MODULATE = 4,
805 SVGA3D_TC_ADD = 5,
806 SVGA3D_TC_ADDSIGNED = 6,
807 SVGA3D_TC_SUBTRACT = 7,
808 SVGA3D_TC_BLENDTEXTUREALPHA = 8,
809 SVGA3D_TC_BLENDDIFFUSEALPHA = 9,
810 SVGA3D_TC_BLENDCURRENTALPHA = 10,
811 SVGA3D_TC_BLENDFACTORALPHA = 11,
812 SVGA3D_TC_MODULATE2X = 12,
813 SVGA3D_TC_MODULATE4X = 13,
814 SVGA3D_TC_DSDT = 14,
815 SVGA3D_TC_DOTPRODUCT3 = 15,
816 SVGA3D_TC_BLENDTEXTUREALPHAPM = 16,
817 SVGA3D_TC_ADDSIGNED2X = 17,
818 SVGA3D_TC_ADDSMOOTH = 18,
819 SVGA3D_TC_PREMODULATE = 19,
820 SVGA3D_TC_MODULATEALPHA_ADDCOLOR = 20,
821 SVGA3D_TC_MODULATECOLOR_ADDALPHA = 21,
822 SVGA3D_TC_MODULATEINVALPHA_ADDCOLOR = 22,
823 SVGA3D_TC_MODULATEINVCOLOR_ADDALPHA = 23,
824 SVGA3D_TC_BUMPENVMAPLUMINANCE = 24,
825 SVGA3D_TC_MULTIPLYADD = 25,
826 SVGA3D_TC_LERP = 26,
827 SVGA3D_TC_MAX
828} SVGA3dTextureCombiner;
829
830#define SVGA3D_TC_CAP_BIT(svga3d_tc_op) (svga3d_tc_op ? (1 << (svga3d_tc_op - 1)) : 0)
831
832typedef enum {
833 SVGA3D_TEX_ADDRESS_INVALID = 0,
834 SVGA3D_TEX_ADDRESS_WRAP = 1,
835 SVGA3D_TEX_ADDRESS_MIRROR = 2,
836 SVGA3D_TEX_ADDRESS_CLAMP = 3,
837 SVGA3D_TEX_ADDRESS_BORDER = 4,
838 SVGA3D_TEX_ADDRESS_MIRRORONCE = 5,
839 SVGA3D_TEX_ADDRESS_EDGE = 6,
840 SVGA3D_TEX_ADDRESS_MAX
841} SVGA3dTextureAddress;
842
843/*
844 * SVGA3D_TEX_FILTER_NONE as the minification filter means mipmapping is
845 * disabled, and the rasterizer should use the magnification filter instead.
846 */
847typedef enum {
848 SVGA3D_TEX_FILTER_NONE = 0,
849 SVGA3D_TEX_FILTER_NEAREST = 1,
850 SVGA3D_TEX_FILTER_LINEAR = 2,
851 SVGA3D_TEX_FILTER_ANISOTROPIC = 3,
8d3713ea
JB		 852 SVGA3D_TEX_FILTER_FLATCUBIC = 4, /* Deprecated, not implemented */
853 SVGA3D_TEX_FILTER_GAUSSIANCUBIC = 5, /* Deprecated, not implemented */
854 SVGA3D_TEX_FILTER_PYRAMIDALQUAD = 6, /* Not currently implemented */
855 SVGA3D_TEX_FILTER_GAUSSIANQUAD = 7, /* Not currently implemented */
632f6117
JB		 856 SVGA3D_TEX_FILTER_MAX
857} SVGA3dTextureFilter;
858
859typedef enum {
860 SVGA3D_TEX_TRANSFORM_OFF = 0,
861 SVGA3D_TEX_TRANSFORM_S = (1 << 0),
862 SVGA3D_TEX_TRANSFORM_T = (1 << 1),
863 SVGA3D_TEX_TRANSFORM_R = (1 << 2),
864 SVGA3D_TEX_TRANSFORM_Q = (1 << 3),
865 SVGA3D_TEX_PROJECTED = (1 << 15),
866} SVGA3dTexTransformFlags;
867
868typedef enum {
869 SVGA3D_TEXCOORD_GEN_OFF = 0,
870 SVGA3D_TEXCOORD_GEN_EYE_POSITION = 1,
871 SVGA3D_TEXCOORD_GEN_EYE_NORMAL = 2,
872 SVGA3D_TEXCOORD_GEN_REFLECTIONVECTOR = 3,
873 SVGA3D_TEXCOORD_GEN_SPHERE = 4,
874 SVGA3D_TEXCOORD_GEN_MAX
875} SVGA3dTextureCoordGen;
876
877/*
878 * Texture argument constants for texture combiner
879 */
880typedef enum {
881 SVGA3D_TA_INVALID = 0,
882 SVGA3D_TA_CONSTANT = 1,
883 SVGA3D_TA_PREVIOUS = 2,
884 SVGA3D_TA_DIFFUSE = 3,
885 SVGA3D_TA_TEXTURE = 4,
886 SVGA3D_TA_SPECULAR = 5,
887 SVGA3D_TA_MAX
888} SVGA3dTextureArgData;
889
890#define SVGA3D_TM_MASK_LEN 4
891
892/* Modifiers for texture argument constants defined above. */
893typedef enum {
894 SVGA3D_TM_NONE = 0,
895 SVGA3D_TM_ALPHA = (1 << SVGA3D_TM_MASK_LEN),
896 SVGA3D_TM_ONE_MINUS = (2 << SVGA3D_TM_MASK_LEN),
897} SVGA3dTextureArgModifier;
898
899#define SVGA3D_INVALID_ID ((uint32)-1)
900#define SVGA3D_MAX_CLIP_PLANES 6
901
902/*
903 * This is the limit to the number of fixed-function texture
904 * transforms and texture coordinates we can support. It does *not*
905 * correspond to the number of texture image units (samplers) we
906 * support!
907 */
908#define SVGA3D_MAX_TEXTURE_COORDS 8
909
910/*
911 * Vertex declarations
912 *
913 * Notes:
914 *
915 * SVGA3D_DECLUSAGE_POSITIONT is for pre-transformed vertices. If you
916 * draw with any POSITIONT vertex arrays, the programmable vertex
917 * pipeline will be implicitly disabled. Drawing will take place as if
918 * no vertex shader was bound.
919 */
920
921typedef enum {
922 SVGA3D_DECLUSAGE_POSITION = 0,
8d3713ea
JB		 923 SVGA3D_DECLUSAGE_BLENDWEIGHT, /* 1 */
924 SVGA3D_DECLUSAGE_BLENDINDICES, /* 2 */
925 SVGA3D_DECLUSAGE_NORMAL, /* 3 */
926 SVGA3D_DECLUSAGE_PSIZE, /* 4 */
927 SVGA3D_DECLUSAGE_TEXCOORD, /* 5 */
928 SVGA3D_DECLUSAGE_TANGENT, /* 6 */
929 SVGA3D_DECLUSAGE_BINORMAL, /* 7 */
930 SVGA3D_DECLUSAGE_TESSFACTOR, /* 8 */
931 SVGA3D_DECLUSAGE_POSITIONT, /* 9 */
932 SVGA3D_DECLUSAGE_COLOR, /* 10 */
933 SVGA3D_DECLUSAGE_FOG, /* 11 */
934 SVGA3D_DECLUSAGE_DEPTH, /* 12 */
935 SVGA3D_DECLUSAGE_SAMPLE, /* 13 */
632f6117
JB		 936 SVGA3D_DECLUSAGE_MAX
937} SVGA3dDeclUsage;
938
939typedef enum {
940 SVGA3D_DECLMETHOD_DEFAULT = 0,
941 SVGA3D_DECLMETHOD_PARTIALU,
942 SVGA3D_DECLMETHOD_PARTIALV,
8d3713ea 943 SVGA3D_DECLMETHOD_CROSSUV, /* Normal */
632f6117 944 SVGA3D_DECLMETHOD_UV,
8d3713ea
JB		 945 SVGA3D_DECLMETHOD_LOOKUP, /* Lookup a displacement map */
946 SVGA3D_DECLMETHOD_LOOKUPPRESAMPLED, /* Lookup a pre-sampled displacement map */
632f6117
JB		 947} SVGA3dDeclMethod;
948
949typedef enum {
950 SVGA3D_DECLTYPE_FLOAT1 = 0,
951 SVGA3D_DECLTYPE_FLOAT2 = 1,
952 SVGA3D_DECLTYPE_FLOAT3 = 2,
953 SVGA3D_DECLTYPE_FLOAT4 = 3,
954 SVGA3D_DECLTYPE_D3DCOLOR = 4,
955 SVGA3D_DECLTYPE_UBYTE4 = 5,
956 SVGA3D_DECLTYPE_SHORT2 = 6,
957 SVGA3D_DECLTYPE_SHORT4 = 7,
958 SVGA3D_DECLTYPE_UBYTE4N = 8,
959 SVGA3D_DECLTYPE_SHORT2N = 9,
960 SVGA3D_DECLTYPE_SHORT4N = 10,
961 SVGA3D_DECLTYPE_USHORT2N = 11,
962 SVGA3D_DECLTYPE_USHORT4N = 12,
963 SVGA3D_DECLTYPE_UDEC3 = 13,
964 SVGA3D_DECLTYPE_DEC3N = 14,
965 SVGA3D_DECLTYPE_FLOAT16_2 = 15,
966 SVGA3D_DECLTYPE_FLOAT16_4 = 16,
967 SVGA3D_DECLTYPE_MAX,
968} SVGA3dDeclType;
969
970/*
971 * This structure is used for the divisor for geometry instancing;
972 * it's a direct translation of the Direct3D equivalent.
973 */
974typedef union {
975 struct {
976 /*
977 * For index data, this number represents the number of instances to draw.
978 * For instance data, this number represents the number of
979 * instances/vertex in this stream
980 */
981 uint32 count : 30;
982
983 /*
984 * This is 1 if this is supposed to be the data that is repeated for
985 * every instance.
986 */
987 uint32 indexedData : 1;
988
989 /*
990 * This is 1 if this is supposed to be the per-instance data.
991 */
992 uint32 instanceData : 1;
993 };
994
995 uint32 value;
996} SVGA3dVertexDivisor;
997
998typedef enum {
999 SVGA3D_PRIMITIVE_INVALID = 0,
1000 SVGA3D_PRIMITIVE_TRIANGLELIST = 1,
1001 SVGA3D_PRIMITIVE_POINTLIST = 2,
1002 SVGA3D_PRIMITIVE_LINELIST = 3,
1003 SVGA3D_PRIMITIVE_LINESTRIP = 4,
1004 SVGA3D_PRIMITIVE_TRIANGLESTRIP = 5,
1005 SVGA3D_PRIMITIVE_TRIANGLEFAN = 6,
1006 SVGA3D_PRIMITIVE_MAX
1007} SVGA3dPrimitiveType;
1008
1009typedef enum {
1010 SVGA3D_COORDINATE_INVALID = 0,
1011 SVGA3D_COORDINATE_LEFTHANDED = 1,
1012 SVGA3D_COORDINATE_RIGHTHANDED = 2,
1013 SVGA3D_COORDINATE_MAX
1014} SVGA3dCoordinateType;
1015
1016typedef enum {
1017 SVGA3D_TRANSFORM_INVALID = 0,
1018 SVGA3D_TRANSFORM_WORLD = 1,
1019 SVGA3D_TRANSFORM_VIEW = 2,
1020 SVGA3D_TRANSFORM_PROJECTION = 3,
1021 SVGA3D_TRANSFORM_TEXTURE0 = 4,
1022 SVGA3D_TRANSFORM_TEXTURE1 = 5,
1023 SVGA3D_TRANSFORM_TEXTURE2 = 6,
1024 SVGA3D_TRANSFORM_TEXTURE3 = 7,
1025 SVGA3D_TRANSFORM_TEXTURE4 = 8,
1026 SVGA3D_TRANSFORM_TEXTURE5 = 9,
1027 SVGA3D_TRANSFORM_TEXTURE6 = 10,
1028 SVGA3D_TRANSFORM_TEXTURE7 = 11,
1029 SVGA3D_TRANSFORM_WORLD1 = 12,
1030 SVGA3D_TRANSFORM_WORLD2 = 13,
1031 SVGA3D_TRANSFORM_WORLD3 = 14,
1032 SVGA3D_TRANSFORM_MAX
1033} SVGA3dTransformType;
1034
1035typedef enum {
1036 SVGA3D_LIGHTTYPE_INVALID = 0,
1037 SVGA3D_LIGHTTYPE_POINT = 1,
1038 SVGA3D_LIGHTTYPE_SPOT1 = 2, /* 1-cone, in degrees */
1039 SVGA3D_LIGHTTYPE_SPOT2 = 3, /* 2-cone, in radians */
1040 SVGA3D_LIGHTTYPE_DIRECTIONAL = 4,
1041 SVGA3D_LIGHTTYPE_MAX
1042} SVGA3dLightType;
1043
1044typedef enum {
1045 SVGA3D_CUBEFACE_POSX = 0,
1046 SVGA3D_CUBEFACE_NEGX = 1,
1047 SVGA3D_CUBEFACE_POSY = 2,
1048 SVGA3D_CUBEFACE_NEGY = 3,
1049 SVGA3D_CUBEFACE_POSZ = 4,
1050 SVGA3D_CUBEFACE_NEGZ = 5,
1051} SVGA3dCubeFace;
1052
1053typedef enum {
d9019498
TH		 1054 SVGA3D_SHADERTYPE_INVALID = 0,
1055 SVGA3D_SHADERTYPE_MIN = 1,
632f6117
JB		 1056 SVGA3D_SHADERTYPE_VS = 1,
1057 SVGA3D_SHADERTYPE_PS = 2,
d9019498
TH		 1058 SVGA3D_SHADERTYPE_MAX = 3,
1059 SVGA3D_SHADERTYPE_GS = 3,
632f6117
JB		 1060} SVGA3dShaderType;
1061
d9019498
TH		 1062#define SVGA3D_NUM_SHADERTYPE (SVGA3D_SHADERTYPE_MAX - SVGA3D_SHADERTYPE_MIN)
1063
632f6117
JB		 1064typedef enum {
1065 SVGA3D_CONST_TYPE_FLOAT = 0,
1066 SVGA3D_CONST_TYPE_INT = 1,
1067 SVGA3D_CONST_TYPE_BOOL = 2,
d9019498 1068 SVGA3D_CONST_TYPE_MAX
632f6117
JB		 1069} SVGA3dShaderConstType;
1070
1071#define SVGA3D_MAX_SURFACE_FACES 6
1072
1073typedef enum {
1074 SVGA3D_STRETCH_BLT_POINT = 0,
1075 SVGA3D_STRETCH_BLT_LINEAR = 1,
1076 SVGA3D_STRETCH_BLT_MAX
1077} SVGA3dStretchBltMode;
1078
1079typedef enum {
1080 SVGA3D_QUERYTYPE_OCCLUSION = 0,
1081 SVGA3D_QUERYTYPE_MAX
1082} SVGA3dQueryType;
1083
1084typedef enum {
1085 SVGA3D_QUERYSTATE_PENDING = 0, /* Waiting on the host (set by guest) */
1086 SVGA3D_QUERYSTATE_SUCCEEDED = 1, /* Completed successfully (set by host) */
1087 SVGA3D_QUERYSTATE_FAILED = 2, /* Completed unsuccessfully (set by host) */
1088 SVGA3D_QUERYSTATE_NEW = 3, /* Never submitted (For guest use only) */
1089} SVGA3dQueryState;
1090
1091typedef enum {
1092 SVGA3D_WRITE_HOST_VRAM = 1,
1093 SVGA3D_READ_HOST_VRAM = 2,
1094} SVGA3dTransferType;
1095
1096/*
8d3713ea 1097 * The maximum number of vertex arrays we're guaranteed to support in
632f6117
JB		 1098 * SVGA_3D_CMD_DRAWPRIMITIVES.
1099 */
1100#define SVGA3D_MAX_VERTEX_ARRAYS 32
1101
8d3713ea
JB		 1102/*
1103 * The maximum number of primitive ranges we're guaranteed to support
1104 * in SVGA_3D_CMD_DRAWPRIMITIVES.
1105 */
1106#define SVGA3D_MAX_DRAW_PRIMITIVE_RANGES 32
1107
632f6117
JB		 1108/*
1109 * Identifiers for commands in the command FIFO.
1110 *
1111 * IDs between 1000 and 1039 (inclusive) were used by obsolete versions of
1112 * the SVGA3D protocol and remain reserved; they should not be used in the
1113 * future.
1114 *
1115 * IDs between 1040 and 1999 (inclusive) are available for use by the
1116 * current SVGA3D protocol.
1117 *
1118 * FIFO clients other than SVGA3D should stay below 1000, or at 2000
1119 * and up.
1120 */
1121
1122#define SVGA_3D_CMD_LEGACY_BASE 1000
1123#define SVGA_3D_CMD_BASE 1040
1124
8d3713ea 1125#define SVGA_3D_CMD_SURFACE_DEFINE SVGA_3D_CMD_BASE + 0 /* Deprecated */
632f6117
JB		 1126#define SVGA_3D_CMD_SURFACE_DESTROY SVGA_3D_CMD_BASE + 1
1127#define SVGA_3D_CMD_SURFACE_COPY SVGA_3D_CMD_BASE + 2
1128#define SVGA_3D_CMD_SURFACE_STRETCHBLT SVGA_3D_CMD_BASE + 3
1129#define SVGA_3D_CMD_SURFACE_DMA SVGA_3D_CMD_BASE + 4
1130#define SVGA_3D_CMD_CONTEXT_DEFINE SVGA_3D_CMD_BASE + 5
1131#define SVGA_3D_CMD_CONTEXT_DESTROY SVGA_3D_CMD_BASE + 6
1132#define SVGA_3D_CMD_SETTRANSFORM SVGA_3D_CMD_BASE + 7
1133#define SVGA_3D_CMD_SETZRANGE SVGA_3D_CMD_BASE + 8
1134#define SVGA_3D_CMD_SETRENDERSTATE SVGA_3D_CMD_BASE + 9
1135#define SVGA_3D_CMD_SETRENDERTARGET SVGA_3D_CMD_BASE + 10
1136#define SVGA_3D_CMD_SETTEXTURESTATE SVGA_3D_CMD_BASE + 11
1137#define SVGA_3D_CMD_SETMATERIAL SVGA_3D_CMD_BASE + 12
1138#define SVGA_3D_CMD_SETLIGHTDATA SVGA_3D_CMD_BASE + 13
1139#define SVGA_3D_CMD_SETLIGHTENABLED SVGA_3D_CMD_BASE + 14
1140#define SVGA_3D_CMD_SETVIEWPORT SVGA_3D_CMD_BASE + 15
1141#define SVGA_3D_CMD_SETCLIPPLANE SVGA_3D_CMD_BASE + 16
1142#define SVGA_3D_CMD_CLEAR SVGA_3D_CMD_BASE + 17
8d3713ea 1143#define SVGA_3D_CMD_PRESENT SVGA_3D_CMD_BASE + 18 /* Deprecated */
632f6117
JB		 1144#define SVGA_3D_CMD_SHADER_DEFINE SVGA_3D_CMD_BASE + 19
1145#define SVGA_3D_CMD_SHADER_DESTROY SVGA_3D_CMD_BASE + 20
1146#define SVGA_3D_CMD_SET_SHADER SVGA_3D_CMD_BASE + 21
1147#define SVGA_3D_CMD_SET_SHADER_CONST SVGA_3D_CMD_BASE + 22
1148#define SVGA_3D_CMD_DRAW_PRIMITIVES SVGA_3D_CMD_BASE + 23
1149#define SVGA_3D_CMD_SETSCISSORRECT SVGA_3D_CMD_BASE + 24
1150#define SVGA_3D_CMD_BEGIN_QUERY SVGA_3D_CMD_BASE + 25
1151#define SVGA_3D_CMD_END_QUERY SVGA_3D_CMD_BASE + 26
1152#define SVGA_3D_CMD_WAIT_FOR_QUERY SVGA_3D_CMD_BASE + 27
8d3713ea 1153#define SVGA_3D_CMD_PRESENT_READBACK SVGA_3D_CMD_BASE + 28 /* Deprecated */
632f6117 1154#define SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN SVGA_3D_CMD_BASE + 29
8d3713ea
JB		 1155#define SVGA_3D_CMD_SURFACE_DEFINE_V2 SVGA_3D_CMD_BASE + 30
1156#define SVGA_3D_CMD_GENERATE_MIPMAPS SVGA_3D_CMD_BASE + 31
1157#define SVGA_3D_CMD_ACTIVATE_SURFACE SVGA_3D_CMD_BASE + 40
1158#define SVGA_3D_CMD_DEACTIVATE_SURFACE SVGA_3D_CMD_BASE + 41
d9019498
TH		 1159#define SVGA_3D_CMD_SCREEN_DMA 1082
1160#define SVGA_3D_CMD_SET_UNITY_SURFACE_COOKIE 1083
1161#define SVGA_3D_CMD_OPEN_CONTEXT_SURFACE 1084
1162
1163#define SVGA_3D_CMD_LOGICOPS_BITBLT 1085
1164#define SVGA_3D_CMD_LOGICOPS_TRANSBLT 1086
1165#define SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1087
1166#define SVGA_3D_CMD_LOGICOPS_COLORFILL 1088
1167#define SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1089
1168#define SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1090
1169
1170#define SVGA_3D_CMD_SET_OTABLE_BASE 1091
1171#define SVGA_3D_CMD_READBACK_OTABLE 1092
1172
1173#define SVGA_3D_CMD_DEFINE_GB_MOB 1093
1174#define SVGA_3D_CMD_DESTROY_GB_MOB 1094
1175#define SVGA_3D_CMD_REDEFINE_GB_MOB 1095
1176#define SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING 1096
1177
1178#define SVGA_3D_CMD_DEFINE_GB_SURFACE 1097
1179#define SVGA_3D_CMD_DESTROY_GB_SURFACE 1098
1180#define SVGA_3D_CMD_BIND_GB_SURFACE 1099
1181#define SVGA_3D_CMD_COND_BIND_GB_SURFACE 1100
1182#define SVGA_3D_CMD_UPDATE_GB_IMAGE 1101
1183#define SVGA_3D_CMD_UPDATE_GB_SURFACE 1102
1184#define SVGA_3D_CMD_READBACK_GB_IMAGE 1103
1185#define SVGA_3D_CMD_READBACK_GB_SURFACE 1104
1186#define SVGA_3D_CMD_INVALIDATE_GB_IMAGE 1105
1187#define SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106
1188
1189#define SVGA_3D_CMD_DEFINE_GB_CONTEXT 1107
1190#define SVGA_3D_CMD_DESTROY_GB_CONTEXT 1108
1191#define SVGA_3D_CMD_BIND_GB_CONTEXT 1109
1192#define SVGA_3D_CMD_READBACK_GB_CONTEXT 1110
1193#define SVGA_3D_CMD_INVALIDATE_GB_CONTEXT 1111
1194
1195#define SVGA_3D_CMD_DEFINE_GB_SHADER 1112
1196#define SVGA_3D_CMD_DESTROY_GB_SHADER 1113
1197#define SVGA_3D_CMD_BIND_GB_SHADER 1114
1198
f2a0dcb1 1199#define SVGA_3D_CMD_SET_OTABLE_BASE64 1115
d9019498
TH		 1200
1201#define SVGA_3D_CMD_BEGIN_GB_QUERY 1116
1202#define SVGA_3D_CMD_END_GB_QUERY 1117
1203#define SVGA_3D_CMD_WAIT_FOR_GB_QUERY 1118
1204
1205#define SVGA_3D_CMD_NOP 1119
1206
1207#define SVGA_3D_CMD_ENABLE_GART 1120
1208#define SVGA_3D_CMD_DISABLE_GART 1121
1209#define SVGA_3D_CMD_MAP_MOB_INTO_GART 1122
1210#define SVGA_3D_CMD_UNMAP_GART_RANGE 1123
1211
1212#define SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124
1213#define SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125
1214#define SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126
1215#define SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127
1216
1217#define SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL 1128
1218#define SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL 1129
1219
1220#define SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE 1130
36e952c1
TH		 1221#define SVGA_3D_CMD_GB_SCREEN_DMA 1131
1222#define SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH 1132
1223#define SVGA_3D_CMD_GB_MOB_FENCE 1133
1224#define SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134
f2a0dcb1
TH		 1225#define SVGA_3D_CMD_DEFINE_GB_MOB64 1135
1226#define SVGA_3D_CMD_REDEFINE_GB_MOB64 1136
36e952c1
TH		 1227#define SVGA_3D_CMD_NOP_ERROR 1137
1228
1229#define SVGA_3D_CMD_RESERVED1 1138
1230#define SVGA_3D_CMD_RESERVED2 1139
1231#define SVGA_3D_CMD_RESERVED3 1140
1232#define SVGA_3D_CMD_RESERVED4 1141
1233#define SVGA_3D_CMD_RESERVED5 1142
f2a0dcb1
TH		 1234
1235#define SVGA_3D_CMD_MAX 1142
d9019498 1236#define SVGA_3D_CMD_FUTURE_MAX 3000
632f6117
JB		 1237
1238/*
1239 * Common substructures used in multiple FIFO commands:
1240 */
1241
1242typedef struct {
1243 union {
1244 struct {
8d3713ea
JB		 1245 uint16 function; /* SVGA3dFogFunction */
1246 uint8 type; /* SVGA3dFogType */
1247 uint8 base; /* SVGA3dFogBase */
632f6117
JB		 1248 };
1249 uint32 uintValue;
1250 };
1251} SVGA3dFogMode;
1252
1253/*
1254 * Uniquely identify one image (a 1D/2D/3D array) from a surface. This
1255 * is a surface ID as well as face/mipmap indices.
1256 */
1257
1258typedef
1259struct SVGA3dSurfaceImageId {
1260 uint32 sid;
1261 uint32 face;
1262 uint32 mipmap;
1263} SVGA3dSurfaceImageId;
1264
1265typedef
1266struct SVGA3dGuestImage {
1267 SVGAGuestPtr ptr;
1268
1269 /*
1270 * A note on interpretation of pitch: This value of pitch is the
1271 * number of bytes between vertically adjacent image
1272 * blocks. Normally this is the number of bytes between the first
1273 * pixel of two adjacent scanlines. With compressed textures,
1274 * however, this may represent the number of bytes between
1275 * compression blocks rather than between rows of pixels.
1276 *
1277 * XXX: Compressed textures currently must be tightly packed in guest memory.
1278 *
1279 * If the image is 1-dimensional, pitch is ignored.
1280 *
1281 * If 'pitch' is zero, the SVGA3D device calculates a pitch value
1282 * assuming each row of blocks is tightly packed.
1283 */
1284 uint32 pitch;
1285} SVGA3dGuestImage;
1286
1287
1288/*
1289 * FIFO command format definitions:
1290 */
1291
1292/*
1293 * The data size header following cmdNum for every 3d command
1294 */
1295typedef
1296struct {
1297 uint32 id;
1298 uint32 size;
1299} SVGA3dCmdHeader;
1300
1301/*
1302 * A surface is a hierarchy of host VRAM surfaces: 1D, 2D, or 3D, with
1303 * optional mipmaps and cube faces.
1304 */
1305
1306typedef
1307struct {
1308 uint32 width;
1309 uint32 height;
1310 uint32 depth;
1311} SVGA3dSize;
1312
1313typedef enum {
1314 SVGA3D_SURFACE_CUBEMAP = (1 << 0),
1315 SVGA3D_SURFACE_HINT_STATIC = (1 << 1),
1316 SVGA3D_SURFACE_HINT_DYNAMIC = (1 << 2),
1317 SVGA3D_SURFACE_HINT_INDEXBUFFER = (1 << 3),
1318 SVGA3D_SURFACE_HINT_VERTEXBUFFER = (1 << 4),
1319 SVGA3D_SURFACE_HINT_TEXTURE = (1 << 5),
1320 SVGA3D_SURFACE_HINT_RENDERTARGET = (1 << 6),
1321 SVGA3D_SURFACE_HINT_DEPTHSTENCIL = (1 << 7),
1322 SVGA3D_SURFACE_HINT_WRITEONLY = (1 << 8),
8d3713ea
JB		 1323 SVGA3D_SURFACE_MASKABLE_ANTIALIAS = (1 << 9),
1324 SVGA3D_SURFACE_AUTOGENMIPMAPS = (1 << 10),
632f6117
JB		 1325} SVGA3dSurfaceFlags;
1326
1327typedef
1328struct {
1329 uint32 numMipLevels;
1330} SVGA3dSurfaceFace;
1331
1332typedef
1333struct {
1334 uint32 sid;
1335 SVGA3dSurfaceFlags surfaceFlags;
1336 SVGA3dSurfaceFormat format;
8d3713ea
JB		 1337 /*
1338 * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
1339 * structures must have the same value of numMipLevels field.
1340 * Otherwise, all but the first SVGA3dSurfaceFace structures must have the
1341 * numMipLevels set to 0.
1342 */
632f6117
JB		 1343 SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
1344 /*
1345 * Followed by an SVGA3dSize structure for each mip level in each face.
1346 *
1347 * A note on surface sizes: Sizes are always specified in pixels,
1348 * even if the true surface size is not a multiple of the minimum
1349 * block size of the surface's format. For example, a 3x3x1 DXT1
1350 * compressed texture would actually be stored as a 4x4x1 image in
1351 * memory.
1352 */
1353} SVGA3dCmdDefineSurface; /* SVGA_3D_CMD_SURFACE_DEFINE */
1354
8d3713ea
JB		 1355typedef
1356struct {
1357 uint32 sid;
1358 SVGA3dSurfaceFlags surfaceFlags;
1359 SVGA3dSurfaceFormat format;
1360 /*
1361 * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
1362 * structures must have the same value of numMipLevels field.
1363 * Otherwise, all but the first SVGA3dSurfaceFace structures must have the
1364 * numMipLevels set to 0.
1365 */
1366 SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
1367 uint32 multisampleCount;
1368 SVGA3dTextureFilter autogenFilter;
1369 /*
1370 * Followed by an SVGA3dSize structure for each mip level in each face.
1371 *
1372 * A note on surface sizes: Sizes are always specified in pixels,
1373 * even if the true surface size is not a multiple of the minimum
1374 * block size of the surface's format. For example, a 3x3x1 DXT1
1375 * compressed texture would actually be stored as a 4x4x1 image in
1376 * memory.
1377 */
1378} SVGA3dCmdDefineSurface_v2; /* SVGA_3D_CMD_SURFACE_DEFINE_V2 */
1379
632f6117
JB		 1380typedef
1381struct {
1382 uint32 sid;
1383} SVGA3dCmdDestroySurface; /* SVGA_3D_CMD_SURFACE_DESTROY */
1384
1385typedef
1386struct {
1387 uint32 cid;
1388} SVGA3dCmdDefineContext; /* SVGA_3D_CMD_CONTEXT_DEFINE */
1389
1390typedef
1391struct {
1392 uint32 cid;
1393} SVGA3dCmdDestroyContext; /* SVGA_3D_CMD_CONTEXT_DESTROY */
1394
1395typedef
1396struct {
1397 uint32 cid;
1398 SVGA3dClearFlag clearFlag;
1399 uint32 color;
1400 float depth;
1401 uint32 stencil;
1402 /* Followed by variable number of SVGA3dRect structures */
1403} SVGA3dCmdClear; /* SVGA_3D_CMD_CLEAR */
1404
1405typedef
1406struct SVGA3dCopyRect {
1407 uint32 x;
1408 uint32 y;
1409 uint32 w;
1410 uint32 h;
1411 uint32 srcx;
1412 uint32 srcy;
1413} SVGA3dCopyRect;
1414
1415typedef
1416struct SVGA3dCopyBox {
1417 uint32 x;
1418 uint32 y;
1419 uint32 z;
1420 uint32 w;
1421 uint32 h;
1422 uint32 d;
1423 uint32 srcx;
1424 uint32 srcy;
1425 uint32 srcz;
1426} SVGA3dCopyBox;
1427
1428typedef
1429struct {
1430 uint32 x;
1431 uint32 y;
1432 uint32 w;
1433 uint32 h;
1434} SVGA3dRect;
1435
1436typedef
1437struct {
1438 uint32 x;
1439 uint32 y;
1440 uint32 z;
1441 uint32 w;
1442 uint32 h;
1443 uint32 d;
1444} SVGA3dBox;
1445
1446typedef
1447struct {
1448 uint32 x;
1449 uint32 y;
1450 uint32 z;
1451} SVGA3dPoint;
1452
1453typedef
1454struct {
1455 SVGA3dLightType type;
1456 SVGA3dBool inWorldSpace;
1457 float diffuse[4];
1458 float specular[4];
1459 float ambient[4];
1460 float position[4];
1461 float direction[4];
1462 float range;
1463 float falloff;
1464 float attenuation0;
1465 float attenuation1;
1466 float attenuation2;
1467 float theta;
1468 float phi;
1469} SVGA3dLightData;
1470
1471typedef
1472struct {
1473 uint32 sid;
1474 /* Followed by variable number of SVGA3dCopyRect structures */
1475} SVGA3dCmdPresent; /* SVGA_3D_CMD_PRESENT */
1476
1477typedef
1478struct {
1479 SVGA3dRenderStateName state;
1480 union {
1481 uint32 uintValue;
1482 float floatValue;
1483 };
1484} SVGA3dRenderState;
1485
1486typedef
1487struct {
1488 uint32 cid;
1489 /* Followed by variable number of SVGA3dRenderState structures */
1490} SVGA3dCmdSetRenderState; /* SVGA_3D_CMD_SETRENDERSTATE */
1491
1492typedef
1493struct {
1494 uint32 cid;
1495 SVGA3dRenderTargetType type;
1496 SVGA3dSurfaceImageId target;
1497} SVGA3dCmdSetRenderTarget; /* SVGA_3D_CMD_SETRENDERTARGET */
1498
1499typedef
1500struct {
1501 SVGA3dSurfaceImageId src;
1502 SVGA3dSurfaceImageId dest;
1503 /* Followed by variable number of SVGA3dCopyBox structures */
1504} SVGA3dCmdSurfaceCopy; /* SVGA_3D_CMD_SURFACE_COPY */
1505
1506typedef
1507struct {
1508 SVGA3dSurfaceImageId src;
1509 SVGA3dSurfaceImageId dest;
1510 SVGA3dBox boxSrc;
1511 SVGA3dBox boxDest;
1512 SVGA3dStretchBltMode mode;
1513} SVGA3dCmdSurfaceStretchBlt; /* SVGA_3D_CMD_SURFACE_STRETCHBLT */
1514
1515typedef
1516struct {
1517 /*
1518 * If the discard flag is present in a surface DMA operation, the host may
1519 * discard the contents of the current mipmap level and face of the target
1520 * surface before applying the surface DMA contents.
1521 */
1522 uint32 discard : 1;
1523
1524 /*
1525 * If the unsynchronized flag is present, the host may perform this upload
1526 * without syncing to pending reads on this surface.
1527 */
1528 uint32 unsynchronized : 1;
1529
1530 /*
1531 * Guests *MUST* set the reserved bits to 0 before submitting the command
1532 * suffix as future flags may occupy these bits.
1533 */
1534 uint32 reserved : 30;
1535} SVGA3dSurfaceDMAFlags;
1536
1537typedef
1538struct {
1539 SVGA3dGuestImage guest;
1540 SVGA3dSurfaceImageId host;
1541 SVGA3dTransferType transfer;
1542 /*
1543 * Followed by variable number of SVGA3dCopyBox structures. For consistency
1544 * in all clipping logic and coordinate translation, we define the
1545 * "source" in each copyBox as the guest image and the
1546 * "destination" as the host image, regardless of transfer
1547 * direction.
1548 *
1549 * For efficiency, the SVGA3D device is free to copy more data than
1550 * specified. For example, it may round copy boxes outwards such
1551 * that they lie on particular alignment boundaries.
1552 */
1553} SVGA3dCmdSurfaceDMA; /* SVGA_3D_CMD_SURFACE_DMA */
1554
1555/*
1556 * SVGA3dCmdSurfaceDMASuffix --
1557 *
1558 * This is a command suffix that will appear after a SurfaceDMA command in
1559 * the FIFO. It contains some extra information that hosts may use to
1560 * optimize performance or protect the guest. This suffix exists to preserve
1561 * backwards compatibility while also allowing for new functionality to be
1562 * implemented.
1563 */
1564
1565typedef
1566struct {
1567 uint32 suffixSize;
1568
1569 /*
1570 * The maximum offset is used to determine the maximum offset from the
1571 * guestPtr base address that will be accessed or written to during this
1572 * surfaceDMA. If the suffix is supported, the host will respect this
1573 * boundary while performing surface DMAs.
1574 *
1575 * Defaults to MAX_UINT32
1576 */
1577 uint32 maximumOffset;
1578
1579 /*
1580 * A set of flags that describes optimizations that the host may perform
1581 * while performing this surface DMA operation. The guest should never rely
1582 * on behaviour that is different when these flags are set for correctness.
1583 *
1584 * Defaults to 0
1585 */
1586 SVGA3dSurfaceDMAFlags flags;
1587} SVGA3dCmdSurfaceDMASuffix;
1588
1589/*
1590 * SVGA_3D_CMD_DRAW_PRIMITIVES --
1591 *
1592 * This command is the SVGA3D device's generic drawing entry point.
1593 * It can draw multiple ranges of primitives, optionally using an
1594 * index buffer, using an arbitrary collection of vertex buffers.
1595 *
1596 * Each SVGA3dVertexDecl defines a distinct vertex array to bind
1597 * during this draw call. The declarations specify which surface
1598 * the vertex data lives in, what that vertex data is used for,
1599 * and how to interpret it.
1600 *
1601 * Each SVGA3dPrimitiveRange defines a collection of primitives
1602 * to render using the same vertex arrays. An index buffer is
1603 * optional.
1604 */
1605
1606typedef
1607struct {
1608 /*
1609 * A range hint is an optional specification for the range of indices
1610 * in an SVGA3dArray that will be used. If 'last' is zero, it is assumed
1611 * that the entire array will be used.
1612 *
1613 * These are only hints. The SVGA3D device may use them for
1614 * performance optimization if possible, but it's also allowed to
1615 * ignore these values.
1616 */
1617 uint32 first;
1618 uint32 last;
1619} SVGA3dArrayRangeHint;
1620
1621typedef
1622struct {
1623 /*
1624 * Define the origin and shape of a vertex or index array. Both
1625 * 'offset' and 'stride' are in bytes. The provided surface will be
1626 * reinterpreted as a flat array of bytes in the same format used
1627 * by surface DMA operations. To avoid unnecessary conversions, the
1628 * surface should be created with the SVGA3D_BUFFER format.
1629 *
1630 * Index 0 in the array starts 'offset' bytes into the surface.
1631 * Index 1 begins at byte 'offset + stride', etc. Array indices may
1632 * not be negative.
1633 */
1634 uint32 surfaceId;
1635 uint32 offset;
1636 uint32 stride;
1637} SVGA3dArray;
1638
1639typedef
1640struct {
1641 /*
1642 * Describe a vertex array's data type, and define how it is to be
1643 * used by the fixed function pipeline or the vertex shader. It
1644 * isn't useful to have two VertexDecls with the same
1645 * VertexArrayIdentity in one draw call.
1646 */
1647 SVGA3dDeclType type;
1648 SVGA3dDeclMethod method;
1649 SVGA3dDeclUsage usage;
1650 uint32 usageIndex;
1651} SVGA3dVertexArrayIdentity;
1652
1653typedef
1654struct {
1655 SVGA3dVertexArrayIdentity identity;
1656 SVGA3dArray array;
1657 SVGA3dArrayRangeHint rangeHint;
1658} SVGA3dVertexDecl;
1659
1660typedef
1661struct {
1662 /*
1663 * Define a group of primitives to render, from sequential indices.
1664 *
1665 * The value of 'primitiveType' and 'primitiveCount' imply the
1666 * total number of vertices that will be rendered.
1667 */
1668 SVGA3dPrimitiveType primType;
1669 uint32 primitiveCount;
1670
1671 /*
1672 * Optional index buffer. If indexArray.surfaceId is
1673 * SVGA3D_INVALID_ID, we render without an index buffer. Rendering
1674 * without an index buffer is identical to rendering with an index
1675 * buffer containing the sequence [0, 1, 2, 3, ...].
1676 *
1677 * If an index buffer is in use, indexWidth specifies the width in
1678 * bytes of each index value. It must be less than or equal to
1679 * indexArray.stride.
1680 *
1681 * (Currently, the SVGA3D device requires index buffers to be tightly
1682 * packed. In other words, indexWidth == indexArray.stride)
1683 */
1684 SVGA3dArray indexArray;
1685 uint32 indexWidth;
1686
1687 /*
1688 * Optional index bias. This number is added to all indices from
1689 * indexArray before they are used as vertex array indices. This
1690 * can be used in multiple ways:
1691 *
1692 * - When not using an indexArray, this bias can be used to
1693 * specify where in the vertex arrays to begin rendering.
1694 *
1695 * - A positive number here is equivalent to increasing the
1696 * offset in each vertex array.
1697 *
1698 * - A negative number can be used to render using a small
1699 * vertex array and an index buffer that contains large
1700 * values. This may be used by some applications that
1701 * crop a vertex buffer without modifying their index
1702 * buffer.
1703 *
1704 * Note that rendering with a negative bias value may be slower and
1705 * use more memory than rendering with a positive or zero bias.
1706 */
1707 int32 indexBias;
1708} SVGA3dPrimitiveRange;
1709
1710typedef
1711struct {
1712 uint32 cid;
1713 uint32 numVertexDecls;
1714 uint32 numRanges;
1715
1716 /*
1717 * There are two variable size arrays after the
1718 * SVGA3dCmdDrawPrimitives structure. In order,
1719 * they are:
1720 *
8d3713ea
JB		 1721 * 1. SVGA3dVertexDecl, quantity 'numVertexDecls', but no more than
1722 * SVGA3D_MAX_VERTEX_ARRAYS;
1723 * 2. SVGA3dPrimitiveRange, quantity 'numRanges', but no more than
1724 * SVGA3D_MAX_DRAW_PRIMITIVE_RANGES;
632f6117 1725 * 3. Optionally, SVGA3dVertexDivisor, quantity 'numVertexDecls' (contains
8d3713ea 1726 * the frequency divisor for the corresponding vertex decl).
632f6117
JB		 1727 */
1728} SVGA3dCmdDrawPrimitives; /* SVGA_3D_CMD_DRAWPRIMITIVES */
1729
1730typedef
1731struct {
1732 uint32 stage;
1733 SVGA3dTextureStateName name;
1734 union {
1735 uint32 value;
1736 float floatValue;
1737 };
1738} SVGA3dTextureState;
1739
1740typedef
1741struct {
1742 uint32 cid;
1743 /* Followed by variable number of SVGA3dTextureState structures */
1744} SVGA3dCmdSetTextureState; /* SVGA_3D_CMD_SETTEXTURESTATE */
1745
1746typedef
1747struct {
1748 uint32 cid;
1749 SVGA3dTransformType type;
1750 float matrix[16];
1751} SVGA3dCmdSetTransform; /* SVGA_3D_CMD_SETTRANSFORM */
1752
1753typedef
1754struct {
1755 float min;
1756 float max;
1757} SVGA3dZRange;
1758
1759typedef
1760struct {
1761 uint32 cid;
1762 SVGA3dZRange zRange;
1763} SVGA3dCmdSetZRange; /* SVGA_3D_CMD_SETZRANGE */
1764
1765typedef
1766struct {
1767 float diffuse[4];
1768 float ambient[4];
1769 float specular[4];
1770 float emissive[4];
1771 float shininess;
1772} SVGA3dMaterial;
1773
1774typedef
1775struct {
1776 uint32 cid;
1777 SVGA3dFace face;
1778 SVGA3dMaterial material;
1779} SVGA3dCmdSetMaterial; /* SVGA_3D_CMD_SETMATERIAL */
1780
1781typedef
1782struct {
1783 uint32 cid;
1784 uint32 index;
1785 SVGA3dLightData data;
1786} SVGA3dCmdSetLightData; /* SVGA_3D_CMD_SETLIGHTDATA */
1787
1788typedef
1789struct {
1790 uint32 cid;
1791 uint32 index;
1792 uint32 enabled;
1793} SVGA3dCmdSetLightEnabled; /* SVGA_3D_CMD_SETLIGHTENABLED */
1794
1795typedef
1796struct {
1797 uint32 cid;
1798 SVGA3dRect rect;
1799} SVGA3dCmdSetViewport; /* SVGA_3D_CMD_SETVIEWPORT */
1800
1801typedef
1802struct {
1803 uint32 cid;
1804 SVGA3dRect rect;
1805} SVGA3dCmdSetScissorRect; /* SVGA_3D_CMD_SETSCISSORRECT */
1806
1807typedef
1808struct {
1809 uint32 cid;
1810 uint32 index;
1811 float plane[4];
1812} SVGA3dCmdSetClipPlane; /* SVGA_3D_CMD_SETCLIPPLANE */
1813
1814typedef
1815struct {
1816 uint32 cid;
1817 uint32 shid;
1818 SVGA3dShaderType type;
1819 /* Followed by variable number of DWORDs for shader bycode */
1820} SVGA3dCmdDefineShader; /* SVGA_3D_CMD_SHADER_DEFINE */
1821
1822typedef
1823struct {
1824 uint32 cid;
1825 uint32 shid;
1826 SVGA3dShaderType type;
1827} SVGA3dCmdDestroyShader; /* SVGA_3D_CMD_SHADER_DESTROY */
1828
1829typedef
1830struct {
1831 uint32 cid;
1832 uint32 reg; /* register number */
1833 SVGA3dShaderType type;
1834 SVGA3dShaderConstType ctype;
1835 uint32 values[4];
1836} SVGA3dCmdSetShaderConst; /* SVGA_3D_CMD_SET_SHADER_CONST */
1837
1838typedef
1839struct {
1840 uint32 cid;
1841 SVGA3dShaderType type;
1842 uint32 shid;
1843} SVGA3dCmdSetShader; /* SVGA_3D_CMD_SET_SHADER */
1844
1845typedef
1846struct {
1847 uint32 cid;
1848 SVGA3dQueryType type;
1849} SVGA3dCmdBeginQuery; /* SVGA_3D_CMD_BEGIN_QUERY */
1850
1851typedef
1852struct {
1853 uint32 cid;
1854 SVGA3dQueryType type;
1855 SVGAGuestPtr guestResult; /* Points to an SVGA3dQueryResult structure */
1856} SVGA3dCmdEndQuery; /* SVGA_3D_CMD_END_QUERY */
1857
1858typedef
1859struct {
1860 uint32 cid; /* Same parameters passed to END_QUERY */
1861 SVGA3dQueryType type;
1862 SVGAGuestPtr guestResult;
1863} SVGA3dCmdWaitForQuery; /* SVGA_3D_CMD_WAIT_FOR_QUERY */
1864
1865typedef
1866struct {
1867 uint32 totalSize; /* Set by guest before query is ended. */
1868 SVGA3dQueryState state; /* Set by host or guest. See SVGA3dQueryState. */
1869 union { /* Set by host on exit from PENDING state */
1870 uint32 result32;
1871 };
1872} SVGA3dQueryResult;
1873
1874/*
1875 * SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN --
1876 *
1877 * This is a blit from an SVGA3D surface to a Screen Object. Just
1878 * like GMR-to-screen blits, this blit may be directed at a
1879 * specific screen or to the virtual coordinate space.
1880 *
1881 * The blit copies from a rectangular region of an SVGA3D surface
1882 * image to a rectangular region of a screen or screens.
1883 *
1884 * This command takes an optional variable-length list of clipping
1885 * rectangles after the body of the command. If no rectangles are
1886 * specified, there is no clipping region. The entire destRect is
1887 * drawn to. If one or more rectangles are included, they describe
1888 * a clipping region. The clip rectangle coordinates are measured
1889 * relative to the top-left corner of destRect.
1890 *
1891 * This clipping region serves multiple purposes:
1892 *
1893 * - It can be used to perform an irregularly shaped blit more
1894 * efficiently than by issuing many separate blit commands.
1895 *
1896 * - It is equivalent to allowing blits with non-integer
1897 * source coordinates. You could blit just one half-pixel
1898 * of a source, for example, by specifying a larger
1899 * destination rectangle than you need, then removing
1900 * part of it using a clip rectangle.
1901 *
1902 * Availability:
1903 * SVGA_FIFO_CAP_SCREEN_OBJECT
1904 *
1905 * Limitations:
1906 *
1907 * - Currently, no backend supports blits from a mipmap or face
1908 * other than the first one.
1909 */
1910
1911typedef
1912struct {
1913 SVGA3dSurfaceImageId srcImage;
1914 SVGASignedRect srcRect;
1915 uint32 destScreenId; /* Screen ID or SVGA_ID_INVALID for virt. coords */
1916 SVGASignedRect destRect; /* Supports scaling if src/rest different size */
1917 /* Clipping: zero or more SVGASignedRects follow */
1918} SVGA3dCmdBlitSurfaceToScreen; /* SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN */
1919
8d3713ea
JB		 1920typedef
1921struct {
1922 uint32 sid;
1923 SVGA3dTextureFilter filter;
1924} SVGA3dCmdGenerateMipmaps; /* SVGA_3D_CMD_GENERATE_MIPMAPS */
1925
632f6117 1926
d9019498
TH		 1927/*
1928 * Guest-backed surface definitions.
1929 */
1930
1931typedef uint32 SVGAMobId;
1932
1933typedef enum SVGAMobFormat {
1934 SVGA3D_MOBFMT_INVALID = SVGA3D_INVALID_ID,
1935 SVGA3D_MOBFMT_PTDEPTH_0 = 0,
1936 SVGA3D_MOBFMT_PTDEPTH_1 = 1,
1937 SVGA3D_MOBFMT_PTDEPTH_2 = 2,
1938 SVGA3D_MOBFMT_RANGE = 3,
f2a0dcb1
TH		 1939 SVGA3D_MOBFMT_PTDEPTH64_0 = 4,
1940 SVGA3D_MOBFMT_PTDEPTH64_1 = 5,
1941 SVGA3D_MOBFMT_PTDEPTH64_2 = 6,
d9019498
TH		 1942 SVGA3D_MOBFMT_MAX,
1943} SVGAMobFormat;
1944
1945/*
1946 * Sizes of opaque types.
1947 */
1948
1949#define SVGA3D_OTABLE_MOB_ENTRY_SIZE 16
1950#define SVGA3D_OTABLE_CONTEXT_ENTRY_SIZE 8
1951#define SVGA3D_OTABLE_SURFACE_ENTRY_SIZE 64
1952#define SVGA3D_OTABLE_SHADER_ENTRY_SIZE 16
7cba9062 1953#define SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE 64
d9019498
TH		 1954#define SVGA3D_CONTEXT_DATA_SIZE 16384
1955
1956/*
1957 * SVGA3dCmdSetOTableBase --
1958 *
1959 * This command allows the guest to specify the base PPN of the
1960 * specified object table.
1961 */
1962
1963typedef enum {
7cba9062
TH		 1964 SVGA_OTABLE_MOB = 0,
1965 SVGA_OTABLE_MIN = 0,
1966 SVGA_OTABLE_SURFACE = 1,
1967 SVGA_OTABLE_CONTEXT = 2,
1968 SVGA_OTABLE_SHADER = 3,
1969 SVGA_OTABLE_SCREEN_TARGET = 4,
1970 SVGA_OTABLE_DX9_MAX = 5,
1971 SVGA_OTABLE_MAX = 8
d9019498
TH		 1972} SVGAOTableType;
1973
1974typedef
1975struct {
1976 SVGAOTableType type;
1977 PPN baseAddress;
1978 uint32 sizeInBytes;
1979 uint32 validSizeInBytes;
1980 SVGAMobFormat ptDepth;
36e952c1 1981} __packed
96b43626 1982SVGA3dCmdSetOTableBase; /* SVGA_3D_CMD_SET_OTABLE_BASE */
d9019498 1983
f2a0dcb1
TH		 1984typedef
1985struct {
1986 SVGAOTableType type;
1987 PPN64 baseAddress;
1988 uint32 sizeInBytes;
1989 uint32 validSizeInBytes;
1990 SVGAMobFormat ptDepth;
36e952c1 1991} __packed
96b43626 1992SVGA3dCmdSetOTableBase64; /* SVGA_3D_CMD_SET_OTABLE_BASE64 */
f2a0dcb1 1993
d9019498
TH		 1994typedef
1995struct {
1996 SVGAOTableType type;
36e952c1 1997} __packed
96b43626 1998SVGA3dCmdReadbackOTable; /* SVGA_3D_CMD_READBACK_OTABLE */
d9019498
TH		 1999
2000/*
2001 * Define a memory object (Mob) in the OTable.
2002 */
2003
2004typedef
2005struct SVGA3dCmdDefineGBMob {
2006 SVGAMobId mobid;
2007 SVGAMobFormat ptDepth;
2008 PPN base;
2009 uint32 sizeInBytes;
36e952c1 2010} __packed
96b43626 2011SVGA3dCmdDefineGBMob; /* SVGA_3D_CMD_DEFINE_GB_MOB */
d9019498
TH		 2012
2013
2014/*
2015 * Destroys an object in the OTable.
2016 */
2017
2018typedef
2019struct SVGA3dCmdDestroyGBMob {
2020 SVGAMobId mobid;
36e952c1 2021} __packed
96b43626 2022SVGA3dCmdDestroyGBMob; /* SVGA_3D_CMD_DESTROY_GB_MOB */
d9019498
TH		 2023
2024/*
2025 * Redefine an object in the OTable.
2026 */
2027
2028typedef
2029struct SVGA3dCmdRedefineGBMob {
2030 SVGAMobId mobid;
2031 SVGAMobFormat ptDepth;
2032 PPN base;
2033 uint32 sizeInBytes;
36e952c1 2034} __packed
96b43626 2035SVGA3dCmdRedefineGBMob; /* SVGA_3D_CMD_REDEFINE_GB_MOB */
d9019498 2036
f2a0dcb1
TH		 2037/*
2038 * Define a memory object (Mob) in the OTable with a PPN64 base.
2039 */
2040
2041typedef
2042struct SVGA3dCmdDefineGBMob64 {
2043 SVGAMobId mobid;
2044 SVGAMobFormat ptDepth;
2045 PPN64 base;
2046 uint32 sizeInBytes;
36e952c1 2047} __packed
f2a0dcb1
TH		 2048SVGA3dCmdDefineGBMob64; /* SVGA_3D_CMD_DEFINE_GB_MOB64 */
2049
2050/*
2051 * Redefine an object in the OTable with PPN64 base.
2052 */
2053
2054typedef
2055struct SVGA3dCmdRedefineGBMob64 {
2056 SVGAMobId mobid;
2057 SVGAMobFormat ptDepth;
2058 PPN64 base;
2059 uint32 sizeInBytes;
36e952c1 2060} __packed
f2a0dcb1
TH		 2061SVGA3dCmdRedefineGBMob64; /* SVGA_3D_CMD_REDEFINE_GB_MOB64 */
2062
d9019498
TH		 2063/*
2064 * Notification that the page tables have been modified.
2065 */
2066
2067typedef
2068struct SVGA3dCmdUpdateGBMobMapping {
2069 SVGAMobId mobid;
36e952c1 2070} __packed
96b43626 2071SVGA3dCmdUpdateGBMobMapping; /* SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING */
d9019498
TH		 2072
2073/*
2074 * Define a guest-backed surface.
2075 */
2076
2077typedef
2078struct SVGA3dCmdDefineGBSurface {
2079 uint32 sid;
2080 SVGA3dSurfaceFlags surfaceFlags;
2081 SVGA3dSurfaceFormat format;
2082 uint32 numMipLevels;
2083 uint32 multisampleCount;
2084 SVGA3dTextureFilter autogenFilter;
2085 SVGA3dSize size;
36e952c1
TH		 2086} __packed
2087SVGA3dCmdDefineGBSurface; /* SVGA_3D_CMD_DEFINE_GB_SURFACE */
d9019498
TH		 2088
2089/*
2090 * Destroy a guest-backed surface.
2091 */
2092
2093typedef
2094struct SVGA3dCmdDestroyGBSurface {
2095 uint32 sid;
36e952c1
TH		 2096} __packed
2097SVGA3dCmdDestroyGBSurface; /* SVGA_3D_CMD_DESTROY_GB_SURFACE */
d9019498
TH		 2098
2099/*
2100 * Bind a guest-backed surface to an object.
2101 */
2102
2103typedef
2104struct SVGA3dCmdBindGBSurface {
2105 uint32 sid;
2106 SVGAMobId mobid;
36e952c1
TH		 2107} __packed
2108SVGA3dCmdBindGBSurface; /* SVGA_3D_CMD_BIND_GB_SURFACE */
d9019498
TH		 2109
2110/*
2111 * Conditionally bind a mob to a guest backed surface if testMobid
2112 * matches the currently bound mob. Optionally issue a readback on
2113 * the surface while it is still bound to the old mobid if the mobid
2114 * is changed by this command.
2115 */
2116
2117#define SVGA3D_COND_BIND_GB_SURFACE_FLAG_READBACK (1 << 0)
2118
2119typedef
2120struct{
2121 uint32 sid;
2122 SVGAMobId testMobid;
2123 SVGAMobId mobid;
2124 uint32 flags;
36e952c1 2125} __packed
d9019498
TH		 2126SVGA3dCmdCondBindGBSurface; /* SVGA_3D_CMD_COND_BIND_GB_SURFACE */
2127
2128/*
2129 * Update an image in a guest-backed surface.
2130 * (Inform the device that the guest-contents have been updated.)
2131 */
2132
2133typedef
2134struct SVGA3dCmdUpdateGBImage {
2135 SVGA3dSurfaceImageId image;
2136 SVGA3dBox box;
36e952c1
TH		 2137} __packed
2138SVGA3dCmdUpdateGBImage; /* SVGA_3D_CMD_UPDATE_GB_IMAGE */
d9019498
TH		 2139
2140/*
2141 * Update an entire guest-backed surface.
2142 * (Inform the device that the guest-contents have been updated.)
2143 */
2144
2145typedef
2146struct SVGA3dCmdUpdateGBSurface {
2147 uint32 sid;
36e952c1
TH		 2148} __packed
2149SVGA3dCmdUpdateGBSurface; /* SVGA_3D_CMD_UPDATE_GB_SURFACE */
d9019498
TH		 2150
2151/*
2152 * Readback an image in a guest-backed surface.
2153 * (Request the device to flush the dirty contents into the guest.)
2154 */
2155
2156typedef
2157struct SVGA3dCmdReadbackGBImage {
2158 SVGA3dSurfaceImageId image;
36e952c1
TH		 2159} __packed
2160SVGA3dCmdReadbackGBImage; /* SVGA_3D_CMD_READBACK_GB_IMAGE*/
d9019498
TH		 2161
2162/*
2163 * Readback an entire guest-backed surface.
2164 * (Request the device to flush the dirty contents into the guest.)
2165 */
2166
2167typedef
2168struct SVGA3dCmdReadbackGBSurface {
2169 uint32 sid;
36e952c1
TH		 2170} __packed
2171SVGA3dCmdReadbackGBSurface; /* SVGA_3D_CMD_READBACK_GB_SURFACE */
d9019498
TH		 2172
2173/*
2174 * Readback a sub rect of an image in a guest-backed surface. After
2175 * issuing this command the driver is required to issue an update call
2176 * of the same region before issuing any other commands that reference
2177 * this surface or rendering is not guaranteed.
2178 */
2179
2180typedef
2181struct SVGA3dCmdReadbackGBImagePartial {
2182 SVGA3dSurfaceImageId image;
2183 SVGA3dBox box;
2184 uint32 invertBox;
36e952c1 2185} __packed
d9019498
TH		 2186SVGA3dCmdReadbackGBImagePartial; /* SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL */
2187
2188/*
2189 * Invalidate an image in a guest-backed surface.
2190 * (Notify the device that the contents can be lost.)
2191 */
2192
2193typedef
2194struct SVGA3dCmdInvalidateGBImage {
2195 SVGA3dSurfaceImageId image;
36e952c1
TH		 2196} __packed
2197SVGA3dCmdInvalidateGBImage; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE */
d9019498
TH		 2198
2199/*
2200 * Invalidate an entire guest-backed surface.
2201 * (Notify the device that the contents if all images can be lost.)
2202 */
2203
2204typedef
2205struct SVGA3dCmdInvalidateGBSurface {
2206 uint32 sid;
36e952c1
TH		 2207} __packed
2208SVGA3dCmdInvalidateGBSurface; /* SVGA_3D_CMD_INVALIDATE_GB_SURFACE */
d9019498
TH		 2209
2210/*
2211 * Invalidate a sub rect of an image in a guest-backed surface. After
2212 * issuing this command the driver is required to issue an update call
2213 * of the same region before issuing any other commands that reference
2214 * this surface or rendering is not guaranteed.
2215 */
2216
2217typedef
2218struct SVGA3dCmdInvalidateGBImagePartial {
2219 SVGA3dSurfaceImageId image;
2220 SVGA3dBox box;
2221 uint32 invertBox;
36e952c1 2222} __packed
d9019498
TH		 2223SVGA3dCmdInvalidateGBImagePartial; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL */
2224
2225/*
2226 * Define a guest-backed context.
2227 */
2228
2229typedef
2230struct SVGA3dCmdDefineGBContext {
2231 uint32 cid;
36e952c1
TH		 2232} __packed
2233SVGA3dCmdDefineGBContext; /* SVGA_3D_CMD_DEFINE_GB_CONTEXT */
d9019498
TH		 2234
2235/*
2236 * Destroy a guest-backed context.
2237 */
2238
2239typedef
2240struct SVGA3dCmdDestroyGBContext {
2241 uint32 cid;
36e952c1
TH		 2242} __packed
2243SVGA3dCmdDestroyGBContext; /* SVGA_3D_CMD_DESTROY_GB_CONTEXT */
d9019498
TH		 2244
2245/*
2246 * Bind a guest-backed context.
2247 *
2248 * validContents should be set to 0 for new contexts,
2249 * and 1 if this is an old context which is getting paged
2250 * back on to the device.
2251 *
2252 * For new contexts, it is recommended that the driver
2253 * issue commands to initialize all interesting state
2254 * prior to rendering.
2255 */
2256
2257typedef
2258struct SVGA3dCmdBindGBContext {
2259 uint32 cid;
2260 SVGAMobId mobid;
2261 uint32 validContents;
36e952c1
TH		 2262} __packed
2263SVGA3dCmdBindGBContext; /* SVGA_3D_CMD_BIND_GB_CONTEXT */
d9019498
TH		 2264
2265/*
2266 * Readback a guest-backed context.
2267 * (Request that the device flush the contents back into guest memory.)
2268 */
2269
2270typedef
2271struct SVGA3dCmdReadbackGBContext {
2272 uint32 cid;
36e952c1
TH		 2273} __packed
2274SVGA3dCmdReadbackGBContext; /* SVGA_3D_CMD_READBACK_GB_CONTEXT */
d9019498
TH		 2275
2276/*
2277 * Invalidate a guest-backed context.
2278 */
2279typedef
2280struct SVGA3dCmdInvalidateGBContext {
2281 uint32 cid;
36e952c1
TH		 2282} __packed
2283SVGA3dCmdInvalidateGBContext; /* SVGA_3D_CMD_INVALIDATE_GB_CONTEXT */
d9019498
TH		 2284
2285/*
2286 * Define a guest-backed shader.
2287 */
2288
2289typedef
2290struct SVGA3dCmdDefineGBShader {
2291 uint32 shid;
2292 SVGA3dShaderType type;
2293 uint32 sizeInBytes;
36e952c1
TH		 2294} __packed
2295SVGA3dCmdDefineGBShader; /* SVGA_3D_CMD_DEFINE_GB_SHADER */
d9019498
TH		 2296
2297/*
2298 * Bind a guest-backed shader.
2299 */
2300
2301typedef struct SVGA3dCmdBindGBShader {
2302 uint32 shid;
2303 SVGAMobId mobid;
2304 uint32 offsetInBytes;
36e952c1
TH		 2305} __packed
2306SVGA3dCmdBindGBShader; /* SVGA_3D_CMD_BIND_GB_SHADER */
d9019498
TH		 2307
2308/*
2309 * Destroy a guest-backed shader.
2310 */
2311
2312typedef struct SVGA3dCmdDestroyGBShader {
2313 uint32 shid;
36e952c1
TH		 2314} __packed
2315SVGA3dCmdDestroyGBShader; /* SVGA_3D_CMD_DESTROY_GB_SHADER */
d9019498 2316
d9019498
TH		 2317typedef
2318struct {
2319 uint32 cid;
2320 uint32 regStart;
2321 SVGA3dShaderType shaderType;
2322 SVGA3dShaderConstType constType;
2323
2324 /*
2325 * Followed by a variable number of shader constants.
2326 *
2327 * Note that FLOAT and INT constants are 4-dwords in length, while
2328 * BOOL constants are 1-dword in length.
2329 */
36e952c1
TH		 2330} __packed
2331SVGA3dCmdSetGBShaderConstInline;
d9019498
TH		 2332/* SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE */
2333
2334typedef
2335struct {
2336 uint32 cid;
2337 SVGA3dQueryType type;
36e952c1
TH		 2338} __packed
2339SVGA3dCmdBeginGBQuery; /* SVGA_3D_CMD_BEGIN_GB_QUERY */
d9019498
TH		 2340
2341typedef
2342struct {
2343 uint32 cid;
2344 SVGA3dQueryType type;
2345 SVGAMobId mobid;
2346 uint32 offset;
36e952c1
TH		 2347} __packed
2348SVGA3dCmdEndGBQuery; /* SVGA_3D_CMD_END_GB_QUERY */
d9019498
TH		 2349
2350
2351/*
2352 * SVGA_3D_CMD_WAIT_FOR_GB_QUERY --
2353 *
2354 * The semantics of this command are identical to the
2355 * SVGA_3D_CMD_WAIT_FOR_QUERY except that the results are written
2356 * to a Mob instead of a GMR.
2357 */
2358
2359typedef
2360struct {
2361 uint32 cid;
2362 SVGA3dQueryType type;
2363 SVGAMobId mobid;
2364 uint32 offset;
36e952c1
TH		 2365} __packed
2366SVGA3dCmdWaitForGBQuery; /* SVGA_3D_CMD_WAIT_FOR_GB_QUERY */
d9019498
TH		 2367
2368typedef
2369struct {
2370 SVGAMobId mobid;
2371 uint32 fbOffset;
2372 uint32 initalized;
36e952c1 2373} __packed
d9019498
TH		 2374SVGA3dCmdEnableGart; /* SVGA_3D_CMD_ENABLE_GART */
2375
2376typedef
2377struct {
2378 SVGAMobId mobid;
2379 uint32 gartOffset;
36e952c1 2380} __packed
d9019498
TH		 2381SVGA3dCmdMapMobIntoGart; /* SVGA_3D_CMD_MAP_MOB_INTO_GART */
2382
2383
2384typedef
2385struct {
2386 uint32 gartOffset;
2387 uint32 numPages;
36e952c1 2388} __packed
d9019498
TH		 2389SVGA3dCmdUnmapGartRange; /* SVGA_3D_CMD_UNMAP_GART_RANGE */
2390
2391
2392/*
2393 * Screen Targets
2394 */
2395#define SVGA_STFLAG_PRIMARY (1 << 0)
2396
2397typedef
2398struct {
2399 uint32 stid;
2400 uint32 width;
2401 uint32 height;
2402 int32 xRoot;
2403 int32 yRoot;
2404 uint32 flags;
36e952c1 2405} __packed
d9019498
TH		 2406SVGA3dCmdDefineGBScreenTarget; /* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET */
2407
2408typedef
2409struct {
2410 uint32 stid;
36e952c1 2411} __packed
d9019498
TH		 2412SVGA3dCmdDestroyGBScreenTarget; /* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET */
2413
2414typedef
2415struct {
2416 uint32 stid;
2417 SVGA3dSurfaceImageId image;
36e952c1 2418} __packed
d9019498
TH		 2419SVGA3dCmdBindGBScreenTarget; /* SVGA_3D_CMD_BIND_GB_SCREENTARGET */
2420
2421typedef
2422struct {
2423 uint32 stid;
2424 SVGA3dBox box;
36e952c1 2425} __packed
d9019498
TH		 2426SVGA3dCmdUpdateGBScreenTarget; /* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET */
2427
632f6117
JB		 2428/*
2429 * Capability query index.
2430 *
2431 * Notes:
2432 *
2433 * 1. SVGA3D_DEVCAP_MAX_TEXTURES reflects the maximum number of
2434 * fixed-function texture units available. Each of these units
2435 * work in both FFP and Shader modes, and they support texture
2436 * transforms and texture coordinates. The host may have additional
2437 * texture image units that are only usable with shaders.
2438 *
2439 * 2. The BUFFER_FORMAT capabilities are deprecated, and they always
2440 * return TRUE. Even on physical hardware that does not support
2441 * these formats natively, the SVGA3D device will provide an emulation
2442 * which should be invisible to the guest OS.
2443 *
2444 * In general, the SVGA3D device should support any operation on
2445 * any surface format, it just may perform some of these
2446 * operations in software depending on the capabilities of the
2447 * available physical hardware.
2448 *
2449 * XXX: In the future, we will add capabilities that describe in
2450 * detail what formats are supported in hardware for what kinds
2451 * of operations.
2452 */
2453
2454typedef enum {
2455 SVGA3D_DEVCAP_3D = 0,
2456 SVGA3D_DEVCAP_MAX_LIGHTS = 1,
2457 SVGA3D_DEVCAP_MAX_TEXTURES = 2, /* See note (1) */
2458 SVGA3D_DEVCAP_MAX_CLIP_PLANES = 3,
2459 SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = 4,
2460 SVGA3D_DEVCAP_VERTEX_SHADER = 5,
2461 SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = 6,
2462 SVGA3D_DEVCAP_FRAGMENT_SHADER = 7,
2463 SVGA3D_DEVCAP_MAX_RENDER_TARGETS = 8,
2464 SVGA3D_DEVCAP_S23E8_TEXTURES = 9,
2465 SVGA3D_DEVCAP_S10E5_TEXTURES = 10,
2466 SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = 11,
2467 SVGA3D_DEVCAP_D16_BUFFER_FORMAT = 12, /* See note (2) */
2468 SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = 13, /* See note (2) */
2469 SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = 14, /* See note (2) */
2470 SVGA3D_DEVCAP_QUERY_TYPES = 15,
2471 SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = 16,
2472 SVGA3D_DEVCAP_MAX_POINT_SIZE = 17,
2473 SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = 18,
2474 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = 19,
2475 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = 20,
2476 SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = 21,
2477 SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = 22,
2478 SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = 23,
2479 SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = 24,
2480 SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = 25,
2481 SVGA3D_DEVCAP_MAX_VERTEX_INDEX = 26,
2482 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = 27,
2483 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = 28,
2484 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = 29,
2485 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = 30,
2486 SVGA3D_DEVCAP_TEXTURE_OPS = 31,
2487 SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = 32,
2488 SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = 33,
2489 SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = 34,
2490 SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = 35,
2491 SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = 36,
2492 SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = 37,
2493 SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = 38,
2494 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = 39,
2495 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = 40,
2496 SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = 41,
2497 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = 42,
2498 SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = 43,
2499 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = 44,
2500 SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = 45,
2501 SVGA3D_DEVCAP_SURFACEFMT_DXT1 = 46,
2502 SVGA3D_DEVCAP_SURFACEFMT_DXT2 = 47,
2503 SVGA3D_DEVCAP_SURFACEFMT_DXT3 = 48,
2504 SVGA3D_DEVCAP_SURFACEFMT_DXT4 = 49,
2505 SVGA3D_DEVCAP_SURFACEFMT_DXT5 = 50,
2506 SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = 51,
2507 SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = 52,
2508 SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = 53,
2509 SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = 54,
2510 SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = 55,
2511 SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = 56,
2512 SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = 57,
2513 SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = 58,
2514 SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = 59,
2515 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = 60,
2516 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = 61,
2517 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = 63,
2518
2519 /*
2520 * Note that MAX_SIMULTANEOUS_RENDER_TARGETS is a maximum count of color
2521 * render targets. This does no include the depth or stencil targets.
2522 */
2523 SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = 64,
2524
2525 SVGA3D_DEVCAP_SURFACEFMT_V16U16 = 65,
2526 SVGA3D_DEVCAP_SURFACEFMT_G16R16 = 66,
2527 SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = 67,
2528 SVGA3D_DEVCAP_SURFACEFMT_UYVY = 68,
2529 SVGA3D_DEVCAP_SURFACEFMT_YUY2 = 69,
8d3713ea
JB		 2530 SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = 70,
2531 SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = 71,
2532 SVGA3D_DEVCAP_ALPHATOCOVERAGE = 72,
2533 SVGA3D_DEVCAP_SUPERSAMPLE = 73,
2534 SVGA3D_DEVCAP_AUTOGENMIPMAPS = 74,
2535 SVGA3D_DEVCAP_SURFACEFMT_NV12 = 75,
2536 SVGA3D_DEVCAP_SURFACEFMT_AYUV = 76,
2537
2538 /*
2539 * This is the maximum number of SVGA context IDs that the guest
2540 * can define using SVGA_3D_CMD_CONTEXT_DEFINE.
2541 */
2542 SVGA3D_DEVCAP_MAX_CONTEXT_IDS = 77,
2543
2544 /*
2545 * This is the maximum number of SVGA surface IDs that the guest
2546 * can define using SVGA_3D_CMD_SURFACE_DEFINE*.
2547 */
2548 SVGA3D_DEVCAP_MAX_SURFACE_IDS = 78,
2549
2550 SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = 79,
2551 SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = 80,
2552 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = 81,
2553
2554 SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = 82,
2555 SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = 83,
632f6117
JB		 2556
2557 /*
d9019498
TH		 2558 * Deprecated.
2559 */
2560 SVGA3D_DEVCAP_VGPU10 = 84,
2561
2562 /*
2563 * This contains several SVGA_3D_CAPS_VIDEO_DECODE elements
2564 * ored together, one for every type of video decoding supported.
632f6117 2565 */
d9019498
TH		 2566 SVGA3D_DEVCAP_VIDEO_DECODE = 85,
2567
2568 /*
2569 * This contains several SVGA_3D_CAPS_VIDEO_PROCESS elements
2570 * ored together, one for every type of video processing supported.
2571 */
2572 SVGA3D_DEVCAP_VIDEO_PROCESS = 86,
2573
2574 SVGA3D_DEVCAP_LINE_AA = 87, /* boolean */
2575 SVGA3D_DEVCAP_LINE_STIPPLE = 88, /* boolean */
2576 SVGA3D_DEVCAP_MAX_LINE_WIDTH = 89, /* float */
2577 SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH = 90, /* float */
2578
2579 SVGA3D_DEVCAP_SURFACEFMT_YV12 = 91,
2580
2581 /*
2582 * Does the host support the SVGA logic ops commands?
2583 */
2584 SVGA3D_DEVCAP_LOGICOPS = 92,
2585
2586 /*
2587 * What support does the host have for screen targets?
2588 *
2589 * See the SVGA3D_SCREENTARGET_CAP bits below.
2590 */
2591 SVGA3D_DEVCAP_SCREENTARGETS = 93,
2592
632f6117
JB		 2593 SVGA3D_DEVCAP_MAX /* This must be the last index. */
2594} SVGA3dDevCapIndex;
2595
2596typedef union {
2597 Bool b;
2598 uint32 u;
2599 int32 i;
2600 float f;
2601} SVGA3dDevCapResult;
2602
a6fc955f
TH		 2603typedef enum {
2604 SVGA3DCAPS_RECORD_UNKNOWN = 0,
2605 SVGA3DCAPS_RECORD_DEVCAPS_MIN = 0x100,
2606 SVGA3DCAPS_RECORD_DEVCAPS = 0x100,
2607 SVGA3DCAPS_RECORD_DEVCAPS_MAX = 0x1ff,
2608} SVGA3dCapsRecordType;
2609
2610typedef
2611struct SVGA3dCapsRecordHeader {
2612 uint32 length;
2613 SVGA3dCapsRecordType type;
2614}
2615SVGA3dCapsRecordHeader;
2616
2617typedef
2618struct SVGA3dCapsRecord {
2619 SVGA3dCapsRecordHeader header;
2620 uint32 data[1];
2621}
2622SVGA3dCapsRecord;
2623
2624
2625typedef uint32 SVGA3dCapPair[2];
2626
632f6117 2627#endif /* _SVGA3D_REG_H_ */
Linux kernel - Deliverables
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