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drm/vmwgfx: Fix an fb unlocking bug
[deliverable/linux.git] / drivers / gpu / drm / vmwgfx / vmwgfx_drv.c
CommitLineData
fb1d9738
JB		 1/**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
e0cd3608 27#include <linux/module.h>
fb1d9738 28
760285e7 29#include <drm/drmP.h>
fb1d9738 30#include "vmwgfx_drv.h"
760285e7
DH		 31#include <drm/ttm/ttm_placement.h>
32#include <drm/ttm/ttm_bo_driver.h>
33#include <drm/ttm/ttm_object.h>
34#include <drm/ttm/ttm_module.h>
d92d9851 35#include <linux/dma_remapping.h>
fb1d9738
JB		 36
37#define VMWGFX_DRIVER_NAME "vmwgfx"
38#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
39#define VMWGFX_CHIP_SVGAII 0
40#define VMW_FB_RESERVATION 0
41
eb4f923b
JB		 42#define VMW_MIN_INITIAL_WIDTH 800
43#define VMW_MIN_INITIAL_HEIGHT 600
44
45
fb1d9738
JB		 46/**
47 * Fully encoded drm commands. Might move to vmw_drm.h
48 */
49
50#define DRM_IOCTL_VMW_GET_PARAM \
51 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
52 struct drm_vmw_getparam_arg)
53#define DRM_IOCTL_VMW_ALLOC_DMABUF \
54 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
55 union drm_vmw_alloc_dmabuf_arg)
56#define DRM_IOCTL_VMW_UNREF_DMABUF \
57 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
58 struct drm_vmw_unref_dmabuf_arg)
59#define DRM_IOCTL_VMW_CURSOR_BYPASS \
60 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
61 struct drm_vmw_cursor_bypass_arg)
62
63#define DRM_IOCTL_VMW_CONTROL_STREAM \
64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
65 struct drm_vmw_control_stream_arg)
66#define DRM_IOCTL_VMW_CLAIM_STREAM \
67 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
68 struct drm_vmw_stream_arg)
69#define DRM_IOCTL_VMW_UNREF_STREAM \
70 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
71 struct drm_vmw_stream_arg)
72
73#define DRM_IOCTL_VMW_CREATE_CONTEXT \
74 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
75 struct drm_vmw_context_arg)
76#define DRM_IOCTL_VMW_UNREF_CONTEXT \
77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
78 struct drm_vmw_context_arg)
79#define DRM_IOCTL_VMW_CREATE_SURFACE \
80 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
81 union drm_vmw_surface_create_arg)
82#define DRM_IOCTL_VMW_UNREF_SURFACE \
83 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
84 struct drm_vmw_surface_arg)
85#define DRM_IOCTL_VMW_REF_SURFACE \
86 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
87 union drm_vmw_surface_reference_arg)
88#define DRM_IOCTL_VMW_EXECBUF \
89 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
90 struct drm_vmw_execbuf_arg)
ae2a1040
TH		 91#define DRM_IOCTL_VMW_GET_3D_CAP \
92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
93 struct drm_vmw_get_3d_cap_arg)
fb1d9738
JB		 94#define DRM_IOCTL_VMW_FENCE_WAIT \
95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
96 struct drm_vmw_fence_wait_arg)
ae2a1040
TH		 97#define DRM_IOCTL_VMW_FENCE_SIGNALED \
98 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
99 struct drm_vmw_fence_signaled_arg)
100#define DRM_IOCTL_VMW_FENCE_UNREF \
101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
102 struct drm_vmw_fence_arg)
57c5ee79
TH		 103#define DRM_IOCTL_VMW_FENCE_EVENT \
104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
105 struct drm_vmw_fence_event_arg)
2fcd5a73
JB		 106#define DRM_IOCTL_VMW_PRESENT \
107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
108 struct drm_vmw_present_arg)
109#define DRM_IOCTL_VMW_PRESENT_READBACK \
110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
111 struct drm_vmw_present_readback_arg)
cd2b89e7
TH		 112#define DRM_IOCTL_VMW_UPDATE_LAYOUT \
113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
114 struct drm_vmw_update_layout_arg)
c74c162f
TH		 115#define DRM_IOCTL_VMW_CREATE_SHADER \
116 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
117 struct drm_vmw_shader_create_arg)
118#define DRM_IOCTL_VMW_UNREF_SHADER \
119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
120 struct drm_vmw_shader_arg)
a97e2192
TH		 121#define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
122 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
123 union drm_vmw_gb_surface_create_arg)
124#define DRM_IOCTL_VMW_GB_SURFACE_REF \
125 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
126 union drm_vmw_gb_surface_reference_arg)
1d7a5cbf
TH		 127#define DRM_IOCTL_VMW_SYNCCPU \
128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
129 struct drm_vmw_synccpu_arg)
fb1d9738
JB		 130
131/**
132 * The core DRM version of this macro doesn't account for
133 * DRM_COMMAND_BASE.
134 */
135
136#define VMW_IOCTL_DEF(ioctl, func, flags) \
7e7392a6 137 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func}
fb1d9738
JB		 138
139/**
140 * Ioctl definitions.
141 */
142
baa70943 143static const struct drm_ioctl_desc vmw_ioctls[] = {
1b2f1489 144 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
03f80263 145 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 146 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
03f80263 147 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 148 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
03f80263 149 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 150 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
e1f78003
TH		 151 vmw_kms_cursor_bypass_ioctl,
152 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
fb1d9738 153
1b2f1489 154 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
e1f78003 155 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
1b2f1489 156 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
e1f78003 157 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
1b2f1489 158 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
e1f78003 159 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
fb1d9738 160
1b2f1489 161 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
03f80263 162 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 163 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
03f80263 164 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 165 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
03f80263 166 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 167 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
03f80263 168 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 169 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
03f80263 170 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 171 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
03f80263 172 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
ae2a1040 173 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
89dcbda6 174 DRM_UNLOCKED | DRM_RENDER_ALLOW),
ae2a1040
TH		 175 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
176 vmw_fence_obj_signaled_ioctl,
89dcbda6 177 DRM_UNLOCKED | DRM_RENDER_ALLOW),
ae2a1040 178 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
03f80263
TH		 179 DRM_UNLOCKED | DRM_RENDER_ALLOW),
180 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
181 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
f63f6a59 182 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
03f80263 183 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
2fcd5a73
JB		 184
185 /* these allow direct access to the framebuffers mark as master only */
186 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
187 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
188 VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
189 vmw_present_readback_ioctl,
190 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
cd2b89e7
TH		 191 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
192 vmw_kms_update_layout_ioctl,
193 DRM_MASTER | DRM_UNLOCKED),
c74c162f
TH		 194 VMW_IOCTL_DEF(VMW_CREATE_SHADER,
195 vmw_shader_define_ioctl,
03f80263 196 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
c74c162f
TH		 197 VMW_IOCTL_DEF(VMW_UNREF_SHADER,
198 vmw_shader_destroy_ioctl,
03f80263 199 DRM_UNLOCKED | DRM_RENDER_ALLOW),
a97e2192
TH		 200 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
201 vmw_gb_surface_define_ioctl,
03f80263 202 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
a97e2192
TH		 203 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
204 vmw_gb_surface_reference_ioctl,
03f80263 205 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
1d7a5cbf
TH		 206 VMW_IOCTL_DEF(VMW_SYNCCPU,
207 vmw_user_dmabuf_synccpu_ioctl,
89dcbda6 208 DRM_UNLOCKED | DRM_RENDER_ALLOW),
fb1d9738
JB		 209};
210
211static struct pci_device_id vmw_pci_id_list[] = {
212 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
213 {0, 0, 0}
214};
c4903429 215MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
fb1d9738 216
5d2afab9 217static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
d92d9851
TH		 218static int vmw_force_iommu;
219static int vmw_restrict_iommu;
220static int vmw_force_coherent;
0d00c488 221static int vmw_restrict_dma_mask;
fb1d9738
JB		 222
223static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
224static void vmw_master_init(struct vmw_master *);
d9f36a00
TH		 225static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
226 void *ptr);
fb1d9738 227
30c78bb8
TH		 228MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
229module_param_named(enable_fbdev, enable_fbdev, int, 0600);
d92d9851
TH		 230MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
231module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
232MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
233module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
234MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
235module_param_named(force_coherent, vmw_force_coherent, int, 0600);
0d00c488
TH		 236MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
237module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
d92d9851 238
30c78bb8 239
fb1d9738
JB		 240static void vmw_print_capabilities(uint32_t capabilities)
241{
242 DRM_INFO("Capabilities:\n");
243 if (capabilities & SVGA_CAP_RECT_COPY)
244 DRM_INFO(" Rect copy.\n");
245 if (capabilities & SVGA_CAP_CURSOR)
246 DRM_INFO(" Cursor.\n");
247 if (capabilities & SVGA_CAP_CURSOR_BYPASS)
248 DRM_INFO(" Cursor bypass.\n");
249 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
250 DRM_INFO(" Cursor bypass 2.\n");
251 if (capabilities & SVGA_CAP_8BIT_EMULATION)
252 DRM_INFO(" 8bit emulation.\n");
253 if (capabilities & SVGA_CAP_ALPHA_CURSOR)
254 DRM_INFO(" Alpha cursor.\n");
255 if (capabilities & SVGA_CAP_3D)
256 DRM_INFO(" 3D.\n");
257 if (capabilities & SVGA_CAP_EXTENDED_FIFO)
258 DRM_INFO(" Extended Fifo.\n");
259 if (capabilities & SVGA_CAP_MULTIMON)
260 DRM_INFO(" Multimon.\n");
261 if (capabilities & SVGA_CAP_PITCHLOCK)
262 DRM_INFO(" Pitchlock.\n");
263 if (capabilities & SVGA_CAP_IRQMASK)
264 DRM_INFO(" Irq mask.\n");
265 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
266 DRM_INFO(" Display Topology.\n");
267 if (capabilities & SVGA_CAP_GMR)
268 DRM_INFO(" GMR.\n");
269 if (capabilities & SVGA_CAP_TRACES)
270 DRM_INFO(" Traces.\n");
dcca2862
TH		 271 if (capabilities & SVGA_CAP_GMR2)
272 DRM_INFO(" GMR2.\n");
273 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
274 DRM_INFO(" Screen Object 2.\n");
c1234db7
TH		 275 if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
276 DRM_INFO(" Command Buffers.\n");
277 if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
278 DRM_INFO(" Command Buffers 2.\n");
279 if (capabilities & SVGA_CAP_GBOBJECTS)
280 DRM_INFO(" Guest Backed Resources.\n");
fb1d9738
JB		 281}
282
e2fa3a76 283/**
4b9e45e6 284 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
e2fa3a76 285 *
4b9e45e6 286 * @dev_priv: A device private structure.
e2fa3a76 287 *
4b9e45e6
TH		 288 * This function creates a small buffer object that holds the query
289 * result for dummy queries emitted as query barriers.
290 * The function will then map the first page and initialize a pending
291 * occlusion query result structure, Finally it will unmap the buffer.
292 * No interruptible waits are done within this function.
e2fa3a76 293 *
4b9e45e6 294 * Returns an error if bo creation or initialization fails.
e2fa3a76 295 */
4b9e45e6 296static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
e2fa3a76 297{
4b9e45e6
TH		 298 int ret;
299 struct ttm_buffer_object *bo;
e2fa3a76
TH		 300 struct ttm_bo_kmap_obj map;
301 volatile SVGA3dQueryResult *result;
302 bool dummy;
e2fa3a76 303
4b9e45e6
TH		 304 /*
305 * Create the bo as pinned, so that a tryreserve will
306 * immediately succeed. This is because we're the only
307 * user of the bo currently.
308 */
309 ret = ttm_bo_create(&dev_priv->bdev,
310 PAGE_SIZE,
311 ttm_bo_type_device,
312 &vmw_sys_ne_placement,
313 0, false, NULL,
314 &bo);
315
e2fa3a76 316 if (unlikely(ret != 0))
4b9e45e6
TH		 317 return ret;
318
ee3939e0 319 ret = ttm_bo_reserve(bo, false, true, false, NULL);
4b9e45e6 320 BUG_ON(ret != 0);
e2fa3a76
TH		 321
322 ret = ttm_bo_kmap(bo, 0, 1, &map);
323 if (likely(ret == 0)) {
324 result = ttm_kmap_obj_virtual(&map, &dummy);
325 result->totalSize = sizeof(*result);
326 result->state = SVGA3D_QUERYSTATE_PENDING;
327 result->result32 = 0xff;
328 ttm_bo_kunmap(&map);
4b9e45e6
TH		 329 }
330 vmw_bo_pin(bo, false);
e2fa3a76 331 ttm_bo_unreserve(bo);
e2fa3a76 332
4b9e45e6
TH		 333 if (unlikely(ret != 0)) {
334 DRM_ERROR("Dummy query buffer map failed.\n");
335 ttm_bo_unref(&bo);
336 } else
337 dev_priv->dummy_query_bo = bo;
e2fa3a76 338
4b9e45e6 339 return ret;
e2fa3a76
TH		 340}
341
fb1d9738
JB		 342static int vmw_request_device(struct vmw_private *dev_priv)
343{
344 int ret;
345
fb1d9738
JB		 346 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
347 if (unlikely(ret != 0)) {
348 DRM_ERROR("Unable to initialize FIFO.\n");
349 return ret;
350 }
ae2a1040 351 vmw_fence_fifo_up(dev_priv->fman);
3530bdc3
TH		 352 if (dev_priv->has_mob) {
353 ret = vmw_otables_setup(dev_priv);
354 if (unlikely(ret != 0)) {
355 DRM_ERROR("Unable to initialize "
356 "guest Memory OBjects.\n");
357 goto out_no_mob;
358 }
359 }
e2fa3a76
TH		 360 ret = vmw_dummy_query_bo_create(dev_priv);
361 if (unlikely(ret != 0))
362 goto out_no_query_bo;
fb1d9738
JB		 363
364 return 0;
e2fa3a76
TH		 365
366out_no_query_bo:
3530bdc3
TH		 367 if (dev_priv->has_mob)
368 vmw_otables_takedown(dev_priv);
369out_no_mob:
e2fa3a76
TH		 370 vmw_fence_fifo_down(dev_priv->fman);
371 vmw_fifo_release(dev_priv, &dev_priv->fifo);
372 return ret;
fb1d9738
JB		 373}
374
375static void vmw_release_device(struct vmw_private *dev_priv)
376{
e2fa3a76
TH		 377 /*
378 * Previous destructions should've released
379 * the pinned bo.
380 */
381
382 BUG_ON(dev_priv->pinned_bo != NULL);
383
384 ttm_bo_unref(&dev_priv->dummy_query_bo);
3530bdc3
TH		 385 if (dev_priv->has_mob)
386 vmw_otables_takedown(dev_priv);
ae2a1040 387 vmw_fence_fifo_down(dev_priv->fman);
fb1d9738 388 vmw_fifo_release(dev_priv, &dev_priv->fifo);
30c78bb8
TH		 389}
390
3530bdc3 391
05730b32
TH		 392/**
393 * Increase the 3d resource refcount.
394 * If the count was prevously zero, initialize the fifo, switching to svga
395 * mode. Note that the master holds a ref as well, and may request an
396 * explicit switch to svga mode if fb is not running, using @unhide_svga.
397 */
398int vmw_3d_resource_inc(struct vmw_private *dev_priv,
399 bool unhide_svga)
30c78bb8
TH		 400{
401 int ret = 0;
402
403 mutex_lock(&dev_priv->release_mutex);
404 if (unlikely(dev_priv->num_3d_resources++ == 0)) {
405 ret = vmw_request_device(dev_priv);
406 if (unlikely(ret != 0))
407 --dev_priv->num_3d_resources;
05730b32 408 } else if (unhide_svga) {
05730b32
TH		 409 vmw_write(dev_priv, SVGA_REG_ENABLE,
410 vmw_read(dev_priv, SVGA_REG_ENABLE) &
411 ~SVGA_REG_ENABLE_HIDE);
30c78bb8 412 }
05730b32 413
30c78bb8
TH		 414 mutex_unlock(&dev_priv->release_mutex);
415 return ret;
fb1d9738
JB		 416}
417
05730b32
TH		 418/**
419 * Decrease the 3d resource refcount.
420 * If the count reaches zero, disable the fifo, switching to vga mode.
421 * Note that the master holds a refcount as well, and may request an
422 * explicit switch to vga mode when it releases its refcount to account
423 * for the situation of an X server vt switch to VGA with 3d resources
424 * active.
425 */
426void vmw_3d_resource_dec(struct vmw_private *dev_priv,
427 bool hide_svga)
30c78bb8
TH		 428{
429 int32_t n3d;
430
431 mutex_lock(&dev_priv->release_mutex);
432 if (unlikely(--dev_priv->num_3d_resources == 0))
433 vmw_release_device(dev_priv);
496eb6fd 434 else if (hide_svga)
05730b32
TH		 435 vmw_write(dev_priv, SVGA_REG_ENABLE,
436 vmw_read(dev_priv, SVGA_REG_ENABLE) |
437 SVGA_REG_ENABLE_HIDE);
05730b32 438
30c78bb8
TH		 439 n3d = (int32_t) dev_priv->num_3d_resources;
440 mutex_unlock(&dev_priv->release_mutex);
441
442 BUG_ON(n3d < 0);
443}
444
eb4f923b
JB		 445/**
446 * Sets the initial_[width|height] fields on the given vmw_private.
447 *
448 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
67d4a87b
TH		 449 * clamping the value to fb_max_[width|height] fields and the
450 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
451 * If the values appear to be invalid, set them to
eb4f923b
JB		 452 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
453 */
454static void vmw_get_initial_size(struct vmw_private *dev_priv)
455{
456 uint32_t width;
457 uint32_t height;
458
459 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
460 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
461
462 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
eb4f923b 463 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
67d4a87b
TH		 464
465 if (width > dev_priv->fb_max_width ||
466 height > dev_priv->fb_max_height) {
467
468 /*
469 * This is a host error and shouldn't occur.
470 */
471
472 width = VMW_MIN_INITIAL_WIDTH;
473 height = VMW_MIN_INITIAL_HEIGHT;
474 }
eb4f923b
JB		 475
476 dev_priv->initial_width = width;
477 dev_priv->initial_height = height;
478}
479
d92d9851
TH		 480/**
481 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
482 * system.
483 *
484 * @dev_priv: Pointer to a struct vmw_private
485 *
486 * This functions tries to determine the IOMMU setup and what actions
487 * need to be taken by the driver to make system pages visible to the
488 * device.
489 * If this function decides that DMA is not possible, it returns -EINVAL.
490 * The driver may then try to disable features of the device that require
491 * DMA.
492 */
493static int vmw_dma_select_mode(struct vmw_private *dev_priv)
494{
d92d9851
TH		 495 static const char *names[vmw_dma_map_max] = {
496 [vmw_dma_phys] = "Using physical TTM page addresses.",
497 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
498 [vmw_dma_map_populate] = "Keeping DMA mappings.",
499 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
e14cd953
TH		 500#ifdef CONFIG_X86
501 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
d92d9851
TH		 502
503#ifdef CONFIG_INTEL_IOMMU
504 if (intel_iommu_enabled) {
505 dev_priv->map_mode = vmw_dma_map_populate;
506 goto out_fixup;
507 }
508#endif
509
510 if (!(vmw_force_iommu || vmw_force_coherent)) {
511 dev_priv->map_mode = vmw_dma_phys;
512 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
513 return 0;
514 }
515
516 dev_priv->map_mode = vmw_dma_map_populate;
517
518 if (dma_ops->sync_single_for_cpu)
519 dev_priv->map_mode = vmw_dma_alloc_coherent;
520#ifdef CONFIG_SWIOTLB
521 if (swiotlb_nr_tbl() == 0)
522 dev_priv->map_mode = vmw_dma_map_populate;
523#endif
524
21136946 525#ifdef CONFIG_INTEL_IOMMU
d92d9851 526out_fixup:
21136946 527#endif
d92d9851
TH		 528 if (dev_priv->map_mode == vmw_dma_map_populate &&
529 vmw_restrict_iommu)
530 dev_priv->map_mode = vmw_dma_map_bind;
531
532 if (vmw_force_coherent)
533 dev_priv->map_mode = vmw_dma_alloc_coherent;
534
535#if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
536 /*
537 * No coherent page pool
538 */
539 if (dev_priv->map_mode == vmw_dma_alloc_coherent)
540 return -EINVAL;
541#endif
542
e14cd953
TH		 543#else /* CONFIG_X86 */
544 dev_priv->map_mode = vmw_dma_map_populate;
545#endif /* CONFIG_X86 */
546
d92d9851
TH		 547 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
548
549 return 0;
550}
551
0d00c488
TH		 552/**
553 * vmw_dma_masks - set required page- and dma masks
554 *
555 * @dev: Pointer to struct drm-device
556 *
557 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
558 * restriction also for 64-bit systems.
559 */
560#ifdef CONFIG_INTEL_IOMMU
561static int vmw_dma_masks(struct vmw_private *dev_priv)
562{
563 struct drm_device *dev = dev_priv->dev;
564
565 if (intel_iommu_enabled &&
566 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
567 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
568 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
569 }
570 return 0;
571}
572#else
573static int vmw_dma_masks(struct vmw_private *dev_priv)
574{
575 return 0;
576}
577#endif
578
fb1d9738
JB		 579static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
580{
581 struct vmw_private *dev_priv;
582 int ret;
c188660f 583 uint32_t svga_id;
c0951b79 584 enum vmw_res_type i;
d92d9851 585 bool refuse_dma = false;
fb1d9738
JB		 586
587 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
588 if (unlikely(dev_priv == NULL)) {
589 DRM_ERROR("Failed allocating a device private struct.\n");
590 return -ENOMEM;
591 }
fb1d9738 592
466e69b8
DA		 593 pci_set_master(dev->pdev);
594
fb1d9738
JB		 595 dev_priv->dev = dev;
596 dev_priv->vmw_chipset = chipset;
6bcd8d3c 597 dev_priv->last_read_seqno = (uint32_t) -100;
fb1d9738 598 mutex_init(&dev_priv->cmdbuf_mutex);
30c78bb8 599 mutex_init(&dev_priv->release_mutex);
173fb7d4 600 mutex_init(&dev_priv->binding_mutex);
fb1d9738 601 rwlock_init(&dev_priv->resource_lock);
294adf7d 602 ttm_lock_init(&dev_priv->reservation_sem);
496eb6fd
TH		 603 spin_lock_init(&dev_priv->hw_lock);
604 spin_lock_init(&dev_priv->waiter_lock);
605 spin_lock_init(&dev_priv->cap_lock);
c0951b79
TH		 606
607 for (i = vmw_res_context; i < vmw_res_max; ++i) {
608 idr_init(&dev_priv->res_idr[i]);
609 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
610 }
611
fb1d9738
JB		 612 mutex_init(&dev_priv->init_mutex);
613 init_waitqueue_head(&dev_priv->fence_queue);
614 init_waitqueue_head(&dev_priv->fifo_queue);
4f73a96b 615 dev_priv->fence_queue_waiters = 0;
fb1d9738 616 atomic_set(&dev_priv->fifo_queue_waiters, 0);
c0951b79 617
5bb39e81 618 dev_priv->used_memory_size = 0;
fb1d9738
JB		 619
620 dev_priv->io_start = pci_resource_start(dev->pdev, 0);
621 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
622 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
623
30c78bb8
TH		 624 dev_priv->enable_fb = enable_fbdev;
625
c188660f
PH		 626 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
627 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
628 if (svga_id != SVGA_ID_2) {
629 ret = -ENOSYS;
49625904 630 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
c188660f
PH		 631 goto out_err0;
632 }
633
fb1d9738 634 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
d92d9851
TH		 635 ret = vmw_dma_select_mode(dev_priv);
636 if (unlikely(ret != 0)) {
637 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
638 refuse_dma = true;
639 }
fb1d9738 640
5bb39e81
TH		 641 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
642 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
643 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
644 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
eb4f923b
JB		 645
646 vmw_get_initial_size(dev_priv);
647
0d00c488 648 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
fb1d9738
JB		 649 dev_priv->max_gmr_ids =
650 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
fb17f189
TH		 651 dev_priv->max_gmr_pages =
652 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
653 dev_priv->memory_size =
654 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
5bb39e81
TH		 655 dev_priv->memory_size -= dev_priv->vram_size;
656 } else {
657 /*
658 * An arbitrary limit of 512MiB on surface
659 * memory. But all HWV8 hardware supports GMR2.
660 */
661 dev_priv->memory_size = 512*1024*1024;
fb17f189 662 }
6da768aa 663 dev_priv->max_mob_pages = 0;
857aea1c 664 dev_priv->max_mob_size = 0;
6da768aa
TH		 665 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
666 uint64_t mem_size =
667 vmw_read(dev_priv,
668 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
669
670 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
afb0e50f
TH		 671 dev_priv->prim_bb_mem =
672 vmw_read(dev_priv,
673 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
857aea1c
CL		 674 dev_priv->max_mob_size =
675 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
afb0e50f
TH		 676 } else
677 dev_priv->prim_bb_mem = dev_priv->vram_size;
fb1d9738 678
0d00c488 679 ret = vmw_dma_masks(dev_priv);
496eb6fd 680 if (unlikely(ret != 0))
0d00c488
TH		 681 goto out_err0;
682
9a72384d
SY		 683 /*
684 * Limit back buffer size to VRAM size. Remove this once
685 * screen targets are implemented.
686 */
687 if (dev_priv->prim_bb_mem > dev_priv->vram_size)
afb0e50f 688 dev_priv->prim_bb_mem = dev_priv->vram_size;
bc2d6508 689
fb1d9738
JB		 690 vmw_print_capabilities(dev_priv->capabilities);
691
0d00c488 692 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
fb1d9738
JB		 693 DRM_INFO("Max GMR ids is %u\n",
694 (unsigned)dev_priv->max_gmr_ids);
fb17f189
TH		 695 DRM_INFO("Max number of GMR pages is %u\n",
696 (unsigned)dev_priv->max_gmr_pages);
5bb39e81
TH		 697 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
698 (unsigned)dev_priv->memory_size / 1024);
fb17f189 699 }
bc2d6508
TH		 700 DRM_INFO("Maximum display memory size is %u kiB\n",
701 dev_priv->prim_bb_mem / 1024);
fb1d9738
JB		 702 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
703 dev_priv->vram_start, dev_priv->vram_size / 1024);
704 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
705 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
706
707 ret = vmw_ttm_global_init(dev_priv);
708 if (unlikely(ret != 0))
709 goto out_err0;
710
711
712 vmw_master_init(&dev_priv->fbdev_master);
713 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
714 dev_priv->active_master = &dev_priv->fbdev_master;
715
a2c06ee2 716
fb1d9738
JB		 717 ret = ttm_bo_device_init(&dev_priv->bdev,
718 dev_priv->bo_global_ref.ref.object,
44d847b7
DH		 719 &vmw_bo_driver,
720 dev->anon_inode->i_mapping,
721 VMWGFX_FILE_PAGE_OFFSET,
fb1d9738
JB		 722 false);
723 if (unlikely(ret != 0)) {
724 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
725 goto out_err1;
726 }
727
247d36d7
AL		 728 dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start,
729 dev_priv->mmio_size);
fb1d9738
JB		 730
731 dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
732 dev_priv->mmio_size);
733
734 if (unlikely(dev_priv->mmio_virt == NULL)) {
735 ret = -ENOMEM;
736 DRM_ERROR("Failed mapping MMIO.\n");
737 goto out_err3;
738 }
739
d7e1958d
JB		 740 /* Need mmio memory to check for fifo pitchlock cap. */
741 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
742 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
743 !vmw_fifo_have_pitchlock(dev_priv)) {
744 ret = -ENOSYS;
745 DRM_ERROR("Hardware has no pitchlock\n");
746 goto out_err4;
747 }
748
fb1d9738 749 dev_priv->tdev = ttm_object_device_init
69977ff5 750 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
fb1d9738
JB		 751
752 if (unlikely(dev_priv->tdev == NULL)) {
753 DRM_ERROR("Unable to initialize TTM object management.\n");
754 ret = -ENOMEM;
755 goto out_err4;
756 }
757
758 dev->dev_private = dev_priv;
759
fb1d9738
JB		 760 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
761 dev_priv->stealth = (ret != 0);
762 if (dev_priv->stealth) {
763 /**
764 * Request at least the mmio PCI resource.
765 */
766
767 DRM_INFO("It appears like vesafb is loaded. "
f2d12b8e 768 "Ignore above error if any.\n");
fb1d9738
JB		 769 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
770 if (unlikely(ret != 0)) {
771 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
772 goto out_no_device;
773 }
fb1d9738 774 }
ae2a1040 775
506ff75c 776 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
bb0f1b5c 777 ret = drm_irq_install(dev, dev->pdev->irq);
506ff75c
TH		 778 if (ret != 0) {
779 DRM_ERROR("Failed installing irq: %d\n", ret);
780 goto out_no_irq;
781 }
782 }
783
ae2a1040 784 dev_priv->fman = vmw_fence_manager_init(dev_priv);
14bbf20c
WY		 785 if (unlikely(dev_priv->fman == NULL)) {
786 ret = -ENOMEM;
ae2a1040 787 goto out_no_fman;
14bbf20c 788 }
56d1c78d 789
3458390b
TH		 790
791 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
792 (dev_priv->vram_size >> PAGE_SHIFT));
793 if (unlikely(ret != 0)) {
794 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
795 goto out_no_vram;
796 }
797
798 dev_priv->has_gmr = true;
799 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
800 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
801 VMW_PL_GMR) != 0) {
802 DRM_INFO("No GMR memory available. "
803 "Graphics memory resources are very limited.\n");
804 dev_priv->has_gmr = false;
805 }
806
807 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
808 dev_priv->has_mob = true;
809 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
810 VMW_PL_MOB) != 0) {
811 DRM_INFO("No MOB memory available. "
812 "3D will be disabled.\n");
813 dev_priv->has_mob = false;
814 }
815 }
816
56d1c78d 817 vmw_kms_save_vga(dev_priv);
56d1c78d
JB		 818
819 /* Start kms and overlay systems, needs fifo. */
7a1c2f6c
TH		 820 ret = vmw_kms_init(dev_priv);
821 if (unlikely(ret != 0))
822 goto out_no_kms;
f2d12b8e 823 vmw_overlay_init(dev_priv);
56d1c78d 824
30c78bb8 825 if (dev_priv->enable_fb) {
506ff75c
TH		 826 ret = vmw_3d_resource_inc(dev_priv, true);
827 if (unlikely(ret != 0))
828 goto out_no_fifo;
30c78bb8 829 vmw_fb_init(dev_priv);
7a1c2f6c
TH		 830 }
831
d9f36a00
TH		 832 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
833 register_pm_notifier(&dev_priv->pm_nb);
834
fb1d9738
JB		 835 return 0;
836
506ff75c 837out_no_fifo:
56d1c78d
JB		 838 vmw_overlay_close(dev_priv);
839 vmw_kms_close(dev_priv);
840out_no_kms:
506ff75c 841 vmw_kms_restore_vga(dev_priv);
3458390b
TH		 842 if (dev_priv->has_mob)
843 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
844 if (dev_priv->has_gmr)
845 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
846 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
847out_no_vram:
ae2a1040
TH		 848 vmw_fence_manager_takedown(dev_priv->fman);
849out_no_fman:
506ff75c
TH		 850 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
851 drm_irq_uninstall(dev_priv->dev);
852out_no_irq:
30c78bb8
TH		 853 if (dev_priv->stealth)
854 pci_release_region(dev->pdev, 2);
855 else
856 pci_release_regions(dev->pdev);
fb1d9738 857out_no_device:
fb1d9738
JB		 858 ttm_object_device_release(&dev_priv->tdev);
859out_err4:
860 iounmap(dev_priv->mmio_virt);
861out_err3:
247d36d7 862 arch_phys_wc_del(dev_priv->mmio_mtrr);
fb1d9738
JB		 863 (void)ttm_bo_device_release(&dev_priv->bdev);
864out_err1:
865 vmw_ttm_global_release(dev_priv);
866out_err0:
c0951b79
TH		 867 for (i = vmw_res_context; i < vmw_res_max; ++i)
868 idr_destroy(&dev_priv->res_idr[i]);
869
fb1d9738
JB		 870 kfree(dev_priv);
871 return ret;
872}
873
874static int vmw_driver_unload(struct drm_device *dev)
875{
876 struct vmw_private *dev_priv = vmw_priv(dev);
c0951b79 877 enum vmw_res_type i;
fb1d9738 878
d9f36a00
TH		 879 unregister_pm_notifier(&dev_priv->pm_nb);
880
c0951b79
TH		 881 if (dev_priv->ctx.res_ht_initialized)
882 drm_ht_remove(&dev_priv->ctx.res_ht);
a3a1a667 883 vfree(dev_priv->ctx.cmd_bounce);
30c78bb8
TH		 884 if (dev_priv->enable_fb) {
885 vmw_fb_close(dev_priv);
886 vmw_kms_restore_vga(dev_priv);
05730b32 887 vmw_3d_resource_dec(dev_priv, false);
30c78bb8 888 }
f2d12b8e
TH		 889 vmw_kms_close(dev_priv);
890 vmw_overlay_close(dev_priv);
3458390b
TH		 891
892 if (dev_priv->has_mob)
893 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
894 if (dev_priv->has_gmr)
895 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
896 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
897
ae2a1040 898 vmw_fence_manager_takedown(dev_priv->fman);
506ff75c
TH		 899 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
900 drm_irq_uninstall(dev_priv->dev);
f2d12b8e 901 if (dev_priv->stealth)
fb1d9738 902 pci_release_region(dev->pdev, 2);
f2d12b8e
TH		 903 else
904 pci_release_regions(dev->pdev);
905
fb1d9738
JB		 906 ttm_object_device_release(&dev_priv->tdev);
907 iounmap(dev_priv->mmio_virt);
247d36d7 908 arch_phys_wc_del(dev_priv->mmio_mtrr);
fb1d9738
JB		 909 (void)ttm_bo_device_release(&dev_priv->bdev);
910 vmw_ttm_global_release(dev_priv);
c0951b79
TH		 911
912 for (i = vmw_res_context; i < vmw_res_max; ++i)
913 idr_destroy(&dev_priv->res_idr[i]);
fb1d9738
JB		 914
915 kfree(dev_priv);
916
917 return 0;
918}
919
6b82ef50
TH		 920static void vmw_preclose(struct drm_device *dev,
921 struct drm_file *file_priv)
922{
923 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
924 struct vmw_private *dev_priv = vmw_priv(dev);
925
926 vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
927}
928
fb1d9738
JB		 929static void vmw_postclose(struct drm_device *dev,
930 struct drm_file *file_priv)
931{
932 struct vmw_fpriv *vmw_fp;
933
934 vmw_fp = vmw_fpriv(file_priv);
c4249855
TH		 935
936 if (vmw_fp->locked_master) {
937 struct vmw_master *vmaster =
938 vmw_master(vmw_fp->locked_master);
939
940 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
941 ttm_vt_unlock(&vmaster->lock);
fb1d9738 942 drm_master_put(&vmw_fp->locked_master);
c4249855
TH		 943 }
944
945 ttm_object_file_release(&vmw_fp->tfile);
fb1d9738
JB		 946 kfree(vmw_fp);
947}
948
949static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
950{
951 struct vmw_private *dev_priv = vmw_priv(dev);
952 struct vmw_fpriv *vmw_fp;
953 int ret = -ENOMEM;
954
955 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
956 if (unlikely(vmw_fp == NULL))
957 return ret;
958
6b82ef50 959 INIT_LIST_HEAD(&vmw_fp->fence_events);
fb1d9738
JB		 960 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
961 if (unlikely(vmw_fp->tfile == NULL))
962 goto out_no_tfile;
963
964 file_priv->driver_priv = vmw_fp;
fb1d9738
JB		 965
966 return 0;
967
968out_no_tfile:
969 kfree(vmw_fp);
970 return ret;
971}
972
64190bde
TH		 973static struct vmw_master *vmw_master_check(struct drm_device *dev,
974 struct drm_file *file_priv,
975 unsigned int flags)
976{
977 int ret;
978 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
979 struct vmw_master *vmaster;
980
981 if (file_priv->minor->type != DRM_MINOR_LEGACY ||
982 !(flags & DRM_AUTH))
983 return NULL;
984
985 ret = mutex_lock_interruptible(&dev->master_mutex);
986 if (unlikely(ret != 0))
987 return ERR_PTR(-ERESTARTSYS);
988
7963e9db 989 if (file_priv->is_master) {
64190bde
TH		 990 mutex_unlock(&dev->master_mutex);
991 return NULL;
992 }
993
994 /*
995 * Check if we were previously master, but now dropped.
996 */
997 if (vmw_fp->locked_master) {
998 mutex_unlock(&dev->master_mutex);
999 DRM_ERROR("Dropped master trying to access ioctl that "
1000 "requires authentication.\n");
1001 return ERR_PTR(-EACCES);
1002 }
1003 mutex_unlock(&dev->master_mutex);
1004
1005 /*
1006 * Taking the drm_global_mutex after the TTM lock might deadlock
1007 */
1008 if (!(flags & DRM_UNLOCKED)) {
1009 DRM_ERROR("Refusing locked ioctl access.\n");
1010 return ERR_PTR(-EDEADLK);
1011 }
1012
1013 /*
1014 * Take the TTM lock. Possibly sleep waiting for the authenticating
1015 * master to become master again, or for a SIGTERM if the
1016 * authenticating master exits.
1017 */
1018 vmaster = vmw_master(file_priv->master);
1019 ret = ttm_read_lock(&vmaster->lock, true);
1020 if (unlikely(ret != 0))
1021 vmaster = ERR_PTR(ret);
1022
1023 return vmaster;
1024}
1025
1026static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1027 unsigned long arg,
1028 long (*ioctl_func)(struct file *, unsigned int,
1029 unsigned long))
fb1d9738
JB		 1030{
1031 struct drm_file *file_priv = filp->private_data;
1032 struct drm_device *dev = file_priv->minor->dev;
1033 unsigned int nr = DRM_IOCTL_NR(cmd);
64190bde
TH		 1034 struct vmw_master *vmaster;
1035 unsigned int flags;
1036 long ret;
fb1d9738
JB		 1037
1038 /*
e1f78003 1039 * Do extra checking on driver private ioctls.
fb1d9738
JB		 1040 */
1041
1042 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1043 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
baa70943 1044 const struct drm_ioctl_desc *ioctl =
64190bde 1045 &vmw_ioctls[nr - DRM_COMMAND_BASE];
fb1d9738 1046
7e7392a6 1047 if (unlikely(ioctl->cmd != cmd)) {
fb1d9738
JB		 1048 DRM_ERROR("Invalid command format, ioctl %d\n",
1049 nr - DRM_COMMAND_BASE);
1050 return -EINVAL;
1051 }
64190bde
TH		 1052 flags = ioctl->flags;
1053 } else if (!drm_ioctl_flags(nr, &flags))
1054 return -EINVAL;
1055
1056 vmaster = vmw_master_check(dev, file_priv, flags);
1057 if (unlikely(IS_ERR(vmaster))) {
e338c4c2
TH		 1058 ret = PTR_ERR(vmaster);
1059
1060 if (ret != -ERESTARTSYS)
1061 DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n",
1062 nr, ret);
1063 return ret;
fb1d9738
JB		 1064 }
1065
64190bde
TH		 1066 ret = ioctl_func(filp, cmd, arg);
1067 if (vmaster)
1068 ttm_read_unlock(&vmaster->lock);
1069
1070 return ret;
1071}
1072
1073static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1074 unsigned long arg)
1075{
1076 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
fb1d9738
JB		 1077}
1078
64190bde
TH		 1079#ifdef CONFIG_COMPAT
1080static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1081 unsigned long arg)
1082{
1083 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1084}
1085#endif
1086
fb1d9738
JB		 1087static void vmw_lastclose(struct drm_device *dev)
1088{
fb1d9738
JB		 1089 struct drm_crtc *crtc;
1090 struct drm_mode_set set;
1091 int ret;
1092
fb1d9738
JB		 1093 set.x = 0;
1094 set.y = 0;
1095 set.fb = NULL;
1096 set.mode = NULL;
1097 set.connectors = NULL;
1098 set.num_connectors = 0;
1099
1100 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1101 set.crtc = crtc;
2d13b679 1102 ret = drm_mode_set_config_internal(&set);
fb1d9738
JB		 1103 WARN_ON(ret != 0);
1104 }
1105
1106}
1107
1108static void vmw_master_init(struct vmw_master *vmaster)
1109{
1110 ttm_lock_init(&vmaster->lock);
3a939a5e
TH		 1111 INIT_LIST_HEAD(&vmaster->fb_surf);
1112 mutex_init(&vmaster->fb_surf_mutex);
fb1d9738
JB		 1113}
1114
1115static int vmw_master_create(struct drm_device *dev,
1116 struct drm_master *master)
1117{
1118 struct vmw_master *vmaster;
1119
fb1d9738
JB		 1120 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1121 if (unlikely(vmaster == NULL))
1122 return -ENOMEM;
1123
3a939a5e 1124 vmw_master_init(vmaster);
fb1d9738
JB		 1125 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1126 master->driver_priv = vmaster;
1127
1128 return 0;
1129}
1130
1131static void vmw_master_destroy(struct drm_device *dev,
1132 struct drm_master *master)
1133{
1134 struct vmw_master *vmaster = vmw_master(master);
1135
fb1d9738
JB		 1136 master->driver_priv = NULL;
1137 kfree(vmaster);
1138}
1139
1140
1141static int vmw_master_set(struct drm_device *dev,
1142 struct drm_file *file_priv,
1143 bool from_open)
1144{
1145 struct vmw_private *dev_priv = vmw_priv(dev);
1146 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1147 struct vmw_master *active = dev_priv->active_master;
1148 struct vmw_master *vmaster = vmw_master(file_priv->master);
1149 int ret = 0;
1150
30c78bb8 1151 if (!dev_priv->enable_fb) {
05730b32 1152 ret = vmw_3d_resource_inc(dev_priv, true);
30c78bb8
TH		 1153 if (unlikely(ret != 0))
1154 return ret;
1155 vmw_kms_save_vga(dev_priv);
30c78bb8 1156 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
30c78bb8
TH		 1157 }
1158
fb1d9738
JB		 1159 if (active) {
1160 BUG_ON(active != &dev_priv->fbdev_master);
1161 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1162 if (unlikely(ret != 0))
1163 goto out_no_active_lock;
1164
1165 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1166 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1167 if (unlikely(ret != 0)) {
1168 DRM_ERROR("Unable to clean VRAM on "
1169 "master drop.\n");
1170 }
1171
1172 dev_priv->active_master = NULL;
1173 }
1174
1175 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1176 if (!from_open) {
1177 ttm_vt_unlock(&vmaster->lock);
1178 BUG_ON(vmw_fp->locked_master != file_priv->master);
1179 drm_master_put(&vmw_fp->locked_master);
1180 }
1181
1182 dev_priv->active_master = vmaster;
1183
1184 return 0;
1185
1186out_no_active_lock:
30c78bb8 1187 if (!dev_priv->enable_fb) {
ba723fe8
TH		 1188 vmw_kms_restore_vga(dev_priv);
1189 vmw_3d_resource_dec(dev_priv, true);
30c78bb8 1190 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
30c78bb8 1191 }
fb1d9738
JB		 1192 return ret;
1193}
1194
1195static void vmw_master_drop(struct drm_device *dev,
1196 struct drm_file *file_priv,
1197 bool from_release)
1198{
1199 struct vmw_private *dev_priv = vmw_priv(dev);
1200 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1201 struct vmw_master *vmaster = vmw_master(file_priv->master);
1202 int ret;
1203
fb1d9738
JB		 1204 /**
1205 * Make sure the master doesn't disappear while we have
1206 * it locked.
1207 */
1208
1209 vmw_fp->locked_master = drm_master_get(file_priv->master);
1210 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
fb1d9738
JB		 1211 if (unlikely((ret != 0))) {
1212 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1213 drm_master_put(&vmw_fp->locked_master);
1214 }
1215
c4249855
TH		 1216 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1217 vmw_execbuf_release_pinned_bo(dev_priv);
fb1d9738 1218
30c78bb8
TH		 1219 if (!dev_priv->enable_fb) {
1220 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1221 if (unlikely(ret != 0))
1222 DRM_ERROR("Unable to clean VRAM on master drop.\n");
ba723fe8
TH		 1223 vmw_kms_restore_vga(dev_priv);
1224 vmw_3d_resource_dec(dev_priv, true);
30c78bb8 1225 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
30c78bb8
TH		 1226 }
1227
fb1d9738
JB		 1228 dev_priv->active_master = &dev_priv->fbdev_master;
1229 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1230 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1231
30c78bb8
TH		 1232 if (dev_priv->enable_fb)
1233 vmw_fb_on(dev_priv);
fb1d9738
JB		 1234}
1235
1236
1237static void vmw_remove(struct pci_dev *pdev)
1238{
1239 struct drm_device *dev = pci_get_drvdata(pdev);
1240
fd3e4d6e 1241 pci_disable_device(pdev);
fb1d9738
JB		 1242 drm_put_dev(dev);
1243}
1244
d9f36a00
TH		 1245static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1246 void *ptr)
1247{
1248 struct vmw_private *dev_priv =
1249 container_of(nb, struct vmw_private, pm_nb);
d9f36a00
TH		 1250
1251 switch (val) {
1252 case PM_HIBERNATION_PREPARE:
1253 case PM_SUSPEND_PREPARE:
294adf7d 1254 ttm_suspend_lock(&dev_priv->reservation_sem);
d9f36a00
TH		 1255
1256 /**
1257 * This empties VRAM and unbinds all GMR bindings.
1258 * Buffer contents is moved to swappable memory.
1259 */
c0951b79
TH		 1260 vmw_execbuf_release_pinned_bo(dev_priv);
1261 vmw_resource_evict_all(dev_priv);
d9f36a00 1262 ttm_bo_swapout_all(&dev_priv->bdev);
094e0fa8 1263
d9f36a00
TH		 1264 break;
1265 case PM_POST_HIBERNATION:
1266 case PM_POST_SUSPEND:
094e0fa8 1267 case PM_POST_RESTORE:
294adf7d 1268 ttm_suspend_unlock(&dev_priv->reservation_sem);
094e0fa8 1269
d9f36a00
TH		 1270 break;
1271 case PM_RESTORE_PREPARE:
1272 break;
d9f36a00
TH		 1273 default:
1274 break;
1275 }
1276 return 0;
1277}
1278
1279/**
1280 * These might not be needed with the virtual SVGA device.
1281 */
1282
7fbd721a 1283static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
d9f36a00 1284{
094e0fa8
TH		 1285 struct drm_device *dev = pci_get_drvdata(pdev);
1286 struct vmw_private *dev_priv = vmw_priv(dev);
1287
1288 if (dev_priv->num_3d_resources != 0) {
1289 DRM_INFO("Can't suspend or hibernate "
1290 "while 3D resources are active.\n");
1291 return -EBUSY;
1292 }
1293
d9f36a00
TH		 1294 pci_save_state(pdev);
1295 pci_disable_device(pdev);
1296 pci_set_power_state(pdev, PCI_D3hot);
1297 return 0;
1298}
1299
7fbd721a 1300static int vmw_pci_resume(struct pci_dev *pdev)
d9f36a00
TH		 1301{
1302 pci_set_power_state(pdev, PCI_D0);
1303 pci_restore_state(pdev);
1304 return pci_enable_device(pdev);
1305}
1306
7fbd721a
TH		 1307static int vmw_pm_suspend(struct device *kdev)
1308{
1309 struct pci_dev *pdev = to_pci_dev(kdev);
1310 struct pm_message dummy;
1311
1312 dummy.event = 0;
1313
1314 return vmw_pci_suspend(pdev, dummy);
1315}
1316
1317static int vmw_pm_resume(struct device *kdev)
1318{
1319 struct pci_dev *pdev = to_pci_dev(kdev);
1320
1321 return vmw_pci_resume(pdev);
1322}
1323
1324static int vmw_pm_prepare(struct device *kdev)
1325{
1326 struct pci_dev *pdev = to_pci_dev(kdev);
1327 struct drm_device *dev = pci_get_drvdata(pdev);
1328 struct vmw_private *dev_priv = vmw_priv(dev);
1329
1330 /**
1331 * Release 3d reference held by fbdev and potentially
1332 * stop fifo.
1333 */
1334 dev_priv->suspended = true;
1335 if (dev_priv->enable_fb)
05730b32 1336 vmw_3d_resource_dec(dev_priv, true);
7fbd721a
TH		 1337
1338 if (dev_priv->num_3d_resources != 0) {
1339
1340 DRM_INFO("Can't suspend or hibernate "
1341 "while 3D resources are active.\n");
1342
1343 if (dev_priv->enable_fb)
05730b32 1344 vmw_3d_resource_inc(dev_priv, true);
7fbd721a
TH		 1345 dev_priv->suspended = false;
1346 return -EBUSY;
1347 }
1348
1349 return 0;
1350}
1351
1352static void vmw_pm_complete(struct device *kdev)
1353{
1354 struct pci_dev *pdev = to_pci_dev(kdev);
1355 struct drm_device *dev = pci_get_drvdata(pdev);
1356 struct vmw_private *dev_priv = vmw_priv(dev);
1357
95e8f6a2
TH		 1358 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1359 (void) vmw_read(dev_priv, SVGA_REG_ID);
95e8f6a2 1360
7fbd721a
TH		 1361 /**
1362 * Reclaim 3d reference held by fbdev and potentially
1363 * start fifo.
1364 */
1365 if (dev_priv->enable_fb)
05730b32 1366 vmw_3d_resource_inc(dev_priv, false);
7fbd721a
TH		 1367
1368 dev_priv->suspended = false;
1369}
1370
1371static const struct dev_pm_ops vmw_pm_ops = {
1372 .prepare = vmw_pm_prepare,
1373 .complete = vmw_pm_complete,
1374 .suspend = vmw_pm_suspend,
1375 .resume = vmw_pm_resume,
1376};
1377
e08e96de
AV		 1378static const struct file_operations vmwgfx_driver_fops = {
1379 .owner = THIS_MODULE,
1380 .open = drm_open,
1381 .release = drm_release,
1382 .unlocked_ioctl = vmw_unlocked_ioctl,
1383 .mmap = vmw_mmap,
1384 .poll = vmw_fops_poll,
1385 .read = vmw_fops_read,
e08e96de 1386#if defined(CONFIG_COMPAT)
64190bde 1387 .compat_ioctl = vmw_compat_ioctl,
e08e96de
AV		 1388#endif
1389 .llseek = noop_llseek,
1390};
1391
fb1d9738
JB		 1392static struct drm_driver driver = {
1393 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
03f80263 1394 DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER,
fb1d9738
JB		 1395 .load = vmw_driver_load,
1396 .unload = vmw_driver_unload,
fb1d9738
JB		 1397 .lastclose = vmw_lastclose,
1398 .irq_preinstall = vmw_irq_preinstall,
1399 .irq_postinstall = vmw_irq_postinstall,
1400 .irq_uninstall = vmw_irq_uninstall,
1401 .irq_handler = vmw_irq_handler,
7a1c2f6c 1402 .get_vblank_counter = vmw_get_vblank_counter,
1c482ab3
JB		 1403 .enable_vblank = vmw_enable_vblank,
1404 .disable_vblank = vmw_disable_vblank,
fb1d9738 1405 .ioctls = vmw_ioctls,
f95aeb17 1406 .num_ioctls = ARRAY_SIZE(vmw_ioctls),
fb1d9738
JB		 1407 .master_create = vmw_master_create,
1408 .master_destroy = vmw_master_destroy,
1409 .master_set = vmw_master_set,
1410 .master_drop = vmw_master_drop,
1411 .open = vmw_driver_open,
6b82ef50 1412 .preclose = vmw_preclose,
fb1d9738 1413 .postclose = vmw_postclose,
915b4d11 1414 .set_busid = drm_pci_set_busid,
5e1782d2
DA		 1415
1416 .dumb_create = vmw_dumb_create,
1417 .dumb_map_offset = vmw_dumb_map_offset,
1418 .dumb_destroy = vmw_dumb_destroy,
1419
69977ff5
TH		 1420 .prime_fd_to_handle = vmw_prime_fd_to_handle,
1421 .prime_handle_to_fd = vmw_prime_handle_to_fd,
1422
e08e96de 1423 .fops = &vmwgfx_driver_fops,
fb1d9738
JB		 1424 .name = VMWGFX_DRIVER_NAME,
1425 .desc = VMWGFX_DRIVER_DESC,
1426 .date = VMWGFX_DRIVER_DATE,
1427 .major = VMWGFX_DRIVER_MAJOR,
1428 .minor = VMWGFX_DRIVER_MINOR,
1429 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1430};
1431
8410ea3b
DA		 1432static struct pci_driver vmw_pci_driver = {
1433 .name = VMWGFX_DRIVER_NAME,
1434 .id_table = vmw_pci_id_list,
1435 .probe = vmw_probe,
1436 .remove = vmw_remove,
1437 .driver = {
1438 .pm = &vmw_pm_ops
1439 }
1440};
1441
fb1d9738
JB		 1442static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1443{
dcdb1674 1444 return drm_get_pci_dev(pdev, ent, &driver);
fb1d9738
JB		 1445}
1446
1447static int __init vmwgfx_init(void)
1448{
1449 int ret;
8410ea3b 1450 ret = drm_pci_init(&driver, &vmw_pci_driver);
fb1d9738
JB		 1451 if (ret)
1452 DRM_ERROR("Failed initializing DRM.\n");
1453 return ret;
1454}
1455
1456static void __exit vmwgfx_exit(void)
1457{
8410ea3b 1458 drm_pci_exit(&driver, &vmw_pci_driver);
fb1d9738
JB		 1459}
1460
1461module_init(vmwgfx_init);
1462module_exit(vmwgfx_exit);
1463
1464MODULE_AUTHOR("VMware Inc. and others");
1465MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1466MODULE_LICENSE("GPL and additional rights");
73558ead
TH		 1467MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1468 __stringify(VMWGFX_DRIVER_MINOR) "."
1469 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1470 "0");
Linux kernel - Deliverables
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