projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/vmwgfx: Make sure that the multisampling is off
[deliverable/linux.git] / drivers / gpu / drm / vmwgfx / vmwgfx_drv.c
CommitLineData
fb1d9738
JB		 1/**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
e0cd3608 27#include <linux/module.h>
fb1d9738 28
760285e7 29#include <drm/drmP.h>
fb1d9738 30#include "vmwgfx_drv.h"
760285e7
DH		 31#include <drm/ttm/ttm_placement.h>
32#include <drm/ttm/ttm_bo_driver.h>
33#include <drm/ttm/ttm_object.h>
34#include <drm/ttm/ttm_module.h>
d92d9851 35#include <linux/dma_remapping.h>
fb1d9738
JB		 36
37#define VMWGFX_DRIVER_NAME "vmwgfx"
38#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
39#define VMWGFX_CHIP_SVGAII 0
40#define VMW_FB_RESERVATION 0
41
eb4f923b
JB		 42#define VMW_MIN_INITIAL_WIDTH 800
43#define VMW_MIN_INITIAL_HEIGHT 600
44
45
fb1d9738
JB		 46/**
47 * Fully encoded drm commands. Might move to vmw_drm.h
48 */
49
50#define DRM_IOCTL_VMW_GET_PARAM \
51 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
52 struct drm_vmw_getparam_arg)
53#define DRM_IOCTL_VMW_ALLOC_DMABUF \
54 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
55 union drm_vmw_alloc_dmabuf_arg)
56#define DRM_IOCTL_VMW_UNREF_DMABUF \
57 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
58 struct drm_vmw_unref_dmabuf_arg)
59#define DRM_IOCTL_VMW_CURSOR_BYPASS \
60 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
61 struct drm_vmw_cursor_bypass_arg)
62
63#define DRM_IOCTL_VMW_CONTROL_STREAM \
64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
65 struct drm_vmw_control_stream_arg)
66#define DRM_IOCTL_VMW_CLAIM_STREAM \
67 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
68 struct drm_vmw_stream_arg)
69#define DRM_IOCTL_VMW_UNREF_STREAM \
70 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
71 struct drm_vmw_stream_arg)
72
73#define DRM_IOCTL_VMW_CREATE_CONTEXT \
74 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
75 struct drm_vmw_context_arg)
76#define DRM_IOCTL_VMW_UNREF_CONTEXT \
77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
78 struct drm_vmw_context_arg)
79#define DRM_IOCTL_VMW_CREATE_SURFACE \
80 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
81 union drm_vmw_surface_create_arg)
82#define DRM_IOCTL_VMW_UNREF_SURFACE \
83 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
84 struct drm_vmw_surface_arg)
85#define DRM_IOCTL_VMW_REF_SURFACE \
86 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
87 union drm_vmw_surface_reference_arg)
88#define DRM_IOCTL_VMW_EXECBUF \
89 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
90 struct drm_vmw_execbuf_arg)
ae2a1040
TH		 91#define DRM_IOCTL_VMW_GET_3D_CAP \
92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
93 struct drm_vmw_get_3d_cap_arg)
fb1d9738
JB		 94#define DRM_IOCTL_VMW_FENCE_WAIT \
95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
96 struct drm_vmw_fence_wait_arg)
ae2a1040
TH		 97#define DRM_IOCTL_VMW_FENCE_SIGNALED \
98 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
99 struct drm_vmw_fence_signaled_arg)
100#define DRM_IOCTL_VMW_FENCE_UNREF \
101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
102 struct drm_vmw_fence_arg)
57c5ee79
TH		 103#define DRM_IOCTL_VMW_FENCE_EVENT \
104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
105 struct drm_vmw_fence_event_arg)
2fcd5a73
JB		 106#define DRM_IOCTL_VMW_PRESENT \
107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
108 struct drm_vmw_present_arg)
109#define DRM_IOCTL_VMW_PRESENT_READBACK \
110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
111 struct drm_vmw_present_readback_arg)
cd2b89e7
TH		 112#define DRM_IOCTL_VMW_UPDATE_LAYOUT \
113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
114 struct drm_vmw_update_layout_arg)
c74c162f
TH		 115#define DRM_IOCTL_VMW_CREATE_SHADER \
116 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
117 struct drm_vmw_shader_create_arg)
118#define DRM_IOCTL_VMW_UNREF_SHADER \
119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
120 struct drm_vmw_shader_arg)
a97e2192
TH		 121#define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
122 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
123 union drm_vmw_gb_surface_create_arg)
124#define DRM_IOCTL_VMW_GB_SURFACE_REF \
125 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
126 union drm_vmw_gb_surface_reference_arg)
fb1d9738
JB		 127
128/**
129 * The core DRM version of this macro doesn't account for
130 * DRM_COMMAND_BASE.
131 */
132
133#define VMW_IOCTL_DEF(ioctl, func, flags) \
1b2f1489 134 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
fb1d9738
JB		 135
136/**
137 * Ioctl definitions.
138 */
139
baa70943 140static const struct drm_ioctl_desc vmw_ioctls[] = {
1b2f1489 141 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
e1f78003 142 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 143 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
e1f78003 144 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 145 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
e1f78003 146 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 147 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
e1f78003
TH		 148 vmw_kms_cursor_bypass_ioctl,
149 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
fb1d9738 150
1b2f1489 151 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
e1f78003 152 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
1b2f1489 153 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
e1f78003 154 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
1b2f1489 155 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
e1f78003 156 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
fb1d9738 157
1b2f1489 158 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
e1f78003 159 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 160 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
e1f78003 161 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 162 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
e1f78003 163 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 164 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
e1f78003 165 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 166 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
e1f78003 167 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 168 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
e1f78003 169 DRM_AUTH | DRM_UNLOCKED),
ae2a1040
TH		 170 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
171 DRM_AUTH | DRM_UNLOCKED),
172 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
173 vmw_fence_obj_signaled_ioctl,
174 DRM_AUTH | DRM_UNLOCKED),
175 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
d8bd19d2 176 DRM_AUTH | DRM_UNLOCKED),
57c5ee79
TH		 177 VMW_IOCTL_DEF(VMW_FENCE_EVENT,
178 vmw_fence_event_ioctl,
179 DRM_AUTH | DRM_UNLOCKED),
f63f6a59
TH		 180 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
181 DRM_AUTH | DRM_UNLOCKED),
2fcd5a73
JB		 182
183 /* these allow direct access to the framebuffers mark as master only */
184 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
185 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
186 VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
187 vmw_present_readback_ioctl,
188 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
cd2b89e7
TH		 189 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
190 vmw_kms_update_layout_ioctl,
191 DRM_MASTER | DRM_UNLOCKED),
c74c162f
TH		 192 VMW_IOCTL_DEF(VMW_CREATE_SHADER,
193 vmw_shader_define_ioctl,
194 DRM_AUTH | DRM_UNLOCKED),
195 VMW_IOCTL_DEF(VMW_UNREF_SHADER,
196 vmw_shader_destroy_ioctl,
197 DRM_AUTH | DRM_UNLOCKED),
a97e2192
TH		 198 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
199 vmw_gb_surface_define_ioctl,
200 DRM_AUTH | DRM_UNLOCKED),
201 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
202 vmw_gb_surface_reference_ioctl,
203 DRM_AUTH | DRM_UNLOCKED),
fb1d9738
JB		 204};
205
206static struct pci_device_id vmw_pci_id_list[] = {
207 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
208 {0, 0, 0}
209};
c4903429 210MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
fb1d9738 211
5d2afab9 212static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
d92d9851
TH		 213static int vmw_force_iommu;
214static int vmw_restrict_iommu;
215static int vmw_force_coherent;
0d00c488 216static int vmw_restrict_dma_mask;
fb1d9738
JB		 217
218static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
219static void vmw_master_init(struct vmw_master *);
d9f36a00
TH		 220static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
221 void *ptr);
fb1d9738 222
30c78bb8
TH		 223MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
224module_param_named(enable_fbdev, enable_fbdev, int, 0600);
d92d9851
TH		 225MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
226module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
227MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
228module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
229MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
230module_param_named(force_coherent, vmw_force_coherent, int, 0600);
0d00c488
TH		 231MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
232module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
d92d9851 233
30c78bb8 234
fb1d9738
JB		 235static void vmw_print_capabilities(uint32_t capabilities)
236{
237 DRM_INFO("Capabilities:\n");
238 if (capabilities & SVGA_CAP_RECT_COPY)
239 DRM_INFO(" Rect copy.\n");
240 if (capabilities & SVGA_CAP_CURSOR)
241 DRM_INFO(" Cursor.\n");
242 if (capabilities & SVGA_CAP_CURSOR_BYPASS)
243 DRM_INFO(" Cursor bypass.\n");
244 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
245 DRM_INFO(" Cursor bypass 2.\n");
246 if (capabilities & SVGA_CAP_8BIT_EMULATION)
247 DRM_INFO(" 8bit emulation.\n");
248 if (capabilities & SVGA_CAP_ALPHA_CURSOR)
249 DRM_INFO(" Alpha cursor.\n");
250 if (capabilities & SVGA_CAP_3D)
251 DRM_INFO(" 3D.\n");
252 if (capabilities & SVGA_CAP_EXTENDED_FIFO)
253 DRM_INFO(" Extended Fifo.\n");
254 if (capabilities & SVGA_CAP_MULTIMON)
255 DRM_INFO(" Multimon.\n");
256 if (capabilities & SVGA_CAP_PITCHLOCK)
257 DRM_INFO(" Pitchlock.\n");
258 if (capabilities & SVGA_CAP_IRQMASK)
259 DRM_INFO(" Irq mask.\n");
260 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
261 DRM_INFO(" Display Topology.\n");
262 if (capabilities & SVGA_CAP_GMR)
263 DRM_INFO(" GMR.\n");
264 if (capabilities & SVGA_CAP_TRACES)
265 DRM_INFO(" Traces.\n");
dcca2862
TH		 266 if (capabilities & SVGA_CAP_GMR2)
267 DRM_INFO(" GMR2.\n");
268 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
269 DRM_INFO(" Screen Object 2.\n");
c1234db7
TH		 270 if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
271 DRM_INFO(" Command Buffers.\n");
272 if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
273 DRM_INFO(" Command Buffers 2.\n");
274 if (capabilities & SVGA_CAP_GBOBJECTS)
275 DRM_INFO(" Guest Backed Resources.\n");
fb1d9738
JB		 276}
277
e2fa3a76
TH		 278
279/**
280 * vmw_execbuf_prepare_dummy_query - Initialize a query result structure at
281 * the start of a buffer object.
282 *
283 * @dev_priv: The device private structure.
284 *
285 * This function will idle the buffer using an uninterruptible wait, then
286 * map the first page and initialize a pending occlusion query result structure,
287 * Finally it will unmap the buffer.
288 *
289 * TODO: Since we're only mapping a single page, we should optimize the map
290 * to use kmap_atomic / iomap_atomic.
291 */
292static void vmw_dummy_query_bo_prepare(struct vmw_private *dev_priv)
293{
294 struct ttm_bo_kmap_obj map;
295 volatile SVGA3dQueryResult *result;
296 bool dummy;
297 int ret;
298 struct ttm_bo_device *bdev = &dev_priv->bdev;
299 struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
300
301 ttm_bo_reserve(bo, false, false, false, 0);
302 spin_lock(&bdev->fence_lock);
1717c0e2 303 ret = ttm_bo_wait(bo, false, false, false);
e2fa3a76
TH		 304 spin_unlock(&bdev->fence_lock);
305 if (unlikely(ret != 0))
306 (void) vmw_fallback_wait(dev_priv, false, true, 0, false,
307 10*HZ);
308
309 ret = ttm_bo_kmap(bo, 0, 1, &map);
310 if (likely(ret == 0)) {
311 result = ttm_kmap_obj_virtual(&map, &dummy);
312 result->totalSize = sizeof(*result);
313 result->state = SVGA3D_QUERYSTATE_PENDING;
314 result->result32 = 0xff;
315 ttm_bo_kunmap(&map);
316 } else
317 DRM_ERROR("Dummy query buffer map failed.\n");
318 ttm_bo_unreserve(bo);
319}
320
321
322/**
323 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
324 *
325 * @dev_priv: A device private structure.
326 *
327 * This function creates a small buffer object that holds the query
328 * result for dummy queries emitted as query barriers.
329 * No interruptible waits are done within this function.
330 *
331 * Returns an error if bo creation fails.
332 */
333static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
334{
335 return ttm_bo_create(&dev_priv->bdev,
336 PAGE_SIZE,
337 ttm_bo_type_device,
338 &vmw_vram_sys_placement,
0b91c4a1 339 0, false, NULL,
e2fa3a76
TH		 340 &dev_priv->dummy_query_bo);
341}
342
343
fb1d9738
JB		 344static int vmw_request_device(struct vmw_private *dev_priv)
345{
346 int ret;
347
fb1d9738
JB		 348 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
349 if (unlikely(ret != 0)) {
350 DRM_ERROR("Unable to initialize FIFO.\n");
351 return ret;
352 }
ae2a1040 353 vmw_fence_fifo_up(dev_priv->fman);
3530bdc3
TH		 354 if (dev_priv->has_mob) {
355 ret = vmw_otables_setup(dev_priv);
356 if (unlikely(ret != 0)) {
357 DRM_ERROR("Unable to initialize "
358 "guest Memory OBjects.\n");
359 goto out_no_mob;
360 }
361 }
e2fa3a76
TH		 362 ret = vmw_dummy_query_bo_create(dev_priv);
363 if (unlikely(ret != 0))
364 goto out_no_query_bo;
365 vmw_dummy_query_bo_prepare(dev_priv);
fb1d9738
JB		 366
367 return 0;
e2fa3a76
TH		 368
369out_no_query_bo:
3530bdc3
TH		 370 if (dev_priv->has_mob)
371 vmw_otables_takedown(dev_priv);
372out_no_mob:
e2fa3a76
TH		 373 vmw_fence_fifo_down(dev_priv->fman);
374 vmw_fifo_release(dev_priv, &dev_priv->fifo);
375 return ret;
fb1d9738
JB		 376}
377
378static void vmw_release_device(struct vmw_private *dev_priv)
379{
e2fa3a76
TH		 380 /*
381 * Previous destructions should've released
382 * the pinned bo.
383 */
384
385 BUG_ON(dev_priv->pinned_bo != NULL);
386
387 ttm_bo_unref(&dev_priv->dummy_query_bo);
3530bdc3
TH		 388 if (dev_priv->has_mob)
389 vmw_otables_takedown(dev_priv);
ae2a1040 390 vmw_fence_fifo_down(dev_priv->fman);
fb1d9738 391 vmw_fifo_release(dev_priv, &dev_priv->fifo);
30c78bb8
TH		 392}
393
3530bdc3 394
05730b32
TH		 395/**
396 * Increase the 3d resource refcount.
397 * If the count was prevously zero, initialize the fifo, switching to svga
398 * mode. Note that the master holds a ref as well, and may request an
399 * explicit switch to svga mode if fb is not running, using @unhide_svga.
400 */
401int vmw_3d_resource_inc(struct vmw_private *dev_priv,
402 bool unhide_svga)
30c78bb8
TH		 403{
404 int ret = 0;
405
406 mutex_lock(&dev_priv->release_mutex);
407 if (unlikely(dev_priv->num_3d_resources++ == 0)) {
408 ret = vmw_request_device(dev_priv);
409 if (unlikely(ret != 0))
410 --dev_priv->num_3d_resources;
05730b32
TH		 411 } else if (unhide_svga) {
412 mutex_lock(&dev_priv->hw_mutex);
413 vmw_write(dev_priv, SVGA_REG_ENABLE,
414 vmw_read(dev_priv, SVGA_REG_ENABLE) &
415 ~SVGA_REG_ENABLE_HIDE);
416 mutex_unlock(&dev_priv->hw_mutex);
30c78bb8 417 }
05730b32 418
30c78bb8
TH		 419 mutex_unlock(&dev_priv->release_mutex);
420 return ret;
fb1d9738
JB		 421}
422
05730b32
TH		 423/**
424 * Decrease the 3d resource refcount.
425 * If the count reaches zero, disable the fifo, switching to vga mode.
426 * Note that the master holds a refcount as well, and may request an
427 * explicit switch to vga mode when it releases its refcount to account
428 * for the situation of an X server vt switch to VGA with 3d resources
429 * active.
430 */
431void vmw_3d_resource_dec(struct vmw_private *dev_priv,
432 bool hide_svga)
30c78bb8
TH		 433{
434 int32_t n3d;
435
436 mutex_lock(&dev_priv->release_mutex);
437 if (unlikely(--dev_priv->num_3d_resources == 0))
438 vmw_release_device(dev_priv);
05730b32
TH		 439 else if (hide_svga) {
440 mutex_lock(&dev_priv->hw_mutex);
441 vmw_write(dev_priv, SVGA_REG_ENABLE,
442 vmw_read(dev_priv, SVGA_REG_ENABLE) |
443 SVGA_REG_ENABLE_HIDE);
444 mutex_unlock(&dev_priv->hw_mutex);
445 }
446
30c78bb8
TH		 447 n3d = (int32_t) dev_priv->num_3d_resources;
448 mutex_unlock(&dev_priv->release_mutex);
449
450 BUG_ON(n3d < 0);
451}
452
eb4f923b
JB		 453/**
454 * Sets the initial_[width|height] fields on the given vmw_private.
455 *
456 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
67d4a87b
TH		 457 * clamping the value to fb_max_[width|height] fields and the
458 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
459 * If the values appear to be invalid, set them to
eb4f923b
JB		 460 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
461 */
462static void vmw_get_initial_size(struct vmw_private *dev_priv)
463{
464 uint32_t width;
465 uint32_t height;
466
467 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
468 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
469
470 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
eb4f923b 471 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
67d4a87b
TH		 472
473 if (width > dev_priv->fb_max_width ||
474 height > dev_priv->fb_max_height) {
475
476 /*
477 * This is a host error and shouldn't occur.
478 */
479
480 width = VMW_MIN_INITIAL_WIDTH;
481 height = VMW_MIN_INITIAL_HEIGHT;
482 }
eb4f923b
JB		 483
484 dev_priv->initial_width = width;
485 dev_priv->initial_height = height;
486}
487
d92d9851
TH		 488/**
489 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
490 * system.
491 *
492 * @dev_priv: Pointer to a struct vmw_private
493 *
494 * This functions tries to determine the IOMMU setup and what actions
495 * need to be taken by the driver to make system pages visible to the
496 * device.
497 * If this function decides that DMA is not possible, it returns -EINVAL.
498 * The driver may then try to disable features of the device that require
499 * DMA.
500 */
501static int vmw_dma_select_mode(struct vmw_private *dev_priv)
502{
d92d9851
TH		 503 static const char *names[vmw_dma_map_max] = {
504 [vmw_dma_phys] = "Using physical TTM page addresses.",
505 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
506 [vmw_dma_map_populate] = "Keeping DMA mappings.",
507 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
e14cd953
TH		 508#ifdef CONFIG_X86
509 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
d92d9851
TH		 510
511#ifdef CONFIG_INTEL_IOMMU
512 if (intel_iommu_enabled) {
513 dev_priv->map_mode = vmw_dma_map_populate;
514 goto out_fixup;
515 }
516#endif
517
518 if (!(vmw_force_iommu || vmw_force_coherent)) {
519 dev_priv->map_mode = vmw_dma_phys;
520 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
521 return 0;
522 }
523
524 dev_priv->map_mode = vmw_dma_map_populate;
525
526 if (dma_ops->sync_single_for_cpu)
527 dev_priv->map_mode = vmw_dma_alloc_coherent;
528#ifdef CONFIG_SWIOTLB
529 if (swiotlb_nr_tbl() == 0)
530 dev_priv->map_mode = vmw_dma_map_populate;
531#endif
532
21136946 533#ifdef CONFIG_INTEL_IOMMU
d92d9851 534out_fixup:
21136946 535#endif
d92d9851
TH		 536 if (dev_priv->map_mode == vmw_dma_map_populate &&
537 vmw_restrict_iommu)
538 dev_priv->map_mode = vmw_dma_map_bind;
539
540 if (vmw_force_coherent)
541 dev_priv->map_mode = vmw_dma_alloc_coherent;
542
543#if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
544 /*
545 * No coherent page pool
546 */
547 if (dev_priv->map_mode == vmw_dma_alloc_coherent)
548 return -EINVAL;
549#endif
550
e14cd953
TH		 551#else /* CONFIG_X86 */
552 dev_priv->map_mode = vmw_dma_map_populate;
553#endif /* CONFIG_X86 */
554
d92d9851
TH		 555 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
556
557 return 0;
558}
559
0d00c488
TH		 560/**
561 * vmw_dma_masks - set required page- and dma masks
562 *
563 * @dev: Pointer to struct drm-device
564 *
565 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
566 * restriction also for 64-bit systems.
567 */
568#ifdef CONFIG_INTEL_IOMMU
569static int vmw_dma_masks(struct vmw_private *dev_priv)
570{
571 struct drm_device *dev = dev_priv->dev;
572
573 if (intel_iommu_enabled &&
574 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
575 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
576 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
577 }
578 return 0;
579}
580#else
581static int vmw_dma_masks(struct vmw_private *dev_priv)
582{
583 return 0;
584}
585#endif
586
fb1d9738
JB		 587static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
588{
589 struct vmw_private *dev_priv;
590 int ret;
c188660f 591 uint32_t svga_id;
c0951b79 592 enum vmw_res_type i;
d92d9851 593 bool refuse_dma = false;
fb1d9738
JB		 594
595 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
596 if (unlikely(dev_priv == NULL)) {
597 DRM_ERROR("Failed allocating a device private struct.\n");
598 return -ENOMEM;
599 }
fb1d9738 600
466e69b8
DA		 601 pci_set_master(dev->pdev);
602
fb1d9738
JB		 603 dev_priv->dev = dev;
604 dev_priv->vmw_chipset = chipset;
6bcd8d3c 605 dev_priv->last_read_seqno = (uint32_t) -100;
fb1d9738
JB		 606 mutex_init(&dev_priv->hw_mutex);
607 mutex_init(&dev_priv->cmdbuf_mutex);
30c78bb8 608 mutex_init(&dev_priv->release_mutex);
fb1d9738 609 rwlock_init(&dev_priv->resource_lock);
c0951b79
TH		 610
611 for (i = vmw_res_context; i < vmw_res_max; ++i) {
612 idr_init(&dev_priv->res_idr[i]);
613 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
614 }
615
fb1d9738
JB		 616 mutex_init(&dev_priv->init_mutex);
617 init_waitqueue_head(&dev_priv->fence_queue);
618 init_waitqueue_head(&dev_priv->fifo_queue);
4f73a96b 619 dev_priv->fence_queue_waiters = 0;
fb1d9738 620 atomic_set(&dev_priv->fifo_queue_waiters, 0);
c0951b79 621
5bb39e81 622 dev_priv->used_memory_size = 0;
fb1d9738
JB		 623
624 dev_priv->io_start = pci_resource_start(dev->pdev, 0);
625 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
626 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
627
30c78bb8
TH		 628 dev_priv->enable_fb = enable_fbdev;
629
fb1d9738 630 mutex_lock(&dev_priv->hw_mutex);
c188660f
PH		 631
632 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
633 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
634 if (svga_id != SVGA_ID_2) {
635 ret = -ENOSYS;
49625904 636 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
c188660f
PH		 637 mutex_unlock(&dev_priv->hw_mutex);
638 goto out_err0;
639 }
640
fb1d9738 641 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
d92d9851
TH		 642 ret = vmw_dma_select_mode(dev_priv);
643 if (unlikely(ret != 0)) {
644 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
645 refuse_dma = true;
646 }
fb1d9738 647
5bb39e81
TH		 648 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
649 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
650 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
651 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
eb4f923b
JB		 652
653 vmw_get_initial_size(dev_priv);
654
0d00c488 655 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
fb1d9738
JB		 656 dev_priv->max_gmr_ids =
657 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
fb17f189
TH		 658 dev_priv->max_gmr_pages =
659 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
660 dev_priv->memory_size =
661 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
5bb39e81
TH		 662 dev_priv->memory_size -= dev_priv->vram_size;
663 } else {
664 /*
665 * An arbitrary limit of 512MiB on surface
666 * memory. But all HWV8 hardware supports GMR2.
667 */
668 dev_priv->memory_size = 512*1024*1024;
fb17f189 669 }
6da768aa
TH		 670 dev_priv->max_mob_pages = 0;
671 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
672 uint64_t mem_size =
673 vmw_read(dev_priv,
674 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
675
676 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
afb0e50f
TH		 677 dev_priv->prim_bb_mem =
678 vmw_read(dev_priv,
679 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
680 } else
681 dev_priv->prim_bb_mem = dev_priv->vram_size;
fb1d9738 682
0d00c488
TH		 683 ret = vmw_dma_masks(dev_priv);
684 if (unlikely(ret != 0))
685 goto out_err0;
686
afb0e50f
TH		 687 if (unlikely(dev_priv->prim_bb_mem < dev_priv->vram_size))
688 dev_priv->prim_bb_mem = dev_priv->vram_size;
bc2d6508 689
fb1d9738
JB		 690 mutex_unlock(&dev_priv->hw_mutex);
691
692 vmw_print_capabilities(dev_priv->capabilities);
693
0d00c488 694 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
fb1d9738
JB		 695 DRM_INFO("Max GMR ids is %u\n",
696 (unsigned)dev_priv->max_gmr_ids);
fb17f189
TH		 697 DRM_INFO("Max number of GMR pages is %u\n",
698 (unsigned)dev_priv->max_gmr_pages);
5bb39e81
TH		 699 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
700 (unsigned)dev_priv->memory_size / 1024);
fb17f189 701 }
bc2d6508
TH		 702 DRM_INFO("Maximum display memory size is %u kiB\n",
703 dev_priv->prim_bb_mem / 1024);
fb1d9738
JB		 704 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
705 dev_priv->vram_start, dev_priv->vram_size / 1024);
706 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
707 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
708
709 ret = vmw_ttm_global_init(dev_priv);
710 if (unlikely(ret != 0))
711 goto out_err0;
712
713
714 vmw_master_init(&dev_priv->fbdev_master);
715 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
716 dev_priv->active_master = &dev_priv->fbdev_master;
717
a2c06ee2 718
fb1d9738
JB		 719 ret = ttm_bo_device_init(&dev_priv->bdev,
720 dev_priv->bo_global_ref.ref.object,
721 &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET,
722 false);
723 if (unlikely(ret != 0)) {
724 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
725 goto out_err1;
726 }
727
728 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
729 (dev_priv->vram_size >> PAGE_SHIFT));
730 if (unlikely(ret != 0)) {
731 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
732 goto out_err2;
733 }
734
135cba0d 735 dev_priv->has_gmr = true;
d92d9851
TH		 736 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
737 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
6da768aa 738 VMW_PL_GMR) != 0) {
135cba0d
TH		 739 DRM_INFO("No GMR memory available. "
740 "Graphics memory resources are very limited.\n");
741 dev_priv->has_gmr = false;
742 }
743
6da768aa 744 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
3530bdc3 745 dev_priv->has_mob = true;
6da768aa
TH		 746 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
747 VMW_PL_MOB) != 0) {
748 DRM_INFO("No MOB memory available. "
749 "3D will be disabled.\n");
750 dev_priv->has_mob = false;
751 }
752 }
3530bdc3 753
247d36d7
AL		 754 dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start,
755 dev_priv->mmio_size);
fb1d9738
JB		 756
757 dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
758 dev_priv->mmio_size);
759
760 if (unlikely(dev_priv->mmio_virt == NULL)) {
761 ret = -ENOMEM;
762 DRM_ERROR("Failed mapping MMIO.\n");
763 goto out_err3;
764 }
765
d7e1958d
JB		 766 /* Need mmio memory to check for fifo pitchlock cap. */
767 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
768 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
769 !vmw_fifo_have_pitchlock(dev_priv)) {
770 ret = -ENOSYS;
771 DRM_ERROR("Hardware has no pitchlock\n");
772 goto out_err4;
773 }
774
fb1d9738 775 dev_priv->tdev = ttm_object_device_init
69977ff5 776 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
fb1d9738
JB		 777
778 if (unlikely(dev_priv->tdev == NULL)) {
779 DRM_ERROR("Unable to initialize TTM object management.\n");
780 ret = -ENOMEM;
781 goto out_err4;
782 }
783
784 dev->dev_private = dev_priv;
785
fb1d9738
JB		 786 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
787 dev_priv->stealth = (ret != 0);
788 if (dev_priv->stealth) {
789 /**
790 * Request at least the mmio PCI resource.
791 */
792
793 DRM_INFO("It appears like vesafb is loaded. "
f2d12b8e 794 "Ignore above error if any.\n");
fb1d9738
JB		 795 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
796 if (unlikely(ret != 0)) {
797 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
798 goto out_no_device;
799 }
fb1d9738 800 }
ae2a1040 801
506ff75c
TH		 802 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
803 ret = drm_irq_install(dev);
804 if (ret != 0) {
805 DRM_ERROR("Failed installing irq: %d\n", ret);
806 goto out_no_irq;
807 }
808 }
809
ae2a1040 810 dev_priv->fman = vmw_fence_manager_init(dev_priv);
14bbf20c
WY		 811 if (unlikely(dev_priv->fman == NULL)) {
812 ret = -ENOMEM;
ae2a1040 813 goto out_no_fman;
14bbf20c 814 }
56d1c78d 815
56d1c78d 816 vmw_kms_save_vga(dev_priv);
56d1c78d
JB		 817
818 /* Start kms and overlay systems, needs fifo. */
7a1c2f6c
TH		 819 ret = vmw_kms_init(dev_priv);
820 if (unlikely(ret != 0))
821 goto out_no_kms;
f2d12b8e 822 vmw_overlay_init(dev_priv);
56d1c78d 823
30c78bb8 824 if (dev_priv->enable_fb) {
506ff75c
TH		 825 ret = vmw_3d_resource_inc(dev_priv, true);
826 if (unlikely(ret != 0))
827 goto out_no_fifo;
30c78bb8 828 vmw_fb_init(dev_priv);
7a1c2f6c
TH		 829 }
830
d9f36a00
TH		 831 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
832 register_pm_notifier(&dev_priv->pm_nb);
833
fb1d9738
JB		 834 return 0;
835
506ff75c 836out_no_fifo:
56d1c78d
JB		 837 vmw_overlay_close(dev_priv);
838 vmw_kms_close(dev_priv);
839out_no_kms:
506ff75c 840 vmw_kms_restore_vga(dev_priv);
ae2a1040
TH		 841 vmw_fence_manager_takedown(dev_priv->fman);
842out_no_fman:
506ff75c
TH		 843 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
844 drm_irq_uninstall(dev_priv->dev);
845out_no_irq:
30c78bb8
TH		 846 if (dev_priv->stealth)
847 pci_release_region(dev->pdev, 2);
848 else
849 pci_release_regions(dev->pdev);
fb1d9738 850out_no_device:
fb1d9738
JB		 851 ttm_object_device_release(&dev_priv->tdev);
852out_err4:
853 iounmap(dev_priv->mmio_virt);
854out_err3:
247d36d7 855 arch_phys_wc_del(dev_priv->mmio_mtrr);
6da768aa
TH		 856 if (dev_priv->has_mob)
857 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
135cba0d
TH		 858 if (dev_priv->has_gmr)
859 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
fb1d9738
JB		 860 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
861out_err2:
862 (void)ttm_bo_device_release(&dev_priv->bdev);
863out_err1:
864 vmw_ttm_global_release(dev_priv);
865out_err0:
c0951b79
TH		 866 for (i = vmw_res_context; i < vmw_res_max; ++i)
867 idr_destroy(&dev_priv->res_idr[i]);
868
fb1d9738
JB		 869 kfree(dev_priv);
870 return ret;
871}
872
873static int vmw_driver_unload(struct drm_device *dev)
874{
875 struct vmw_private *dev_priv = vmw_priv(dev);
c0951b79 876 enum vmw_res_type i;
fb1d9738 877
d9f36a00
TH		 878 unregister_pm_notifier(&dev_priv->pm_nb);
879
c0951b79
TH		 880 if (dev_priv->ctx.res_ht_initialized)
881 drm_ht_remove(&dev_priv->ctx.res_ht);
be38ab6e
TH		 882 if (dev_priv->ctx.cmd_bounce)
883 vfree(dev_priv->ctx.cmd_bounce);
30c78bb8
TH		 884 if (dev_priv->enable_fb) {
885 vmw_fb_close(dev_priv);
886 vmw_kms_restore_vga(dev_priv);
05730b32 887 vmw_3d_resource_dec(dev_priv, false);
30c78bb8 888 }
f2d12b8e
TH		 889 vmw_kms_close(dev_priv);
890 vmw_overlay_close(dev_priv);
ae2a1040 891 vmw_fence_manager_takedown(dev_priv->fman);
506ff75c
TH		 892 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
893 drm_irq_uninstall(dev_priv->dev);
f2d12b8e 894 if (dev_priv->stealth)
fb1d9738 895 pci_release_region(dev->pdev, 2);
f2d12b8e
TH		 896 else
897 pci_release_regions(dev->pdev);
898
fb1d9738
JB		 899 ttm_object_device_release(&dev_priv->tdev);
900 iounmap(dev_priv->mmio_virt);
247d36d7 901 arch_phys_wc_del(dev_priv->mmio_mtrr);
6da768aa
TH		 902 if (dev_priv->has_mob)
903 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
135cba0d
TH		 904 if (dev_priv->has_gmr)
905 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
fb1d9738
JB		 906 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
907 (void)ttm_bo_device_release(&dev_priv->bdev);
908 vmw_ttm_global_release(dev_priv);
c0951b79
TH		 909
910 for (i = vmw_res_context; i < vmw_res_max; ++i)
911 idr_destroy(&dev_priv->res_idr[i]);
fb1d9738
JB		 912
913 kfree(dev_priv);
914
915 return 0;
916}
917
6b82ef50
TH		 918static void vmw_preclose(struct drm_device *dev,
919 struct drm_file *file_priv)
920{
921 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
922 struct vmw_private *dev_priv = vmw_priv(dev);
923
924 vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
925}
926
fb1d9738
JB		 927static void vmw_postclose(struct drm_device *dev,
928 struct drm_file *file_priv)
929{
930 struct vmw_fpriv *vmw_fp;
931
932 vmw_fp = vmw_fpriv(file_priv);
c4249855
TH		 933
934 if (vmw_fp->locked_master) {
935 struct vmw_master *vmaster =
936 vmw_master(vmw_fp->locked_master);
937
938 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
939 ttm_vt_unlock(&vmaster->lock);
fb1d9738 940 drm_master_put(&vmw_fp->locked_master);
c4249855
TH		 941 }
942
943 ttm_object_file_release(&vmw_fp->tfile);
fb1d9738
JB		 944 kfree(vmw_fp);
945}
946
947static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
948{
949 struct vmw_private *dev_priv = vmw_priv(dev);
950 struct vmw_fpriv *vmw_fp;
951 int ret = -ENOMEM;
952
953 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
954 if (unlikely(vmw_fp == NULL))
955 return ret;
956
6b82ef50 957 INIT_LIST_HEAD(&vmw_fp->fence_events);
fb1d9738
JB		 958 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
959 if (unlikely(vmw_fp->tfile == NULL))
960 goto out_no_tfile;
961
962 file_priv->driver_priv = vmw_fp;
949c4a34 963 dev_priv->bdev.dev_mapping = dev->dev_mapping;
fb1d9738
JB		 964
965 return 0;
966
967out_no_tfile:
968 kfree(vmw_fp);
969 return ret;
970}
971
972static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
973 unsigned long arg)
974{
975 struct drm_file *file_priv = filp->private_data;
976 struct drm_device *dev = file_priv->minor->dev;
977 unsigned int nr = DRM_IOCTL_NR(cmd);
fb1d9738
JB		 978
979 /*
e1f78003 980 * Do extra checking on driver private ioctls.
fb1d9738
JB		 981 */
982
983 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
984 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
baa70943 985 const struct drm_ioctl_desc *ioctl =
fb1d9738
JB		 986 &vmw_ioctls[nr - DRM_COMMAND_BASE];
987
2854eeda 988 if (unlikely(ioctl->cmd_drv != cmd)) {
fb1d9738
JB		 989 DRM_ERROR("Invalid command format, ioctl %d\n",
990 nr - DRM_COMMAND_BASE);
991 return -EINVAL;
992 }
fb1d9738
JB		 993 }
994
e1f78003 995 return drm_ioctl(filp, cmd, arg);
fb1d9738
JB		 996}
997
fb1d9738
JB		 998static void vmw_lastclose(struct drm_device *dev)
999{
fb1d9738
JB		 1000 struct drm_crtc *crtc;
1001 struct drm_mode_set set;
1002 int ret;
1003
fb1d9738
JB		 1004 set.x = 0;
1005 set.y = 0;
1006 set.fb = NULL;
1007 set.mode = NULL;
1008 set.connectors = NULL;
1009 set.num_connectors = 0;
1010
1011 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1012 set.crtc = crtc;
2d13b679 1013 ret = drm_mode_set_config_internal(&set);
fb1d9738
JB		 1014 WARN_ON(ret != 0);
1015 }
1016
1017}
1018
1019static void vmw_master_init(struct vmw_master *vmaster)
1020{
1021 ttm_lock_init(&vmaster->lock);
3a939a5e
TH		 1022 INIT_LIST_HEAD(&vmaster->fb_surf);
1023 mutex_init(&vmaster->fb_surf_mutex);
fb1d9738
JB		 1024}
1025
1026static int vmw_master_create(struct drm_device *dev,
1027 struct drm_master *master)
1028{
1029 struct vmw_master *vmaster;
1030
fb1d9738
JB		 1031 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1032 if (unlikely(vmaster == NULL))
1033 return -ENOMEM;
1034
3a939a5e 1035 vmw_master_init(vmaster);
fb1d9738
JB		 1036 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1037 master->driver_priv = vmaster;
1038
1039 return 0;
1040}
1041
1042static void vmw_master_destroy(struct drm_device *dev,
1043 struct drm_master *master)
1044{
1045 struct vmw_master *vmaster = vmw_master(master);
1046
fb1d9738
JB		 1047 master->driver_priv = NULL;
1048 kfree(vmaster);
1049}
1050
1051
1052static int vmw_master_set(struct drm_device *dev,
1053 struct drm_file *file_priv,
1054 bool from_open)
1055{
1056 struct vmw_private *dev_priv = vmw_priv(dev);
1057 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1058 struct vmw_master *active = dev_priv->active_master;
1059 struct vmw_master *vmaster = vmw_master(file_priv->master);
1060 int ret = 0;
1061
30c78bb8 1062 if (!dev_priv->enable_fb) {
05730b32 1063 ret = vmw_3d_resource_inc(dev_priv, true);
30c78bb8
TH		 1064 if (unlikely(ret != 0))
1065 return ret;
1066 vmw_kms_save_vga(dev_priv);
1067 mutex_lock(&dev_priv->hw_mutex);
1068 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
1069 mutex_unlock(&dev_priv->hw_mutex);
1070 }
1071
fb1d9738
JB		 1072 if (active) {
1073 BUG_ON(active != &dev_priv->fbdev_master);
1074 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1075 if (unlikely(ret != 0))
1076 goto out_no_active_lock;
1077
1078 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1079 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1080 if (unlikely(ret != 0)) {
1081 DRM_ERROR("Unable to clean VRAM on "
1082 "master drop.\n");
1083 }
1084
1085 dev_priv->active_master = NULL;
1086 }
1087
1088 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1089 if (!from_open) {
1090 ttm_vt_unlock(&vmaster->lock);
1091 BUG_ON(vmw_fp->locked_master != file_priv->master);
1092 drm_master_put(&vmw_fp->locked_master);
1093 }
1094
1095 dev_priv->active_master = vmaster;
1096
1097 return 0;
1098
1099out_no_active_lock:
30c78bb8 1100 if (!dev_priv->enable_fb) {
ba723fe8
TH		 1101 vmw_kms_restore_vga(dev_priv);
1102 vmw_3d_resource_dec(dev_priv, true);
30c78bb8
TH		 1103 mutex_lock(&dev_priv->hw_mutex);
1104 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1105 mutex_unlock(&dev_priv->hw_mutex);
30c78bb8 1106 }
fb1d9738
JB		 1107 return ret;
1108}
1109
1110static void vmw_master_drop(struct drm_device *dev,
1111 struct drm_file *file_priv,
1112 bool from_release)
1113{
1114 struct vmw_private *dev_priv = vmw_priv(dev);
1115 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1116 struct vmw_master *vmaster = vmw_master(file_priv->master);
1117 int ret;
1118
fb1d9738
JB		 1119 /**
1120 * Make sure the master doesn't disappear while we have
1121 * it locked.
1122 */
1123
1124 vmw_fp->locked_master = drm_master_get(file_priv->master);
1125 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
fb1d9738
JB		 1126 if (unlikely((ret != 0))) {
1127 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1128 drm_master_put(&vmw_fp->locked_master);
1129 }
1130
c4249855
TH		 1131 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1132 vmw_execbuf_release_pinned_bo(dev_priv);
fb1d9738 1133
30c78bb8
TH		 1134 if (!dev_priv->enable_fb) {
1135 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1136 if (unlikely(ret != 0))
1137 DRM_ERROR("Unable to clean VRAM on master drop.\n");
ba723fe8
TH		 1138 vmw_kms_restore_vga(dev_priv);
1139 vmw_3d_resource_dec(dev_priv, true);
30c78bb8
TH		 1140 mutex_lock(&dev_priv->hw_mutex);
1141 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1142 mutex_unlock(&dev_priv->hw_mutex);
30c78bb8
TH		 1143 }
1144
fb1d9738
JB		 1145 dev_priv->active_master = &dev_priv->fbdev_master;
1146 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1147 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1148
30c78bb8
TH		 1149 if (dev_priv->enable_fb)
1150 vmw_fb_on(dev_priv);
fb1d9738
JB		 1151}
1152
1153
1154static void vmw_remove(struct pci_dev *pdev)
1155{
1156 struct drm_device *dev = pci_get_drvdata(pdev);
1157
1158 drm_put_dev(dev);
1159}
1160
d9f36a00
TH		 1161static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1162 void *ptr)
1163{
1164 struct vmw_private *dev_priv =
1165 container_of(nb, struct vmw_private, pm_nb);
1166 struct vmw_master *vmaster = dev_priv->active_master;
1167
1168 switch (val) {
1169 case PM_HIBERNATION_PREPARE:
1170 case PM_SUSPEND_PREPARE:
1171 ttm_suspend_lock(&vmaster->lock);
1172
1173 /**
1174 * This empties VRAM and unbinds all GMR bindings.
1175 * Buffer contents is moved to swappable memory.
1176 */
c0951b79
TH		 1177 vmw_execbuf_release_pinned_bo(dev_priv);
1178 vmw_resource_evict_all(dev_priv);
d9f36a00 1179 ttm_bo_swapout_all(&dev_priv->bdev);
094e0fa8 1180
d9f36a00
TH		 1181 break;
1182 case PM_POST_HIBERNATION:
1183 case PM_POST_SUSPEND:
094e0fa8 1184 case PM_POST_RESTORE:
d9f36a00 1185 ttm_suspend_unlock(&vmaster->lock);
094e0fa8 1186
d9f36a00
TH		 1187 break;
1188 case PM_RESTORE_PREPARE:
1189 break;
d9f36a00
TH		 1190 default:
1191 break;
1192 }
1193 return 0;
1194}
1195
1196/**
1197 * These might not be needed with the virtual SVGA device.
1198 */
1199
7fbd721a 1200static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
d9f36a00 1201{
094e0fa8
TH		 1202 struct drm_device *dev = pci_get_drvdata(pdev);
1203 struct vmw_private *dev_priv = vmw_priv(dev);
1204
1205 if (dev_priv->num_3d_resources != 0) {
1206 DRM_INFO("Can't suspend or hibernate "
1207 "while 3D resources are active.\n");
1208 return -EBUSY;
1209 }
1210
d9f36a00
TH		 1211 pci_save_state(pdev);
1212 pci_disable_device(pdev);
1213 pci_set_power_state(pdev, PCI_D3hot);
1214 return 0;
1215}
1216
7fbd721a 1217static int vmw_pci_resume(struct pci_dev *pdev)
d9f36a00
TH		 1218{
1219 pci_set_power_state(pdev, PCI_D0);
1220 pci_restore_state(pdev);
1221 return pci_enable_device(pdev);
1222}
1223
7fbd721a
TH		 1224static int vmw_pm_suspend(struct device *kdev)
1225{
1226 struct pci_dev *pdev = to_pci_dev(kdev);
1227 struct pm_message dummy;
1228
1229 dummy.event = 0;
1230
1231 return vmw_pci_suspend(pdev, dummy);
1232}
1233
1234static int vmw_pm_resume(struct device *kdev)
1235{
1236 struct pci_dev *pdev = to_pci_dev(kdev);
1237
1238 return vmw_pci_resume(pdev);
1239}
1240
1241static int vmw_pm_prepare(struct device *kdev)
1242{
1243 struct pci_dev *pdev = to_pci_dev(kdev);
1244 struct drm_device *dev = pci_get_drvdata(pdev);
1245 struct vmw_private *dev_priv = vmw_priv(dev);
1246
1247 /**
1248 * Release 3d reference held by fbdev and potentially
1249 * stop fifo.
1250 */
1251 dev_priv->suspended = true;
1252 if (dev_priv->enable_fb)
05730b32 1253 vmw_3d_resource_dec(dev_priv, true);
7fbd721a
TH		 1254
1255 if (dev_priv->num_3d_resources != 0) {
1256
1257 DRM_INFO("Can't suspend or hibernate "
1258 "while 3D resources are active.\n");
1259
1260 if (dev_priv->enable_fb)
05730b32 1261 vmw_3d_resource_inc(dev_priv, true);
7fbd721a
TH		 1262 dev_priv->suspended = false;
1263 return -EBUSY;
1264 }
1265
1266 return 0;
1267}
1268
1269static void vmw_pm_complete(struct device *kdev)
1270{
1271 struct pci_dev *pdev = to_pci_dev(kdev);
1272 struct drm_device *dev = pci_get_drvdata(pdev);
1273 struct vmw_private *dev_priv = vmw_priv(dev);
1274
95e8f6a2
TH		 1275 mutex_lock(&dev_priv->hw_mutex);
1276 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1277 (void) vmw_read(dev_priv, SVGA_REG_ID);
1278 mutex_unlock(&dev_priv->hw_mutex);
1279
7fbd721a
TH		 1280 /**
1281 * Reclaim 3d reference held by fbdev and potentially
1282 * start fifo.
1283 */
1284 if (dev_priv->enable_fb)
05730b32 1285 vmw_3d_resource_inc(dev_priv, false);
7fbd721a
TH		 1286
1287 dev_priv->suspended = false;
1288}
1289
1290static const struct dev_pm_ops vmw_pm_ops = {
1291 .prepare = vmw_pm_prepare,
1292 .complete = vmw_pm_complete,
1293 .suspend = vmw_pm_suspend,
1294 .resume = vmw_pm_resume,
1295};
1296
e08e96de
AV		 1297static const struct file_operations vmwgfx_driver_fops = {
1298 .owner = THIS_MODULE,
1299 .open = drm_open,
1300 .release = drm_release,
1301 .unlocked_ioctl = vmw_unlocked_ioctl,
1302 .mmap = vmw_mmap,
1303 .poll = vmw_fops_poll,
1304 .read = vmw_fops_read,
e08e96de
AV		 1305#if defined(CONFIG_COMPAT)
1306 .compat_ioctl = drm_compat_ioctl,
1307#endif
1308 .llseek = noop_llseek,
1309};
1310
fb1d9738
JB		 1311static struct drm_driver driver = {
1312 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
69977ff5 1313 DRIVER_MODESET | DRIVER_PRIME,
fb1d9738
JB		 1314 .load = vmw_driver_load,
1315 .unload = vmw_driver_unload,
fb1d9738
JB		 1316 .lastclose = vmw_lastclose,
1317 .irq_preinstall = vmw_irq_preinstall,
1318 .irq_postinstall = vmw_irq_postinstall,
1319 .irq_uninstall = vmw_irq_uninstall,
1320 .irq_handler = vmw_irq_handler,
7a1c2f6c 1321 .get_vblank_counter = vmw_get_vblank_counter,
1c482ab3
JB		 1322 .enable_vblank = vmw_enable_vblank,
1323 .disable_vblank = vmw_disable_vblank,
fb1d9738
JB		 1324 .ioctls = vmw_ioctls,
1325 .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
fb1d9738
JB		 1326 .master_create = vmw_master_create,
1327 .master_destroy = vmw_master_destroy,
1328 .master_set = vmw_master_set,
1329 .master_drop = vmw_master_drop,
1330 .open = vmw_driver_open,
6b82ef50 1331 .preclose = vmw_preclose,
fb1d9738 1332 .postclose = vmw_postclose,
5e1782d2
DA		 1333
1334 .dumb_create = vmw_dumb_create,
1335 .dumb_map_offset = vmw_dumb_map_offset,
1336 .dumb_destroy = vmw_dumb_destroy,
1337
69977ff5
TH		 1338 .prime_fd_to_handle = vmw_prime_fd_to_handle,
1339 .prime_handle_to_fd = vmw_prime_handle_to_fd,
1340
e08e96de 1341 .fops = &vmwgfx_driver_fops,
fb1d9738
JB		 1342 .name = VMWGFX_DRIVER_NAME,
1343 .desc = VMWGFX_DRIVER_DESC,
1344 .date = VMWGFX_DRIVER_DATE,
1345 .major = VMWGFX_DRIVER_MAJOR,
1346 .minor = VMWGFX_DRIVER_MINOR,
1347 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1348};
1349
8410ea3b
DA		 1350static struct pci_driver vmw_pci_driver = {
1351 .name = VMWGFX_DRIVER_NAME,
1352 .id_table = vmw_pci_id_list,
1353 .probe = vmw_probe,
1354 .remove = vmw_remove,
1355 .driver = {
1356 .pm = &vmw_pm_ops
1357 }
1358};
1359
fb1d9738
JB		 1360static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1361{
dcdb1674 1362 return drm_get_pci_dev(pdev, ent, &driver);
fb1d9738
JB		 1363}
1364
1365static int __init vmwgfx_init(void)
1366{
1367 int ret;
8410ea3b 1368 ret = drm_pci_init(&driver, &vmw_pci_driver);
fb1d9738
JB		 1369 if (ret)
1370 DRM_ERROR("Failed initializing DRM.\n");
1371 return ret;
1372}
1373
1374static void __exit vmwgfx_exit(void)
1375{
8410ea3b 1376 drm_pci_exit(&driver, &vmw_pci_driver);
fb1d9738
JB		 1377}
1378
1379module_init(vmwgfx_init);
1380module_exit(vmwgfx_exit);
1381
1382MODULE_AUTHOR("VMware Inc. and others");
1383MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1384MODULE_LICENSE("GPL and additional rights");
73558ead
TH		 1385MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1386 __stringify(VMWGFX_DRIVER_MINOR) "."
1387 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1388 "0");
Linux kernel - Deliverables
This page took 0.3077 seconds and 5 git commands to generate.