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vmwgfx: vt-switch (master drop) fixes
[deliverable/linux.git] / drivers / gpu / drm / vmwgfx / vmwgfx_drv.c
CommitLineData
fb1d9738
JB		 1/**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#include "drmP.h"
29#include "vmwgfx_drv.h"
30#include "ttm/ttm_placement.h"
31#include "ttm/ttm_bo_driver.h"
32#include "ttm/ttm_object.h"
33#include "ttm/ttm_module.h"
34
35#define VMWGFX_DRIVER_NAME "vmwgfx"
36#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
37#define VMWGFX_CHIP_SVGAII 0
38#define VMW_FB_RESERVATION 0
39
40/**
41 * Fully encoded drm commands. Might move to vmw_drm.h
42 */
43
44#define DRM_IOCTL_VMW_GET_PARAM \
45 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
46 struct drm_vmw_getparam_arg)
47#define DRM_IOCTL_VMW_ALLOC_DMABUF \
48 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
49 union drm_vmw_alloc_dmabuf_arg)
50#define DRM_IOCTL_VMW_UNREF_DMABUF \
51 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
52 struct drm_vmw_unref_dmabuf_arg)
53#define DRM_IOCTL_VMW_CURSOR_BYPASS \
54 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
55 struct drm_vmw_cursor_bypass_arg)
56
57#define DRM_IOCTL_VMW_CONTROL_STREAM \
58 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
59 struct drm_vmw_control_stream_arg)
60#define DRM_IOCTL_VMW_CLAIM_STREAM \
61 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
62 struct drm_vmw_stream_arg)
63#define DRM_IOCTL_VMW_UNREF_STREAM \
64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
65 struct drm_vmw_stream_arg)
66
67#define DRM_IOCTL_VMW_CREATE_CONTEXT \
68 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
69 struct drm_vmw_context_arg)
70#define DRM_IOCTL_VMW_UNREF_CONTEXT \
71 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
72 struct drm_vmw_context_arg)
73#define DRM_IOCTL_VMW_CREATE_SURFACE \
74 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
75 union drm_vmw_surface_create_arg)
76#define DRM_IOCTL_VMW_UNREF_SURFACE \
77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
78 struct drm_vmw_surface_arg)
79#define DRM_IOCTL_VMW_REF_SURFACE \
80 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
81 union drm_vmw_surface_reference_arg)
82#define DRM_IOCTL_VMW_EXECBUF \
83 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
84 struct drm_vmw_execbuf_arg)
85#define DRM_IOCTL_VMW_FIFO_DEBUG \
86 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FIFO_DEBUG, \
87 struct drm_vmw_fifo_debug_arg)
88#define DRM_IOCTL_VMW_FENCE_WAIT \
89 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
90 struct drm_vmw_fence_wait_arg)
d8bd19d2
JB		 91#define DRM_IOCTL_VMW_UPDATE_LAYOUT \
92 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
93 struct drm_vmw_update_layout_arg)
fb1d9738
JB		 94
95
96/**
97 * The core DRM version of this macro doesn't account for
98 * DRM_COMMAND_BASE.
99 */
100
101#define VMW_IOCTL_DEF(ioctl, func, flags) \
1b2f1489 102 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
fb1d9738
JB		 103
104/**
105 * Ioctl definitions.
106 */
107
108static struct drm_ioctl_desc vmw_ioctls[] = {
1b2f1489 109 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
e1f78003 110 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 111 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
e1f78003 112 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 113 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
e1f78003 114 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 115 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
e1f78003
TH		 116 vmw_kms_cursor_bypass_ioctl,
117 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
fb1d9738 118
1b2f1489 119 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
e1f78003 120 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
1b2f1489 121 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
e1f78003 122 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
1b2f1489 123 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
e1f78003 124 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
fb1d9738 125
1b2f1489 126 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
e1f78003 127 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 128 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
e1f78003 129 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 130 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
e1f78003 131 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 132 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
e1f78003 133 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 134 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
e1f78003 135 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 136 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
e1f78003 137 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 138 VMW_IOCTL_DEF(VMW_FIFO_DEBUG, vmw_fifo_debug_ioctl,
e1f78003 139 DRM_AUTH | DRM_ROOT_ONLY | DRM_MASTER | DRM_UNLOCKED),
1b2f1489 140 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_wait_ioctl,
d8bd19d2 141 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 142 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, vmw_kms_update_layout_ioctl,
d8bd19d2 143 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED)
fb1d9738
JB		 144};
145
146static struct pci_device_id vmw_pci_id_list[] = {
147 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
148 {0, 0, 0}
149};
150
151static char *vmw_devname = "vmwgfx";
30c78bb8 152static int enable_fbdev;
fb1d9738
JB		 153
154static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
155static void vmw_master_init(struct vmw_master *);
d9f36a00
TH		 156static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
157 void *ptr);
fb1d9738 158
30c78bb8
TH		 159MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
160module_param_named(enable_fbdev, enable_fbdev, int, 0600);
161
fb1d9738
JB		 162static void vmw_print_capabilities(uint32_t capabilities)
163{
164 DRM_INFO("Capabilities:\n");
165 if (capabilities & SVGA_CAP_RECT_COPY)
166 DRM_INFO(" Rect copy.\n");
167 if (capabilities & SVGA_CAP_CURSOR)
168 DRM_INFO(" Cursor.\n");
169 if (capabilities & SVGA_CAP_CURSOR_BYPASS)
170 DRM_INFO(" Cursor bypass.\n");
171 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
172 DRM_INFO(" Cursor bypass 2.\n");
173 if (capabilities & SVGA_CAP_8BIT_EMULATION)
174 DRM_INFO(" 8bit emulation.\n");
175 if (capabilities & SVGA_CAP_ALPHA_CURSOR)
176 DRM_INFO(" Alpha cursor.\n");
177 if (capabilities & SVGA_CAP_3D)
178 DRM_INFO(" 3D.\n");
179 if (capabilities & SVGA_CAP_EXTENDED_FIFO)
180 DRM_INFO(" Extended Fifo.\n");
181 if (capabilities & SVGA_CAP_MULTIMON)
182 DRM_INFO(" Multimon.\n");
183 if (capabilities & SVGA_CAP_PITCHLOCK)
184 DRM_INFO(" Pitchlock.\n");
185 if (capabilities & SVGA_CAP_IRQMASK)
186 DRM_INFO(" Irq mask.\n");
187 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
188 DRM_INFO(" Display Topology.\n");
189 if (capabilities & SVGA_CAP_GMR)
190 DRM_INFO(" GMR.\n");
191 if (capabilities & SVGA_CAP_TRACES)
192 DRM_INFO(" Traces.\n");
193}
194
195static int vmw_request_device(struct vmw_private *dev_priv)
196{
197 int ret;
198
fb1d9738
JB		 199 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
200 if (unlikely(ret != 0)) {
201 DRM_ERROR("Unable to initialize FIFO.\n");
202 return ret;
203 }
204
205 return 0;
206}
207
208static void vmw_release_device(struct vmw_private *dev_priv)
209{
210 vmw_fifo_release(dev_priv, &dev_priv->fifo);
30c78bb8
TH		 211}
212
213int vmw_3d_resource_inc(struct vmw_private *dev_priv)
214{
215 int ret = 0;
216
217 mutex_lock(&dev_priv->release_mutex);
218 if (unlikely(dev_priv->num_3d_resources++ == 0)) {
219 ret = vmw_request_device(dev_priv);
220 if (unlikely(ret != 0))
221 --dev_priv->num_3d_resources;
222 }
223 mutex_unlock(&dev_priv->release_mutex);
224 return ret;
fb1d9738
JB		 225}
226
227
30c78bb8
TH		 228void vmw_3d_resource_dec(struct vmw_private *dev_priv)
229{
230 int32_t n3d;
231
232 mutex_lock(&dev_priv->release_mutex);
233 if (unlikely(--dev_priv->num_3d_resources == 0))
234 vmw_release_device(dev_priv);
235 n3d = (int32_t) dev_priv->num_3d_resources;
236 mutex_unlock(&dev_priv->release_mutex);
237
238 BUG_ON(n3d < 0);
239}
240
fb1d9738
JB		 241static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
242{
243 struct vmw_private *dev_priv;
244 int ret;
c188660f 245 uint32_t svga_id;
fb1d9738
JB		 246
247 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
248 if (unlikely(dev_priv == NULL)) {
249 DRM_ERROR("Failed allocating a device private struct.\n");
250 return -ENOMEM;
251 }
252 memset(dev_priv, 0, sizeof(*dev_priv));
253
254 dev_priv->dev = dev;
255 dev_priv->vmw_chipset = chipset;
7704befb 256 dev_priv->last_read_sequence = (uint32_t) -100;
fb1d9738
JB		 257 mutex_init(&dev_priv->hw_mutex);
258 mutex_init(&dev_priv->cmdbuf_mutex);
30c78bb8 259 mutex_init(&dev_priv->release_mutex);
fb1d9738
JB		 260 rwlock_init(&dev_priv->resource_lock);
261 idr_init(&dev_priv->context_idr);
262 idr_init(&dev_priv->surface_idr);
263 idr_init(&dev_priv->stream_idr);
264 ida_init(&dev_priv->gmr_ida);
265 mutex_init(&dev_priv->init_mutex);
266 init_waitqueue_head(&dev_priv->fence_queue);
267 init_waitqueue_head(&dev_priv->fifo_queue);
268 atomic_set(&dev_priv->fence_queue_waiters, 0);
269 atomic_set(&dev_priv->fifo_queue_waiters, 0);
270 INIT_LIST_HEAD(&dev_priv->gmr_lru);
271
272 dev_priv->io_start = pci_resource_start(dev->pdev, 0);
273 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
274 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
275
30c78bb8
TH		 276 dev_priv->enable_fb = enable_fbdev;
277
fb1d9738 278 mutex_lock(&dev_priv->hw_mutex);
c188660f
PH		 279
280 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
281 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
282 if (svga_id != SVGA_ID_2) {
283 ret = -ENOSYS;
284 DRM_ERROR("Unsuported SVGA ID 0x%x\n", svga_id);
285 mutex_unlock(&dev_priv->hw_mutex);
286 goto out_err0;
287 }
288
fb1d9738
JB		 289 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
290
291 if (dev_priv->capabilities & SVGA_CAP_GMR) {
292 dev_priv->max_gmr_descriptors =
293 vmw_read(dev_priv,
294 SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
295 dev_priv->max_gmr_ids =
296 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
297 }
298
299 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
300 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
301 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
302 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
303
304 mutex_unlock(&dev_priv->hw_mutex);
305
306 vmw_print_capabilities(dev_priv->capabilities);
307
308 if (dev_priv->capabilities & SVGA_CAP_GMR) {
309 DRM_INFO("Max GMR ids is %u\n",
310 (unsigned)dev_priv->max_gmr_ids);
311 DRM_INFO("Max GMR descriptors is %u\n",
312 (unsigned)dev_priv->max_gmr_descriptors);
313 }
314 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
315 dev_priv->vram_start, dev_priv->vram_size / 1024);
316 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
317 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
318
319 ret = vmw_ttm_global_init(dev_priv);
320 if (unlikely(ret != 0))
321 goto out_err0;
322
323
324 vmw_master_init(&dev_priv->fbdev_master);
325 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
326 dev_priv->active_master = &dev_priv->fbdev_master;
327
328
329 ret = ttm_bo_device_init(&dev_priv->bdev,
330 dev_priv->bo_global_ref.ref.object,
331 &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET,
332 false);
333 if (unlikely(ret != 0)) {
334 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
335 goto out_err1;
336 }
337
338 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
339 (dev_priv->vram_size >> PAGE_SHIFT));
340 if (unlikely(ret != 0)) {
341 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
342 goto out_err2;
343 }
344
345 dev_priv->mmio_mtrr = drm_mtrr_add(dev_priv->mmio_start,
346 dev_priv->mmio_size, DRM_MTRR_WC);
347
348 dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
349 dev_priv->mmio_size);
350
351 if (unlikely(dev_priv->mmio_virt == NULL)) {
352 ret = -ENOMEM;
353 DRM_ERROR("Failed mapping MMIO.\n");
354 goto out_err3;
355 }
356
d7e1958d
JB		 357 /* Need mmio memory to check for fifo pitchlock cap. */
358 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
359 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
360 !vmw_fifo_have_pitchlock(dev_priv)) {
361 ret = -ENOSYS;
362 DRM_ERROR("Hardware has no pitchlock\n");
363 goto out_err4;
364 }
365
fb1d9738
JB		 366 dev_priv->tdev = ttm_object_device_init
367 (dev_priv->mem_global_ref.object, 12);
368
369 if (unlikely(dev_priv->tdev == NULL)) {
370 DRM_ERROR("Unable to initialize TTM object management.\n");
371 ret = -ENOMEM;
372 goto out_err4;
373 }
374
375 dev->dev_private = dev_priv;
376
377 if (!dev->devname)
378 dev->devname = vmw_devname;
379
380 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
381 ret = drm_irq_install(dev);
382 if (unlikely(ret != 0)) {
383 DRM_ERROR("Failed installing irq: %d\n", ret);
384 goto out_no_irq;
385 }
386 }
387
388 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
389 dev_priv->stealth = (ret != 0);
390 if (dev_priv->stealth) {
391 /**
392 * Request at least the mmio PCI resource.
393 */
394
395 DRM_INFO("It appears like vesafb is loaded. "
f2d12b8e 396 "Ignore above error if any.\n");
fb1d9738
JB		 397 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
398 if (unlikely(ret != 0)) {
399 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
400 goto out_no_device;
401 }
fb1d9738 402 }
f2d12b8e
TH		 403 vmw_kms_init(dev_priv);
404 vmw_overlay_init(dev_priv);
30c78bb8
TH		 405 if (dev_priv->enable_fb) {
406 ret = vmw_3d_resource_inc(dev_priv);
407 if (unlikely(ret != 0))
408 goto out_no_fifo;
409 vmw_kms_save_vga(dev_priv);
410 vmw_fb_init(dev_priv);
411 DRM_INFO("%s", vmw_fifo_have_3d(dev_priv) ?
412 "Detected device 3D availability.\n" :
413 "Detected no device 3D availability.\n");
414 } else {
415 DRM_INFO("Delayed 3D detection since we're not "
416 "running the device in SVGA mode yet.\n");
417 }
fb1d9738 418
d9f36a00
TH		 419 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
420 register_pm_notifier(&dev_priv->pm_nb);
421
fb1d9738
JB		 422 return 0;
423
30c78bb8
TH		 424out_no_fifo:
425 vmw_overlay_close(dev_priv);
426 vmw_kms_close(dev_priv);
427 if (dev_priv->stealth)
428 pci_release_region(dev->pdev, 2);
429 else
430 pci_release_regions(dev->pdev);
fb1d9738
JB		 431out_no_device:
432 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
433 drm_irq_uninstall(dev_priv->dev);
434 if (dev->devname == vmw_devname)
435 dev->devname = NULL;
436out_no_irq:
437 ttm_object_device_release(&dev_priv->tdev);
438out_err4:
439 iounmap(dev_priv->mmio_virt);
440out_err3:
441 drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
442 dev_priv->mmio_size, DRM_MTRR_WC);
443 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
444out_err2:
445 (void)ttm_bo_device_release(&dev_priv->bdev);
446out_err1:
447 vmw_ttm_global_release(dev_priv);
448out_err0:
449 ida_destroy(&dev_priv->gmr_ida);
450 idr_destroy(&dev_priv->surface_idr);
451 idr_destroy(&dev_priv->context_idr);
452 idr_destroy(&dev_priv->stream_idr);
453 kfree(dev_priv);
454 return ret;
455}
456
457static int vmw_driver_unload(struct drm_device *dev)
458{
459 struct vmw_private *dev_priv = vmw_priv(dev);
460
d9f36a00
TH		 461 unregister_pm_notifier(&dev_priv->pm_nb);
462
30c78bb8
TH		 463 if (dev_priv->enable_fb) {
464 vmw_fb_close(dev_priv);
465 vmw_kms_restore_vga(dev_priv);
466 vmw_3d_resource_dec(dev_priv);
467 }
f2d12b8e
TH		 468 vmw_kms_close(dev_priv);
469 vmw_overlay_close(dev_priv);
f2d12b8e 470 if (dev_priv->stealth)
fb1d9738 471 pci_release_region(dev->pdev, 2);
f2d12b8e
TH		 472 else
473 pci_release_regions(dev->pdev);
474
fb1d9738
JB		 475 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
476 drm_irq_uninstall(dev_priv->dev);
477 if (dev->devname == vmw_devname)
478 dev->devname = NULL;
479 ttm_object_device_release(&dev_priv->tdev);
480 iounmap(dev_priv->mmio_virt);
481 drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
482 dev_priv->mmio_size, DRM_MTRR_WC);
483 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
484 (void)ttm_bo_device_release(&dev_priv->bdev);
485 vmw_ttm_global_release(dev_priv);
486 ida_destroy(&dev_priv->gmr_ida);
487 idr_destroy(&dev_priv->surface_idr);
488 idr_destroy(&dev_priv->context_idr);
489 idr_destroy(&dev_priv->stream_idr);
490
491 kfree(dev_priv);
492
493 return 0;
494}
495
496static void vmw_postclose(struct drm_device *dev,
497 struct drm_file *file_priv)
498{
499 struct vmw_fpriv *vmw_fp;
500
501 vmw_fp = vmw_fpriv(file_priv);
502 ttm_object_file_release(&vmw_fp->tfile);
503 if (vmw_fp->locked_master)
504 drm_master_put(&vmw_fp->locked_master);
505 kfree(vmw_fp);
506}
507
508static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
509{
510 struct vmw_private *dev_priv = vmw_priv(dev);
511 struct vmw_fpriv *vmw_fp;
512 int ret = -ENOMEM;
513
514 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
515 if (unlikely(vmw_fp == NULL))
516 return ret;
517
518 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
519 if (unlikely(vmw_fp->tfile == NULL))
520 goto out_no_tfile;
521
522 file_priv->driver_priv = vmw_fp;
523
524 if (unlikely(dev_priv->bdev.dev_mapping == NULL))
525 dev_priv->bdev.dev_mapping =
526 file_priv->filp->f_path.dentry->d_inode->i_mapping;
527
528 return 0;
529
530out_no_tfile:
531 kfree(vmw_fp);
532 return ret;
533}
534
535static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
536 unsigned long arg)
537{
538 struct drm_file *file_priv = filp->private_data;
539 struct drm_device *dev = file_priv->minor->dev;
540 unsigned int nr = DRM_IOCTL_NR(cmd);
fb1d9738
JB		 541
542 /*
e1f78003 543 * Do extra checking on driver private ioctls.
fb1d9738
JB		 544 */
545
546 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
547 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
548 struct drm_ioctl_desc *ioctl =
549 &vmw_ioctls[nr - DRM_COMMAND_BASE];
550
2854eeda 551 if (unlikely(ioctl->cmd_drv != cmd)) {
fb1d9738
JB		 552 DRM_ERROR("Invalid command format, ioctl %d\n",
553 nr - DRM_COMMAND_BASE);
554 return -EINVAL;
555 }
fb1d9738
JB		 556 }
557
e1f78003 558 return drm_ioctl(filp, cmd, arg);
fb1d9738
JB		 559}
560
561static int vmw_firstopen(struct drm_device *dev)
562{
563 struct vmw_private *dev_priv = vmw_priv(dev);
564 dev_priv->is_opened = true;
565
566 return 0;
567}
568
569static void vmw_lastclose(struct drm_device *dev)
570{
571 struct vmw_private *dev_priv = vmw_priv(dev);
572 struct drm_crtc *crtc;
573 struct drm_mode_set set;
574 int ret;
575
576 /**
577 * Do nothing on the lastclose call from drm_unload.
578 */
579
580 if (!dev_priv->is_opened)
581 return;
582
583 dev_priv->is_opened = false;
584 set.x = 0;
585 set.y = 0;
586 set.fb = NULL;
587 set.mode = NULL;
588 set.connectors = NULL;
589 set.num_connectors = 0;
590
591 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
592 set.crtc = crtc;
593 ret = crtc->funcs->set_config(&set);
594 WARN_ON(ret != 0);
595 }
596
597}
598
599static void vmw_master_init(struct vmw_master *vmaster)
600{
601 ttm_lock_init(&vmaster->lock);
602}
603
604static int vmw_master_create(struct drm_device *dev,
605 struct drm_master *master)
606{
607 struct vmw_master *vmaster;
608
fb1d9738
JB		 609 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
610 if (unlikely(vmaster == NULL))
611 return -ENOMEM;
612
613 ttm_lock_init(&vmaster->lock);
614 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
615 master->driver_priv = vmaster;
616
617 return 0;
618}
619
620static void vmw_master_destroy(struct drm_device *dev,
621 struct drm_master *master)
622{
623 struct vmw_master *vmaster = vmw_master(master);
624
fb1d9738
JB		 625 master->driver_priv = NULL;
626 kfree(vmaster);
627}
628
629
630static int vmw_master_set(struct drm_device *dev,
631 struct drm_file *file_priv,
632 bool from_open)
633{
634 struct vmw_private *dev_priv = vmw_priv(dev);
635 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
636 struct vmw_master *active = dev_priv->active_master;
637 struct vmw_master *vmaster = vmw_master(file_priv->master);
638 int ret = 0;
639
30c78bb8
TH		 640 if (!dev_priv->enable_fb) {
641 ret = vmw_3d_resource_inc(dev_priv);
642 if (unlikely(ret != 0))
643 return ret;
644 vmw_kms_save_vga(dev_priv);
645 mutex_lock(&dev_priv->hw_mutex);
646 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
647 mutex_unlock(&dev_priv->hw_mutex);
648 }
649
fb1d9738
JB		 650 if (active) {
651 BUG_ON(active != &dev_priv->fbdev_master);
652 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
653 if (unlikely(ret != 0))
654 goto out_no_active_lock;
655
656 ttm_lock_set_kill(&active->lock, true, SIGTERM);
657 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
658 if (unlikely(ret != 0)) {
659 DRM_ERROR("Unable to clean VRAM on "
660 "master drop.\n");
661 }
662
663 dev_priv->active_master = NULL;
664 }
665
666 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
667 if (!from_open) {
668 ttm_vt_unlock(&vmaster->lock);
669 BUG_ON(vmw_fp->locked_master != file_priv->master);
670 drm_master_put(&vmw_fp->locked_master);
671 }
672
673 dev_priv->active_master = vmaster;
674
675 return 0;
676
677out_no_active_lock:
30c78bb8
TH		 678 if (!dev_priv->enable_fb) {
679 mutex_lock(&dev_priv->hw_mutex);
680 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
681 mutex_unlock(&dev_priv->hw_mutex);
682 vmw_kms_restore_vga(dev_priv);
683 vmw_3d_resource_dec(dev_priv);
684 }
fb1d9738
JB		 685 return ret;
686}
687
688static void vmw_master_drop(struct drm_device *dev,
689 struct drm_file *file_priv,
690 bool from_release)
691{
692 struct vmw_private *dev_priv = vmw_priv(dev);
693 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
694 struct vmw_master *vmaster = vmw_master(file_priv->master);
695 int ret;
696
fb1d9738
JB		 697 /**
698 * Make sure the master doesn't disappear while we have
699 * it locked.
700 */
701
702 vmw_fp->locked_master = drm_master_get(file_priv->master);
703 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
704
705 if (unlikely((ret != 0))) {
706 DRM_ERROR("Unable to lock TTM at VT switch.\n");
707 drm_master_put(&vmw_fp->locked_master);
708 }
709
710 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
711
30c78bb8
TH		 712 if (!dev_priv->enable_fb) {
713 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
714 if (unlikely(ret != 0))
715 DRM_ERROR("Unable to clean VRAM on master drop.\n");
716 mutex_lock(&dev_priv->hw_mutex);
717 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
718 mutex_unlock(&dev_priv->hw_mutex);
719 vmw_kms_restore_vga(dev_priv);
720 vmw_3d_resource_dec(dev_priv);
721 }
722
fb1d9738
JB		 723 dev_priv->active_master = &dev_priv->fbdev_master;
724 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
725 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
726
30c78bb8
TH		 727 if (dev_priv->enable_fb)
728 vmw_fb_on(dev_priv);
fb1d9738
JB		 729}
730
731
732static void vmw_remove(struct pci_dev *pdev)
733{
734 struct drm_device *dev = pci_get_drvdata(pdev);
735
736 drm_put_dev(dev);
737}
738
d9f36a00
TH		 739static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
740 void *ptr)
741{
742 struct vmw_private *dev_priv =
743 container_of(nb, struct vmw_private, pm_nb);
744 struct vmw_master *vmaster = dev_priv->active_master;
745
746 switch (val) {
747 case PM_HIBERNATION_PREPARE:
748 case PM_SUSPEND_PREPARE:
749 ttm_suspend_lock(&vmaster->lock);
750
751 /**
752 * This empties VRAM and unbinds all GMR bindings.
753 * Buffer contents is moved to swappable memory.
754 */
755 ttm_bo_swapout_all(&dev_priv->bdev);
756 break;
757 case PM_POST_HIBERNATION:
758 case PM_POST_SUSPEND:
759 ttm_suspend_unlock(&vmaster->lock);
760 break;
761 case PM_RESTORE_PREPARE:
762 break;
763 case PM_POST_RESTORE:
764 break;
765 default:
766 break;
767 }
768 return 0;
769}
770
771/**
772 * These might not be needed with the virtual SVGA device.
773 */
774
775int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
776{
777 pci_save_state(pdev);
778 pci_disable_device(pdev);
779 pci_set_power_state(pdev, PCI_D3hot);
780 return 0;
781}
782
783int vmw_pci_resume(struct pci_dev *pdev)
784{
785 pci_set_power_state(pdev, PCI_D0);
786 pci_restore_state(pdev);
787 return pci_enable_device(pdev);
788}
789
fb1d9738
JB		 790static struct drm_driver driver = {
791 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
792 DRIVER_MODESET,
793 .load = vmw_driver_load,
794 .unload = vmw_driver_unload,
795 .firstopen = vmw_firstopen,
796 .lastclose = vmw_lastclose,
797 .irq_preinstall = vmw_irq_preinstall,
798 .irq_postinstall = vmw_irq_postinstall,
799 .irq_uninstall = vmw_irq_uninstall,
800 .irq_handler = vmw_irq_handler,
801 .reclaim_buffers_locked = NULL,
802 .get_map_ofs = drm_core_get_map_ofs,
803 .get_reg_ofs = drm_core_get_reg_ofs,
804 .ioctls = vmw_ioctls,
805 .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
806 .dma_quiescent = NULL, /*vmw_dma_quiescent, */
807 .master_create = vmw_master_create,
808 .master_destroy = vmw_master_destroy,
809 .master_set = vmw_master_set,
810 .master_drop = vmw_master_drop,
811 .open = vmw_driver_open,
812 .postclose = vmw_postclose,
813 .fops = {
814 .owner = THIS_MODULE,
815 .open = drm_open,
816 .release = drm_release,
817 .unlocked_ioctl = vmw_unlocked_ioctl,
818 .mmap = vmw_mmap,
819 .poll = drm_poll,
820 .fasync = drm_fasync,
821#if defined(CONFIG_COMPAT)
822 .compat_ioctl = drm_compat_ioctl,
823#endif
824 },
825 .pci_driver = {
826 .name = VMWGFX_DRIVER_NAME,
827 .id_table = vmw_pci_id_list,
828 .probe = vmw_probe,
d9f36a00
TH		 829 .remove = vmw_remove,
830 .suspend = vmw_pci_suspend,
831 .resume = vmw_pci_resume
fb1d9738
JB		 832 },
833 .name = VMWGFX_DRIVER_NAME,
834 .desc = VMWGFX_DRIVER_DESC,
835 .date = VMWGFX_DRIVER_DATE,
836 .major = VMWGFX_DRIVER_MAJOR,
837 .minor = VMWGFX_DRIVER_MINOR,
838 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
839};
840
841static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
842{
dcdb1674 843 return drm_get_pci_dev(pdev, ent, &driver);
fb1d9738
JB		 844}
845
846static int __init vmwgfx_init(void)
847{
848 int ret;
849 ret = drm_init(&driver);
850 if (ret)
851 DRM_ERROR("Failed initializing DRM.\n");
852 return ret;
853}
854
855static void __exit vmwgfx_exit(void)
856{
857 drm_exit(&driver);
858}
859
860module_init(vmwgfx_init);
861module_exit(vmwgfx_exit);
862
863MODULE_AUTHOR("VMware Inc. and others");
864MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
865MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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