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fb1d9738 JB |
1 | /************************************************************************** |
2 | * | |
3 | * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sub license, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial portions | |
16 | * of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | **************************************************************************/ | |
e0cd3608 | 27 | #include <linux/module.h> |
fb1d9738 | 28 | |
760285e7 | 29 | #include <drm/drmP.h> |
fb1d9738 | 30 | #include "vmwgfx_drv.h" |
760285e7 DH |
31 | #include <drm/ttm/ttm_placement.h> |
32 | #include <drm/ttm/ttm_bo_driver.h> | |
33 | #include <drm/ttm/ttm_object.h> | |
34 | #include <drm/ttm/ttm_module.h> | |
fb1d9738 JB |
35 | |
36 | #define VMWGFX_DRIVER_NAME "vmwgfx" | |
37 | #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" | |
38 | #define VMWGFX_CHIP_SVGAII 0 | |
39 | #define VMW_FB_RESERVATION 0 | |
40 | ||
eb4f923b JB |
41 | #define VMW_MIN_INITIAL_WIDTH 800 |
42 | #define VMW_MIN_INITIAL_HEIGHT 600 | |
43 | ||
44 | ||
fb1d9738 JB |
45 | /** |
46 | * Fully encoded drm commands. Might move to vmw_drm.h | |
47 | */ | |
48 | ||
49 | #define DRM_IOCTL_VMW_GET_PARAM \ | |
50 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ | |
51 | struct drm_vmw_getparam_arg) | |
52 | #define DRM_IOCTL_VMW_ALLOC_DMABUF \ | |
53 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ | |
54 | union drm_vmw_alloc_dmabuf_arg) | |
55 | #define DRM_IOCTL_VMW_UNREF_DMABUF \ | |
56 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ | |
57 | struct drm_vmw_unref_dmabuf_arg) | |
58 | #define DRM_IOCTL_VMW_CURSOR_BYPASS \ | |
59 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ | |
60 | struct drm_vmw_cursor_bypass_arg) | |
61 | ||
62 | #define DRM_IOCTL_VMW_CONTROL_STREAM \ | |
63 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ | |
64 | struct drm_vmw_control_stream_arg) | |
65 | #define DRM_IOCTL_VMW_CLAIM_STREAM \ | |
66 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ | |
67 | struct drm_vmw_stream_arg) | |
68 | #define DRM_IOCTL_VMW_UNREF_STREAM \ | |
69 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ | |
70 | struct drm_vmw_stream_arg) | |
71 | ||
72 | #define DRM_IOCTL_VMW_CREATE_CONTEXT \ | |
73 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ | |
74 | struct drm_vmw_context_arg) | |
75 | #define DRM_IOCTL_VMW_UNREF_CONTEXT \ | |
76 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ | |
77 | struct drm_vmw_context_arg) | |
78 | #define DRM_IOCTL_VMW_CREATE_SURFACE \ | |
79 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ | |
80 | union drm_vmw_surface_create_arg) | |
81 | #define DRM_IOCTL_VMW_UNREF_SURFACE \ | |
82 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ | |
83 | struct drm_vmw_surface_arg) | |
84 | #define DRM_IOCTL_VMW_REF_SURFACE \ | |
85 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ | |
86 | union drm_vmw_surface_reference_arg) | |
87 | #define DRM_IOCTL_VMW_EXECBUF \ | |
88 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ | |
89 | struct drm_vmw_execbuf_arg) | |
ae2a1040 TH |
90 | #define DRM_IOCTL_VMW_GET_3D_CAP \ |
91 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ | |
92 | struct drm_vmw_get_3d_cap_arg) | |
fb1d9738 JB |
93 | #define DRM_IOCTL_VMW_FENCE_WAIT \ |
94 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ | |
95 | struct drm_vmw_fence_wait_arg) | |
ae2a1040 TH |
96 | #define DRM_IOCTL_VMW_FENCE_SIGNALED \ |
97 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ | |
98 | struct drm_vmw_fence_signaled_arg) | |
99 | #define DRM_IOCTL_VMW_FENCE_UNREF \ | |
100 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ | |
101 | struct drm_vmw_fence_arg) | |
57c5ee79 TH |
102 | #define DRM_IOCTL_VMW_FENCE_EVENT \ |
103 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ | |
104 | struct drm_vmw_fence_event_arg) | |
2fcd5a73 JB |
105 | #define DRM_IOCTL_VMW_PRESENT \ |
106 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ | |
107 | struct drm_vmw_present_arg) | |
108 | #define DRM_IOCTL_VMW_PRESENT_READBACK \ | |
109 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ | |
110 | struct drm_vmw_present_readback_arg) | |
cd2b89e7 TH |
111 | #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ |
112 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ | |
113 | struct drm_vmw_update_layout_arg) | |
fb1d9738 JB |
114 | |
115 | /** | |
116 | * The core DRM version of this macro doesn't account for | |
117 | * DRM_COMMAND_BASE. | |
118 | */ | |
119 | ||
120 | #define VMW_IOCTL_DEF(ioctl, func, flags) \ | |
1b2f1489 | 121 | [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl} |
fb1d9738 JB |
122 | |
123 | /** | |
124 | * Ioctl definitions. | |
125 | */ | |
126 | ||
127 | static struct drm_ioctl_desc vmw_ioctls[] = { | |
1b2f1489 | 128 | VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, |
e1f78003 | 129 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 130 | VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, |
e1f78003 | 131 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 132 | VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, |
e1f78003 | 133 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 134 | VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, |
e1f78003 TH |
135 | vmw_kms_cursor_bypass_ioctl, |
136 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), | |
fb1d9738 | 137 | |
1b2f1489 | 138 | VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, |
e1f78003 | 139 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
1b2f1489 | 140 | VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, |
e1f78003 | 141 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
1b2f1489 | 142 | VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, |
e1f78003 | 143 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
fb1d9738 | 144 | |
1b2f1489 | 145 | VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, |
e1f78003 | 146 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 147 | VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, |
e1f78003 | 148 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 149 | VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, |
e1f78003 | 150 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 151 | VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, |
e1f78003 | 152 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 153 | VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, |
e1f78003 | 154 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 155 | VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, |
e1f78003 | 156 | DRM_AUTH | DRM_UNLOCKED), |
ae2a1040 TH |
157 | VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, |
158 | DRM_AUTH | DRM_UNLOCKED), | |
159 | VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, | |
160 | vmw_fence_obj_signaled_ioctl, | |
161 | DRM_AUTH | DRM_UNLOCKED), | |
162 | VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, | |
d8bd19d2 | 163 | DRM_AUTH | DRM_UNLOCKED), |
57c5ee79 TH |
164 | VMW_IOCTL_DEF(VMW_FENCE_EVENT, |
165 | vmw_fence_event_ioctl, | |
166 | DRM_AUTH | DRM_UNLOCKED), | |
f63f6a59 TH |
167 | VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, |
168 | DRM_AUTH | DRM_UNLOCKED), | |
2fcd5a73 JB |
169 | |
170 | /* these allow direct access to the framebuffers mark as master only */ | |
171 | VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, | |
172 | DRM_MASTER | DRM_AUTH | DRM_UNLOCKED), | |
173 | VMW_IOCTL_DEF(VMW_PRESENT_READBACK, | |
174 | vmw_present_readback_ioctl, | |
175 | DRM_MASTER | DRM_AUTH | DRM_UNLOCKED), | |
cd2b89e7 TH |
176 | VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, |
177 | vmw_kms_update_layout_ioctl, | |
178 | DRM_MASTER | DRM_UNLOCKED), | |
fb1d9738 JB |
179 | }; |
180 | ||
181 | static struct pci_device_id vmw_pci_id_list[] = { | |
182 | {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, | |
183 | {0, 0, 0} | |
184 | }; | |
c4903429 | 185 | MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); |
fb1d9738 | 186 | |
5d2afab9 | 187 | static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); |
fb1d9738 JB |
188 | |
189 | static int vmw_probe(struct pci_dev *, const struct pci_device_id *); | |
190 | static void vmw_master_init(struct vmw_master *); | |
d9f36a00 TH |
191 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
192 | void *ptr); | |
fb1d9738 | 193 | |
30c78bb8 TH |
194 | MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); |
195 | module_param_named(enable_fbdev, enable_fbdev, int, 0600); | |
196 | ||
fb1d9738 JB |
197 | static void vmw_print_capabilities(uint32_t capabilities) |
198 | { | |
199 | DRM_INFO("Capabilities:\n"); | |
200 | if (capabilities & SVGA_CAP_RECT_COPY) | |
201 | DRM_INFO(" Rect copy.\n"); | |
202 | if (capabilities & SVGA_CAP_CURSOR) | |
203 | DRM_INFO(" Cursor.\n"); | |
204 | if (capabilities & SVGA_CAP_CURSOR_BYPASS) | |
205 | DRM_INFO(" Cursor bypass.\n"); | |
206 | if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) | |
207 | DRM_INFO(" Cursor bypass 2.\n"); | |
208 | if (capabilities & SVGA_CAP_8BIT_EMULATION) | |
209 | DRM_INFO(" 8bit emulation.\n"); | |
210 | if (capabilities & SVGA_CAP_ALPHA_CURSOR) | |
211 | DRM_INFO(" Alpha cursor.\n"); | |
212 | if (capabilities & SVGA_CAP_3D) | |
213 | DRM_INFO(" 3D.\n"); | |
214 | if (capabilities & SVGA_CAP_EXTENDED_FIFO) | |
215 | DRM_INFO(" Extended Fifo.\n"); | |
216 | if (capabilities & SVGA_CAP_MULTIMON) | |
217 | DRM_INFO(" Multimon.\n"); | |
218 | if (capabilities & SVGA_CAP_PITCHLOCK) | |
219 | DRM_INFO(" Pitchlock.\n"); | |
220 | if (capabilities & SVGA_CAP_IRQMASK) | |
221 | DRM_INFO(" Irq mask.\n"); | |
222 | if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) | |
223 | DRM_INFO(" Display Topology.\n"); | |
224 | if (capabilities & SVGA_CAP_GMR) | |
225 | DRM_INFO(" GMR.\n"); | |
226 | if (capabilities & SVGA_CAP_TRACES) | |
227 | DRM_INFO(" Traces.\n"); | |
dcca2862 TH |
228 | if (capabilities & SVGA_CAP_GMR2) |
229 | DRM_INFO(" GMR2.\n"); | |
230 | if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) | |
231 | DRM_INFO(" Screen Object 2.\n"); | |
fb1d9738 JB |
232 | } |
233 | ||
e2fa3a76 TH |
234 | |
235 | /** | |
236 | * vmw_execbuf_prepare_dummy_query - Initialize a query result structure at | |
237 | * the start of a buffer object. | |
238 | * | |
239 | * @dev_priv: The device private structure. | |
240 | * | |
241 | * This function will idle the buffer using an uninterruptible wait, then | |
242 | * map the first page and initialize a pending occlusion query result structure, | |
243 | * Finally it will unmap the buffer. | |
244 | * | |
245 | * TODO: Since we're only mapping a single page, we should optimize the map | |
246 | * to use kmap_atomic / iomap_atomic. | |
247 | */ | |
248 | static void vmw_dummy_query_bo_prepare(struct vmw_private *dev_priv) | |
249 | { | |
250 | struct ttm_bo_kmap_obj map; | |
251 | volatile SVGA3dQueryResult *result; | |
252 | bool dummy; | |
253 | int ret; | |
254 | struct ttm_bo_device *bdev = &dev_priv->bdev; | |
255 | struct ttm_buffer_object *bo = dev_priv->dummy_query_bo; | |
256 | ||
257 | ttm_bo_reserve(bo, false, false, false, 0); | |
258 | spin_lock(&bdev->fence_lock); | |
1717c0e2 | 259 | ret = ttm_bo_wait(bo, false, false, false); |
e2fa3a76 TH |
260 | spin_unlock(&bdev->fence_lock); |
261 | if (unlikely(ret != 0)) | |
262 | (void) vmw_fallback_wait(dev_priv, false, true, 0, false, | |
263 | 10*HZ); | |
264 | ||
265 | ret = ttm_bo_kmap(bo, 0, 1, &map); | |
266 | if (likely(ret == 0)) { | |
267 | result = ttm_kmap_obj_virtual(&map, &dummy); | |
268 | result->totalSize = sizeof(*result); | |
269 | result->state = SVGA3D_QUERYSTATE_PENDING; | |
270 | result->result32 = 0xff; | |
271 | ttm_bo_kunmap(&map); | |
272 | } else | |
273 | DRM_ERROR("Dummy query buffer map failed.\n"); | |
274 | ttm_bo_unreserve(bo); | |
275 | } | |
276 | ||
277 | ||
278 | /** | |
279 | * vmw_dummy_query_bo_create - create a bo to hold a dummy query result | |
280 | * | |
281 | * @dev_priv: A device private structure. | |
282 | * | |
283 | * This function creates a small buffer object that holds the query | |
284 | * result for dummy queries emitted as query barriers. | |
285 | * No interruptible waits are done within this function. | |
286 | * | |
287 | * Returns an error if bo creation fails. | |
288 | */ | |
289 | static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) | |
290 | { | |
291 | return ttm_bo_create(&dev_priv->bdev, | |
292 | PAGE_SIZE, | |
293 | ttm_bo_type_device, | |
294 | &vmw_vram_sys_placement, | |
0b91c4a1 | 295 | 0, false, NULL, |
e2fa3a76 TH |
296 | &dev_priv->dummy_query_bo); |
297 | } | |
298 | ||
299 | ||
fb1d9738 JB |
300 | static int vmw_request_device(struct vmw_private *dev_priv) |
301 | { | |
302 | int ret; | |
303 | ||
fb1d9738 JB |
304 | ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); |
305 | if (unlikely(ret != 0)) { | |
306 | DRM_ERROR("Unable to initialize FIFO.\n"); | |
307 | return ret; | |
308 | } | |
ae2a1040 | 309 | vmw_fence_fifo_up(dev_priv->fman); |
e2fa3a76 TH |
310 | ret = vmw_dummy_query_bo_create(dev_priv); |
311 | if (unlikely(ret != 0)) | |
312 | goto out_no_query_bo; | |
313 | vmw_dummy_query_bo_prepare(dev_priv); | |
fb1d9738 JB |
314 | |
315 | return 0; | |
e2fa3a76 TH |
316 | |
317 | out_no_query_bo: | |
318 | vmw_fence_fifo_down(dev_priv->fman); | |
319 | vmw_fifo_release(dev_priv, &dev_priv->fifo); | |
320 | return ret; | |
fb1d9738 JB |
321 | } |
322 | ||
323 | static void vmw_release_device(struct vmw_private *dev_priv) | |
324 | { | |
e2fa3a76 TH |
325 | /* |
326 | * Previous destructions should've released | |
327 | * the pinned bo. | |
328 | */ | |
329 | ||
330 | BUG_ON(dev_priv->pinned_bo != NULL); | |
331 | ||
332 | ttm_bo_unref(&dev_priv->dummy_query_bo); | |
ae2a1040 | 333 | vmw_fence_fifo_down(dev_priv->fman); |
fb1d9738 | 334 | vmw_fifo_release(dev_priv, &dev_priv->fifo); |
30c78bb8 TH |
335 | } |
336 | ||
05730b32 TH |
337 | /** |
338 | * Increase the 3d resource refcount. | |
339 | * If the count was prevously zero, initialize the fifo, switching to svga | |
340 | * mode. Note that the master holds a ref as well, and may request an | |
341 | * explicit switch to svga mode if fb is not running, using @unhide_svga. | |
342 | */ | |
343 | int vmw_3d_resource_inc(struct vmw_private *dev_priv, | |
344 | bool unhide_svga) | |
30c78bb8 TH |
345 | { |
346 | int ret = 0; | |
347 | ||
348 | mutex_lock(&dev_priv->release_mutex); | |
349 | if (unlikely(dev_priv->num_3d_resources++ == 0)) { | |
350 | ret = vmw_request_device(dev_priv); | |
351 | if (unlikely(ret != 0)) | |
352 | --dev_priv->num_3d_resources; | |
05730b32 TH |
353 | } else if (unhide_svga) { |
354 | mutex_lock(&dev_priv->hw_mutex); | |
355 | vmw_write(dev_priv, SVGA_REG_ENABLE, | |
356 | vmw_read(dev_priv, SVGA_REG_ENABLE) & | |
357 | ~SVGA_REG_ENABLE_HIDE); | |
358 | mutex_unlock(&dev_priv->hw_mutex); | |
30c78bb8 | 359 | } |
05730b32 | 360 | |
30c78bb8 TH |
361 | mutex_unlock(&dev_priv->release_mutex); |
362 | return ret; | |
fb1d9738 JB |
363 | } |
364 | ||
05730b32 TH |
365 | /** |
366 | * Decrease the 3d resource refcount. | |
367 | * If the count reaches zero, disable the fifo, switching to vga mode. | |
368 | * Note that the master holds a refcount as well, and may request an | |
369 | * explicit switch to vga mode when it releases its refcount to account | |
370 | * for the situation of an X server vt switch to VGA with 3d resources | |
371 | * active. | |
372 | */ | |
373 | void vmw_3d_resource_dec(struct vmw_private *dev_priv, | |
374 | bool hide_svga) | |
30c78bb8 TH |
375 | { |
376 | int32_t n3d; | |
377 | ||
378 | mutex_lock(&dev_priv->release_mutex); | |
379 | if (unlikely(--dev_priv->num_3d_resources == 0)) | |
380 | vmw_release_device(dev_priv); | |
05730b32 TH |
381 | else if (hide_svga) { |
382 | mutex_lock(&dev_priv->hw_mutex); | |
383 | vmw_write(dev_priv, SVGA_REG_ENABLE, | |
384 | vmw_read(dev_priv, SVGA_REG_ENABLE) | | |
385 | SVGA_REG_ENABLE_HIDE); | |
386 | mutex_unlock(&dev_priv->hw_mutex); | |
387 | } | |
388 | ||
30c78bb8 TH |
389 | n3d = (int32_t) dev_priv->num_3d_resources; |
390 | mutex_unlock(&dev_priv->release_mutex); | |
391 | ||
392 | BUG_ON(n3d < 0); | |
393 | } | |
394 | ||
eb4f923b JB |
395 | /** |
396 | * Sets the initial_[width|height] fields on the given vmw_private. | |
397 | * | |
398 | * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then | |
67d4a87b TH |
399 | * clamping the value to fb_max_[width|height] fields and the |
400 | * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. | |
401 | * If the values appear to be invalid, set them to | |
eb4f923b JB |
402 | * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. |
403 | */ | |
404 | static void vmw_get_initial_size(struct vmw_private *dev_priv) | |
405 | { | |
406 | uint32_t width; | |
407 | uint32_t height; | |
408 | ||
409 | width = vmw_read(dev_priv, SVGA_REG_WIDTH); | |
410 | height = vmw_read(dev_priv, SVGA_REG_HEIGHT); | |
411 | ||
412 | width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); | |
eb4f923b | 413 | height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); |
67d4a87b TH |
414 | |
415 | if (width > dev_priv->fb_max_width || | |
416 | height > dev_priv->fb_max_height) { | |
417 | ||
418 | /* | |
419 | * This is a host error and shouldn't occur. | |
420 | */ | |
421 | ||
422 | width = VMW_MIN_INITIAL_WIDTH; | |
423 | height = VMW_MIN_INITIAL_HEIGHT; | |
424 | } | |
eb4f923b JB |
425 | |
426 | dev_priv->initial_width = width; | |
427 | dev_priv->initial_height = height; | |
428 | } | |
429 | ||
fb1d9738 JB |
430 | static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) |
431 | { | |
432 | struct vmw_private *dev_priv; | |
433 | int ret; | |
c188660f | 434 | uint32_t svga_id; |
c0951b79 | 435 | enum vmw_res_type i; |
fb1d9738 JB |
436 | |
437 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | |
438 | if (unlikely(dev_priv == NULL)) { | |
439 | DRM_ERROR("Failed allocating a device private struct.\n"); | |
440 | return -ENOMEM; | |
441 | } | |
fb1d9738 | 442 | |
466e69b8 DA |
443 | pci_set_master(dev->pdev); |
444 | ||
fb1d9738 JB |
445 | dev_priv->dev = dev; |
446 | dev_priv->vmw_chipset = chipset; | |
6bcd8d3c | 447 | dev_priv->last_read_seqno = (uint32_t) -100; |
fb1d9738 JB |
448 | mutex_init(&dev_priv->hw_mutex); |
449 | mutex_init(&dev_priv->cmdbuf_mutex); | |
30c78bb8 | 450 | mutex_init(&dev_priv->release_mutex); |
fb1d9738 | 451 | rwlock_init(&dev_priv->resource_lock); |
c0951b79 TH |
452 | |
453 | for (i = vmw_res_context; i < vmw_res_max; ++i) { | |
454 | idr_init(&dev_priv->res_idr[i]); | |
455 | INIT_LIST_HEAD(&dev_priv->res_lru[i]); | |
456 | } | |
457 | ||
fb1d9738 JB |
458 | mutex_init(&dev_priv->init_mutex); |
459 | init_waitqueue_head(&dev_priv->fence_queue); | |
460 | init_waitqueue_head(&dev_priv->fifo_queue); | |
4f73a96b | 461 | dev_priv->fence_queue_waiters = 0; |
fb1d9738 | 462 | atomic_set(&dev_priv->fifo_queue_waiters, 0); |
c0951b79 | 463 | |
5bb39e81 | 464 | dev_priv->used_memory_size = 0; |
fb1d9738 JB |
465 | |
466 | dev_priv->io_start = pci_resource_start(dev->pdev, 0); | |
467 | dev_priv->vram_start = pci_resource_start(dev->pdev, 1); | |
468 | dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); | |
469 | ||
30c78bb8 TH |
470 | dev_priv->enable_fb = enable_fbdev; |
471 | ||
fb1d9738 | 472 | mutex_lock(&dev_priv->hw_mutex); |
c188660f PH |
473 | |
474 | vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); | |
475 | svga_id = vmw_read(dev_priv, SVGA_REG_ID); | |
476 | if (svga_id != SVGA_ID_2) { | |
477 | ret = -ENOSYS; | |
49625904 | 478 | DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); |
c188660f PH |
479 | mutex_unlock(&dev_priv->hw_mutex); |
480 | goto out_err0; | |
481 | } | |
482 | ||
fb1d9738 JB |
483 | dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); |
484 | ||
5bb39e81 TH |
485 | dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); |
486 | dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); | |
487 | dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); | |
488 | dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); | |
eb4f923b JB |
489 | |
490 | vmw_get_initial_size(dev_priv); | |
491 | ||
fb1d9738 JB |
492 | if (dev_priv->capabilities & SVGA_CAP_GMR) { |
493 | dev_priv->max_gmr_descriptors = | |
494 | vmw_read(dev_priv, | |
495 | SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH); | |
496 | dev_priv->max_gmr_ids = | |
497 | vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); | |
498 | } | |
fb17f189 TH |
499 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
500 | dev_priv->max_gmr_pages = | |
501 | vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); | |
502 | dev_priv->memory_size = | |
503 | vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); | |
5bb39e81 TH |
504 | dev_priv->memory_size -= dev_priv->vram_size; |
505 | } else { | |
506 | /* | |
507 | * An arbitrary limit of 512MiB on surface | |
508 | * memory. But all HWV8 hardware supports GMR2. | |
509 | */ | |
510 | dev_priv->memory_size = 512*1024*1024; | |
fb17f189 | 511 | } |
fb1d9738 | 512 | |
fb1d9738 JB |
513 | mutex_unlock(&dev_priv->hw_mutex); |
514 | ||
515 | vmw_print_capabilities(dev_priv->capabilities); | |
516 | ||
517 | if (dev_priv->capabilities & SVGA_CAP_GMR) { | |
518 | DRM_INFO("Max GMR ids is %u\n", | |
519 | (unsigned)dev_priv->max_gmr_ids); | |
520 | DRM_INFO("Max GMR descriptors is %u\n", | |
521 | (unsigned)dev_priv->max_gmr_descriptors); | |
522 | } | |
fb17f189 TH |
523 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
524 | DRM_INFO("Max number of GMR pages is %u\n", | |
525 | (unsigned)dev_priv->max_gmr_pages); | |
5bb39e81 TH |
526 | DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", |
527 | (unsigned)dev_priv->memory_size / 1024); | |
fb17f189 | 528 | } |
fb1d9738 JB |
529 | DRM_INFO("VRAM at 0x%08x size is %u kiB\n", |
530 | dev_priv->vram_start, dev_priv->vram_size / 1024); | |
531 | DRM_INFO("MMIO at 0x%08x size is %u kiB\n", | |
532 | dev_priv->mmio_start, dev_priv->mmio_size / 1024); | |
533 | ||
534 | ret = vmw_ttm_global_init(dev_priv); | |
535 | if (unlikely(ret != 0)) | |
536 | goto out_err0; | |
537 | ||
538 | ||
539 | vmw_master_init(&dev_priv->fbdev_master); | |
540 | ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); | |
541 | dev_priv->active_master = &dev_priv->fbdev_master; | |
542 | ||
a2c06ee2 | 543 | |
fb1d9738 JB |
544 | ret = ttm_bo_device_init(&dev_priv->bdev, |
545 | dev_priv->bo_global_ref.ref.object, | |
546 | &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET, | |
547 | false); | |
548 | if (unlikely(ret != 0)) { | |
549 | DRM_ERROR("Failed initializing TTM buffer object driver.\n"); | |
550 | goto out_err1; | |
551 | } | |
552 | ||
553 | ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, | |
554 | (dev_priv->vram_size >> PAGE_SHIFT)); | |
555 | if (unlikely(ret != 0)) { | |
556 | DRM_ERROR("Failed initializing memory manager for VRAM.\n"); | |
557 | goto out_err2; | |
558 | } | |
559 | ||
135cba0d TH |
560 | dev_priv->has_gmr = true; |
561 | if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, | |
562 | dev_priv->max_gmr_ids) != 0) { | |
563 | DRM_INFO("No GMR memory available. " | |
564 | "Graphics memory resources are very limited.\n"); | |
565 | dev_priv->has_gmr = false; | |
566 | } | |
567 | ||
247d36d7 AL |
568 | dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start, |
569 | dev_priv->mmio_size); | |
fb1d9738 JB |
570 | |
571 | dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start, | |
572 | dev_priv->mmio_size); | |
573 | ||
574 | if (unlikely(dev_priv->mmio_virt == NULL)) { | |
575 | ret = -ENOMEM; | |
576 | DRM_ERROR("Failed mapping MMIO.\n"); | |
577 | goto out_err3; | |
578 | } | |
579 | ||
d7e1958d JB |
580 | /* Need mmio memory to check for fifo pitchlock cap. */ |
581 | if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && | |
582 | !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && | |
583 | !vmw_fifo_have_pitchlock(dev_priv)) { | |
584 | ret = -ENOSYS; | |
585 | DRM_ERROR("Hardware has no pitchlock\n"); | |
586 | goto out_err4; | |
587 | } | |
588 | ||
fb1d9738 JB |
589 | dev_priv->tdev = ttm_object_device_init |
590 | (dev_priv->mem_global_ref.object, 12); | |
591 | ||
592 | if (unlikely(dev_priv->tdev == NULL)) { | |
593 | DRM_ERROR("Unable to initialize TTM object management.\n"); | |
594 | ret = -ENOMEM; | |
595 | goto out_err4; | |
596 | } | |
597 | ||
598 | dev->dev_private = dev_priv; | |
599 | ||
fb1d9738 JB |
600 | ret = pci_request_regions(dev->pdev, "vmwgfx probe"); |
601 | dev_priv->stealth = (ret != 0); | |
602 | if (dev_priv->stealth) { | |
603 | /** | |
604 | * Request at least the mmio PCI resource. | |
605 | */ | |
606 | ||
607 | DRM_INFO("It appears like vesafb is loaded. " | |
f2d12b8e | 608 | "Ignore above error if any.\n"); |
fb1d9738 JB |
609 | ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); |
610 | if (unlikely(ret != 0)) { | |
611 | DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); | |
612 | goto out_no_device; | |
613 | } | |
fb1d9738 | 614 | } |
ae2a1040 | 615 | |
506ff75c TH |
616 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { |
617 | ret = drm_irq_install(dev); | |
618 | if (ret != 0) { | |
619 | DRM_ERROR("Failed installing irq: %d\n", ret); | |
620 | goto out_no_irq; | |
621 | } | |
622 | } | |
623 | ||
ae2a1040 TH |
624 | dev_priv->fman = vmw_fence_manager_init(dev_priv); |
625 | if (unlikely(dev_priv->fman == NULL)) | |
626 | goto out_no_fman; | |
56d1c78d | 627 | |
56d1c78d | 628 | vmw_kms_save_vga(dev_priv); |
56d1c78d JB |
629 | |
630 | /* Start kms and overlay systems, needs fifo. */ | |
7a1c2f6c TH |
631 | ret = vmw_kms_init(dev_priv); |
632 | if (unlikely(ret != 0)) | |
633 | goto out_no_kms; | |
f2d12b8e | 634 | vmw_overlay_init(dev_priv); |
56d1c78d | 635 | |
30c78bb8 | 636 | if (dev_priv->enable_fb) { |
506ff75c TH |
637 | ret = vmw_3d_resource_inc(dev_priv, true); |
638 | if (unlikely(ret != 0)) | |
639 | goto out_no_fifo; | |
30c78bb8 | 640 | vmw_fb_init(dev_priv); |
7a1c2f6c TH |
641 | } |
642 | ||
d9f36a00 TH |
643 | dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; |
644 | register_pm_notifier(&dev_priv->pm_nb); | |
645 | ||
fb1d9738 JB |
646 | return 0; |
647 | ||
506ff75c | 648 | out_no_fifo: |
56d1c78d JB |
649 | vmw_overlay_close(dev_priv); |
650 | vmw_kms_close(dev_priv); | |
651 | out_no_kms: | |
506ff75c | 652 | vmw_kms_restore_vga(dev_priv); |
ae2a1040 TH |
653 | vmw_fence_manager_takedown(dev_priv->fman); |
654 | out_no_fman: | |
506ff75c TH |
655 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
656 | drm_irq_uninstall(dev_priv->dev); | |
657 | out_no_irq: | |
30c78bb8 TH |
658 | if (dev_priv->stealth) |
659 | pci_release_region(dev->pdev, 2); | |
660 | else | |
661 | pci_release_regions(dev->pdev); | |
fb1d9738 | 662 | out_no_device: |
fb1d9738 JB |
663 | ttm_object_device_release(&dev_priv->tdev); |
664 | out_err4: | |
665 | iounmap(dev_priv->mmio_virt); | |
666 | out_err3: | |
247d36d7 | 667 | arch_phys_wc_del(dev_priv->mmio_mtrr); |
135cba0d TH |
668 | if (dev_priv->has_gmr) |
669 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | |
fb1d9738 JB |
670 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); |
671 | out_err2: | |
672 | (void)ttm_bo_device_release(&dev_priv->bdev); | |
673 | out_err1: | |
674 | vmw_ttm_global_release(dev_priv); | |
675 | out_err0: | |
c0951b79 TH |
676 | for (i = vmw_res_context; i < vmw_res_max; ++i) |
677 | idr_destroy(&dev_priv->res_idr[i]); | |
678 | ||
fb1d9738 JB |
679 | kfree(dev_priv); |
680 | return ret; | |
681 | } | |
682 | ||
683 | static int vmw_driver_unload(struct drm_device *dev) | |
684 | { | |
685 | struct vmw_private *dev_priv = vmw_priv(dev); | |
c0951b79 | 686 | enum vmw_res_type i; |
fb1d9738 | 687 | |
d9f36a00 TH |
688 | unregister_pm_notifier(&dev_priv->pm_nb); |
689 | ||
c0951b79 TH |
690 | if (dev_priv->ctx.res_ht_initialized) |
691 | drm_ht_remove(&dev_priv->ctx.res_ht); | |
be38ab6e TH |
692 | if (dev_priv->ctx.cmd_bounce) |
693 | vfree(dev_priv->ctx.cmd_bounce); | |
30c78bb8 TH |
694 | if (dev_priv->enable_fb) { |
695 | vmw_fb_close(dev_priv); | |
696 | vmw_kms_restore_vga(dev_priv); | |
05730b32 | 697 | vmw_3d_resource_dec(dev_priv, false); |
30c78bb8 | 698 | } |
f2d12b8e TH |
699 | vmw_kms_close(dev_priv); |
700 | vmw_overlay_close(dev_priv); | |
ae2a1040 | 701 | vmw_fence_manager_takedown(dev_priv->fman); |
506ff75c TH |
702 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
703 | drm_irq_uninstall(dev_priv->dev); | |
f2d12b8e | 704 | if (dev_priv->stealth) |
fb1d9738 | 705 | pci_release_region(dev->pdev, 2); |
f2d12b8e TH |
706 | else |
707 | pci_release_regions(dev->pdev); | |
708 | ||
fb1d9738 JB |
709 | ttm_object_device_release(&dev_priv->tdev); |
710 | iounmap(dev_priv->mmio_virt); | |
247d36d7 | 711 | arch_phys_wc_del(dev_priv->mmio_mtrr); |
135cba0d TH |
712 | if (dev_priv->has_gmr) |
713 | (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | |
fb1d9738 JB |
714 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); |
715 | (void)ttm_bo_device_release(&dev_priv->bdev); | |
716 | vmw_ttm_global_release(dev_priv); | |
c0951b79 TH |
717 | |
718 | for (i = vmw_res_context; i < vmw_res_max; ++i) | |
719 | idr_destroy(&dev_priv->res_idr[i]); | |
fb1d9738 JB |
720 | |
721 | kfree(dev_priv); | |
722 | ||
723 | return 0; | |
724 | } | |
725 | ||
6b82ef50 TH |
726 | static void vmw_preclose(struct drm_device *dev, |
727 | struct drm_file *file_priv) | |
728 | { | |
729 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
730 | struct vmw_private *dev_priv = vmw_priv(dev); | |
731 | ||
732 | vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events); | |
733 | } | |
734 | ||
fb1d9738 JB |
735 | static void vmw_postclose(struct drm_device *dev, |
736 | struct drm_file *file_priv) | |
737 | { | |
738 | struct vmw_fpriv *vmw_fp; | |
739 | ||
740 | vmw_fp = vmw_fpriv(file_priv); | |
741 | ttm_object_file_release(&vmw_fp->tfile); | |
742 | if (vmw_fp->locked_master) | |
743 | drm_master_put(&vmw_fp->locked_master); | |
744 | kfree(vmw_fp); | |
745 | } | |
746 | ||
747 | static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) | |
748 | { | |
749 | struct vmw_private *dev_priv = vmw_priv(dev); | |
750 | struct vmw_fpriv *vmw_fp; | |
751 | int ret = -ENOMEM; | |
752 | ||
753 | vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); | |
754 | if (unlikely(vmw_fp == NULL)) | |
755 | return ret; | |
756 | ||
6b82ef50 | 757 | INIT_LIST_HEAD(&vmw_fp->fence_events); |
fb1d9738 JB |
758 | vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); |
759 | if (unlikely(vmw_fp->tfile == NULL)) | |
760 | goto out_no_tfile; | |
761 | ||
762 | file_priv->driver_priv = vmw_fp; | |
949c4a34 | 763 | dev_priv->bdev.dev_mapping = dev->dev_mapping; |
fb1d9738 JB |
764 | |
765 | return 0; | |
766 | ||
767 | out_no_tfile: | |
768 | kfree(vmw_fp); | |
769 | return ret; | |
770 | } | |
771 | ||
772 | static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, | |
773 | unsigned long arg) | |
774 | { | |
775 | struct drm_file *file_priv = filp->private_data; | |
776 | struct drm_device *dev = file_priv->minor->dev; | |
777 | unsigned int nr = DRM_IOCTL_NR(cmd); | |
fb1d9738 JB |
778 | |
779 | /* | |
e1f78003 | 780 | * Do extra checking on driver private ioctls. |
fb1d9738 JB |
781 | */ |
782 | ||
783 | if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) | |
784 | && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { | |
785 | struct drm_ioctl_desc *ioctl = | |
786 | &vmw_ioctls[nr - DRM_COMMAND_BASE]; | |
787 | ||
2854eeda | 788 | if (unlikely(ioctl->cmd_drv != cmd)) { |
fb1d9738 JB |
789 | DRM_ERROR("Invalid command format, ioctl %d\n", |
790 | nr - DRM_COMMAND_BASE); | |
791 | return -EINVAL; | |
792 | } | |
fb1d9738 JB |
793 | } |
794 | ||
e1f78003 | 795 | return drm_ioctl(filp, cmd, arg); |
fb1d9738 JB |
796 | } |
797 | ||
798 | static int vmw_firstopen(struct drm_device *dev) | |
799 | { | |
800 | struct vmw_private *dev_priv = vmw_priv(dev); | |
801 | dev_priv->is_opened = true; | |
802 | ||
803 | return 0; | |
804 | } | |
805 | ||
806 | static void vmw_lastclose(struct drm_device *dev) | |
807 | { | |
808 | struct vmw_private *dev_priv = vmw_priv(dev); | |
809 | struct drm_crtc *crtc; | |
810 | struct drm_mode_set set; | |
811 | int ret; | |
812 | ||
813 | /** | |
814 | * Do nothing on the lastclose call from drm_unload. | |
815 | */ | |
816 | ||
817 | if (!dev_priv->is_opened) | |
818 | return; | |
819 | ||
820 | dev_priv->is_opened = false; | |
821 | set.x = 0; | |
822 | set.y = 0; | |
823 | set.fb = NULL; | |
824 | set.mode = NULL; | |
825 | set.connectors = NULL; | |
826 | set.num_connectors = 0; | |
827 | ||
828 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
829 | set.crtc = crtc; | |
2d13b679 | 830 | ret = drm_mode_set_config_internal(&set); |
fb1d9738 JB |
831 | WARN_ON(ret != 0); |
832 | } | |
833 | ||
834 | } | |
835 | ||
836 | static void vmw_master_init(struct vmw_master *vmaster) | |
837 | { | |
838 | ttm_lock_init(&vmaster->lock); | |
3a939a5e TH |
839 | INIT_LIST_HEAD(&vmaster->fb_surf); |
840 | mutex_init(&vmaster->fb_surf_mutex); | |
fb1d9738 JB |
841 | } |
842 | ||
843 | static int vmw_master_create(struct drm_device *dev, | |
844 | struct drm_master *master) | |
845 | { | |
846 | struct vmw_master *vmaster; | |
847 | ||
fb1d9738 JB |
848 | vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); |
849 | if (unlikely(vmaster == NULL)) | |
850 | return -ENOMEM; | |
851 | ||
3a939a5e | 852 | vmw_master_init(vmaster); |
fb1d9738 JB |
853 | ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); |
854 | master->driver_priv = vmaster; | |
855 | ||
856 | return 0; | |
857 | } | |
858 | ||
859 | static void vmw_master_destroy(struct drm_device *dev, | |
860 | struct drm_master *master) | |
861 | { | |
862 | struct vmw_master *vmaster = vmw_master(master); | |
863 | ||
fb1d9738 JB |
864 | master->driver_priv = NULL; |
865 | kfree(vmaster); | |
866 | } | |
867 | ||
868 | ||
869 | static int vmw_master_set(struct drm_device *dev, | |
870 | struct drm_file *file_priv, | |
871 | bool from_open) | |
872 | { | |
873 | struct vmw_private *dev_priv = vmw_priv(dev); | |
874 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
875 | struct vmw_master *active = dev_priv->active_master; | |
876 | struct vmw_master *vmaster = vmw_master(file_priv->master); | |
877 | int ret = 0; | |
878 | ||
30c78bb8 | 879 | if (!dev_priv->enable_fb) { |
05730b32 | 880 | ret = vmw_3d_resource_inc(dev_priv, true); |
30c78bb8 TH |
881 | if (unlikely(ret != 0)) |
882 | return ret; | |
883 | vmw_kms_save_vga(dev_priv); | |
884 | mutex_lock(&dev_priv->hw_mutex); | |
885 | vmw_write(dev_priv, SVGA_REG_TRACES, 0); | |
886 | mutex_unlock(&dev_priv->hw_mutex); | |
887 | } | |
888 | ||
fb1d9738 JB |
889 | if (active) { |
890 | BUG_ON(active != &dev_priv->fbdev_master); | |
891 | ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); | |
892 | if (unlikely(ret != 0)) | |
893 | goto out_no_active_lock; | |
894 | ||
895 | ttm_lock_set_kill(&active->lock, true, SIGTERM); | |
896 | ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); | |
897 | if (unlikely(ret != 0)) { | |
898 | DRM_ERROR("Unable to clean VRAM on " | |
899 | "master drop.\n"); | |
900 | } | |
901 | ||
902 | dev_priv->active_master = NULL; | |
903 | } | |
904 | ||
905 | ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); | |
906 | if (!from_open) { | |
907 | ttm_vt_unlock(&vmaster->lock); | |
908 | BUG_ON(vmw_fp->locked_master != file_priv->master); | |
909 | drm_master_put(&vmw_fp->locked_master); | |
910 | } | |
911 | ||
912 | dev_priv->active_master = vmaster; | |
913 | ||
914 | return 0; | |
915 | ||
916 | out_no_active_lock: | |
30c78bb8 | 917 | if (!dev_priv->enable_fb) { |
ba723fe8 TH |
918 | vmw_kms_restore_vga(dev_priv); |
919 | vmw_3d_resource_dec(dev_priv, true); | |
30c78bb8 TH |
920 | mutex_lock(&dev_priv->hw_mutex); |
921 | vmw_write(dev_priv, SVGA_REG_TRACES, 1); | |
922 | mutex_unlock(&dev_priv->hw_mutex); | |
30c78bb8 | 923 | } |
fb1d9738 JB |
924 | return ret; |
925 | } | |
926 | ||
927 | static void vmw_master_drop(struct drm_device *dev, | |
928 | struct drm_file *file_priv, | |
929 | bool from_release) | |
930 | { | |
931 | struct vmw_private *dev_priv = vmw_priv(dev); | |
932 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
933 | struct vmw_master *vmaster = vmw_master(file_priv->master); | |
934 | int ret; | |
935 | ||
fb1d9738 JB |
936 | /** |
937 | * Make sure the master doesn't disappear while we have | |
938 | * it locked. | |
939 | */ | |
940 | ||
941 | vmw_fp->locked_master = drm_master_get(file_priv->master); | |
942 | ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); | |
c0951b79 | 943 | vmw_execbuf_release_pinned_bo(dev_priv); |
e2fa3a76 | 944 | |
fb1d9738 JB |
945 | if (unlikely((ret != 0))) { |
946 | DRM_ERROR("Unable to lock TTM at VT switch.\n"); | |
947 | drm_master_put(&vmw_fp->locked_master); | |
948 | } | |
949 | ||
950 | ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); | |
951 | ||
30c78bb8 TH |
952 | if (!dev_priv->enable_fb) { |
953 | ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); | |
954 | if (unlikely(ret != 0)) | |
955 | DRM_ERROR("Unable to clean VRAM on master drop.\n"); | |
ba723fe8 TH |
956 | vmw_kms_restore_vga(dev_priv); |
957 | vmw_3d_resource_dec(dev_priv, true); | |
30c78bb8 TH |
958 | mutex_lock(&dev_priv->hw_mutex); |
959 | vmw_write(dev_priv, SVGA_REG_TRACES, 1); | |
960 | mutex_unlock(&dev_priv->hw_mutex); | |
30c78bb8 TH |
961 | } |
962 | ||
fb1d9738 JB |
963 | dev_priv->active_master = &dev_priv->fbdev_master; |
964 | ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); | |
965 | ttm_vt_unlock(&dev_priv->fbdev_master.lock); | |
966 | ||
30c78bb8 TH |
967 | if (dev_priv->enable_fb) |
968 | vmw_fb_on(dev_priv); | |
fb1d9738 JB |
969 | } |
970 | ||
971 | ||
972 | static void vmw_remove(struct pci_dev *pdev) | |
973 | { | |
974 | struct drm_device *dev = pci_get_drvdata(pdev); | |
975 | ||
976 | drm_put_dev(dev); | |
977 | } | |
978 | ||
d9f36a00 TH |
979 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
980 | void *ptr) | |
981 | { | |
982 | struct vmw_private *dev_priv = | |
983 | container_of(nb, struct vmw_private, pm_nb); | |
984 | struct vmw_master *vmaster = dev_priv->active_master; | |
985 | ||
986 | switch (val) { | |
987 | case PM_HIBERNATION_PREPARE: | |
988 | case PM_SUSPEND_PREPARE: | |
989 | ttm_suspend_lock(&vmaster->lock); | |
990 | ||
991 | /** | |
992 | * This empties VRAM and unbinds all GMR bindings. | |
993 | * Buffer contents is moved to swappable memory. | |
994 | */ | |
c0951b79 TH |
995 | vmw_execbuf_release_pinned_bo(dev_priv); |
996 | vmw_resource_evict_all(dev_priv); | |
d9f36a00 | 997 | ttm_bo_swapout_all(&dev_priv->bdev); |
094e0fa8 | 998 | |
d9f36a00 TH |
999 | break; |
1000 | case PM_POST_HIBERNATION: | |
1001 | case PM_POST_SUSPEND: | |
094e0fa8 | 1002 | case PM_POST_RESTORE: |
d9f36a00 | 1003 | ttm_suspend_unlock(&vmaster->lock); |
094e0fa8 | 1004 | |
d9f36a00 TH |
1005 | break; |
1006 | case PM_RESTORE_PREPARE: | |
1007 | break; | |
d9f36a00 TH |
1008 | default: |
1009 | break; | |
1010 | } | |
1011 | return 0; | |
1012 | } | |
1013 | ||
1014 | /** | |
1015 | * These might not be needed with the virtual SVGA device. | |
1016 | */ | |
1017 | ||
7fbd721a | 1018 | static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
d9f36a00 | 1019 | { |
094e0fa8 TH |
1020 | struct drm_device *dev = pci_get_drvdata(pdev); |
1021 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1022 | ||
1023 | if (dev_priv->num_3d_resources != 0) { | |
1024 | DRM_INFO("Can't suspend or hibernate " | |
1025 | "while 3D resources are active.\n"); | |
1026 | return -EBUSY; | |
1027 | } | |
1028 | ||
d9f36a00 TH |
1029 | pci_save_state(pdev); |
1030 | pci_disable_device(pdev); | |
1031 | pci_set_power_state(pdev, PCI_D3hot); | |
1032 | return 0; | |
1033 | } | |
1034 | ||
7fbd721a | 1035 | static int vmw_pci_resume(struct pci_dev *pdev) |
d9f36a00 TH |
1036 | { |
1037 | pci_set_power_state(pdev, PCI_D0); | |
1038 | pci_restore_state(pdev); | |
1039 | return pci_enable_device(pdev); | |
1040 | } | |
1041 | ||
7fbd721a TH |
1042 | static int vmw_pm_suspend(struct device *kdev) |
1043 | { | |
1044 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1045 | struct pm_message dummy; | |
1046 | ||
1047 | dummy.event = 0; | |
1048 | ||
1049 | return vmw_pci_suspend(pdev, dummy); | |
1050 | } | |
1051 | ||
1052 | static int vmw_pm_resume(struct device *kdev) | |
1053 | { | |
1054 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1055 | ||
1056 | return vmw_pci_resume(pdev); | |
1057 | } | |
1058 | ||
1059 | static int vmw_pm_prepare(struct device *kdev) | |
1060 | { | |
1061 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1062 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1063 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1064 | ||
1065 | /** | |
1066 | * Release 3d reference held by fbdev and potentially | |
1067 | * stop fifo. | |
1068 | */ | |
1069 | dev_priv->suspended = true; | |
1070 | if (dev_priv->enable_fb) | |
05730b32 | 1071 | vmw_3d_resource_dec(dev_priv, true); |
7fbd721a TH |
1072 | |
1073 | if (dev_priv->num_3d_resources != 0) { | |
1074 | ||
1075 | DRM_INFO("Can't suspend or hibernate " | |
1076 | "while 3D resources are active.\n"); | |
1077 | ||
1078 | if (dev_priv->enable_fb) | |
05730b32 | 1079 | vmw_3d_resource_inc(dev_priv, true); |
7fbd721a TH |
1080 | dev_priv->suspended = false; |
1081 | return -EBUSY; | |
1082 | } | |
1083 | ||
1084 | return 0; | |
1085 | } | |
1086 | ||
1087 | static void vmw_pm_complete(struct device *kdev) | |
1088 | { | |
1089 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1090 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1091 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1092 | ||
95e8f6a2 TH |
1093 | mutex_lock(&dev_priv->hw_mutex); |
1094 | vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); | |
1095 | (void) vmw_read(dev_priv, SVGA_REG_ID); | |
1096 | mutex_unlock(&dev_priv->hw_mutex); | |
1097 | ||
7fbd721a TH |
1098 | /** |
1099 | * Reclaim 3d reference held by fbdev and potentially | |
1100 | * start fifo. | |
1101 | */ | |
1102 | if (dev_priv->enable_fb) | |
05730b32 | 1103 | vmw_3d_resource_inc(dev_priv, false); |
7fbd721a TH |
1104 | |
1105 | dev_priv->suspended = false; | |
1106 | } | |
1107 | ||
1108 | static const struct dev_pm_ops vmw_pm_ops = { | |
1109 | .prepare = vmw_pm_prepare, | |
1110 | .complete = vmw_pm_complete, | |
1111 | .suspend = vmw_pm_suspend, | |
1112 | .resume = vmw_pm_resume, | |
1113 | }; | |
1114 | ||
e08e96de AV |
1115 | static const struct file_operations vmwgfx_driver_fops = { |
1116 | .owner = THIS_MODULE, | |
1117 | .open = drm_open, | |
1118 | .release = drm_release, | |
1119 | .unlocked_ioctl = vmw_unlocked_ioctl, | |
1120 | .mmap = vmw_mmap, | |
1121 | .poll = vmw_fops_poll, | |
1122 | .read = vmw_fops_read, | |
1123 | .fasync = drm_fasync, | |
1124 | #if defined(CONFIG_COMPAT) | |
1125 | .compat_ioctl = drm_compat_ioctl, | |
1126 | #endif | |
1127 | .llseek = noop_llseek, | |
1128 | }; | |
1129 | ||
fb1d9738 JB |
1130 | static struct drm_driver driver = { |
1131 | .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | | |
1132 | DRIVER_MODESET, | |
1133 | .load = vmw_driver_load, | |
1134 | .unload = vmw_driver_unload, | |
1135 | .firstopen = vmw_firstopen, | |
1136 | .lastclose = vmw_lastclose, | |
1137 | .irq_preinstall = vmw_irq_preinstall, | |
1138 | .irq_postinstall = vmw_irq_postinstall, | |
1139 | .irq_uninstall = vmw_irq_uninstall, | |
1140 | .irq_handler = vmw_irq_handler, | |
7a1c2f6c | 1141 | .get_vblank_counter = vmw_get_vblank_counter, |
1c482ab3 JB |
1142 | .enable_vblank = vmw_enable_vblank, |
1143 | .disable_vblank = vmw_disable_vblank, | |
fb1d9738 JB |
1144 | .ioctls = vmw_ioctls, |
1145 | .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls), | |
1146 | .dma_quiescent = NULL, /*vmw_dma_quiescent, */ | |
1147 | .master_create = vmw_master_create, | |
1148 | .master_destroy = vmw_master_destroy, | |
1149 | .master_set = vmw_master_set, | |
1150 | .master_drop = vmw_master_drop, | |
1151 | .open = vmw_driver_open, | |
6b82ef50 | 1152 | .preclose = vmw_preclose, |
fb1d9738 | 1153 | .postclose = vmw_postclose, |
5e1782d2 DA |
1154 | |
1155 | .dumb_create = vmw_dumb_create, | |
1156 | .dumb_map_offset = vmw_dumb_map_offset, | |
1157 | .dumb_destroy = vmw_dumb_destroy, | |
1158 | ||
e08e96de | 1159 | .fops = &vmwgfx_driver_fops, |
fb1d9738 JB |
1160 | .name = VMWGFX_DRIVER_NAME, |
1161 | .desc = VMWGFX_DRIVER_DESC, | |
1162 | .date = VMWGFX_DRIVER_DATE, | |
1163 | .major = VMWGFX_DRIVER_MAJOR, | |
1164 | .minor = VMWGFX_DRIVER_MINOR, | |
1165 | .patchlevel = VMWGFX_DRIVER_PATCHLEVEL | |
1166 | }; | |
1167 | ||
8410ea3b DA |
1168 | static struct pci_driver vmw_pci_driver = { |
1169 | .name = VMWGFX_DRIVER_NAME, | |
1170 | .id_table = vmw_pci_id_list, | |
1171 | .probe = vmw_probe, | |
1172 | .remove = vmw_remove, | |
1173 | .driver = { | |
1174 | .pm = &vmw_pm_ops | |
1175 | } | |
1176 | }; | |
1177 | ||
fb1d9738 JB |
1178 | static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
1179 | { | |
dcdb1674 | 1180 | return drm_get_pci_dev(pdev, ent, &driver); |
fb1d9738 JB |
1181 | } |
1182 | ||
1183 | static int __init vmwgfx_init(void) | |
1184 | { | |
1185 | int ret; | |
8410ea3b | 1186 | ret = drm_pci_init(&driver, &vmw_pci_driver); |
fb1d9738 JB |
1187 | if (ret) |
1188 | DRM_ERROR("Failed initializing DRM.\n"); | |
1189 | return ret; | |
1190 | } | |
1191 | ||
1192 | static void __exit vmwgfx_exit(void) | |
1193 | { | |
8410ea3b | 1194 | drm_pci_exit(&driver, &vmw_pci_driver); |
fb1d9738 JB |
1195 | } |
1196 | ||
1197 | module_init(vmwgfx_init); | |
1198 | module_exit(vmwgfx_exit); | |
1199 | ||
1200 | MODULE_AUTHOR("VMware Inc. and others"); | |
1201 | MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); | |
1202 | MODULE_LICENSE("GPL and additional rights"); | |
73558ead TH |
1203 | MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." |
1204 | __stringify(VMWGFX_DRIVER_MINOR) "." | |
1205 | __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." | |
1206 | "0"); |