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drm/vmwgfx: Add MOB management
[deliverable/linux.git] / drivers / gpu / drm / vmwgfx / vmwgfx_drv.c
CommitLineData
fb1d9738
JB		 1/**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
e0cd3608 27#include <linux/module.h>
fb1d9738 28
760285e7 29#include <drm/drmP.h>
fb1d9738 30#include "vmwgfx_drv.h"
760285e7
DH		 31#include <drm/ttm/ttm_placement.h>
32#include <drm/ttm/ttm_bo_driver.h>
33#include <drm/ttm/ttm_object.h>
34#include <drm/ttm/ttm_module.h>
d92d9851 35#include <linux/dma_remapping.h>
fb1d9738
JB		 36
37#define VMWGFX_DRIVER_NAME "vmwgfx"
38#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
39#define VMWGFX_CHIP_SVGAII 0
40#define VMW_FB_RESERVATION 0
41
eb4f923b
JB		 42#define VMW_MIN_INITIAL_WIDTH 800
43#define VMW_MIN_INITIAL_HEIGHT 600
44
45
fb1d9738
JB		 46/**
47 * Fully encoded drm commands. Might move to vmw_drm.h
48 */
49
50#define DRM_IOCTL_VMW_GET_PARAM \
51 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
52 struct drm_vmw_getparam_arg)
53#define DRM_IOCTL_VMW_ALLOC_DMABUF \
54 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
55 union drm_vmw_alloc_dmabuf_arg)
56#define DRM_IOCTL_VMW_UNREF_DMABUF \
57 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
58 struct drm_vmw_unref_dmabuf_arg)
59#define DRM_IOCTL_VMW_CURSOR_BYPASS \
60 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
61 struct drm_vmw_cursor_bypass_arg)
62
63#define DRM_IOCTL_VMW_CONTROL_STREAM \
64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
65 struct drm_vmw_control_stream_arg)
66#define DRM_IOCTL_VMW_CLAIM_STREAM \
67 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
68 struct drm_vmw_stream_arg)
69#define DRM_IOCTL_VMW_UNREF_STREAM \
70 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
71 struct drm_vmw_stream_arg)
72
73#define DRM_IOCTL_VMW_CREATE_CONTEXT \
74 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
75 struct drm_vmw_context_arg)
76#define DRM_IOCTL_VMW_UNREF_CONTEXT \
77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
78 struct drm_vmw_context_arg)
79#define DRM_IOCTL_VMW_CREATE_SURFACE \
80 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
81 union drm_vmw_surface_create_arg)
82#define DRM_IOCTL_VMW_UNREF_SURFACE \
83 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
84 struct drm_vmw_surface_arg)
85#define DRM_IOCTL_VMW_REF_SURFACE \
86 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
87 union drm_vmw_surface_reference_arg)
88#define DRM_IOCTL_VMW_EXECBUF \
89 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
90 struct drm_vmw_execbuf_arg)
ae2a1040
TH		 91#define DRM_IOCTL_VMW_GET_3D_CAP \
92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
93 struct drm_vmw_get_3d_cap_arg)
fb1d9738
JB		 94#define DRM_IOCTL_VMW_FENCE_WAIT \
95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
96 struct drm_vmw_fence_wait_arg)
ae2a1040
TH		 97#define DRM_IOCTL_VMW_FENCE_SIGNALED \
98 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
99 struct drm_vmw_fence_signaled_arg)
100#define DRM_IOCTL_VMW_FENCE_UNREF \
101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
102 struct drm_vmw_fence_arg)
57c5ee79
TH		 103#define DRM_IOCTL_VMW_FENCE_EVENT \
104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
105 struct drm_vmw_fence_event_arg)
2fcd5a73
JB		 106#define DRM_IOCTL_VMW_PRESENT \
107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
108 struct drm_vmw_present_arg)
109#define DRM_IOCTL_VMW_PRESENT_READBACK \
110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
111 struct drm_vmw_present_readback_arg)
cd2b89e7
TH		 112#define DRM_IOCTL_VMW_UPDATE_LAYOUT \
113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
114 struct drm_vmw_update_layout_arg)
fb1d9738
JB		 115
116/**
117 * The core DRM version of this macro doesn't account for
118 * DRM_COMMAND_BASE.
119 */
120
121#define VMW_IOCTL_DEF(ioctl, func, flags) \
1b2f1489 122 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
fb1d9738
JB		 123
124/**
125 * Ioctl definitions.
126 */
127
baa70943 128static const struct drm_ioctl_desc vmw_ioctls[] = {
1b2f1489 129 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
e1f78003 130 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 131 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
e1f78003 132 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 133 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
e1f78003 134 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 135 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
e1f78003
TH		 136 vmw_kms_cursor_bypass_ioctl,
137 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
fb1d9738 138
1b2f1489 139 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
e1f78003 140 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
1b2f1489 141 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
e1f78003 142 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
1b2f1489 143 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
e1f78003 144 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
fb1d9738 145
1b2f1489 146 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
e1f78003 147 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 148 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
e1f78003 149 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 150 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
e1f78003 151 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 152 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
e1f78003 153 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 154 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
e1f78003 155 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 156 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
e1f78003 157 DRM_AUTH | DRM_UNLOCKED),
ae2a1040
TH		 158 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
159 DRM_AUTH | DRM_UNLOCKED),
160 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
161 vmw_fence_obj_signaled_ioctl,
162 DRM_AUTH | DRM_UNLOCKED),
163 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
d8bd19d2 164 DRM_AUTH | DRM_UNLOCKED),
57c5ee79
TH		 165 VMW_IOCTL_DEF(VMW_FENCE_EVENT,
166 vmw_fence_event_ioctl,
167 DRM_AUTH | DRM_UNLOCKED),
f63f6a59
TH		 168 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
169 DRM_AUTH | DRM_UNLOCKED),
2fcd5a73
JB		 170
171 /* these allow direct access to the framebuffers mark as master only */
172 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
173 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
174 VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
175 vmw_present_readback_ioctl,
176 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
cd2b89e7
TH		 177 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
178 vmw_kms_update_layout_ioctl,
179 DRM_MASTER | DRM_UNLOCKED),
fb1d9738
JB		 180};
181
182static struct pci_device_id vmw_pci_id_list[] = {
183 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
184 {0, 0, 0}
185};
c4903429 186MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
fb1d9738 187
5d2afab9 188static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
d92d9851
TH		 189static int vmw_force_iommu;
190static int vmw_restrict_iommu;
191static int vmw_force_coherent;
0d00c488 192static int vmw_restrict_dma_mask;
fb1d9738
JB		 193
194static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
195static void vmw_master_init(struct vmw_master *);
d9f36a00
TH		 196static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
197 void *ptr);
fb1d9738 198
30c78bb8
TH		 199MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
200module_param_named(enable_fbdev, enable_fbdev, int, 0600);
d92d9851
TH		 201MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
202module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
203MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
204module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
205MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
206module_param_named(force_coherent, vmw_force_coherent, int, 0600);
0d00c488
TH		 207MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
208module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
d92d9851 209
30c78bb8 210
fb1d9738
JB		 211static void vmw_print_capabilities(uint32_t capabilities)
212{
213 DRM_INFO("Capabilities:\n");
214 if (capabilities & SVGA_CAP_RECT_COPY)
215 DRM_INFO(" Rect copy.\n");
216 if (capabilities & SVGA_CAP_CURSOR)
217 DRM_INFO(" Cursor.\n");
218 if (capabilities & SVGA_CAP_CURSOR_BYPASS)
219 DRM_INFO(" Cursor bypass.\n");
220 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
221 DRM_INFO(" Cursor bypass 2.\n");
222 if (capabilities & SVGA_CAP_8BIT_EMULATION)
223 DRM_INFO(" 8bit emulation.\n");
224 if (capabilities & SVGA_CAP_ALPHA_CURSOR)
225 DRM_INFO(" Alpha cursor.\n");
226 if (capabilities & SVGA_CAP_3D)
227 DRM_INFO(" 3D.\n");
228 if (capabilities & SVGA_CAP_EXTENDED_FIFO)
229 DRM_INFO(" Extended Fifo.\n");
230 if (capabilities & SVGA_CAP_MULTIMON)
231 DRM_INFO(" Multimon.\n");
232 if (capabilities & SVGA_CAP_PITCHLOCK)
233 DRM_INFO(" Pitchlock.\n");
234 if (capabilities & SVGA_CAP_IRQMASK)
235 DRM_INFO(" Irq mask.\n");
236 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
237 DRM_INFO(" Display Topology.\n");
238 if (capabilities & SVGA_CAP_GMR)
239 DRM_INFO(" GMR.\n");
240 if (capabilities & SVGA_CAP_TRACES)
241 DRM_INFO(" Traces.\n");
dcca2862
TH		 242 if (capabilities & SVGA_CAP_GMR2)
243 DRM_INFO(" GMR2.\n");
244 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
245 DRM_INFO(" Screen Object 2.\n");
c1234db7
TH		 246 if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
247 DRM_INFO(" Command Buffers.\n");
248 if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
249 DRM_INFO(" Command Buffers 2.\n");
250 if (capabilities & SVGA_CAP_GBOBJECTS)
251 DRM_INFO(" Guest Backed Resources.\n");
fb1d9738
JB		 252}
253
e2fa3a76
TH		 254
255/**
256 * vmw_execbuf_prepare_dummy_query - Initialize a query result structure at
257 * the start of a buffer object.
258 *
259 * @dev_priv: The device private structure.
260 *
261 * This function will idle the buffer using an uninterruptible wait, then
262 * map the first page and initialize a pending occlusion query result structure,
263 * Finally it will unmap the buffer.
264 *
265 * TODO: Since we're only mapping a single page, we should optimize the map
266 * to use kmap_atomic / iomap_atomic.
267 */
268static void vmw_dummy_query_bo_prepare(struct vmw_private *dev_priv)
269{
270 struct ttm_bo_kmap_obj map;
271 volatile SVGA3dQueryResult *result;
272 bool dummy;
273 int ret;
274 struct ttm_bo_device *bdev = &dev_priv->bdev;
275 struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
276
277 ttm_bo_reserve(bo, false, false, false, 0);
278 spin_lock(&bdev->fence_lock);
1717c0e2 279 ret = ttm_bo_wait(bo, false, false, false);
e2fa3a76
TH		 280 spin_unlock(&bdev->fence_lock);
281 if (unlikely(ret != 0))
282 (void) vmw_fallback_wait(dev_priv, false, true, 0, false,
283 10*HZ);
284
285 ret = ttm_bo_kmap(bo, 0, 1, &map);
286 if (likely(ret == 0)) {
287 result = ttm_kmap_obj_virtual(&map, &dummy);
288 result->totalSize = sizeof(*result);
289 result->state = SVGA3D_QUERYSTATE_PENDING;
290 result->result32 = 0xff;
291 ttm_bo_kunmap(&map);
292 } else
293 DRM_ERROR("Dummy query buffer map failed.\n");
294 ttm_bo_unreserve(bo);
295}
296
297
298/**
299 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
300 *
301 * @dev_priv: A device private structure.
302 *
303 * This function creates a small buffer object that holds the query
304 * result for dummy queries emitted as query barriers.
305 * No interruptible waits are done within this function.
306 *
307 * Returns an error if bo creation fails.
308 */
309static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
310{
311 return ttm_bo_create(&dev_priv->bdev,
312 PAGE_SIZE,
313 ttm_bo_type_device,
314 &vmw_vram_sys_placement,
0b91c4a1 315 0, false, NULL,
e2fa3a76
TH		 316 &dev_priv->dummy_query_bo);
317}
318
319
fb1d9738
JB		 320static int vmw_request_device(struct vmw_private *dev_priv)
321{
322 int ret;
323
fb1d9738
JB		 324 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
325 if (unlikely(ret != 0)) {
326 DRM_ERROR("Unable to initialize FIFO.\n");
327 return ret;
328 }
ae2a1040 329 vmw_fence_fifo_up(dev_priv->fman);
3530bdc3
TH		 330 if (dev_priv->has_mob) {
331 ret = vmw_otables_setup(dev_priv);
332 if (unlikely(ret != 0)) {
333 DRM_ERROR("Unable to initialize "
334 "guest Memory OBjects.\n");
335 goto out_no_mob;
336 }
337 }
e2fa3a76
TH		 338 ret = vmw_dummy_query_bo_create(dev_priv);
339 if (unlikely(ret != 0))
340 goto out_no_query_bo;
341 vmw_dummy_query_bo_prepare(dev_priv);
fb1d9738
JB		 342
343 return 0;
e2fa3a76
TH		 344
345out_no_query_bo:
3530bdc3
TH		 346 if (dev_priv->has_mob)
347 vmw_otables_takedown(dev_priv);
348out_no_mob:
e2fa3a76
TH		 349 vmw_fence_fifo_down(dev_priv->fman);
350 vmw_fifo_release(dev_priv, &dev_priv->fifo);
351 return ret;
fb1d9738
JB		 352}
353
354static void vmw_release_device(struct vmw_private *dev_priv)
355{
e2fa3a76
TH		 356 /*
357 * Previous destructions should've released
358 * the pinned bo.
359 */
360
361 BUG_ON(dev_priv->pinned_bo != NULL);
362
363 ttm_bo_unref(&dev_priv->dummy_query_bo);
3530bdc3
TH		 364 if (dev_priv->has_mob)
365 vmw_otables_takedown(dev_priv);
ae2a1040 366 vmw_fence_fifo_down(dev_priv->fman);
fb1d9738 367 vmw_fifo_release(dev_priv, &dev_priv->fifo);
30c78bb8
TH		 368}
369
3530bdc3 370
05730b32
TH		 371/**
372 * Increase the 3d resource refcount.
373 * If the count was prevously zero, initialize the fifo, switching to svga
374 * mode. Note that the master holds a ref as well, and may request an
375 * explicit switch to svga mode if fb is not running, using @unhide_svga.
376 */
377int vmw_3d_resource_inc(struct vmw_private *dev_priv,
378 bool unhide_svga)
30c78bb8
TH		 379{
380 int ret = 0;
381
382 mutex_lock(&dev_priv->release_mutex);
383 if (unlikely(dev_priv->num_3d_resources++ == 0)) {
384 ret = vmw_request_device(dev_priv);
385 if (unlikely(ret != 0))
386 --dev_priv->num_3d_resources;
05730b32
TH		 387 } else if (unhide_svga) {
388 mutex_lock(&dev_priv->hw_mutex);
389 vmw_write(dev_priv, SVGA_REG_ENABLE,
390 vmw_read(dev_priv, SVGA_REG_ENABLE) &
391 ~SVGA_REG_ENABLE_HIDE);
392 mutex_unlock(&dev_priv->hw_mutex);
30c78bb8 393 }
05730b32 394
30c78bb8
TH		 395 mutex_unlock(&dev_priv->release_mutex);
396 return ret;
fb1d9738
JB		 397}
398
05730b32
TH		 399/**
400 * Decrease the 3d resource refcount.
401 * If the count reaches zero, disable the fifo, switching to vga mode.
402 * Note that the master holds a refcount as well, and may request an
403 * explicit switch to vga mode when it releases its refcount to account
404 * for the situation of an X server vt switch to VGA with 3d resources
405 * active.
406 */
407void vmw_3d_resource_dec(struct vmw_private *dev_priv,
408 bool hide_svga)
30c78bb8
TH		 409{
410 int32_t n3d;
411
412 mutex_lock(&dev_priv->release_mutex);
413 if (unlikely(--dev_priv->num_3d_resources == 0))
414 vmw_release_device(dev_priv);
05730b32
TH		 415 else if (hide_svga) {
416 mutex_lock(&dev_priv->hw_mutex);
417 vmw_write(dev_priv, SVGA_REG_ENABLE,
418 vmw_read(dev_priv, SVGA_REG_ENABLE) |
419 SVGA_REG_ENABLE_HIDE);
420 mutex_unlock(&dev_priv->hw_mutex);
421 }
422
30c78bb8
TH		 423 n3d = (int32_t) dev_priv->num_3d_resources;
424 mutex_unlock(&dev_priv->release_mutex);
425
426 BUG_ON(n3d < 0);
427}
428
eb4f923b
JB		 429/**
430 * Sets the initial_[width|height] fields on the given vmw_private.
431 *
432 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
67d4a87b
TH		 433 * clamping the value to fb_max_[width|height] fields and the
434 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
435 * If the values appear to be invalid, set them to
eb4f923b
JB		 436 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
437 */
438static void vmw_get_initial_size(struct vmw_private *dev_priv)
439{
440 uint32_t width;
441 uint32_t height;
442
443 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
444 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
445
446 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
eb4f923b 447 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
67d4a87b
TH		 448
449 if (width > dev_priv->fb_max_width ||
450 height > dev_priv->fb_max_height) {
451
452 /*
453 * This is a host error and shouldn't occur.
454 */
455
456 width = VMW_MIN_INITIAL_WIDTH;
457 height = VMW_MIN_INITIAL_HEIGHT;
458 }
eb4f923b
JB		 459
460 dev_priv->initial_width = width;
461 dev_priv->initial_height = height;
462}
463
d92d9851
TH		 464/**
465 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
466 * system.
467 *
468 * @dev_priv: Pointer to a struct vmw_private
469 *
470 * This functions tries to determine the IOMMU setup and what actions
471 * need to be taken by the driver to make system pages visible to the
472 * device.
473 * If this function decides that DMA is not possible, it returns -EINVAL.
474 * The driver may then try to disable features of the device that require
475 * DMA.
476 */
477static int vmw_dma_select_mode(struct vmw_private *dev_priv)
478{
d92d9851
TH		 479 static const char *names[vmw_dma_map_max] = {
480 [vmw_dma_phys] = "Using physical TTM page addresses.",
481 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
482 [vmw_dma_map_populate] = "Keeping DMA mappings.",
483 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
e14cd953
TH		 484#ifdef CONFIG_X86
485 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
d92d9851
TH		 486
487#ifdef CONFIG_INTEL_IOMMU
488 if (intel_iommu_enabled) {
489 dev_priv->map_mode = vmw_dma_map_populate;
490 goto out_fixup;
491 }
492#endif
493
494 if (!(vmw_force_iommu || vmw_force_coherent)) {
495 dev_priv->map_mode = vmw_dma_phys;
496 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
497 return 0;
498 }
499
500 dev_priv->map_mode = vmw_dma_map_populate;
501
502 if (dma_ops->sync_single_for_cpu)
503 dev_priv->map_mode = vmw_dma_alloc_coherent;
504#ifdef CONFIG_SWIOTLB
505 if (swiotlb_nr_tbl() == 0)
506 dev_priv->map_mode = vmw_dma_map_populate;
507#endif
508
21136946 509#ifdef CONFIG_INTEL_IOMMU
d92d9851 510out_fixup:
21136946 511#endif
d92d9851
TH		 512 if (dev_priv->map_mode == vmw_dma_map_populate &&
513 vmw_restrict_iommu)
514 dev_priv->map_mode = vmw_dma_map_bind;
515
516 if (vmw_force_coherent)
517 dev_priv->map_mode = vmw_dma_alloc_coherent;
518
519#if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
520 /*
521 * No coherent page pool
522 */
523 if (dev_priv->map_mode == vmw_dma_alloc_coherent)
524 return -EINVAL;
525#endif
526
e14cd953
TH		 527#else /* CONFIG_X86 */
528 dev_priv->map_mode = vmw_dma_map_populate;
529#endif /* CONFIG_X86 */
530
d92d9851
TH		 531 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
532
533 return 0;
534}
535
0d00c488
TH		 536/**
537 * vmw_dma_masks - set required page- and dma masks
538 *
539 * @dev: Pointer to struct drm-device
540 *
541 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
542 * restriction also for 64-bit systems.
543 */
544#ifdef CONFIG_INTEL_IOMMU
545static int vmw_dma_masks(struct vmw_private *dev_priv)
546{
547 struct drm_device *dev = dev_priv->dev;
548
549 if (intel_iommu_enabled &&
550 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
551 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
552 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
553 }
554 return 0;
555}
556#else
557static int vmw_dma_masks(struct vmw_private *dev_priv)
558{
559 return 0;
560}
561#endif
562
fb1d9738
JB		 563static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
564{
565 struct vmw_private *dev_priv;
566 int ret;
c188660f 567 uint32_t svga_id;
c0951b79 568 enum vmw_res_type i;
d92d9851 569 bool refuse_dma = false;
fb1d9738
JB		 570
571 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
572 if (unlikely(dev_priv == NULL)) {
573 DRM_ERROR("Failed allocating a device private struct.\n");
574 return -ENOMEM;
575 }
fb1d9738 576
466e69b8
DA		 577 pci_set_master(dev->pdev);
578
fb1d9738
JB		 579 dev_priv->dev = dev;
580 dev_priv->vmw_chipset = chipset;
6bcd8d3c 581 dev_priv->last_read_seqno = (uint32_t) -100;
fb1d9738
JB		 582 mutex_init(&dev_priv->hw_mutex);
583 mutex_init(&dev_priv->cmdbuf_mutex);
30c78bb8 584 mutex_init(&dev_priv->release_mutex);
fb1d9738 585 rwlock_init(&dev_priv->resource_lock);
c0951b79
TH		 586
587 for (i = vmw_res_context; i < vmw_res_max; ++i) {
588 idr_init(&dev_priv->res_idr[i]);
589 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
590 }
591
fb1d9738
JB		 592 mutex_init(&dev_priv->init_mutex);
593 init_waitqueue_head(&dev_priv->fence_queue);
594 init_waitqueue_head(&dev_priv->fifo_queue);
4f73a96b 595 dev_priv->fence_queue_waiters = 0;
fb1d9738 596 atomic_set(&dev_priv->fifo_queue_waiters, 0);
c0951b79 597
5bb39e81 598 dev_priv->used_memory_size = 0;
fb1d9738
JB		 599
600 dev_priv->io_start = pci_resource_start(dev->pdev, 0);
601 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
602 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
603
30c78bb8
TH		 604 dev_priv->enable_fb = enable_fbdev;
605
fb1d9738 606 mutex_lock(&dev_priv->hw_mutex);
c188660f
PH		 607
608 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
609 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
610 if (svga_id != SVGA_ID_2) {
611 ret = -ENOSYS;
49625904 612 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
c188660f
PH		 613 mutex_unlock(&dev_priv->hw_mutex);
614 goto out_err0;
615 }
616
fb1d9738 617 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
d92d9851
TH		 618 ret = vmw_dma_select_mode(dev_priv);
619 if (unlikely(ret != 0)) {
620 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
621 refuse_dma = true;
622 }
fb1d9738 623
5bb39e81
TH		 624 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
625 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
626 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
627 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
eb4f923b
JB		 628
629 vmw_get_initial_size(dev_priv);
630
0d00c488 631 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
fb1d9738
JB		 632 dev_priv->max_gmr_ids =
633 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
fb17f189
TH		 634 dev_priv->max_gmr_pages =
635 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
636 dev_priv->memory_size =
637 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
5bb39e81
TH		 638 dev_priv->memory_size -= dev_priv->vram_size;
639 } else {
640 /*
641 * An arbitrary limit of 512MiB on surface
642 * memory. But all HWV8 hardware supports GMR2.
643 */
644 dev_priv->memory_size = 512*1024*1024;
fb17f189 645 }
fb1d9738 646
0d00c488
TH		 647 ret = vmw_dma_masks(dev_priv);
648 if (unlikely(ret != 0))
649 goto out_err0;
650
bc2d6508
TH		 651 dev_priv->prim_bb_mem = dev_priv->vram_size;
652
fb1d9738
JB		 653 mutex_unlock(&dev_priv->hw_mutex);
654
655 vmw_print_capabilities(dev_priv->capabilities);
656
0d00c488 657 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
fb1d9738
JB		 658 DRM_INFO("Max GMR ids is %u\n",
659 (unsigned)dev_priv->max_gmr_ids);
fb17f189
TH		 660 DRM_INFO("Max number of GMR pages is %u\n",
661 (unsigned)dev_priv->max_gmr_pages);
5bb39e81
TH		 662 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
663 (unsigned)dev_priv->memory_size / 1024);
fb17f189 664 }
bc2d6508
TH		 665 DRM_INFO("Maximum display memory size is %u kiB\n",
666 dev_priv->prim_bb_mem / 1024);
fb1d9738
JB		 667 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
668 dev_priv->vram_start, dev_priv->vram_size / 1024);
669 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
670 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
671
672 ret = vmw_ttm_global_init(dev_priv);
673 if (unlikely(ret != 0))
674 goto out_err0;
675
676
677 vmw_master_init(&dev_priv->fbdev_master);
678 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
679 dev_priv->active_master = &dev_priv->fbdev_master;
680
a2c06ee2 681
fb1d9738
JB		 682 ret = ttm_bo_device_init(&dev_priv->bdev,
683 dev_priv->bo_global_ref.ref.object,
684 &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET,
685 false);
686 if (unlikely(ret != 0)) {
687 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
688 goto out_err1;
689 }
690
691 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
692 (dev_priv->vram_size >> PAGE_SHIFT));
693 if (unlikely(ret != 0)) {
694 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
695 goto out_err2;
696 }
697
135cba0d 698 dev_priv->has_gmr = true;
d92d9851
TH		 699 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
700 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
701 dev_priv->max_gmr_ids) != 0) {
135cba0d
TH		 702 DRM_INFO("No GMR memory available. "
703 "Graphics memory resources are very limited.\n");
704 dev_priv->has_gmr = false;
705 }
706
3530bdc3
TH		 707 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS)
708 dev_priv->has_mob = true;
709
247d36d7
AL		 710 dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start,
711 dev_priv->mmio_size);
fb1d9738
JB		 712
713 dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
714 dev_priv->mmio_size);
715
716 if (unlikely(dev_priv->mmio_virt == NULL)) {
717 ret = -ENOMEM;
718 DRM_ERROR("Failed mapping MMIO.\n");
719 goto out_err3;
720 }
721
d7e1958d
JB		 722 /* Need mmio memory to check for fifo pitchlock cap. */
723 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
724 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
725 !vmw_fifo_have_pitchlock(dev_priv)) {
726 ret = -ENOSYS;
727 DRM_ERROR("Hardware has no pitchlock\n");
728 goto out_err4;
729 }
730
fb1d9738 731 dev_priv->tdev = ttm_object_device_init
69977ff5 732 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
fb1d9738
JB		 733
734 if (unlikely(dev_priv->tdev == NULL)) {
735 DRM_ERROR("Unable to initialize TTM object management.\n");
736 ret = -ENOMEM;
737 goto out_err4;
738 }
739
740 dev->dev_private = dev_priv;
741
fb1d9738
JB		 742 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
743 dev_priv->stealth = (ret != 0);
744 if (dev_priv->stealth) {
745 /**
746 * Request at least the mmio PCI resource.
747 */
748
749 DRM_INFO("It appears like vesafb is loaded. "
f2d12b8e 750 "Ignore above error if any.\n");
fb1d9738
JB		 751 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
752 if (unlikely(ret != 0)) {
753 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
754 goto out_no_device;
755 }
fb1d9738 756 }
ae2a1040 757
506ff75c
TH		 758 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
759 ret = drm_irq_install(dev);
760 if (ret != 0) {
761 DRM_ERROR("Failed installing irq: %d\n", ret);
762 goto out_no_irq;
763 }
764 }
765
ae2a1040 766 dev_priv->fman = vmw_fence_manager_init(dev_priv);
14bbf20c
WY		 767 if (unlikely(dev_priv->fman == NULL)) {
768 ret = -ENOMEM;
ae2a1040 769 goto out_no_fman;
14bbf20c 770 }
56d1c78d 771
56d1c78d 772 vmw_kms_save_vga(dev_priv);
56d1c78d
JB		 773
774 /* Start kms and overlay systems, needs fifo. */
7a1c2f6c
TH		 775 ret = vmw_kms_init(dev_priv);
776 if (unlikely(ret != 0))
777 goto out_no_kms;
f2d12b8e 778 vmw_overlay_init(dev_priv);
56d1c78d 779
30c78bb8 780 if (dev_priv->enable_fb) {
506ff75c
TH		 781 ret = vmw_3d_resource_inc(dev_priv, true);
782 if (unlikely(ret != 0))
783 goto out_no_fifo;
30c78bb8 784 vmw_fb_init(dev_priv);
7a1c2f6c
TH		 785 }
786
d9f36a00
TH		 787 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
788 register_pm_notifier(&dev_priv->pm_nb);
789
fb1d9738
JB		 790 return 0;
791
506ff75c 792out_no_fifo:
56d1c78d
JB		 793 vmw_overlay_close(dev_priv);
794 vmw_kms_close(dev_priv);
795out_no_kms:
506ff75c 796 vmw_kms_restore_vga(dev_priv);
ae2a1040
TH		 797 vmw_fence_manager_takedown(dev_priv->fman);
798out_no_fman:
506ff75c
TH		 799 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
800 drm_irq_uninstall(dev_priv->dev);
801out_no_irq:
30c78bb8
TH		 802 if (dev_priv->stealth)
803 pci_release_region(dev->pdev, 2);
804 else
805 pci_release_regions(dev->pdev);
fb1d9738 806out_no_device:
fb1d9738
JB		 807 ttm_object_device_release(&dev_priv->tdev);
808out_err4:
809 iounmap(dev_priv->mmio_virt);
810out_err3:
247d36d7 811 arch_phys_wc_del(dev_priv->mmio_mtrr);
135cba0d
TH		 812 if (dev_priv->has_gmr)
813 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
fb1d9738
JB		 814 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
815out_err2:
816 (void)ttm_bo_device_release(&dev_priv->bdev);
817out_err1:
818 vmw_ttm_global_release(dev_priv);
819out_err0:
c0951b79
TH		 820 for (i = vmw_res_context; i < vmw_res_max; ++i)
821 idr_destroy(&dev_priv->res_idr[i]);
822
fb1d9738
JB		 823 kfree(dev_priv);
824 return ret;
825}
826
827static int vmw_driver_unload(struct drm_device *dev)
828{
829 struct vmw_private *dev_priv = vmw_priv(dev);
c0951b79 830 enum vmw_res_type i;
fb1d9738 831
d9f36a00
TH		 832 unregister_pm_notifier(&dev_priv->pm_nb);
833
c0951b79
TH		 834 if (dev_priv->ctx.res_ht_initialized)
835 drm_ht_remove(&dev_priv->ctx.res_ht);
be38ab6e
TH		 836 if (dev_priv->ctx.cmd_bounce)
837 vfree(dev_priv->ctx.cmd_bounce);
30c78bb8
TH		 838 if (dev_priv->enable_fb) {
839 vmw_fb_close(dev_priv);
840 vmw_kms_restore_vga(dev_priv);
05730b32 841 vmw_3d_resource_dec(dev_priv, false);
30c78bb8 842 }
f2d12b8e
TH		 843 vmw_kms_close(dev_priv);
844 vmw_overlay_close(dev_priv);
ae2a1040 845 vmw_fence_manager_takedown(dev_priv->fman);
506ff75c
TH		 846 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
847 drm_irq_uninstall(dev_priv->dev);
f2d12b8e 848 if (dev_priv->stealth)
fb1d9738 849 pci_release_region(dev->pdev, 2);
f2d12b8e
TH		 850 else
851 pci_release_regions(dev->pdev);
852
fb1d9738
JB		 853 ttm_object_device_release(&dev_priv->tdev);
854 iounmap(dev_priv->mmio_virt);
247d36d7 855 arch_phys_wc_del(dev_priv->mmio_mtrr);
135cba0d
TH		 856 if (dev_priv->has_gmr)
857 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
fb1d9738
JB		 858 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
859 (void)ttm_bo_device_release(&dev_priv->bdev);
860 vmw_ttm_global_release(dev_priv);
c0951b79
TH		 861
862 for (i = vmw_res_context; i < vmw_res_max; ++i)
863 idr_destroy(&dev_priv->res_idr[i]);
fb1d9738
JB		 864
865 kfree(dev_priv);
866
867 return 0;
868}
869
6b82ef50
TH		 870static void vmw_preclose(struct drm_device *dev,
871 struct drm_file *file_priv)
872{
873 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
874 struct vmw_private *dev_priv = vmw_priv(dev);
875
876 vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
877}
878
fb1d9738
JB		 879static void vmw_postclose(struct drm_device *dev,
880 struct drm_file *file_priv)
881{
882 struct vmw_fpriv *vmw_fp;
883
884 vmw_fp = vmw_fpriv(file_priv);
c4249855
TH		 885
886 if (vmw_fp->locked_master) {
887 struct vmw_master *vmaster =
888 vmw_master(vmw_fp->locked_master);
889
890 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
891 ttm_vt_unlock(&vmaster->lock);
fb1d9738 892 drm_master_put(&vmw_fp->locked_master);
c4249855
TH		 893 }
894
895 ttm_object_file_release(&vmw_fp->tfile);
fb1d9738
JB		 896 kfree(vmw_fp);
897}
898
899static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
900{
901 struct vmw_private *dev_priv = vmw_priv(dev);
902 struct vmw_fpriv *vmw_fp;
903 int ret = -ENOMEM;
904
905 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
906 if (unlikely(vmw_fp == NULL))
907 return ret;
908
6b82ef50 909 INIT_LIST_HEAD(&vmw_fp->fence_events);
fb1d9738
JB		 910 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
911 if (unlikely(vmw_fp->tfile == NULL))
912 goto out_no_tfile;
913
914 file_priv->driver_priv = vmw_fp;
949c4a34 915 dev_priv->bdev.dev_mapping = dev->dev_mapping;
fb1d9738
JB		 916
917 return 0;
918
919out_no_tfile:
920 kfree(vmw_fp);
921 return ret;
922}
923
924static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
925 unsigned long arg)
926{
927 struct drm_file *file_priv = filp->private_data;
928 struct drm_device *dev = file_priv->minor->dev;
929 unsigned int nr = DRM_IOCTL_NR(cmd);
fb1d9738
JB		 930
931 /*
e1f78003 932 * Do extra checking on driver private ioctls.
fb1d9738
JB		 933 */
934
935 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
936 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
baa70943 937 const struct drm_ioctl_desc *ioctl =
fb1d9738
JB		 938 &vmw_ioctls[nr - DRM_COMMAND_BASE];
939
2854eeda 940 if (unlikely(ioctl->cmd_drv != cmd)) {
fb1d9738
JB		 941 DRM_ERROR("Invalid command format, ioctl %d\n",
942 nr - DRM_COMMAND_BASE);
943 return -EINVAL;
944 }
fb1d9738
JB		 945 }
946
e1f78003 947 return drm_ioctl(filp, cmd, arg);
fb1d9738
JB		 948}
949
fb1d9738
JB		 950static void vmw_lastclose(struct drm_device *dev)
951{
fb1d9738
JB		 952 struct drm_crtc *crtc;
953 struct drm_mode_set set;
954 int ret;
955
fb1d9738
JB		 956 set.x = 0;
957 set.y = 0;
958 set.fb = NULL;
959 set.mode = NULL;
960 set.connectors = NULL;
961 set.num_connectors = 0;
962
963 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
964 set.crtc = crtc;
2d13b679 965 ret = drm_mode_set_config_internal(&set);
fb1d9738
JB		 966 WARN_ON(ret != 0);
967 }
968
969}
970
971static void vmw_master_init(struct vmw_master *vmaster)
972{
973 ttm_lock_init(&vmaster->lock);
3a939a5e
TH		 974 INIT_LIST_HEAD(&vmaster->fb_surf);
975 mutex_init(&vmaster->fb_surf_mutex);
fb1d9738
JB		 976}
977
978static int vmw_master_create(struct drm_device *dev,
979 struct drm_master *master)
980{
981 struct vmw_master *vmaster;
982
fb1d9738
JB		 983 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
984 if (unlikely(vmaster == NULL))
985 return -ENOMEM;
986
3a939a5e 987 vmw_master_init(vmaster);
fb1d9738
JB		 988 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
989 master->driver_priv = vmaster;
990
991 return 0;
992}
993
994static void vmw_master_destroy(struct drm_device *dev,
995 struct drm_master *master)
996{
997 struct vmw_master *vmaster = vmw_master(master);
998
fb1d9738
JB		 999 master->driver_priv = NULL;
1000 kfree(vmaster);
1001}
1002
1003
1004static int vmw_master_set(struct drm_device *dev,
1005 struct drm_file *file_priv,
1006 bool from_open)
1007{
1008 struct vmw_private *dev_priv = vmw_priv(dev);
1009 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1010 struct vmw_master *active = dev_priv->active_master;
1011 struct vmw_master *vmaster = vmw_master(file_priv->master);
1012 int ret = 0;
1013
30c78bb8 1014 if (!dev_priv->enable_fb) {
05730b32 1015 ret = vmw_3d_resource_inc(dev_priv, true);
30c78bb8
TH		 1016 if (unlikely(ret != 0))
1017 return ret;
1018 vmw_kms_save_vga(dev_priv);
1019 mutex_lock(&dev_priv->hw_mutex);
1020 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
1021 mutex_unlock(&dev_priv->hw_mutex);
1022 }
1023
fb1d9738
JB		 1024 if (active) {
1025 BUG_ON(active != &dev_priv->fbdev_master);
1026 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1027 if (unlikely(ret != 0))
1028 goto out_no_active_lock;
1029
1030 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1031 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1032 if (unlikely(ret != 0)) {
1033 DRM_ERROR("Unable to clean VRAM on "
1034 "master drop.\n");
1035 }
1036
1037 dev_priv->active_master = NULL;
1038 }
1039
1040 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1041 if (!from_open) {
1042 ttm_vt_unlock(&vmaster->lock);
1043 BUG_ON(vmw_fp->locked_master != file_priv->master);
1044 drm_master_put(&vmw_fp->locked_master);
1045 }
1046
1047 dev_priv->active_master = vmaster;
1048
1049 return 0;
1050
1051out_no_active_lock:
30c78bb8 1052 if (!dev_priv->enable_fb) {
ba723fe8
TH		 1053 vmw_kms_restore_vga(dev_priv);
1054 vmw_3d_resource_dec(dev_priv, true);
30c78bb8
TH		 1055 mutex_lock(&dev_priv->hw_mutex);
1056 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1057 mutex_unlock(&dev_priv->hw_mutex);
30c78bb8 1058 }
fb1d9738
JB		 1059 return ret;
1060}
1061
1062static void vmw_master_drop(struct drm_device *dev,
1063 struct drm_file *file_priv,
1064 bool from_release)
1065{
1066 struct vmw_private *dev_priv = vmw_priv(dev);
1067 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1068 struct vmw_master *vmaster = vmw_master(file_priv->master);
1069 int ret;
1070
fb1d9738
JB		 1071 /**
1072 * Make sure the master doesn't disappear while we have
1073 * it locked.
1074 */
1075
1076 vmw_fp->locked_master = drm_master_get(file_priv->master);
1077 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
fb1d9738
JB		 1078 if (unlikely((ret != 0))) {
1079 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1080 drm_master_put(&vmw_fp->locked_master);
1081 }
1082
c4249855
TH		 1083 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1084 vmw_execbuf_release_pinned_bo(dev_priv);
fb1d9738 1085
30c78bb8
TH		 1086 if (!dev_priv->enable_fb) {
1087 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1088 if (unlikely(ret != 0))
1089 DRM_ERROR("Unable to clean VRAM on master drop.\n");
ba723fe8
TH		 1090 vmw_kms_restore_vga(dev_priv);
1091 vmw_3d_resource_dec(dev_priv, true);
30c78bb8
TH		 1092 mutex_lock(&dev_priv->hw_mutex);
1093 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1094 mutex_unlock(&dev_priv->hw_mutex);
30c78bb8
TH		 1095 }
1096
fb1d9738
JB		 1097 dev_priv->active_master = &dev_priv->fbdev_master;
1098 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1099 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1100
30c78bb8
TH		 1101 if (dev_priv->enable_fb)
1102 vmw_fb_on(dev_priv);
fb1d9738
JB		 1103}
1104
1105
1106static void vmw_remove(struct pci_dev *pdev)
1107{
1108 struct drm_device *dev = pci_get_drvdata(pdev);
1109
1110 drm_put_dev(dev);
1111}
1112
d9f36a00
TH		 1113static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1114 void *ptr)
1115{
1116 struct vmw_private *dev_priv =
1117 container_of(nb, struct vmw_private, pm_nb);
1118 struct vmw_master *vmaster = dev_priv->active_master;
1119
1120 switch (val) {
1121 case PM_HIBERNATION_PREPARE:
1122 case PM_SUSPEND_PREPARE:
1123 ttm_suspend_lock(&vmaster->lock);
1124
1125 /**
1126 * This empties VRAM and unbinds all GMR bindings.
1127 * Buffer contents is moved to swappable memory.
1128 */
c0951b79
TH		 1129 vmw_execbuf_release_pinned_bo(dev_priv);
1130 vmw_resource_evict_all(dev_priv);
d9f36a00 1131 ttm_bo_swapout_all(&dev_priv->bdev);
094e0fa8 1132
d9f36a00
TH		 1133 break;
1134 case PM_POST_HIBERNATION:
1135 case PM_POST_SUSPEND:
094e0fa8 1136 case PM_POST_RESTORE:
d9f36a00 1137 ttm_suspend_unlock(&vmaster->lock);
094e0fa8 1138
d9f36a00
TH		 1139 break;
1140 case PM_RESTORE_PREPARE:
1141 break;
d9f36a00
TH		 1142 default:
1143 break;
1144 }
1145 return 0;
1146}
1147
1148/**
1149 * These might not be needed with the virtual SVGA device.
1150 */
1151
7fbd721a 1152static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
d9f36a00 1153{
094e0fa8
TH		 1154 struct drm_device *dev = pci_get_drvdata(pdev);
1155 struct vmw_private *dev_priv = vmw_priv(dev);
1156
1157 if (dev_priv->num_3d_resources != 0) {
1158 DRM_INFO("Can't suspend or hibernate "
1159 "while 3D resources are active.\n");
1160 return -EBUSY;
1161 }
1162
d9f36a00
TH		 1163 pci_save_state(pdev);
1164 pci_disable_device(pdev);
1165 pci_set_power_state(pdev, PCI_D3hot);
1166 return 0;
1167}
1168
7fbd721a 1169static int vmw_pci_resume(struct pci_dev *pdev)
d9f36a00
TH		 1170{
1171 pci_set_power_state(pdev, PCI_D0);
1172 pci_restore_state(pdev);
1173 return pci_enable_device(pdev);
1174}
1175
7fbd721a
TH		 1176static int vmw_pm_suspend(struct device *kdev)
1177{
1178 struct pci_dev *pdev = to_pci_dev(kdev);
1179 struct pm_message dummy;
1180
1181 dummy.event = 0;
1182
1183 return vmw_pci_suspend(pdev, dummy);
1184}
1185
1186static int vmw_pm_resume(struct device *kdev)
1187{
1188 struct pci_dev *pdev = to_pci_dev(kdev);
1189
1190 return vmw_pci_resume(pdev);
1191}
1192
1193static int vmw_pm_prepare(struct device *kdev)
1194{
1195 struct pci_dev *pdev = to_pci_dev(kdev);
1196 struct drm_device *dev = pci_get_drvdata(pdev);
1197 struct vmw_private *dev_priv = vmw_priv(dev);
1198
1199 /**
1200 * Release 3d reference held by fbdev and potentially
1201 * stop fifo.
1202 */
1203 dev_priv->suspended = true;
1204 if (dev_priv->enable_fb)
05730b32 1205 vmw_3d_resource_dec(dev_priv, true);
7fbd721a
TH		 1206
1207 if (dev_priv->num_3d_resources != 0) {
1208
1209 DRM_INFO("Can't suspend or hibernate "
1210 "while 3D resources are active.\n");
1211
1212 if (dev_priv->enable_fb)
05730b32 1213 vmw_3d_resource_inc(dev_priv, true);
7fbd721a
TH		 1214 dev_priv->suspended = false;
1215 return -EBUSY;
1216 }
1217
1218 return 0;
1219}
1220
1221static void vmw_pm_complete(struct device *kdev)
1222{
1223 struct pci_dev *pdev = to_pci_dev(kdev);
1224 struct drm_device *dev = pci_get_drvdata(pdev);
1225 struct vmw_private *dev_priv = vmw_priv(dev);
1226
95e8f6a2
TH		 1227 mutex_lock(&dev_priv->hw_mutex);
1228 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1229 (void) vmw_read(dev_priv, SVGA_REG_ID);
1230 mutex_unlock(&dev_priv->hw_mutex);
1231
7fbd721a
TH		 1232 /**
1233 * Reclaim 3d reference held by fbdev and potentially
1234 * start fifo.
1235 */
1236 if (dev_priv->enable_fb)
05730b32 1237 vmw_3d_resource_inc(dev_priv, false);
7fbd721a
TH		 1238
1239 dev_priv->suspended = false;
1240}
1241
1242static const struct dev_pm_ops vmw_pm_ops = {
1243 .prepare = vmw_pm_prepare,
1244 .complete = vmw_pm_complete,
1245 .suspend = vmw_pm_suspend,
1246 .resume = vmw_pm_resume,
1247};
1248
e08e96de
AV		 1249static const struct file_operations vmwgfx_driver_fops = {
1250 .owner = THIS_MODULE,
1251 .open = drm_open,
1252 .release = drm_release,
1253 .unlocked_ioctl = vmw_unlocked_ioctl,
1254 .mmap = vmw_mmap,
1255 .poll = vmw_fops_poll,
1256 .read = vmw_fops_read,
e08e96de
AV		 1257#if defined(CONFIG_COMPAT)
1258 .compat_ioctl = drm_compat_ioctl,
1259#endif
1260 .llseek = noop_llseek,
1261};
1262
fb1d9738
JB		 1263static struct drm_driver driver = {
1264 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
69977ff5 1265 DRIVER_MODESET | DRIVER_PRIME,
fb1d9738
JB		 1266 .load = vmw_driver_load,
1267 .unload = vmw_driver_unload,
fb1d9738
JB		 1268 .lastclose = vmw_lastclose,
1269 .irq_preinstall = vmw_irq_preinstall,
1270 .irq_postinstall = vmw_irq_postinstall,
1271 .irq_uninstall = vmw_irq_uninstall,
1272 .irq_handler = vmw_irq_handler,
7a1c2f6c 1273 .get_vblank_counter = vmw_get_vblank_counter,
1c482ab3
JB		 1274 .enable_vblank = vmw_enable_vblank,
1275 .disable_vblank = vmw_disable_vblank,
fb1d9738
JB		 1276 .ioctls = vmw_ioctls,
1277 .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
fb1d9738
JB		 1278 .master_create = vmw_master_create,
1279 .master_destroy = vmw_master_destroy,
1280 .master_set = vmw_master_set,
1281 .master_drop = vmw_master_drop,
1282 .open = vmw_driver_open,
6b82ef50 1283 .preclose = vmw_preclose,
fb1d9738 1284 .postclose = vmw_postclose,
5e1782d2
DA		 1285
1286 .dumb_create = vmw_dumb_create,
1287 .dumb_map_offset = vmw_dumb_map_offset,
1288 .dumb_destroy = vmw_dumb_destroy,
1289
69977ff5
TH		 1290 .prime_fd_to_handle = vmw_prime_fd_to_handle,
1291 .prime_handle_to_fd = vmw_prime_handle_to_fd,
1292
e08e96de 1293 .fops = &vmwgfx_driver_fops,
fb1d9738
JB		 1294 .name = VMWGFX_DRIVER_NAME,
1295 .desc = VMWGFX_DRIVER_DESC,
1296 .date = VMWGFX_DRIVER_DATE,
1297 .major = VMWGFX_DRIVER_MAJOR,
1298 .minor = VMWGFX_DRIVER_MINOR,
1299 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1300};
1301
8410ea3b
DA		 1302static struct pci_driver vmw_pci_driver = {
1303 .name = VMWGFX_DRIVER_NAME,
1304 .id_table = vmw_pci_id_list,
1305 .probe = vmw_probe,
1306 .remove = vmw_remove,
1307 .driver = {
1308 .pm = &vmw_pm_ops
1309 }
1310};
1311
fb1d9738
JB		 1312static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1313{
dcdb1674 1314 return drm_get_pci_dev(pdev, ent, &driver);
fb1d9738
JB		 1315}
1316
1317static int __init vmwgfx_init(void)
1318{
1319 int ret;
8410ea3b 1320 ret = drm_pci_init(&driver, &vmw_pci_driver);
fb1d9738
JB		 1321 if (ret)
1322 DRM_ERROR("Failed initializing DRM.\n");
1323 return ret;
1324}
1325
1326static void __exit vmwgfx_exit(void)
1327{
8410ea3b 1328 drm_pci_exit(&driver, &vmw_pci_driver);
fb1d9738
JB		 1329}
1330
1331module_init(vmwgfx_init);
1332module_exit(vmwgfx_exit);
1333
1334MODULE_AUTHOR("VMware Inc. and others");
1335MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1336MODULE_LICENSE("GPL and additional rights");
73558ead
TH		 1337MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1338 __stringify(VMWGFX_DRIVER_MINOR) "."
1339 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1340 "0");
Linux kernel - Deliverables
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