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drm/vmwgfx: Reinstate and tighten security around legacy master model
[deliverable/linux.git] / drivers / gpu / drm / vmwgfx / vmwgfx_drv.c
CommitLineData
fb1d9738
JB		 1/**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
e0cd3608 27#include <linux/module.h>
fb1d9738 28
760285e7 29#include <drm/drmP.h>
fb1d9738 30#include "vmwgfx_drv.h"
760285e7
DH		 31#include <drm/ttm/ttm_placement.h>
32#include <drm/ttm/ttm_bo_driver.h>
33#include <drm/ttm/ttm_object.h>
34#include <drm/ttm/ttm_module.h>
d92d9851 35#include <linux/dma_remapping.h>
fb1d9738
JB		 36
37#define VMWGFX_DRIVER_NAME "vmwgfx"
38#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
39#define VMWGFX_CHIP_SVGAII 0
40#define VMW_FB_RESERVATION 0
41
eb4f923b
JB		 42#define VMW_MIN_INITIAL_WIDTH 800
43#define VMW_MIN_INITIAL_HEIGHT 600
44
45
fb1d9738
JB		 46/**
47 * Fully encoded drm commands. Might move to vmw_drm.h
48 */
49
50#define DRM_IOCTL_VMW_GET_PARAM \
51 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
52 struct drm_vmw_getparam_arg)
53#define DRM_IOCTL_VMW_ALLOC_DMABUF \
54 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
55 union drm_vmw_alloc_dmabuf_arg)
56#define DRM_IOCTL_VMW_UNREF_DMABUF \
57 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
58 struct drm_vmw_unref_dmabuf_arg)
59#define DRM_IOCTL_VMW_CURSOR_BYPASS \
60 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
61 struct drm_vmw_cursor_bypass_arg)
62
63#define DRM_IOCTL_VMW_CONTROL_STREAM \
64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
65 struct drm_vmw_control_stream_arg)
66#define DRM_IOCTL_VMW_CLAIM_STREAM \
67 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
68 struct drm_vmw_stream_arg)
69#define DRM_IOCTL_VMW_UNREF_STREAM \
70 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
71 struct drm_vmw_stream_arg)
72
73#define DRM_IOCTL_VMW_CREATE_CONTEXT \
74 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
75 struct drm_vmw_context_arg)
76#define DRM_IOCTL_VMW_UNREF_CONTEXT \
77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
78 struct drm_vmw_context_arg)
79#define DRM_IOCTL_VMW_CREATE_SURFACE \
80 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
81 union drm_vmw_surface_create_arg)
82#define DRM_IOCTL_VMW_UNREF_SURFACE \
83 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
84 struct drm_vmw_surface_arg)
85#define DRM_IOCTL_VMW_REF_SURFACE \
86 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
87 union drm_vmw_surface_reference_arg)
88#define DRM_IOCTL_VMW_EXECBUF \
89 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
90 struct drm_vmw_execbuf_arg)
ae2a1040
TH		 91#define DRM_IOCTL_VMW_GET_3D_CAP \
92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
93 struct drm_vmw_get_3d_cap_arg)
fb1d9738
JB		 94#define DRM_IOCTL_VMW_FENCE_WAIT \
95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
96 struct drm_vmw_fence_wait_arg)
ae2a1040
TH		 97#define DRM_IOCTL_VMW_FENCE_SIGNALED \
98 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
99 struct drm_vmw_fence_signaled_arg)
100#define DRM_IOCTL_VMW_FENCE_UNREF \
101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
102 struct drm_vmw_fence_arg)
57c5ee79
TH		 103#define DRM_IOCTL_VMW_FENCE_EVENT \
104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
105 struct drm_vmw_fence_event_arg)
2fcd5a73
JB		 106#define DRM_IOCTL_VMW_PRESENT \
107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
108 struct drm_vmw_present_arg)
109#define DRM_IOCTL_VMW_PRESENT_READBACK \
110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
111 struct drm_vmw_present_readback_arg)
cd2b89e7
TH		 112#define DRM_IOCTL_VMW_UPDATE_LAYOUT \
113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
114 struct drm_vmw_update_layout_arg)
c74c162f
TH		 115#define DRM_IOCTL_VMW_CREATE_SHADER \
116 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
117 struct drm_vmw_shader_create_arg)
118#define DRM_IOCTL_VMW_UNREF_SHADER \
119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
120 struct drm_vmw_shader_arg)
a97e2192
TH		 121#define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
122 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
123 union drm_vmw_gb_surface_create_arg)
124#define DRM_IOCTL_VMW_GB_SURFACE_REF \
125 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
126 union drm_vmw_gb_surface_reference_arg)
1d7a5cbf
TH		 127#define DRM_IOCTL_VMW_SYNCCPU \
128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
129 struct drm_vmw_synccpu_arg)
fb1d9738
JB		 130
131/**
132 * The core DRM version of this macro doesn't account for
133 * DRM_COMMAND_BASE.
134 */
135
136#define VMW_IOCTL_DEF(ioctl, func, flags) \
1b2f1489 137 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
fb1d9738
JB		 138
139/**
140 * Ioctl definitions.
141 */
142
baa70943 143static const struct drm_ioctl_desc vmw_ioctls[] = {
1b2f1489 144 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
e1f78003 145 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 146 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
e1f78003 147 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 148 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
e1f78003 149 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 150 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
e1f78003
TH		 151 vmw_kms_cursor_bypass_ioctl,
152 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
fb1d9738 153
1b2f1489 154 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
e1f78003 155 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
1b2f1489 156 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
e1f78003 157 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
1b2f1489 158 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
e1f78003 159 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
fb1d9738 160
1b2f1489 161 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
e1f78003 162 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 163 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
e1f78003 164 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 165 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
e1f78003 166 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 167 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
e1f78003 168 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 169 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
e1f78003 170 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 171 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
e1f78003 172 DRM_AUTH | DRM_UNLOCKED),
ae2a1040
TH		 173 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
174 DRM_AUTH | DRM_UNLOCKED),
175 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
176 vmw_fence_obj_signaled_ioctl,
177 DRM_AUTH | DRM_UNLOCKED),
178 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
d8bd19d2 179 DRM_AUTH | DRM_UNLOCKED),
57c5ee79
TH		 180 VMW_IOCTL_DEF(VMW_FENCE_EVENT,
181 vmw_fence_event_ioctl,
182 DRM_AUTH | DRM_UNLOCKED),
f63f6a59
TH		 183 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
184 DRM_AUTH | DRM_UNLOCKED),
2fcd5a73
JB		 185
186 /* these allow direct access to the framebuffers mark as master only */
187 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
188 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
189 VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
190 vmw_present_readback_ioctl,
191 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
cd2b89e7
TH		 192 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
193 vmw_kms_update_layout_ioctl,
194 DRM_MASTER | DRM_UNLOCKED),
c74c162f
TH		 195 VMW_IOCTL_DEF(VMW_CREATE_SHADER,
196 vmw_shader_define_ioctl,
197 DRM_AUTH | DRM_UNLOCKED),
198 VMW_IOCTL_DEF(VMW_UNREF_SHADER,
199 vmw_shader_destroy_ioctl,
200 DRM_AUTH | DRM_UNLOCKED),
a97e2192
TH		 201 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
202 vmw_gb_surface_define_ioctl,
203 DRM_AUTH | DRM_UNLOCKED),
204 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
205 vmw_gb_surface_reference_ioctl,
206 DRM_AUTH | DRM_UNLOCKED),
1d7a5cbf
TH		 207 VMW_IOCTL_DEF(VMW_SYNCCPU,
208 vmw_user_dmabuf_synccpu_ioctl,
209 DRM_AUTH | DRM_UNLOCKED),
fb1d9738
JB		 210};
211
212static struct pci_device_id vmw_pci_id_list[] = {
213 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
214 {0, 0, 0}
215};
c4903429 216MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
fb1d9738 217
5d2afab9 218static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
d92d9851
TH		 219static int vmw_force_iommu;
220static int vmw_restrict_iommu;
221static int vmw_force_coherent;
0d00c488 222static int vmw_restrict_dma_mask;
fb1d9738
JB		 223
224static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
225static void vmw_master_init(struct vmw_master *);
d9f36a00
TH		 226static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
227 void *ptr);
fb1d9738 228
30c78bb8
TH		 229MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
230module_param_named(enable_fbdev, enable_fbdev, int, 0600);
d92d9851
TH		 231MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
232module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
233MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
234module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
235MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
236module_param_named(force_coherent, vmw_force_coherent, int, 0600);
0d00c488
TH		 237MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
238module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
d92d9851 239
30c78bb8 240
fb1d9738
JB		 241static void vmw_print_capabilities(uint32_t capabilities)
242{
243 DRM_INFO("Capabilities:\n");
244 if (capabilities & SVGA_CAP_RECT_COPY)
245 DRM_INFO(" Rect copy.\n");
246 if (capabilities & SVGA_CAP_CURSOR)
247 DRM_INFO(" Cursor.\n");
248 if (capabilities & SVGA_CAP_CURSOR_BYPASS)
249 DRM_INFO(" Cursor bypass.\n");
250 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
251 DRM_INFO(" Cursor bypass 2.\n");
252 if (capabilities & SVGA_CAP_8BIT_EMULATION)
253 DRM_INFO(" 8bit emulation.\n");
254 if (capabilities & SVGA_CAP_ALPHA_CURSOR)
255 DRM_INFO(" Alpha cursor.\n");
256 if (capabilities & SVGA_CAP_3D)
257 DRM_INFO(" 3D.\n");
258 if (capabilities & SVGA_CAP_EXTENDED_FIFO)
259 DRM_INFO(" Extended Fifo.\n");
260 if (capabilities & SVGA_CAP_MULTIMON)
261 DRM_INFO(" Multimon.\n");
262 if (capabilities & SVGA_CAP_PITCHLOCK)
263 DRM_INFO(" Pitchlock.\n");
264 if (capabilities & SVGA_CAP_IRQMASK)
265 DRM_INFO(" Irq mask.\n");
266 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
267 DRM_INFO(" Display Topology.\n");
268 if (capabilities & SVGA_CAP_GMR)
269 DRM_INFO(" GMR.\n");
270 if (capabilities & SVGA_CAP_TRACES)
271 DRM_INFO(" Traces.\n");
dcca2862
TH		 272 if (capabilities & SVGA_CAP_GMR2)
273 DRM_INFO(" GMR2.\n");
274 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
275 DRM_INFO(" Screen Object 2.\n");
c1234db7
TH		 276 if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
277 DRM_INFO(" Command Buffers.\n");
278 if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
279 DRM_INFO(" Command Buffers 2.\n");
280 if (capabilities & SVGA_CAP_GBOBJECTS)
281 DRM_INFO(" Guest Backed Resources.\n");
fb1d9738
JB		 282}
283
e2fa3a76 284/**
4b9e45e6 285 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
e2fa3a76 286 *
4b9e45e6 287 * @dev_priv: A device private structure.
e2fa3a76 288 *
4b9e45e6
TH		 289 * This function creates a small buffer object that holds the query
290 * result for dummy queries emitted as query barriers.
291 * The function will then map the first page and initialize a pending
292 * occlusion query result structure, Finally it will unmap the buffer.
293 * No interruptible waits are done within this function.
e2fa3a76 294 *
4b9e45e6 295 * Returns an error if bo creation or initialization fails.
e2fa3a76 296 */
4b9e45e6 297static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
e2fa3a76 298{
4b9e45e6
TH		 299 int ret;
300 struct ttm_buffer_object *bo;
e2fa3a76
TH		 301 struct ttm_bo_kmap_obj map;
302 volatile SVGA3dQueryResult *result;
303 bool dummy;
e2fa3a76 304
4b9e45e6
TH		 305 /*
306 * Create the bo as pinned, so that a tryreserve will
307 * immediately succeed. This is because we're the only
308 * user of the bo currently.
309 */
310 ret = ttm_bo_create(&dev_priv->bdev,
311 PAGE_SIZE,
312 ttm_bo_type_device,
313 &vmw_sys_ne_placement,
314 0, false, NULL,
315 &bo);
316
e2fa3a76 317 if (unlikely(ret != 0))
4b9e45e6
TH		 318 return ret;
319
320 ret = ttm_bo_reserve(bo, false, true, false, 0);
321 BUG_ON(ret != 0);
e2fa3a76
TH		 322
323 ret = ttm_bo_kmap(bo, 0, 1, &map);
324 if (likely(ret == 0)) {
325 result = ttm_kmap_obj_virtual(&map, &dummy);
326 result->totalSize = sizeof(*result);
327 result->state = SVGA3D_QUERYSTATE_PENDING;
328 result->result32 = 0xff;
329 ttm_bo_kunmap(&map);
4b9e45e6
TH		 330 }
331 vmw_bo_pin(bo, false);
e2fa3a76 332 ttm_bo_unreserve(bo);
e2fa3a76 333
4b9e45e6
TH		 334 if (unlikely(ret != 0)) {
335 DRM_ERROR("Dummy query buffer map failed.\n");
336 ttm_bo_unref(&bo);
337 } else
338 dev_priv->dummy_query_bo = bo;
e2fa3a76 339
4b9e45e6 340 return ret;
e2fa3a76
TH		 341}
342
fb1d9738
JB		 343static int vmw_request_device(struct vmw_private *dev_priv)
344{
345 int ret;
346
fb1d9738
JB		 347 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
348 if (unlikely(ret != 0)) {
349 DRM_ERROR("Unable to initialize FIFO.\n");
350 return ret;
351 }
ae2a1040 352 vmw_fence_fifo_up(dev_priv->fman);
3530bdc3
TH		 353 if (dev_priv->has_mob) {
354 ret = vmw_otables_setup(dev_priv);
355 if (unlikely(ret != 0)) {
356 DRM_ERROR("Unable to initialize "
357 "guest Memory OBjects.\n");
358 goto out_no_mob;
359 }
360 }
e2fa3a76
TH		 361 ret = vmw_dummy_query_bo_create(dev_priv);
362 if (unlikely(ret != 0))
363 goto out_no_query_bo;
fb1d9738
JB		 364
365 return 0;
e2fa3a76
TH		 366
367out_no_query_bo:
3530bdc3
TH		 368 if (dev_priv->has_mob)
369 vmw_otables_takedown(dev_priv);
370out_no_mob:
e2fa3a76
TH		 371 vmw_fence_fifo_down(dev_priv->fman);
372 vmw_fifo_release(dev_priv, &dev_priv->fifo);
373 return ret;
fb1d9738
JB		 374}
375
376static void vmw_release_device(struct vmw_private *dev_priv)
377{
e2fa3a76
TH		 378 /*
379 * Previous destructions should've released
380 * the pinned bo.
381 */
382
383 BUG_ON(dev_priv->pinned_bo != NULL);
384
385 ttm_bo_unref(&dev_priv->dummy_query_bo);
3530bdc3
TH		 386 if (dev_priv->has_mob)
387 vmw_otables_takedown(dev_priv);
ae2a1040 388 vmw_fence_fifo_down(dev_priv->fman);
fb1d9738 389 vmw_fifo_release(dev_priv, &dev_priv->fifo);
30c78bb8
TH		 390}
391
3530bdc3 392
05730b32
TH		 393/**
394 * Increase the 3d resource refcount.
395 * If the count was prevously zero, initialize the fifo, switching to svga
396 * mode. Note that the master holds a ref as well, and may request an
397 * explicit switch to svga mode if fb is not running, using @unhide_svga.
398 */
399int vmw_3d_resource_inc(struct vmw_private *dev_priv,
400 bool unhide_svga)
30c78bb8
TH		 401{
402 int ret = 0;
403
404 mutex_lock(&dev_priv->release_mutex);
405 if (unlikely(dev_priv->num_3d_resources++ == 0)) {
406 ret = vmw_request_device(dev_priv);
407 if (unlikely(ret != 0))
408 --dev_priv->num_3d_resources;
05730b32
TH		 409 } else if (unhide_svga) {
410 mutex_lock(&dev_priv->hw_mutex);
411 vmw_write(dev_priv, SVGA_REG_ENABLE,
412 vmw_read(dev_priv, SVGA_REG_ENABLE) &
413 ~SVGA_REG_ENABLE_HIDE);
414 mutex_unlock(&dev_priv->hw_mutex);
30c78bb8 415 }
05730b32 416
30c78bb8
TH		 417 mutex_unlock(&dev_priv->release_mutex);
418 return ret;
fb1d9738
JB		 419}
420
05730b32
TH		 421/**
422 * Decrease the 3d resource refcount.
423 * If the count reaches zero, disable the fifo, switching to vga mode.
424 * Note that the master holds a refcount as well, and may request an
425 * explicit switch to vga mode when it releases its refcount to account
426 * for the situation of an X server vt switch to VGA with 3d resources
427 * active.
428 */
429void vmw_3d_resource_dec(struct vmw_private *dev_priv,
430 bool hide_svga)
30c78bb8
TH		 431{
432 int32_t n3d;
433
434 mutex_lock(&dev_priv->release_mutex);
435 if (unlikely(--dev_priv->num_3d_resources == 0))
436 vmw_release_device(dev_priv);
05730b32
TH		 437 else if (hide_svga) {
438 mutex_lock(&dev_priv->hw_mutex);
439 vmw_write(dev_priv, SVGA_REG_ENABLE,
440 vmw_read(dev_priv, SVGA_REG_ENABLE) |
441 SVGA_REG_ENABLE_HIDE);
442 mutex_unlock(&dev_priv->hw_mutex);
443 }
444
30c78bb8
TH		 445 n3d = (int32_t) dev_priv->num_3d_resources;
446 mutex_unlock(&dev_priv->release_mutex);
447
448 BUG_ON(n3d < 0);
449}
450
eb4f923b
JB		 451/**
452 * Sets the initial_[width|height] fields on the given vmw_private.
453 *
454 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
67d4a87b
TH		 455 * clamping the value to fb_max_[width|height] fields and the
456 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
457 * If the values appear to be invalid, set them to
eb4f923b
JB		 458 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
459 */
460static void vmw_get_initial_size(struct vmw_private *dev_priv)
461{
462 uint32_t width;
463 uint32_t height;
464
465 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
466 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
467
468 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
eb4f923b 469 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
67d4a87b
TH		 470
471 if (width > dev_priv->fb_max_width ||
472 height > dev_priv->fb_max_height) {
473
474 /*
475 * This is a host error and shouldn't occur.
476 */
477
478 width = VMW_MIN_INITIAL_WIDTH;
479 height = VMW_MIN_INITIAL_HEIGHT;
480 }
eb4f923b
JB		 481
482 dev_priv->initial_width = width;
483 dev_priv->initial_height = height;
484}
485
d92d9851
TH		 486/**
487 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
488 * system.
489 *
490 * @dev_priv: Pointer to a struct vmw_private
491 *
492 * This functions tries to determine the IOMMU setup and what actions
493 * need to be taken by the driver to make system pages visible to the
494 * device.
495 * If this function decides that DMA is not possible, it returns -EINVAL.
496 * The driver may then try to disable features of the device that require
497 * DMA.
498 */
499static int vmw_dma_select_mode(struct vmw_private *dev_priv)
500{
d92d9851
TH		 501 static const char *names[vmw_dma_map_max] = {
502 [vmw_dma_phys] = "Using physical TTM page addresses.",
503 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
504 [vmw_dma_map_populate] = "Keeping DMA mappings.",
505 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
e14cd953
TH		 506#ifdef CONFIG_X86
507 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
d92d9851
TH		 508
509#ifdef CONFIG_INTEL_IOMMU
510 if (intel_iommu_enabled) {
511 dev_priv->map_mode = vmw_dma_map_populate;
512 goto out_fixup;
513 }
514#endif
515
516 if (!(vmw_force_iommu || vmw_force_coherent)) {
517 dev_priv->map_mode = vmw_dma_phys;
518 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
519 return 0;
520 }
521
522 dev_priv->map_mode = vmw_dma_map_populate;
523
524 if (dma_ops->sync_single_for_cpu)
525 dev_priv->map_mode = vmw_dma_alloc_coherent;
526#ifdef CONFIG_SWIOTLB
527 if (swiotlb_nr_tbl() == 0)
528 dev_priv->map_mode = vmw_dma_map_populate;
529#endif
530
21136946 531#ifdef CONFIG_INTEL_IOMMU
d92d9851 532out_fixup:
21136946 533#endif
d92d9851
TH		 534 if (dev_priv->map_mode == vmw_dma_map_populate &&
535 vmw_restrict_iommu)
536 dev_priv->map_mode = vmw_dma_map_bind;
537
538 if (vmw_force_coherent)
539 dev_priv->map_mode = vmw_dma_alloc_coherent;
540
541#if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
542 /*
543 * No coherent page pool
544 */
545 if (dev_priv->map_mode == vmw_dma_alloc_coherent)
546 return -EINVAL;
547#endif
548
e14cd953
TH		 549#else /* CONFIG_X86 */
550 dev_priv->map_mode = vmw_dma_map_populate;
551#endif /* CONFIG_X86 */
552
d92d9851
TH		 553 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
554
555 return 0;
556}
557
0d00c488
TH		 558/**
559 * vmw_dma_masks - set required page- and dma masks
560 *
561 * @dev: Pointer to struct drm-device
562 *
563 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
564 * restriction also for 64-bit systems.
565 */
566#ifdef CONFIG_INTEL_IOMMU
567static int vmw_dma_masks(struct vmw_private *dev_priv)
568{
569 struct drm_device *dev = dev_priv->dev;
570
571 if (intel_iommu_enabled &&
572 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
573 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
574 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
575 }
576 return 0;
577}
578#else
579static int vmw_dma_masks(struct vmw_private *dev_priv)
580{
581 return 0;
582}
583#endif
584
fb1d9738
JB		 585static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
586{
587 struct vmw_private *dev_priv;
588 int ret;
c188660f 589 uint32_t svga_id;
c0951b79 590 enum vmw_res_type i;
d92d9851 591 bool refuse_dma = false;
fb1d9738
JB		 592
593 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
594 if (unlikely(dev_priv == NULL)) {
595 DRM_ERROR("Failed allocating a device private struct.\n");
596 return -ENOMEM;
597 }
fb1d9738 598
466e69b8
DA		 599 pci_set_master(dev->pdev);
600
fb1d9738
JB		 601 dev_priv->dev = dev;
602 dev_priv->vmw_chipset = chipset;
6bcd8d3c 603 dev_priv->last_read_seqno = (uint32_t) -100;
fb1d9738
JB		 604 mutex_init(&dev_priv->hw_mutex);
605 mutex_init(&dev_priv->cmdbuf_mutex);
30c78bb8 606 mutex_init(&dev_priv->release_mutex);
173fb7d4 607 mutex_init(&dev_priv->binding_mutex);
fb1d9738 608 rwlock_init(&dev_priv->resource_lock);
294adf7d 609 ttm_lock_init(&dev_priv->reservation_sem);
c0951b79
TH		 610
611 for (i = vmw_res_context; i < vmw_res_max; ++i) {
612 idr_init(&dev_priv->res_idr[i]);
613 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
614 }
615
fb1d9738
JB		 616 mutex_init(&dev_priv->init_mutex);
617 init_waitqueue_head(&dev_priv->fence_queue);
618 init_waitqueue_head(&dev_priv->fifo_queue);
4f73a96b 619 dev_priv->fence_queue_waiters = 0;
fb1d9738 620 atomic_set(&dev_priv->fifo_queue_waiters, 0);
c0951b79 621
5bb39e81 622 dev_priv->used_memory_size = 0;
fb1d9738
JB		 623
624 dev_priv->io_start = pci_resource_start(dev->pdev, 0);
625 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
626 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
627
30c78bb8
TH		 628 dev_priv->enable_fb = enable_fbdev;
629
fb1d9738 630 mutex_lock(&dev_priv->hw_mutex);
c188660f
PH		 631
632 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
633 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
634 if (svga_id != SVGA_ID_2) {
635 ret = -ENOSYS;
49625904 636 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
c188660f
PH		 637 mutex_unlock(&dev_priv->hw_mutex);
638 goto out_err0;
639 }
640
fb1d9738 641 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
d92d9851
TH		 642 ret = vmw_dma_select_mode(dev_priv);
643 if (unlikely(ret != 0)) {
644 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
645 refuse_dma = true;
646 }
fb1d9738 647
5bb39e81
TH		 648 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
649 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
650 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
651 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
eb4f923b
JB		 652
653 vmw_get_initial_size(dev_priv);
654
0d00c488 655 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
fb1d9738
JB		 656 dev_priv->max_gmr_ids =
657 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
fb17f189
TH		 658 dev_priv->max_gmr_pages =
659 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
660 dev_priv->memory_size =
661 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
5bb39e81
TH		 662 dev_priv->memory_size -= dev_priv->vram_size;
663 } else {
664 /*
665 * An arbitrary limit of 512MiB on surface
666 * memory. But all HWV8 hardware supports GMR2.
667 */
668 dev_priv->memory_size = 512*1024*1024;
fb17f189 669 }
6da768aa 670 dev_priv->max_mob_pages = 0;
857aea1c 671 dev_priv->max_mob_size = 0;
6da768aa
TH		 672 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
673 uint64_t mem_size =
674 vmw_read(dev_priv,
675 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
676
677 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
afb0e50f
TH		 678 dev_priv->prim_bb_mem =
679 vmw_read(dev_priv,
680 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
857aea1c
CL		 681 dev_priv->max_mob_size =
682 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
afb0e50f
TH		 683 } else
684 dev_priv->prim_bb_mem = dev_priv->vram_size;
fb1d9738 685
0d00c488 686 ret = vmw_dma_masks(dev_priv);
3e894a62
TH		 687 if (unlikely(ret != 0)) {
688 mutex_unlock(&dev_priv->hw_mutex);
0d00c488 689 goto out_err0;
3e894a62 690 }
0d00c488 691
afb0e50f
TH		 692 if (unlikely(dev_priv->prim_bb_mem < dev_priv->vram_size))
693 dev_priv->prim_bb_mem = dev_priv->vram_size;
bc2d6508 694
fb1d9738
JB		 695 mutex_unlock(&dev_priv->hw_mutex);
696
697 vmw_print_capabilities(dev_priv->capabilities);
698
0d00c488 699 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
fb1d9738
JB		 700 DRM_INFO("Max GMR ids is %u\n",
701 (unsigned)dev_priv->max_gmr_ids);
fb17f189
TH		 702 DRM_INFO("Max number of GMR pages is %u\n",
703 (unsigned)dev_priv->max_gmr_pages);
5bb39e81
TH		 704 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
705 (unsigned)dev_priv->memory_size / 1024);
fb17f189 706 }
bc2d6508
TH		 707 DRM_INFO("Maximum display memory size is %u kiB\n",
708 dev_priv->prim_bb_mem / 1024);
fb1d9738
JB		 709 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
710 dev_priv->vram_start, dev_priv->vram_size / 1024);
711 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
712 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
713
714 ret = vmw_ttm_global_init(dev_priv);
715 if (unlikely(ret != 0))
716 goto out_err0;
717
718
719 vmw_master_init(&dev_priv->fbdev_master);
720 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
721 dev_priv->active_master = &dev_priv->fbdev_master;
722
a2c06ee2 723
fb1d9738
JB		 724 ret = ttm_bo_device_init(&dev_priv->bdev,
725 dev_priv->bo_global_ref.ref.object,
44d847b7
DH		 726 &vmw_bo_driver,
727 dev->anon_inode->i_mapping,
728 VMWGFX_FILE_PAGE_OFFSET,
fb1d9738
JB		 729 false);
730 if (unlikely(ret != 0)) {
731 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
732 goto out_err1;
733 }
734
735 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
736 (dev_priv->vram_size >> PAGE_SHIFT));
737 if (unlikely(ret != 0)) {
738 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
739 goto out_err2;
740 }
741
135cba0d 742 dev_priv->has_gmr = true;
d92d9851
TH		 743 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
744 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
6da768aa 745 VMW_PL_GMR) != 0) {
135cba0d
TH		 746 DRM_INFO("No GMR memory available. "
747 "Graphics memory resources are very limited.\n");
748 dev_priv->has_gmr = false;
749 }
750
6da768aa 751 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
3530bdc3 752 dev_priv->has_mob = true;
6da768aa
TH		 753 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
754 VMW_PL_MOB) != 0) {
755 DRM_INFO("No MOB memory available. "
756 "3D will be disabled.\n");
757 dev_priv->has_mob = false;
758 }
759 }
3530bdc3 760
247d36d7
AL		 761 dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start,
762 dev_priv->mmio_size);
fb1d9738
JB		 763
764 dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
765 dev_priv->mmio_size);
766
767 if (unlikely(dev_priv->mmio_virt == NULL)) {
768 ret = -ENOMEM;
769 DRM_ERROR("Failed mapping MMIO.\n");
770 goto out_err3;
771 }
772
d7e1958d
JB		 773 /* Need mmio memory to check for fifo pitchlock cap. */
774 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
775 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
776 !vmw_fifo_have_pitchlock(dev_priv)) {
777 ret = -ENOSYS;
778 DRM_ERROR("Hardware has no pitchlock\n");
779 goto out_err4;
780 }
781
fb1d9738 782 dev_priv->tdev = ttm_object_device_init
69977ff5 783 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
fb1d9738
JB		 784
785 if (unlikely(dev_priv->tdev == NULL)) {
786 DRM_ERROR("Unable to initialize TTM object management.\n");
787 ret = -ENOMEM;
788 goto out_err4;
789 }
790
791 dev->dev_private = dev_priv;
792
fb1d9738
JB		 793 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
794 dev_priv->stealth = (ret != 0);
795 if (dev_priv->stealth) {
796 /**
797 * Request at least the mmio PCI resource.
798 */
799
800 DRM_INFO("It appears like vesafb is loaded. "
f2d12b8e 801 "Ignore above error if any.\n");
fb1d9738
JB		 802 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
803 if (unlikely(ret != 0)) {
804 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
805 goto out_no_device;
806 }
fb1d9738 807 }
ae2a1040 808
506ff75c
TH		 809 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
810 ret = drm_irq_install(dev);
811 if (ret != 0) {
812 DRM_ERROR("Failed installing irq: %d\n", ret);
813 goto out_no_irq;
814 }
815 }
816
ae2a1040 817 dev_priv->fman = vmw_fence_manager_init(dev_priv);
14bbf20c
WY		 818 if (unlikely(dev_priv->fman == NULL)) {
819 ret = -ENOMEM;
ae2a1040 820 goto out_no_fman;
14bbf20c 821 }
56d1c78d 822
56d1c78d 823 vmw_kms_save_vga(dev_priv);
56d1c78d
JB		 824
825 /* Start kms and overlay systems, needs fifo. */
7a1c2f6c
TH		 826 ret = vmw_kms_init(dev_priv);
827 if (unlikely(ret != 0))
828 goto out_no_kms;
f2d12b8e 829 vmw_overlay_init(dev_priv);
56d1c78d 830
30c78bb8 831 if (dev_priv->enable_fb) {
506ff75c
TH		 832 ret = vmw_3d_resource_inc(dev_priv, true);
833 if (unlikely(ret != 0))
834 goto out_no_fifo;
30c78bb8 835 vmw_fb_init(dev_priv);
7a1c2f6c
TH		 836 }
837
d9f36a00
TH		 838 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
839 register_pm_notifier(&dev_priv->pm_nb);
840
fb1d9738
JB		 841 return 0;
842
506ff75c 843out_no_fifo:
56d1c78d
JB		 844 vmw_overlay_close(dev_priv);
845 vmw_kms_close(dev_priv);
846out_no_kms:
506ff75c 847 vmw_kms_restore_vga(dev_priv);
ae2a1040
TH		 848 vmw_fence_manager_takedown(dev_priv->fman);
849out_no_fman:
506ff75c
TH		 850 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
851 drm_irq_uninstall(dev_priv->dev);
852out_no_irq:
30c78bb8
TH		 853 if (dev_priv->stealth)
854 pci_release_region(dev->pdev, 2);
855 else
856 pci_release_regions(dev->pdev);
fb1d9738 857out_no_device:
fb1d9738
JB		 858 ttm_object_device_release(&dev_priv->tdev);
859out_err4:
860 iounmap(dev_priv->mmio_virt);
861out_err3:
247d36d7 862 arch_phys_wc_del(dev_priv->mmio_mtrr);
6da768aa
TH		 863 if (dev_priv->has_mob)
864 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
135cba0d
TH		 865 if (dev_priv->has_gmr)
866 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
fb1d9738
JB		 867 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
868out_err2:
869 (void)ttm_bo_device_release(&dev_priv->bdev);
870out_err1:
871 vmw_ttm_global_release(dev_priv);
872out_err0:
c0951b79
TH		 873 for (i = vmw_res_context; i < vmw_res_max; ++i)
874 idr_destroy(&dev_priv->res_idr[i]);
875
fb1d9738
JB		 876 kfree(dev_priv);
877 return ret;
878}
879
880static int vmw_driver_unload(struct drm_device *dev)
881{
882 struct vmw_private *dev_priv = vmw_priv(dev);
c0951b79 883 enum vmw_res_type i;
fb1d9738 884
d9f36a00
TH		 885 unregister_pm_notifier(&dev_priv->pm_nb);
886
c0951b79
TH		 887 if (dev_priv->ctx.res_ht_initialized)
888 drm_ht_remove(&dev_priv->ctx.res_ht);
be38ab6e
TH		 889 if (dev_priv->ctx.cmd_bounce)
890 vfree(dev_priv->ctx.cmd_bounce);
30c78bb8
TH		 891 if (dev_priv->enable_fb) {
892 vmw_fb_close(dev_priv);
893 vmw_kms_restore_vga(dev_priv);
05730b32 894 vmw_3d_resource_dec(dev_priv, false);
30c78bb8 895 }
f2d12b8e
TH		 896 vmw_kms_close(dev_priv);
897 vmw_overlay_close(dev_priv);
ae2a1040 898 vmw_fence_manager_takedown(dev_priv->fman);
506ff75c
TH		 899 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
900 drm_irq_uninstall(dev_priv->dev);
f2d12b8e 901 if (dev_priv->stealth)
fb1d9738 902 pci_release_region(dev->pdev, 2);
f2d12b8e
TH		 903 else
904 pci_release_regions(dev->pdev);
905
fb1d9738
JB		 906 ttm_object_device_release(&dev_priv->tdev);
907 iounmap(dev_priv->mmio_virt);
247d36d7 908 arch_phys_wc_del(dev_priv->mmio_mtrr);
6da768aa
TH		 909 if (dev_priv->has_mob)
910 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
135cba0d
TH		 911 if (dev_priv->has_gmr)
912 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
fb1d9738
JB		 913 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
914 (void)ttm_bo_device_release(&dev_priv->bdev);
915 vmw_ttm_global_release(dev_priv);
c0951b79
TH		 916
917 for (i = vmw_res_context; i < vmw_res_max; ++i)
918 idr_destroy(&dev_priv->res_idr[i]);
fb1d9738
JB		 919
920 kfree(dev_priv);
921
922 return 0;
923}
924
6b82ef50
TH		 925static void vmw_preclose(struct drm_device *dev,
926 struct drm_file *file_priv)
927{
928 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
929 struct vmw_private *dev_priv = vmw_priv(dev);
930
931 vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
932}
933
fb1d9738
JB		 934static void vmw_postclose(struct drm_device *dev,
935 struct drm_file *file_priv)
936{
937 struct vmw_fpriv *vmw_fp;
938
939 vmw_fp = vmw_fpriv(file_priv);
c4249855
TH		 940
941 if (vmw_fp->locked_master) {
942 struct vmw_master *vmaster =
943 vmw_master(vmw_fp->locked_master);
944
945 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
946 ttm_vt_unlock(&vmaster->lock);
fb1d9738 947 drm_master_put(&vmw_fp->locked_master);
c4249855
TH		 948 }
949
d5bde956 950 vmw_compat_shader_man_destroy(vmw_fp->shman);
c4249855 951 ttm_object_file_release(&vmw_fp->tfile);
fb1d9738
JB		 952 kfree(vmw_fp);
953}
954
955static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
956{
957 struct vmw_private *dev_priv = vmw_priv(dev);
958 struct vmw_fpriv *vmw_fp;
959 int ret = -ENOMEM;
960
961 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
962 if (unlikely(vmw_fp == NULL))
963 return ret;
964
6b82ef50 965 INIT_LIST_HEAD(&vmw_fp->fence_events);
fb1d9738
JB		 966 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
967 if (unlikely(vmw_fp->tfile == NULL))
968 goto out_no_tfile;
969
d5bde956
TH		 970 vmw_fp->shman = vmw_compat_shader_man_create(dev_priv);
971 if (IS_ERR(vmw_fp->shman))
972 goto out_no_shman;
973
fb1d9738 974 file_priv->driver_priv = vmw_fp;
fb1d9738
JB		 975
976 return 0;
977
d5bde956
TH		 978out_no_shman:
979 ttm_object_file_release(&vmw_fp->tfile);
fb1d9738
JB		 980out_no_tfile:
981 kfree(vmw_fp);
982 return ret;
983}
984
64190bde
TH		 985static struct vmw_master *vmw_master_check(struct drm_device *dev,
986 struct drm_file *file_priv,
987 unsigned int flags)
988{
989 int ret;
990 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
991 struct vmw_master *vmaster;
992
993 if (file_priv->minor->type != DRM_MINOR_LEGACY ||
994 !(flags & DRM_AUTH))
995 return NULL;
996
997 ret = mutex_lock_interruptible(&dev->master_mutex);
998 if (unlikely(ret != 0))
999 return ERR_PTR(-ERESTARTSYS);
1000
1001 if (file_priv->is_master) {
1002 mutex_unlock(&dev->master_mutex);
1003 return NULL;
1004 }
1005
1006 /*
1007 * Check if we were previously master, but now dropped.
1008 */
1009 if (vmw_fp->locked_master) {
1010 mutex_unlock(&dev->master_mutex);
1011 DRM_ERROR("Dropped master trying to access ioctl that "
1012 "requires authentication.\n");
1013 return ERR_PTR(-EACCES);
1014 }
1015 mutex_unlock(&dev->master_mutex);
1016
1017 /*
1018 * Taking the drm_global_mutex after the TTM lock might deadlock
1019 */
1020 if (!(flags & DRM_UNLOCKED)) {
1021 DRM_ERROR("Refusing locked ioctl access.\n");
1022 return ERR_PTR(-EDEADLK);
1023 }
1024
1025 /*
1026 * Take the TTM lock. Possibly sleep waiting for the authenticating
1027 * master to become master again, or for a SIGTERM if the
1028 * authenticating master exits.
1029 */
1030 vmaster = vmw_master(file_priv->master);
1031 ret = ttm_read_lock(&vmaster->lock, true);
1032 if (unlikely(ret != 0))
1033 vmaster = ERR_PTR(ret);
1034
1035 return vmaster;
1036}
1037
1038static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1039 unsigned long arg,
1040 long (*ioctl_func)(struct file *, unsigned int,
1041 unsigned long))
fb1d9738
JB		 1042{
1043 struct drm_file *file_priv = filp->private_data;
1044 struct drm_device *dev = file_priv->minor->dev;
1045 unsigned int nr = DRM_IOCTL_NR(cmd);
64190bde
TH		 1046 struct vmw_master *vmaster;
1047 unsigned int flags;
1048 long ret;
fb1d9738
JB		 1049
1050 /*
e1f78003 1051 * Do extra checking on driver private ioctls.
fb1d9738
JB		 1052 */
1053
1054 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1055 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
baa70943 1056 const struct drm_ioctl_desc *ioctl =
64190bde 1057 &vmw_ioctls[nr - DRM_COMMAND_BASE];
fb1d9738 1058
2854eeda 1059 if (unlikely(ioctl->cmd_drv != cmd)) {
fb1d9738
JB		 1060 DRM_ERROR("Invalid command format, ioctl %d\n",
1061 nr - DRM_COMMAND_BASE);
1062 return -EINVAL;
1063 }
64190bde
TH		 1064 flags = ioctl->flags;
1065 } else if (!drm_ioctl_flags(nr, &flags))
1066 return -EINVAL;
1067
1068 vmaster = vmw_master_check(dev, file_priv, flags);
1069 if (unlikely(IS_ERR(vmaster))) {
1070 DRM_INFO("IOCTL ERROR %d\n", nr);
1071 return PTR_ERR(vmaster);
fb1d9738
JB		 1072 }
1073
64190bde
TH		 1074 ret = ioctl_func(filp, cmd, arg);
1075 if (vmaster)
1076 ttm_read_unlock(&vmaster->lock);
1077
1078 return ret;
1079}
1080
1081static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1082 unsigned long arg)
1083{
1084 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
fb1d9738
JB		 1085}
1086
64190bde
TH		 1087#ifdef CONFIG_COMPAT
1088static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1089 unsigned long arg)
1090{
1091 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1092}
1093#endif
1094
fb1d9738
JB		 1095static void vmw_lastclose(struct drm_device *dev)
1096{
fb1d9738
JB		 1097 struct drm_crtc *crtc;
1098 struct drm_mode_set set;
1099 int ret;
1100
fb1d9738
JB		 1101 set.x = 0;
1102 set.y = 0;
1103 set.fb = NULL;
1104 set.mode = NULL;
1105 set.connectors = NULL;
1106 set.num_connectors = 0;
1107
1108 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1109 set.crtc = crtc;
2d13b679 1110 ret = drm_mode_set_config_internal(&set);
fb1d9738
JB		 1111 WARN_ON(ret != 0);
1112 }
1113
1114}
1115
1116static void vmw_master_init(struct vmw_master *vmaster)
1117{
1118 ttm_lock_init(&vmaster->lock);
3a939a5e
TH		 1119 INIT_LIST_HEAD(&vmaster->fb_surf);
1120 mutex_init(&vmaster->fb_surf_mutex);
fb1d9738
JB		 1121}
1122
1123static int vmw_master_create(struct drm_device *dev,
1124 struct drm_master *master)
1125{
1126 struct vmw_master *vmaster;
1127
fb1d9738
JB		 1128 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1129 if (unlikely(vmaster == NULL))
1130 return -ENOMEM;
1131
3a939a5e 1132 vmw_master_init(vmaster);
fb1d9738
JB		 1133 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1134 master->driver_priv = vmaster;
1135
1136 return 0;
1137}
1138
1139static void vmw_master_destroy(struct drm_device *dev,
1140 struct drm_master *master)
1141{
1142 struct vmw_master *vmaster = vmw_master(master);
1143
fb1d9738
JB		 1144 master->driver_priv = NULL;
1145 kfree(vmaster);
1146}
1147
1148
1149static int vmw_master_set(struct drm_device *dev,
1150 struct drm_file *file_priv,
1151 bool from_open)
1152{
1153 struct vmw_private *dev_priv = vmw_priv(dev);
1154 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1155 struct vmw_master *active = dev_priv->active_master;
1156 struct vmw_master *vmaster = vmw_master(file_priv->master);
1157 int ret = 0;
1158
30c78bb8 1159 if (!dev_priv->enable_fb) {
05730b32 1160 ret = vmw_3d_resource_inc(dev_priv, true);
30c78bb8
TH		 1161 if (unlikely(ret != 0))
1162 return ret;
1163 vmw_kms_save_vga(dev_priv);
1164 mutex_lock(&dev_priv->hw_mutex);
1165 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
1166 mutex_unlock(&dev_priv->hw_mutex);
1167 }
1168
fb1d9738
JB		 1169 if (active) {
1170 BUG_ON(active != &dev_priv->fbdev_master);
1171 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1172 if (unlikely(ret != 0))
1173 goto out_no_active_lock;
1174
1175 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1176 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1177 if (unlikely(ret != 0)) {
1178 DRM_ERROR("Unable to clean VRAM on "
1179 "master drop.\n");
1180 }
1181
1182 dev_priv->active_master = NULL;
1183 }
1184
1185 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1186 if (!from_open) {
1187 ttm_vt_unlock(&vmaster->lock);
1188 BUG_ON(vmw_fp->locked_master != file_priv->master);
1189 drm_master_put(&vmw_fp->locked_master);
1190 }
1191
1192 dev_priv->active_master = vmaster;
1193
1194 return 0;
1195
1196out_no_active_lock:
30c78bb8 1197 if (!dev_priv->enable_fb) {
ba723fe8
TH		 1198 vmw_kms_restore_vga(dev_priv);
1199 vmw_3d_resource_dec(dev_priv, true);
30c78bb8
TH		 1200 mutex_lock(&dev_priv->hw_mutex);
1201 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1202 mutex_unlock(&dev_priv->hw_mutex);
30c78bb8 1203 }
fb1d9738
JB		 1204 return ret;
1205}
1206
1207static void vmw_master_drop(struct drm_device *dev,
1208 struct drm_file *file_priv,
1209 bool from_release)
1210{
1211 struct vmw_private *dev_priv = vmw_priv(dev);
1212 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1213 struct vmw_master *vmaster = vmw_master(file_priv->master);
1214 int ret;
1215
fb1d9738
JB		 1216 /**
1217 * Make sure the master doesn't disappear while we have
1218 * it locked.
1219 */
1220
1221 vmw_fp->locked_master = drm_master_get(file_priv->master);
1222 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
fb1d9738
JB		 1223 if (unlikely((ret != 0))) {
1224 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1225 drm_master_put(&vmw_fp->locked_master);
1226 }
1227
c4249855
TH		 1228 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1229 vmw_execbuf_release_pinned_bo(dev_priv);
fb1d9738 1230
30c78bb8
TH		 1231 if (!dev_priv->enable_fb) {
1232 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1233 if (unlikely(ret != 0))
1234 DRM_ERROR("Unable to clean VRAM on master drop.\n");
ba723fe8
TH		 1235 vmw_kms_restore_vga(dev_priv);
1236 vmw_3d_resource_dec(dev_priv, true);
30c78bb8
TH		 1237 mutex_lock(&dev_priv->hw_mutex);
1238 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1239 mutex_unlock(&dev_priv->hw_mutex);
30c78bb8
TH		 1240 }
1241
fb1d9738
JB		 1242 dev_priv->active_master = &dev_priv->fbdev_master;
1243 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1244 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1245
30c78bb8
TH		 1246 if (dev_priv->enable_fb)
1247 vmw_fb_on(dev_priv);
fb1d9738
JB		 1248}
1249
1250
1251static void vmw_remove(struct pci_dev *pdev)
1252{
1253 struct drm_device *dev = pci_get_drvdata(pdev);
1254
1255 drm_put_dev(dev);
1256}
1257
d9f36a00
TH		 1258static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1259 void *ptr)
1260{
1261 struct vmw_private *dev_priv =
1262 container_of(nb, struct vmw_private, pm_nb);
d9f36a00
TH		 1263
1264 switch (val) {
1265 case PM_HIBERNATION_PREPARE:
1266 case PM_SUSPEND_PREPARE:
294adf7d 1267 ttm_suspend_lock(&dev_priv->reservation_sem);
d9f36a00
TH		 1268
1269 /**
1270 * This empties VRAM and unbinds all GMR bindings.
1271 * Buffer contents is moved to swappable memory.
1272 */
c0951b79
TH		 1273 vmw_execbuf_release_pinned_bo(dev_priv);
1274 vmw_resource_evict_all(dev_priv);
d9f36a00 1275 ttm_bo_swapout_all(&dev_priv->bdev);
094e0fa8 1276
d9f36a00
TH		 1277 break;
1278 case PM_POST_HIBERNATION:
1279 case PM_POST_SUSPEND:
094e0fa8 1280 case PM_POST_RESTORE:
294adf7d 1281 ttm_suspend_unlock(&dev_priv->reservation_sem);
094e0fa8 1282
d9f36a00
TH		 1283 break;
1284 case PM_RESTORE_PREPARE:
1285 break;
d9f36a00
TH		 1286 default:
1287 break;
1288 }
1289 return 0;
1290}
1291
1292/**
1293 * These might not be needed with the virtual SVGA device.
1294 */
1295
7fbd721a 1296static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
d9f36a00 1297{
094e0fa8
TH		 1298 struct drm_device *dev = pci_get_drvdata(pdev);
1299 struct vmw_private *dev_priv = vmw_priv(dev);
1300
1301 if (dev_priv->num_3d_resources != 0) {
1302 DRM_INFO("Can't suspend or hibernate "
1303 "while 3D resources are active.\n");
1304 return -EBUSY;
1305 }
1306
d9f36a00
TH		 1307 pci_save_state(pdev);
1308 pci_disable_device(pdev);
1309 pci_set_power_state(pdev, PCI_D3hot);
1310 return 0;
1311}
1312
7fbd721a 1313static int vmw_pci_resume(struct pci_dev *pdev)
d9f36a00
TH		 1314{
1315 pci_set_power_state(pdev, PCI_D0);
1316 pci_restore_state(pdev);
1317 return pci_enable_device(pdev);
1318}
1319
7fbd721a
TH		 1320static int vmw_pm_suspend(struct device *kdev)
1321{
1322 struct pci_dev *pdev = to_pci_dev(kdev);
1323 struct pm_message dummy;
1324
1325 dummy.event = 0;
1326
1327 return vmw_pci_suspend(pdev, dummy);
1328}
1329
1330static int vmw_pm_resume(struct device *kdev)
1331{
1332 struct pci_dev *pdev = to_pci_dev(kdev);
1333
1334 return vmw_pci_resume(pdev);
1335}
1336
1337static int vmw_pm_prepare(struct device *kdev)
1338{
1339 struct pci_dev *pdev = to_pci_dev(kdev);
1340 struct drm_device *dev = pci_get_drvdata(pdev);
1341 struct vmw_private *dev_priv = vmw_priv(dev);
1342
1343 /**
1344 * Release 3d reference held by fbdev and potentially
1345 * stop fifo.
1346 */
1347 dev_priv->suspended = true;
1348 if (dev_priv->enable_fb)
05730b32 1349 vmw_3d_resource_dec(dev_priv, true);
7fbd721a
TH		 1350
1351 if (dev_priv->num_3d_resources != 0) {
1352
1353 DRM_INFO("Can't suspend or hibernate "
1354 "while 3D resources are active.\n");
1355
1356 if (dev_priv->enable_fb)
05730b32 1357 vmw_3d_resource_inc(dev_priv, true);
7fbd721a
TH		 1358 dev_priv->suspended = false;
1359 return -EBUSY;
1360 }
1361
1362 return 0;
1363}
1364
1365static void vmw_pm_complete(struct device *kdev)
1366{
1367 struct pci_dev *pdev = to_pci_dev(kdev);
1368 struct drm_device *dev = pci_get_drvdata(pdev);
1369 struct vmw_private *dev_priv = vmw_priv(dev);
1370
95e8f6a2
TH		 1371 mutex_lock(&dev_priv->hw_mutex);
1372 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1373 (void) vmw_read(dev_priv, SVGA_REG_ID);
1374 mutex_unlock(&dev_priv->hw_mutex);
1375
7fbd721a
TH		 1376 /**
1377 * Reclaim 3d reference held by fbdev and potentially
1378 * start fifo.
1379 */
1380 if (dev_priv->enable_fb)
05730b32 1381 vmw_3d_resource_inc(dev_priv, false);
7fbd721a
TH		 1382
1383 dev_priv->suspended = false;
1384}
1385
1386static const struct dev_pm_ops vmw_pm_ops = {
1387 .prepare = vmw_pm_prepare,
1388 .complete = vmw_pm_complete,
1389 .suspend = vmw_pm_suspend,
1390 .resume = vmw_pm_resume,
1391};
1392
e08e96de
AV		 1393static const struct file_operations vmwgfx_driver_fops = {
1394 .owner = THIS_MODULE,
1395 .open = drm_open,
1396 .release = drm_release,
1397 .unlocked_ioctl = vmw_unlocked_ioctl,
1398 .mmap = vmw_mmap,
1399 .poll = vmw_fops_poll,
1400 .read = vmw_fops_read,
e08e96de 1401#if defined(CONFIG_COMPAT)
64190bde 1402 .compat_ioctl = vmw_compat_ioctl,
e08e96de
AV		 1403#endif
1404 .llseek = noop_llseek,
1405};
1406
fb1d9738
JB		 1407static struct drm_driver driver = {
1408 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
69977ff5 1409 DRIVER_MODESET | DRIVER_PRIME,
fb1d9738
JB		 1410 .load = vmw_driver_load,
1411 .unload = vmw_driver_unload,
fb1d9738
JB		 1412 .lastclose = vmw_lastclose,
1413 .irq_preinstall = vmw_irq_preinstall,
1414 .irq_postinstall = vmw_irq_postinstall,
1415 .irq_uninstall = vmw_irq_uninstall,
1416 .irq_handler = vmw_irq_handler,
7a1c2f6c 1417 .get_vblank_counter = vmw_get_vblank_counter,
1c482ab3
JB		 1418 .enable_vblank = vmw_enable_vblank,
1419 .disable_vblank = vmw_disable_vblank,
fb1d9738
JB		 1420 .ioctls = vmw_ioctls,
1421 .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
fb1d9738
JB		 1422 .master_create = vmw_master_create,
1423 .master_destroy = vmw_master_destroy,
1424 .master_set = vmw_master_set,
1425 .master_drop = vmw_master_drop,
1426 .open = vmw_driver_open,
6b82ef50 1427 .preclose = vmw_preclose,
fb1d9738 1428 .postclose = vmw_postclose,
5e1782d2
DA		 1429
1430 .dumb_create = vmw_dumb_create,
1431 .dumb_map_offset = vmw_dumb_map_offset,
1432 .dumb_destroy = vmw_dumb_destroy,
1433
69977ff5
TH		 1434 .prime_fd_to_handle = vmw_prime_fd_to_handle,
1435 .prime_handle_to_fd = vmw_prime_handle_to_fd,
1436
e08e96de 1437 .fops = &vmwgfx_driver_fops,
fb1d9738
JB		 1438 .name = VMWGFX_DRIVER_NAME,
1439 .desc = VMWGFX_DRIVER_DESC,
1440 .date = VMWGFX_DRIVER_DATE,
1441 .major = VMWGFX_DRIVER_MAJOR,
1442 .minor = VMWGFX_DRIVER_MINOR,
1443 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1444};
1445
8410ea3b
DA		 1446static struct pci_driver vmw_pci_driver = {
1447 .name = VMWGFX_DRIVER_NAME,
1448 .id_table = vmw_pci_id_list,
1449 .probe = vmw_probe,
1450 .remove = vmw_remove,
1451 .driver = {
1452 .pm = &vmw_pm_ops
1453 }
1454};
1455
fb1d9738
JB		 1456static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1457{
dcdb1674 1458 return drm_get_pci_dev(pdev, ent, &driver);
fb1d9738
JB		 1459}
1460
1461static int __init vmwgfx_init(void)
1462{
1463 int ret;
8410ea3b 1464 ret = drm_pci_init(&driver, &vmw_pci_driver);
fb1d9738
JB		 1465 if (ret)
1466 DRM_ERROR("Failed initializing DRM.\n");
1467 return ret;
1468}
1469
1470static void __exit vmwgfx_exit(void)
1471{
8410ea3b 1472 drm_pci_exit(&driver, &vmw_pci_driver);
fb1d9738
JB		 1473}
1474
1475module_init(vmwgfx_init);
1476module_exit(vmwgfx_exit);
1477
1478MODULE_AUTHOR("VMware Inc. and others");
1479MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1480MODULE_LICENSE("GPL and additional rights");
73558ead
TH		 1481MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1482 __stringify(VMWGFX_DRIVER_MINOR) "."
1483 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1484 "0");
Linux kernel - Deliverables
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