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drm/vmwgfx: Add "quirk" to handling command verification exceptions
[deliverable/linux.git] / drivers / gpu / drm / vmwgfx / vmwgfx_drv.c
CommitLineData
fb1d9738
JB		 1/**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
e0cd3608 27#include <linux/module.h>
fb1d9738 28
760285e7 29#include <drm/drmP.h>
fb1d9738 30#include "vmwgfx_drv.h"
760285e7
DH		 31#include <drm/ttm/ttm_placement.h>
32#include <drm/ttm/ttm_bo_driver.h>
33#include <drm/ttm/ttm_object.h>
34#include <drm/ttm/ttm_module.h>
d92d9851 35#include <linux/dma_remapping.h>
fb1d9738
JB		 36
37#define VMWGFX_DRIVER_NAME "vmwgfx"
38#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
39#define VMWGFX_CHIP_SVGAII 0
40#define VMW_FB_RESERVATION 0
41
eb4f923b
JB		 42#define VMW_MIN_INITIAL_WIDTH 800
43#define VMW_MIN_INITIAL_HEIGHT 600
44
45
fb1d9738
JB		 46/**
47 * Fully encoded drm commands. Might move to vmw_drm.h
48 */
49
50#define DRM_IOCTL_VMW_GET_PARAM \
51 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
52 struct drm_vmw_getparam_arg)
53#define DRM_IOCTL_VMW_ALLOC_DMABUF \
54 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
55 union drm_vmw_alloc_dmabuf_arg)
56#define DRM_IOCTL_VMW_UNREF_DMABUF \
57 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
58 struct drm_vmw_unref_dmabuf_arg)
59#define DRM_IOCTL_VMW_CURSOR_BYPASS \
60 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
61 struct drm_vmw_cursor_bypass_arg)
62
63#define DRM_IOCTL_VMW_CONTROL_STREAM \
64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
65 struct drm_vmw_control_stream_arg)
66#define DRM_IOCTL_VMW_CLAIM_STREAM \
67 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
68 struct drm_vmw_stream_arg)
69#define DRM_IOCTL_VMW_UNREF_STREAM \
70 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
71 struct drm_vmw_stream_arg)
72
73#define DRM_IOCTL_VMW_CREATE_CONTEXT \
74 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
75 struct drm_vmw_context_arg)
76#define DRM_IOCTL_VMW_UNREF_CONTEXT \
77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
78 struct drm_vmw_context_arg)
79#define DRM_IOCTL_VMW_CREATE_SURFACE \
80 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
81 union drm_vmw_surface_create_arg)
82#define DRM_IOCTL_VMW_UNREF_SURFACE \
83 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
84 struct drm_vmw_surface_arg)
85#define DRM_IOCTL_VMW_REF_SURFACE \
86 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
87 union drm_vmw_surface_reference_arg)
88#define DRM_IOCTL_VMW_EXECBUF \
89 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
90 struct drm_vmw_execbuf_arg)
ae2a1040
TH		 91#define DRM_IOCTL_VMW_GET_3D_CAP \
92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
93 struct drm_vmw_get_3d_cap_arg)
fb1d9738
JB		 94#define DRM_IOCTL_VMW_FENCE_WAIT \
95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
96 struct drm_vmw_fence_wait_arg)
ae2a1040
TH		 97#define DRM_IOCTL_VMW_FENCE_SIGNALED \
98 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
99 struct drm_vmw_fence_signaled_arg)
100#define DRM_IOCTL_VMW_FENCE_UNREF \
101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
102 struct drm_vmw_fence_arg)
57c5ee79
TH		 103#define DRM_IOCTL_VMW_FENCE_EVENT \
104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
105 struct drm_vmw_fence_event_arg)
2fcd5a73
JB		 106#define DRM_IOCTL_VMW_PRESENT \
107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
108 struct drm_vmw_present_arg)
109#define DRM_IOCTL_VMW_PRESENT_READBACK \
110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
111 struct drm_vmw_present_readback_arg)
cd2b89e7
TH		 112#define DRM_IOCTL_VMW_UPDATE_LAYOUT \
113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
114 struct drm_vmw_update_layout_arg)
c74c162f
TH		 115#define DRM_IOCTL_VMW_CREATE_SHADER \
116 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
117 struct drm_vmw_shader_create_arg)
118#define DRM_IOCTL_VMW_UNREF_SHADER \
119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
120 struct drm_vmw_shader_arg)
a97e2192
TH		 121#define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
122 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
123 union drm_vmw_gb_surface_create_arg)
124#define DRM_IOCTL_VMW_GB_SURFACE_REF \
125 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
126 union drm_vmw_gb_surface_reference_arg)
1d7a5cbf
TH		 127#define DRM_IOCTL_VMW_SYNCCPU \
128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
129 struct drm_vmw_synccpu_arg)
fb1d9738
JB		 130
131/**
132 * The core DRM version of this macro doesn't account for
133 * DRM_COMMAND_BASE.
134 */
135
136#define VMW_IOCTL_DEF(ioctl, func, flags) \
7e7392a6 137 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func}
fb1d9738
JB		 138
139/**
140 * Ioctl definitions.
141 */
142
baa70943 143static const struct drm_ioctl_desc vmw_ioctls[] = {
1b2f1489 144 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
03f80263 145 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 146 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
03f80263 147 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 148 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
03f80263 149 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 150 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
e1f78003
TH		 151 vmw_kms_cursor_bypass_ioctl,
152 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
fb1d9738 153
1b2f1489 154 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
e1f78003 155 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
1b2f1489 156 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
e1f78003 157 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
1b2f1489 158 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
e1f78003 159 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
fb1d9738 160
1b2f1489 161 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
03f80263 162 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 163 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
03f80263 164 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 165 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
03f80263 166 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 167 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
03f80263 168 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 169 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
03f80263 170 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 171 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
03f80263 172 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
ae2a1040 173 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
89dcbda6 174 DRM_UNLOCKED | DRM_RENDER_ALLOW),
ae2a1040
TH		 175 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
176 vmw_fence_obj_signaled_ioctl,
89dcbda6 177 DRM_UNLOCKED | DRM_RENDER_ALLOW),
ae2a1040 178 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
03f80263
TH		 179 DRM_UNLOCKED | DRM_RENDER_ALLOW),
180 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
181 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
f63f6a59 182 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
03f80263 183 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
2fcd5a73
JB		 184
185 /* these allow direct access to the framebuffers mark as master only */
186 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
187 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
188 VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
189 vmw_present_readback_ioctl,
190 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
cd2b89e7
TH		 191 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
192 vmw_kms_update_layout_ioctl,
193 DRM_MASTER | DRM_UNLOCKED),
c74c162f
TH		 194 VMW_IOCTL_DEF(VMW_CREATE_SHADER,
195 vmw_shader_define_ioctl,
03f80263 196 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
c74c162f
TH		 197 VMW_IOCTL_DEF(VMW_UNREF_SHADER,
198 vmw_shader_destroy_ioctl,
03f80263 199 DRM_UNLOCKED | DRM_RENDER_ALLOW),
a97e2192
TH		 200 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
201 vmw_gb_surface_define_ioctl,
03f80263 202 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
a97e2192
TH		 203 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
204 vmw_gb_surface_reference_ioctl,
03f80263 205 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
1d7a5cbf
TH		 206 VMW_IOCTL_DEF(VMW_SYNCCPU,
207 vmw_user_dmabuf_synccpu_ioctl,
89dcbda6 208 DRM_UNLOCKED | DRM_RENDER_ALLOW),
fb1d9738
JB		 209};
210
211static struct pci_device_id vmw_pci_id_list[] = {
212 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
213 {0, 0, 0}
214};
c4903429 215MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
fb1d9738 216
5d2afab9 217static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
d92d9851
TH		 218static int vmw_force_iommu;
219static int vmw_restrict_iommu;
220static int vmw_force_coherent;
0d00c488 221static int vmw_restrict_dma_mask;
fb1d9738
JB		 222
223static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
224static void vmw_master_init(struct vmw_master *);
d9f36a00
TH		 225static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
226 void *ptr);
fb1d9738 227
30c78bb8
TH		 228MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
229module_param_named(enable_fbdev, enable_fbdev, int, 0600);
d92d9851
TH		 230MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
231module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
232MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
233module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
234MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
235module_param_named(force_coherent, vmw_force_coherent, int, 0600);
0d00c488
TH		 236MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
237module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
d92d9851 238
30c78bb8 239
fb1d9738
JB		 240static void vmw_print_capabilities(uint32_t capabilities)
241{
242 DRM_INFO("Capabilities:\n");
243 if (capabilities & SVGA_CAP_RECT_COPY)
244 DRM_INFO(" Rect copy.\n");
245 if (capabilities & SVGA_CAP_CURSOR)
246 DRM_INFO(" Cursor.\n");
247 if (capabilities & SVGA_CAP_CURSOR_BYPASS)
248 DRM_INFO(" Cursor bypass.\n");
249 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
250 DRM_INFO(" Cursor bypass 2.\n");
251 if (capabilities & SVGA_CAP_8BIT_EMULATION)
252 DRM_INFO(" 8bit emulation.\n");
253 if (capabilities & SVGA_CAP_ALPHA_CURSOR)
254 DRM_INFO(" Alpha cursor.\n");
255 if (capabilities & SVGA_CAP_3D)
256 DRM_INFO(" 3D.\n");
257 if (capabilities & SVGA_CAP_EXTENDED_FIFO)
258 DRM_INFO(" Extended Fifo.\n");
259 if (capabilities & SVGA_CAP_MULTIMON)
260 DRM_INFO(" Multimon.\n");
261 if (capabilities & SVGA_CAP_PITCHLOCK)
262 DRM_INFO(" Pitchlock.\n");
263 if (capabilities & SVGA_CAP_IRQMASK)
264 DRM_INFO(" Irq mask.\n");
265 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
266 DRM_INFO(" Display Topology.\n");
267 if (capabilities & SVGA_CAP_GMR)
268 DRM_INFO(" GMR.\n");
269 if (capabilities & SVGA_CAP_TRACES)
270 DRM_INFO(" Traces.\n");
dcca2862
TH		 271 if (capabilities & SVGA_CAP_GMR2)
272 DRM_INFO(" GMR2.\n");
273 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
274 DRM_INFO(" Screen Object 2.\n");
c1234db7
TH		 275 if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
276 DRM_INFO(" Command Buffers.\n");
277 if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
278 DRM_INFO(" Command Buffers 2.\n");
279 if (capabilities & SVGA_CAP_GBOBJECTS)
280 DRM_INFO(" Guest Backed Resources.\n");
3eab3d9e
TH		 281 if (capabilities & SVGA_CAP_CMD_BUFFERS_3)
282 DRM_INFO(" Command Buffers 3.\n");
fb1d9738
JB		 283}
284
e2fa3a76 285/**
4b9e45e6 286 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
e2fa3a76 287 *
4b9e45e6 288 * @dev_priv: A device private structure.
e2fa3a76 289 *
4b9e45e6
TH		 290 * This function creates a small buffer object that holds the query
291 * result for dummy queries emitted as query barriers.
292 * The function will then map the first page and initialize a pending
293 * occlusion query result structure, Finally it will unmap the buffer.
294 * No interruptible waits are done within this function.
e2fa3a76 295 *
4b9e45e6 296 * Returns an error if bo creation or initialization fails.
e2fa3a76 297 */
4b9e45e6 298static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
e2fa3a76 299{
4b9e45e6
TH		 300 int ret;
301 struct ttm_buffer_object *bo;
e2fa3a76
TH		 302 struct ttm_bo_kmap_obj map;
303 volatile SVGA3dQueryResult *result;
304 bool dummy;
e2fa3a76 305
4b9e45e6
TH		 306 /*
307 * Create the bo as pinned, so that a tryreserve will
308 * immediately succeed. This is because we're the only
309 * user of the bo currently.
310 */
311 ret = ttm_bo_create(&dev_priv->bdev,
312 PAGE_SIZE,
313 ttm_bo_type_device,
314 &vmw_sys_ne_placement,
315 0, false, NULL,
316 &bo);
317
e2fa3a76 318 if (unlikely(ret != 0))
4b9e45e6
TH		 319 return ret;
320
ee3939e0 321 ret = ttm_bo_reserve(bo, false, true, false, NULL);
4b9e45e6 322 BUG_ON(ret != 0);
e2fa3a76
TH		 323
324 ret = ttm_bo_kmap(bo, 0, 1, &map);
325 if (likely(ret == 0)) {
326 result = ttm_kmap_obj_virtual(&map, &dummy);
327 result->totalSize = sizeof(*result);
328 result->state = SVGA3D_QUERYSTATE_PENDING;
329 result->result32 = 0xff;
330 ttm_bo_kunmap(&map);
4b9e45e6
TH		 331 }
332 vmw_bo_pin(bo, false);
e2fa3a76 333 ttm_bo_unreserve(bo);
e2fa3a76 334
4b9e45e6
TH		 335 if (unlikely(ret != 0)) {
336 DRM_ERROR("Dummy query buffer map failed.\n");
337 ttm_bo_unref(&bo);
338 } else
339 dev_priv->dummy_query_bo = bo;
e2fa3a76 340
4b9e45e6 341 return ret;
e2fa3a76
TH		 342}
343
153b3d5b
TH		 344/**
345 * vmw_request_device_late - Perform late device setup
346 *
347 * @dev_priv: Pointer to device private.
348 *
349 * This function performs setup of otables and enables large command
350 * buffer submission. These tasks are split out to a separate function
351 * because it reverts vmw_release_device_early and is intended to be used
352 * by an error path in the hibernation code.
353 */
354static int vmw_request_device_late(struct vmw_private *dev_priv)
fb1d9738
JB		 355{
356 int ret;
357
3530bdc3
TH		 358 if (dev_priv->has_mob) {
359 ret = vmw_otables_setup(dev_priv);
360 if (unlikely(ret != 0)) {
361 DRM_ERROR("Unable to initialize "
362 "guest Memory OBjects.\n");
153b3d5b 363 return ret;
3530bdc3
TH		 364 }
365 }
153b3d5b 366
3eab3d9e
TH		 367 if (dev_priv->cman) {
368 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman,
369 256*4096, 2*4096);
370 if (ret) {
371 struct vmw_cmdbuf_man *man = dev_priv->cman;
372
373 dev_priv->cman = NULL;
374 vmw_cmdbuf_man_destroy(man);
375 }
376 }
377
153b3d5b
TH		 378 return 0;
379}
380
381static int vmw_request_device(struct vmw_private *dev_priv)
382{
383 int ret;
384
385 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
386 if (unlikely(ret != 0)) {
387 DRM_ERROR("Unable to initialize FIFO.\n");
388 return ret;
389 }
390 vmw_fence_fifo_up(dev_priv->fman);
3eab3d9e
TH		 391 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
392 if (IS_ERR(dev_priv->cman))
393 dev_priv->cman = NULL;
153b3d5b
TH		 394
395 ret = vmw_request_device_late(dev_priv);
396 if (ret)
397 goto out_no_mob;
398
e2fa3a76
TH		 399 ret = vmw_dummy_query_bo_create(dev_priv);
400 if (unlikely(ret != 0))
401 goto out_no_query_bo;
fb1d9738
JB		 402
403 return 0;
e2fa3a76
TH		 404
405out_no_query_bo:
3eab3d9e
TH		 406 if (dev_priv->cman)
407 vmw_cmdbuf_remove_pool(dev_priv->cman);
153b3d5b
TH		 408 if (dev_priv->has_mob) {
409 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
3530bdc3 410 vmw_otables_takedown(dev_priv);
153b3d5b 411 }
3eab3d9e
TH		 412 if (dev_priv->cman)
413 vmw_cmdbuf_man_destroy(dev_priv->cman);
3530bdc3 414out_no_mob:
e2fa3a76
TH		 415 vmw_fence_fifo_down(dev_priv->fman);
416 vmw_fifo_release(dev_priv, &dev_priv->fifo);
417 return ret;
fb1d9738
JB		 418}
419
153b3d5b
TH		 420/**
421 * vmw_release_device_early - Early part of fifo takedown.
422 *
423 * @dev_priv: Pointer to device private struct.
424 *
425 * This is the first part of command submission takedown, to be called before
426 * buffer management is taken down.
427 */
428static void vmw_release_device_early(struct vmw_private *dev_priv)
fb1d9738 429{
e2fa3a76
TH		 430 /*
431 * Previous destructions should've released
432 * the pinned bo.
433 */
434
435 BUG_ON(dev_priv->pinned_bo != NULL);
436
437 ttm_bo_unref(&dev_priv->dummy_query_bo);
3eab3d9e
TH		 438 if (dev_priv->cman)
439 vmw_cmdbuf_remove_pool(dev_priv->cman);
440
153b3d5b
TH		 441 if (dev_priv->has_mob) {
442 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
3530bdc3 443 vmw_otables_takedown(dev_priv);
30c78bb8 444 }
fb1d9738
JB		 445}
446
05730b32 447/**
153b3d5b
TH		 448 * vmw_release_device_late - Late part of fifo takedown.
449 *
450 * @dev_priv: Pointer to device private struct.
451 *
452 * This is the last part of the command submission takedown, to be called when
453 * command submission is no longer needed. It may wait on pending fences.
05730b32 454 */
153b3d5b 455static void vmw_release_device_late(struct vmw_private *dev_priv)
30c78bb8 456{
153b3d5b 457 vmw_fence_fifo_down(dev_priv->fman);
3eab3d9e
TH		 458 if (dev_priv->cman)
459 vmw_cmdbuf_man_destroy(dev_priv->cman);
460
153b3d5b 461 vmw_fifo_release(dev_priv, &dev_priv->fifo);
30c78bb8
TH		 462}
463
eb4f923b
JB		 464/**
465 * Sets the initial_[width|height] fields on the given vmw_private.
466 *
467 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
67d4a87b
TH		 468 * clamping the value to fb_max_[width|height] fields and the
469 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
470 * If the values appear to be invalid, set them to
eb4f923b
JB		 471 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
472 */
473static void vmw_get_initial_size(struct vmw_private *dev_priv)
474{
475 uint32_t width;
476 uint32_t height;
477
478 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
479 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
480
481 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
eb4f923b 482 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
67d4a87b
TH		 483
484 if (width > dev_priv->fb_max_width ||
485 height > dev_priv->fb_max_height) {
486
487 /*
488 * This is a host error and shouldn't occur.
489 */
490
491 width = VMW_MIN_INITIAL_WIDTH;
492 height = VMW_MIN_INITIAL_HEIGHT;
493 }
eb4f923b
JB		 494
495 dev_priv->initial_width = width;
496 dev_priv->initial_height = height;
497}
498
d92d9851
TH		 499/**
500 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
501 * system.
502 *
503 * @dev_priv: Pointer to a struct vmw_private
504 *
505 * This functions tries to determine the IOMMU setup and what actions
506 * need to be taken by the driver to make system pages visible to the
507 * device.
508 * If this function decides that DMA is not possible, it returns -EINVAL.
509 * The driver may then try to disable features of the device that require
510 * DMA.
511 */
512static int vmw_dma_select_mode(struct vmw_private *dev_priv)
513{
d92d9851
TH		 514 static const char *names[vmw_dma_map_max] = {
515 [vmw_dma_phys] = "Using physical TTM page addresses.",
516 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
517 [vmw_dma_map_populate] = "Keeping DMA mappings.",
518 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
e14cd953
TH		 519#ifdef CONFIG_X86
520 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
d92d9851
TH		 521
522#ifdef CONFIG_INTEL_IOMMU
523 if (intel_iommu_enabled) {
524 dev_priv->map_mode = vmw_dma_map_populate;
525 goto out_fixup;
526 }
527#endif
528
529 if (!(vmw_force_iommu || vmw_force_coherent)) {
530 dev_priv->map_mode = vmw_dma_phys;
531 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
532 return 0;
533 }
534
535 dev_priv->map_mode = vmw_dma_map_populate;
536
537 if (dma_ops->sync_single_for_cpu)
538 dev_priv->map_mode = vmw_dma_alloc_coherent;
539#ifdef CONFIG_SWIOTLB
540 if (swiotlb_nr_tbl() == 0)
541 dev_priv->map_mode = vmw_dma_map_populate;
542#endif
543
21136946 544#ifdef CONFIG_INTEL_IOMMU
d92d9851 545out_fixup:
21136946 546#endif
d92d9851
TH		 547 if (dev_priv->map_mode == vmw_dma_map_populate &&
548 vmw_restrict_iommu)
549 dev_priv->map_mode = vmw_dma_map_bind;
550
551 if (vmw_force_coherent)
552 dev_priv->map_mode = vmw_dma_alloc_coherent;
553
554#if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
555 /*
556 * No coherent page pool
557 */
558 if (dev_priv->map_mode == vmw_dma_alloc_coherent)
559 return -EINVAL;
560#endif
561
e14cd953
TH		 562#else /* CONFIG_X86 */
563 dev_priv->map_mode = vmw_dma_map_populate;
564#endif /* CONFIG_X86 */
565
d92d9851
TH		 566 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
567
568 return 0;
569}
570
0d00c488
TH		 571/**
572 * vmw_dma_masks - set required page- and dma masks
573 *
574 * @dev: Pointer to struct drm-device
575 *
576 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
577 * restriction also for 64-bit systems.
578 */
579#ifdef CONFIG_INTEL_IOMMU
580static int vmw_dma_masks(struct vmw_private *dev_priv)
581{
582 struct drm_device *dev = dev_priv->dev;
583
584 if (intel_iommu_enabled &&
585 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
586 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
587 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
588 }
589 return 0;
590}
591#else
592static int vmw_dma_masks(struct vmw_private *dev_priv)
593{
594 return 0;
595}
596#endif
597
fb1d9738
JB		 598static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
599{
600 struct vmw_private *dev_priv;
601 int ret;
c188660f 602 uint32_t svga_id;
c0951b79 603 enum vmw_res_type i;
d92d9851 604 bool refuse_dma = false;
fb1d9738
JB		 605
606 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
607 if (unlikely(dev_priv == NULL)) {
608 DRM_ERROR("Failed allocating a device private struct.\n");
609 return -ENOMEM;
610 }
fb1d9738 611
466e69b8
DA		 612 pci_set_master(dev->pdev);
613
fb1d9738
JB		 614 dev_priv->dev = dev;
615 dev_priv->vmw_chipset = chipset;
6bcd8d3c 616 dev_priv->last_read_seqno = (uint32_t) -100;
fb1d9738 617 mutex_init(&dev_priv->cmdbuf_mutex);
30c78bb8 618 mutex_init(&dev_priv->release_mutex);
173fb7d4 619 mutex_init(&dev_priv->binding_mutex);
fb1d9738 620 rwlock_init(&dev_priv->resource_lock);
294adf7d 621 ttm_lock_init(&dev_priv->reservation_sem);
496eb6fd
TH		 622 spin_lock_init(&dev_priv->hw_lock);
623 spin_lock_init(&dev_priv->waiter_lock);
624 spin_lock_init(&dev_priv->cap_lock);
153b3d5b 625 spin_lock_init(&dev_priv->svga_lock);
c0951b79
TH		 626
627 for (i = vmw_res_context; i < vmw_res_max; ++i) {
628 idr_init(&dev_priv->res_idr[i]);
629 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
630 }
631
fb1d9738
JB		 632 mutex_init(&dev_priv->init_mutex);
633 init_waitqueue_head(&dev_priv->fence_queue);
634 init_waitqueue_head(&dev_priv->fifo_queue);
4f73a96b 635 dev_priv->fence_queue_waiters = 0;
fb1d9738 636 atomic_set(&dev_priv->fifo_queue_waiters, 0);
c0951b79 637
5bb39e81 638 dev_priv->used_memory_size = 0;
fb1d9738
JB		 639
640 dev_priv->io_start = pci_resource_start(dev->pdev, 0);
641 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
642 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
643
30c78bb8
TH		 644 dev_priv->enable_fb = enable_fbdev;
645
c188660f
PH		 646 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
647 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
648 if (svga_id != SVGA_ID_2) {
649 ret = -ENOSYS;
49625904 650 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
c188660f
PH		 651 goto out_err0;
652 }
653
fb1d9738 654 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
d92d9851
TH		 655 ret = vmw_dma_select_mode(dev_priv);
656 if (unlikely(ret != 0)) {
657 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
658 refuse_dma = true;
659 }
fb1d9738 660
5bb39e81
TH		 661 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
662 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
663 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
664 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
eb4f923b
JB		 665
666 vmw_get_initial_size(dev_priv);
667
0d00c488 668 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
fb1d9738
JB		 669 dev_priv->max_gmr_ids =
670 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
fb17f189
TH		 671 dev_priv->max_gmr_pages =
672 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
673 dev_priv->memory_size =
674 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
5bb39e81
TH		 675 dev_priv->memory_size -= dev_priv->vram_size;
676 } else {
677 /*
678 * An arbitrary limit of 512MiB on surface
679 * memory. But all HWV8 hardware supports GMR2.
680 */
681 dev_priv->memory_size = 512*1024*1024;
fb17f189 682 }
6da768aa 683 dev_priv->max_mob_pages = 0;
857aea1c 684 dev_priv->max_mob_size = 0;
6da768aa
TH		 685 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
686 uint64_t mem_size =
687 vmw_read(dev_priv,
688 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
689
690 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
afb0e50f
TH		 691 dev_priv->prim_bb_mem =
692 vmw_read(dev_priv,
693 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
857aea1c
CL		 694 dev_priv->max_mob_size =
695 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
afb0e50f
TH		 696 } else
697 dev_priv->prim_bb_mem = dev_priv->vram_size;
fb1d9738 698
0d00c488 699 ret = vmw_dma_masks(dev_priv);
496eb6fd 700 if (unlikely(ret != 0))
0d00c488
TH		 701 goto out_err0;
702
9a72384d
SY		 703 /*
704 * Limit back buffer size to VRAM size. Remove this once
705 * screen targets are implemented.
706 */
707 if (dev_priv->prim_bb_mem > dev_priv->vram_size)
afb0e50f 708 dev_priv->prim_bb_mem = dev_priv->vram_size;
bc2d6508 709
fb1d9738
JB		 710 vmw_print_capabilities(dev_priv->capabilities);
711
0d00c488 712 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
fb1d9738
JB		 713 DRM_INFO("Max GMR ids is %u\n",
714 (unsigned)dev_priv->max_gmr_ids);
fb17f189
TH		 715 DRM_INFO("Max number of GMR pages is %u\n",
716 (unsigned)dev_priv->max_gmr_pages);
5bb39e81
TH		 717 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
718 (unsigned)dev_priv->memory_size / 1024);
fb17f189 719 }
bc2d6508
TH		 720 DRM_INFO("Maximum display memory size is %u kiB\n",
721 dev_priv->prim_bb_mem / 1024);
fb1d9738
JB		 722 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
723 dev_priv->vram_start, dev_priv->vram_size / 1024);
724 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
725 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
726
727 ret = vmw_ttm_global_init(dev_priv);
728 if (unlikely(ret != 0))
729 goto out_err0;
730
731
732 vmw_master_init(&dev_priv->fbdev_master);
733 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
734 dev_priv->active_master = &dev_priv->fbdev_master;
735
a2c06ee2 736
247d36d7
AL		 737 dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start,
738 dev_priv->mmio_size);
fb1d9738
JB		 739
740 dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
741 dev_priv->mmio_size);
742
743 if (unlikely(dev_priv->mmio_virt == NULL)) {
744 ret = -ENOMEM;
745 DRM_ERROR("Failed mapping MMIO.\n");
746 goto out_err3;
747 }
748
d7e1958d
JB		 749 /* Need mmio memory to check for fifo pitchlock cap. */
750 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
751 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
752 !vmw_fifo_have_pitchlock(dev_priv)) {
753 ret = -ENOSYS;
754 DRM_ERROR("Hardware has no pitchlock\n");
755 goto out_err4;
756 }
757
fb1d9738 758 dev_priv->tdev = ttm_object_device_init
69977ff5 759 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
fb1d9738
JB		 760
761 if (unlikely(dev_priv->tdev == NULL)) {
762 DRM_ERROR("Unable to initialize TTM object management.\n");
763 ret = -ENOMEM;
764 goto out_err4;
765 }
766
767 dev->dev_private = dev_priv;
768
fb1d9738
JB		 769 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
770 dev_priv->stealth = (ret != 0);
771 if (dev_priv->stealth) {
772 /**
773 * Request at least the mmio PCI resource.
774 */
775
776 DRM_INFO("It appears like vesafb is loaded. "
f2d12b8e 777 "Ignore above error if any.\n");
fb1d9738
JB		 778 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
779 if (unlikely(ret != 0)) {
780 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
781 goto out_no_device;
782 }
fb1d9738 783 }
ae2a1040 784
506ff75c 785 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
bb0f1b5c 786 ret = drm_irq_install(dev, dev->pdev->irq);
506ff75c
TH		 787 if (ret != 0) {
788 DRM_ERROR("Failed installing irq: %d\n", ret);
789 goto out_no_irq;
790 }
791 }
792
ae2a1040 793 dev_priv->fman = vmw_fence_manager_init(dev_priv);
14bbf20c
WY		 794 if (unlikely(dev_priv->fman == NULL)) {
795 ret = -ENOMEM;
ae2a1040 796 goto out_no_fman;
14bbf20c 797 }
56d1c78d 798
153b3d5b
TH		 799 ret = ttm_bo_device_init(&dev_priv->bdev,
800 dev_priv->bo_global_ref.ref.object,
801 &vmw_bo_driver,
802 dev->anon_inode->i_mapping,
803 VMWGFX_FILE_PAGE_OFFSET,
804 false);
805 if (unlikely(ret != 0)) {
806 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
807 goto out_no_bdev;
808 }
3458390b 809
153b3d5b
TH		 810 /*
811 * Enable VRAM, but initially don't use it until SVGA is enabled and
812 * unhidden.
813 */
3458390b
TH		 814 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
815 (dev_priv->vram_size >> PAGE_SHIFT));
816 if (unlikely(ret != 0)) {
817 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
818 goto out_no_vram;
819 }
153b3d5b 820 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
3458390b
TH		 821
822 dev_priv->has_gmr = true;
823 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
824 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
825 VMW_PL_GMR) != 0) {
826 DRM_INFO("No GMR memory available. "
827 "Graphics memory resources are very limited.\n");
828 dev_priv->has_gmr = false;
829 }
830
831 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
832 dev_priv->has_mob = true;
833 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
834 VMW_PL_MOB) != 0) {
835 DRM_INFO("No MOB memory available. "
836 "3D will be disabled.\n");
837 dev_priv->has_mob = false;
838 }
839 }
840
7a1c2f6c
TH		 841 ret = vmw_kms_init(dev_priv);
842 if (unlikely(ret != 0))
843 goto out_no_kms;
f2d12b8e 844 vmw_overlay_init(dev_priv);
56d1c78d 845
153b3d5b
TH		 846 ret = vmw_request_device(dev_priv);
847 if (ret)
848 goto out_no_fifo;
849
30c78bb8 850 if (dev_priv->enable_fb) {
153b3d5b
TH		 851 vmw_fifo_resource_inc(dev_priv);
852 vmw_svga_enable(dev_priv);
30c78bb8 853 vmw_fb_init(dev_priv);
7a1c2f6c
TH		 854 }
855
d9f36a00
TH		 856 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
857 register_pm_notifier(&dev_priv->pm_nb);
858
fb1d9738
JB		 859 return 0;
860
506ff75c 861out_no_fifo:
56d1c78d
JB		 862 vmw_overlay_close(dev_priv);
863 vmw_kms_close(dev_priv);
864out_no_kms:
3458390b
TH		 865 if (dev_priv->has_mob)
866 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
867 if (dev_priv->has_gmr)
868 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
869 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
870out_no_vram:
153b3d5b
TH		 871 (void)ttm_bo_device_release(&dev_priv->bdev);
872out_no_bdev:
ae2a1040
TH		 873 vmw_fence_manager_takedown(dev_priv->fman);
874out_no_fman:
506ff75c
TH		 875 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
876 drm_irq_uninstall(dev_priv->dev);
877out_no_irq:
30c78bb8
TH		 878 if (dev_priv->stealth)
879 pci_release_region(dev->pdev, 2);
880 else
881 pci_release_regions(dev->pdev);
fb1d9738 882out_no_device:
fb1d9738
JB		 883 ttm_object_device_release(&dev_priv->tdev);
884out_err4:
885 iounmap(dev_priv->mmio_virt);
886out_err3:
247d36d7 887 arch_phys_wc_del(dev_priv->mmio_mtrr);
fb1d9738
JB		 888 vmw_ttm_global_release(dev_priv);
889out_err0:
c0951b79
TH		 890 for (i = vmw_res_context; i < vmw_res_max; ++i)
891 idr_destroy(&dev_priv->res_idr[i]);
892
fb1d9738
JB		 893 kfree(dev_priv);
894 return ret;
895}
896
897static int vmw_driver_unload(struct drm_device *dev)
898{
899 struct vmw_private *dev_priv = vmw_priv(dev);
c0951b79 900 enum vmw_res_type i;
fb1d9738 901
d9f36a00
TH		 902 unregister_pm_notifier(&dev_priv->pm_nb);
903
c0951b79
TH		 904 if (dev_priv->ctx.res_ht_initialized)
905 drm_ht_remove(&dev_priv->ctx.res_ht);
a3a1a667 906 vfree(dev_priv->ctx.cmd_bounce);
30c78bb8
TH		 907 if (dev_priv->enable_fb) {
908 vmw_fb_close(dev_priv);
153b3d5b
TH		 909 vmw_fifo_resource_dec(dev_priv);
910 vmw_svga_disable(dev_priv);
30c78bb8 911 }
153b3d5b 912
f2d12b8e
TH		 913 vmw_kms_close(dev_priv);
914 vmw_overlay_close(dev_priv);
3458390b 915
3458390b
TH		 916 if (dev_priv->has_gmr)
917 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
918 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
919
153b3d5b
TH		 920 vmw_release_device_early(dev_priv);
921 if (dev_priv->has_mob)
922 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
923 (void) ttm_bo_device_release(&dev_priv->bdev);
924 vmw_release_device_late(dev_priv);
ae2a1040 925 vmw_fence_manager_takedown(dev_priv->fman);
506ff75c
TH		 926 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
927 drm_irq_uninstall(dev_priv->dev);
f2d12b8e 928 if (dev_priv->stealth)
fb1d9738 929 pci_release_region(dev->pdev, 2);
f2d12b8e
TH		 930 else
931 pci_release_regions(dev->pdev);
932
fb1d9738
JB		 933 ttm_object_device_release(&dev_priv->tdev);
934 iounmap(dev_priv->mmio_virt);
247d36d7 935 arch_phys_wc_del(dev_priv->mmio_mtrr);
fb1d9738
JB		 936 (void)ttm_bo_device_release(&dev_priv->bdev);
937 vmw_ttm_global_release(dev_priv);
c0951b79
TH		 938
939 for (i = vmw_res_context; i < vmw_res_max; ++i)
940 idr_destroy(&dev_priv->res_idr[i]);
fb1d9738
JB		 941
942 kfree(dev_priv);
943
944 return 0;
945}
946
6b82ef50
TH		 947static void vmw_preclose(struct drm_device *dev,
948 struct drm_file *file_priv)
949{
950 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
951 struct vmw_private *dev_priv = vmw_priv(dev);
952
953 vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
954}
955
fb1d9738
JB		 956static void vmw_postclose(struct drm_device *dev,
957 struct drm_file *file_priv)
958{
959 struct vmw_fpriv *vmw_fp;
960
961 vmw_fp = vmw_fpriv(file_priv);
c4249855
TH		 962
963 if (vmw_fp->locked_master) {
964 struct vmw_master *vmaster =
965 vmw_master(vmw_fp->locked_master);
966
967 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
968 ttm_vt_unlock(&vmaster->lock);
fb1d9738 969 drm_master_put(&vmw_fp->locked_master);
c4249855
TH		 970 }
971
972 ttm_object_file_release(&vmw_fp->tfile);
fb1d9738
JB		 973 kfree(vmw_fp);
974}
975
976static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
977{
978 struct vmw_private *dev_priv = vmw_priv(dev);
979 struct vmw_fpriv *vmw_fp;
980 int ret = -ENOMEM;
981
982 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
983 if (unlikely(vmw_fp == NULL))
984 return ret;
985
6b82ef50 986 INIT_LIST_HEAD(&vmw_fp->fence_events);
fb1d9738
JB		 987 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
988 if (unlikely(vmw_fp->tfile == NULL))
989 goto out_no_tfile;
990
991 file_priv->driver_priv = vmw_fp;
fb1d9738
JB		 992
993 return 0;
994
995out_no_tfile:
996 kfree(vmw_fp);
997 return ret;
998}
999
64190bde
TH		 1000static struct vmw_master *vmw_master_check(struct drm_device *dev,
1001 struct drm_file *file_priv,
1002 unsigned int flags)
1003{
1004 int ret;
1005 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1006 struct vmw_master *vmaster;
1007
1008 if (file_priv->minor->type != DRM_MINOR_LEGACY ||
1009 !(flags & DRM_AUTH))
1010 return NULL;
1011
1012 ret = mutex_lock_interruptible(&dev->master_mutex);
1013 if (unlikely(ret != 0))
1014 return ERR_PTR(-ERESTARTSYS);
1015
7963e9db 1016 if (file_priv->is_master) {
64190bde
TH		 1017 mutex_unlock(&dev->master_mutex);
1018 return NULL;
1019 }
1020
1021 /*
1022 * Check if we were previously master, but now dropped.
1023 */
1024 if (vmw_fp->locked_master) {
1025 mutex_unlock(&dev->master_mutex);
1026 DRM_ERROR("Dropped master trying to access ioctl that "
1027 "requires authentication.\n");
1028 return ERR_PTR(-EACCES);
1029 }
1030 mutex_unlock(&dev->master_mutex);
1031
1032 /*
1033 * Taking the drm_global_mutex after the TTM lock might deadlock
1034 */
1035 if (!(flags & DRM_UNLOCKED)) {
1036 DRM_ERROR("Refusing locked ioctl access.\n");
1037 return ERR_PTR(-EDEADLK);
1038 }
1039
1040 /*
1041 * Take the TTM lock. Possibly sleep waiting for the authenticating
1042 * master to become master again, or for a SIGTERM if the
1043 * authenticating master exits.
1044 */
1045 vmaster = vmw_master(file_priv->master);
1046 ret = ttm_read_lock(&vmaster->lock, true);
1047 if (unlikely(ret != 0))
1048 vmaster = ERR_PTR(ret);
1049
1050 return vmaster;
1051}
1052
1053static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1054 unsigned long arg,
1055 long (*ioctl_func)(struct file *, unsigned int,
1056 unsigned long))
fb1d9738
JB		 1057{
1058 struct drm_file *file_priv = filp->private_data;
1059 struct drm_device *dev = file_priv->minor->dev;
1060 unsigned int nr = DRM_IOCTL_NR(cmd);
64190bde
TH		 1061 struct vmw_master *vmaster;
1062 unsigned int flags;
1063 long ret;
fb1d9738
JB		 1064
1065 /*
e1f78003 1066 * Do extra checking on driver private ioctls.
fb1d9738
JB		 1067 */
1068
1069 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1070 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
baa70943 1071 const struct drm_ioctl_desc *ioctl =
64190bde 1072 &vmw_ioctls[nr - DRM_COMMAND_BASE];
fb1d9738 1073
7e7392a6 1074 if (unlikely(ioctl->cmd != cmd)) {
fb1d9738
JB		 1075 DRM_ERROR("Invalid command format, ioctl %d\n",
1076 nr - DRM_COMMAND_BASE);
1077 return -EINVAL;
1078 }
64190bde
TH		 1079 flags = ioctl->flags;
1080 } else if (!drm_ioctl_flags(nr, &flags))
1081 return -EINVAL;
1082
1083 vmaster = vmw_master_check(dev, file_priv, flags);
1084 if (unlikely(IS_ERR(vmaster))) {
e338c4c2
TH		 1085 ret = PTR_ERR(vmaster);
1086
1087 if (ret != -ERESTARTSYS)
1088 DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n",
1089 nr, ret);
1090 return ret;
fb1d9738
JB		 1091 }
1092
64190bde
TH		 1093 ret = ioctl_func(filp, cmd, arg);
1094 if (vmaster)
1095 ttm_read_unlock(&vmaster->lock);
1096
1097 return ret;
1098}
1099
1100static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1101 unsigned long arg)
1102{
1103 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
fb1d9738
JB		 1104}
1105
64190bde
TH		 1106#ifdef CONFIG_COMPAT
1107static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1108 unsigned long arg)
1109{
1110 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1111}
1112#endif
1113
fb1d9738
JB		 1114static void vmw_lastclose(struct drm_device *dev)
1115{
fb1d9738
JB		 1116 struct drm_crtc *crtc;
1117 struct drm_mode_set set;
1118 int ret;
1119
fb1d9738
JB		 1120 set.x = 0;
1121 set.y = 0;
1122 set.fb = NULL;
1123 set.mode = NULL;
1124 set.connectors = NULL;
1125 set.num_connectors = 0;
1126
1127 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1128 set.crtc = crtc;
2d13b679 1129 ret = drm_mode_set_config_internal(&set);
fb1d9738
JB		 1130 WARN_ON(ret != 0);
1131 }
1132
1133}
1134
1135static void vmw_master_init(struct vmw_master *vmaster)
1136{
1137 ttm_lock_init(&vmaster->lock);
3a939a5e
TH		 1138 INIT_LIST_HEAD(&vmaster->fb_surf);
1139 mutex_init(&vmaster->fb_surf_mutex);
fb1d9738
JB		 1140}
1141
1142static int vmw_master_create(struct drm_device *dev,
1143 struct drm_master *master)
1144{
1145 struct vmw_master *vmaster;
1146
fb1d9738
JB		 1147 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1148 if (unlikely(vmaster == NULL))
1149 return -ENOMEM;
1150
3a939a5e 1151 vmw_master_init(vmaster);
fb1d9738
JB		 1152 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1153 master->driver_priv = vmaster;
1154
1155 return 0;
1156}
1157
1158static void vmw_master_destroy(struct drm_device *dev,
1159 struct drm_master *master)
1160{
1161 struct vmw_master *vmaster = vmw_master(master);
1162
fb1d9738
JB		 1163 master->driver_priv = NULL;
1164 kfree(vmaster);
1165}
1166
1167
1168static int vmw_master_set(struct drm_device *dev,
1169 struct drm_file *file_priv,
1170 bool from_open)
1171{
1172 struct vmw_private *dev_priv = vmw_priv(dev);
1173 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1174 struct vmw_master *active = dev_priv->active_master;
1175 struct vmw_master *vmaster = vmw_master(file_priv->master);
1176 int ret = 0;
1177
fb1d9738
JB		 1178 if (active) {
1179 BUG_ON(active != &dev_priv->fbdev_master);
1180 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1181 if (unlikely(ret != 0))
153b3d5b 1182 return ret;
fb1d9738
JB		 1183
1184 ttm_lock_set_kill(&active->lock, true, SIGTERM);
fb1d9738
JB		 1185 dev_priv->active_master = NULL;
1186 }
1187
1188 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1189 if (!from_open) {
1190 ttm_vt_unlock(&vmaster->lock);
1191 BUG_ON(vmw_fp->locked_master != file_priv->master);
1192 drm_master_put(&vmw_fp->locked_master);
1193 }
1194
1195 dev_priv->active_master = vmaster;
1196
1197 return 0;
fb1d9738
JB		 1198}
1199
1200static void vmw_master_drop(struct drm_device *dev,
1201 struct drm_file *file_priv,
1202 bool from_release)
1203{
1204 struct vmw_private *dev_priv = vmw_priv(dev);
1205 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1206 struct vmw_master *vmaster = vmw_master(file_priv->master);
1207 int ret;
1208
fb1d9738
JB		 1209 /**
1210 * Make sure the master doesn't disappear while we have
1211 * it locked.
1212 */
1213
1214 vmw_fp->locked_master = drm_master_get(file_priv->master);
1215 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
fb1d9738
JB		 1216 if (unlikely((ret != 0))) {
1217 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1218 drm_master_put(&vmw_fp->locked_master);
1219 }
1220
c4249855 1221 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
fb1d9738 1222
153b3d5b
TH		 1223 if (!dev_priv->enable_fb)
1224 vmw_svga_disable(dev_priv);
30c78bb8 1225
fb1d9738
JB		 1226 dev_priv->active_master = &dev_priv->fbdev_master;
1227 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1228 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1229
30c78bb8
TH		 1230 if (dev_priv->enable_fb)
1231 vmw_fb_on(dev_priv);
fb1d9738
JB		 1232}
1233
153b3d5b
TH		 1234/**
1235 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1236 *
1237 * @dev_priv: Pointer to device private struct.
1238 * Needs the reservation sem to be held in non-exclusive mode.
1239 */
1240void __vmw_svga_enable(struct vmw_private *dev_priv)
1241{
1242 spin_lock(&dev_priv->svga_lock);
1243 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1244 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE);
1245 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true;
1246 }
1247 spin_unlock(&dev_priv->svga_lock);
1248}
1249
1250/**
1251 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1252 *
1253 * @dev_priv: Pointer to device private struct.
1254 */
1255void vmw_svga_enable(struct vmw_private *dev_priv)
1256{
1257 ttm_read_lock(&dev_priv->reservation_sem, false);
1258 __vmw_svga_enable(dev_priv);
1259 ttm_read_unlock(&dev_priv->reservation_sem);
1260}
1261
1262/**
1263 * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
1264 *
1265 * @dev_priv: Pointer to device private struct.
1266 * Needs the reservation sem to be held in exclusive mode.
1267 * Will not empty VRAM. VRAM must be emptied by caller.
1268 */
1269void __vmw_svga_disable(struct vmw_private *dev_priv)
1270{
1271 spin_lock(&dev_priv->svga_lock);
1272 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1273 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1274 vmw_write(dev_priv, SVGA_REG_ENABLE,
1275 SVGA_REG_ENABLE_ENABLE_HIDE);
1276 }
1277 spin_unlock(&dev_priv->svga_lock);
1278}
1279
1280/**
1281 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
1282 * running.
1283 *
1284 * @dev_priv: Pointer to device private struct.
1285 * Will empty VRAM.
1286 */
1287void vmw_svga_disable(struct vmw_private *dev_priv)
1288{
1289 ttm_write_lock(&dev_priv->reservation_sem, false);
1290 spin_lock(&dev_priv->svga_lock);
1291 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1292 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1293 vmw_write(dev_priv, SVGA_REG_ENABLE,
1294 SVGA_REG_ENABLE_ENABLE_HIDE);
1295 spin_unlock(&dev_priv->svga_lock);
1296 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM))
1297 DRM_ERROR("Failed evicting VRAM buffers.\n");
1298 } else
1299 spin_unlock(&dev_priv->svga_lock);
1300 ttm_write_unlock(&dev_priv->reservation_sem);
1301}
fb1d9738
JB		 1302
1303static void vmw_remove(struct pci_dev *pdev)
1304{
1305 struct drm_device *dev = pci_get_drvdata(pdev);
1306
fd3e4d6e 1307 pci_disable_device(pdev);
fb1d9738
JB		 1308 drm_put_dev(dev);
1309}
1310
d9f36a00
TH		 1311static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1312 void *ptr)
1313{
1314 struct vmw_private *dev_priv =
1315 container_of(nb, struct vmw_private, pm_nb);
d9f36a00
TH		 1316
1317 switch (val) {
1318 case PM_HIBERNATION_PREPARE:
294adf7d 1319 ttm_suspend_lock(&dev_priv->reservation_sem);
d9f36a00 1320
153b3d5b 1321 /*
d9f36a00
TH		 1322 * This empties VRAM and unbinds all GMR bindings.
1323 * Buffer contents is moved to swappable memory.
1324 */
c0951b79
TH		 1325 vmw_execbuf_release_pinned_bo(dev_priv);
1326 vmw_resource_evict_all(dev_priv);
153b3d5b 1327 vmw_release_device_early(dev_priv);
d9f36a00 1328 ttm_bo_swapout_all(&dev_priv->bdev);
153b3d5b 1329 vmw_fence_fifo_down(dev_priv->fman);
d9f36a00
TH		 1330 break;
1331 case PM_POST_HIBERNATION:
094e0fa8 1332 case PM_POST_RESTORE:
153b3d5b 1333 vmw_fence_fifo_up(dev_priv->fman);
294adf7d 1334 ttm_suspend_unlock(&dev_priv->reservation_sem);
094e0fa8 1335
d9f36a00
TH		 1336 break;
1337 case PM_RESTORE_PREPARE:
1338 break;
d9f36a00
TH		 1339 default:
1340 break;
1341 }
1342 return 0;
1343}
1344
7fbd721a 1345static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
d9f36a00 1346{
094e0fa8
TH		 1347 struct drm_device *dev = pci_get_drvdata(pdev);
1348 struct vmw_private *dev_priv = vmw_priv(dev);
1349
153b3d5b 1350 if (dev_priv->refuse_hibernation)
094e0fa8 1351 return -EBUSY;
094e0fa8 1352
d9f36a00
TH		 1353 pci_save_state(pdev);
1354 pci_disable_device(pdev);
1355 pci_set_power_state(pdev, PCI_D3hot);
1356 return 0;
1357}
1358
7fbd721a 1359static int vmw_pci_resume(struct pci_dev *pdev)
d9f36a00
TH		 1360{
1361 pci_set_power_state(pdev, PCI_D0);
1362 pci_restore_state(pdev);
1363 return pci_enable_device(pdev);
1364}
1365
7fbd721a
TH		 1366static int vmw_pm_suspend(struct device *kdev)
1367{
1368 struct pci_dev *pdev = to_pci_dev(kdev);
1369 struct pm_message dummy;
1370
1371 dummy.event = 0;
1372
1373 return vmw_pci_suspend(pdev, dummy);
1374}
1375
1376static int vmw_pm_resume(struct device *kdev)
1377{
1378 struct pci_dev *pdev = to_pci_dev(kdev);
1379
1380 return vmw_pci_resume(pdev);
1381}
1382
153b3d5b 1383static int vmw_pm_freeze(struct device *kdev)
7fbd721a
TH		 1384{
1385 struct pci_dev *pdev = to_pci_dev(kdev);
1386 struct drm_device *dev = pci_get_drvdata(pdev);
1387 struct vmw_private *dev_priv = vmw_priv(dev);
1388
7fbd721a
TH		 1389 dev_priv->suspended = true;
1390 if (dev_priv->enable_fb)
153b3d5b 1391 vmw_fifo_resource_dec(dev_priv);
7fbd721a 1392
153b3d5b
TH		 1393 if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
1394 DRM_ERROR("Can't hibernate while 3D resources are active.\n");
7fbd721a 1395 if (dev_priv->enable_fb)
153b3d5b
TH		 1396 vmw_fifo_resource_inc(dev_priv);
1397 WARN_ON(vmw_request_device_late(dev_priv));
7fbd721a
TH		 1398 dev_priv->suspended = false;
1399 return -EBUSY;
1400 }
1401
153b3d5b
TH		 1402 if (dev_priv->enable_fb)
1403 __vmw_svga_disable(dev_priv);
1404
1405 vmw_release_device_late(dev_priv);
1406
7fbd721a
TH		 1407 return 0;
1408}
1409
153b3d5b 1410static int vmw_pm_restore(struct device *kdev)
7fbd721a
TH		 1411{
1412 struct pci_dev *pdev = to_pci_dev(kdev);
1413 struct drm_device *dev = pci_get_drvdata(pdev);
1414 struct vmw_private *dev_priv = vmw_priv(dev);
153b3d5b 1415 int ret;
7fbd721a 1416
95e8f6a2
TH		 1417 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1418 (void) vmw_read(dev_priv, SVGA_REG_ID);
95e8f6a2 1419
7fbd721a 1420 if (dev_priv->enable_fb)
153b3d5b
TH		 1421 vmw_fifo_resource_inc(dev_priv);
1422
1423 ret = vmw_request_device(dev_priv);
1424 if (ret)
1425 return ret;
1426
1427 if (dev_priv->enable_fb)
1428 __vmw_svga_enable(dev_priv);
7fbd721a
TH		 1429
1430 dev_priv->suspended = false;
153b3d5b
TH		 1431
1432 return 0;
7fbd721a
TH		 1433}
1434
1435static const struct dev_pm_ops vmw_pm_ops = {
153b3d5b
TH		 1436 .freeze = vmw_pm_freeze,
1437 .thaw = vmw_pm_restore,
1438 .restore = vmw_pm_restore,
7fbd721a
TH		 1439 .suspend = vmw_pm_suspend,
1440 .resume = vmw_pm_resume,
1441};
1442
e08e96de
AV		 1443static const struct file_operations vmwgfx_driver_fops = {
1444 .owner = THIS_MODULE,
1445 .open = drm_open,
1446 .release = drm_release,
1447 .unlocked_ioctl = vmw_unlocked_ioctl,
1448 .mmap = vmw_mmap,
1449 .poll = vmw_fops_poll,
1450 .read = vmw_fops_read,
e08e96de 1451#if defined(CONFIG_COMPAT)
64190bde 1452 .compat_ioctl = vmw_compat_ioctl,
e08e96de
AV		 1453#endif
1454 .llseek = noop_llseek,
1455};
1456
fb1d9738
JB		 1457static struct drm_driver driver = {
1458 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
03f80263 1459 DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER,
fb1d9738
JB		 1460 .load = vmw_driver_load,
1461 .unload = vmw_driver_unload,
fb1d9738
JB		 1462 .lastclose = vmw_lastclose,
1463 .irq_preinstall = vmw_irq_preinstall,
1464 .irq_postinstall = vmw_irq_postinstall,
1465 .irq_uninstall = vmw_irq_uninstall,
1466 .irq_handler = vmw_irq_handler,
7a1c2f6c 1467 .get_vblank_counter = vmw_get_vblank_counter,
1c482ab3
JB		 1468 .enable_vblank = vmw_enable_vblank,
1469 .disable_vblank = vmw_disable_vblank,
fb1d9738 1470 .ioctls = vmw_ioctls,
f95aeb17 1471 .num_ioctls = ARRAY_SIZE(vmw_ioctls),
fb1d9738
JB		 1472 .master_create = vmw_master_create,
1473 .master_destroy = vmw_master_destroy,
1474 .master_set = vmw_master_set,
1475 .master_drop = vmw_master_drop,
1476 .open = vmw_driver_open,
6b82ef50 1477 .preclose = vmw_preclose,
fb1d9738 1478 .postclose = vmw_postclose,
915b4d11 1479 .set_busid = drm_pci_set_busid,
5e1782d2
DA		 1480
1481 .dumb_create = vmw_dumb_create,
1482 .dumb_map_offset = vmw_dumb_map_offset,
1483 .dumb_destroy = vmw_dumb_destroy,
1484
69977ff5
TH		 1485 .prime_fd_to_handle = vmw_prime_fd_to_handle,
1486 .prime_handle_to_fd = vmw_prime_handle_to_fd,
1487
e08e96de 1488 .fops = &vmwgfx_driver_fops,
fb1d9738
JB		 1489 .name = VMWGFX_DRIVER_NAME,
1490 .desc = VMWGFX_DRIVER_DESC,
1491 .date = VMWGFX_DRIVER_DATE,
1492 .major = VMWGFX_DRIVER_MAJOR,
1493 .minor = VMWGFX_DRIVER_MINOR,
1494 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1495};
1496
8410ea3b
DA		 1497static struct pci_driver vmw_pci_driver = {
1498 .name = VMWGFX_DRIVER_NAME,
1499 .id_table = vmw_pci_id_list,
1500 .probe = vmw_probe,
1501 .remove = vmw_remove,
1502 .driver = {
1503 .pm = &vmw_pm_ops
1504 }
1505};
1506
fb1d9738
JB		 1507static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1508{
dcdb1674 1509 return drm_get_pci_dev(pdev, ent, &driver);
fb1d9738
JB		 1510}
1511
1512static int __init vmwgfx_init(void)
1513{
1514 int ret;
8410ea3b 1515 ret = drm_pci_init(&driver, &vmw_pci_driver);
fb1d9738
JB		 1516 if (ret)
1517 DRM_ERROR("Failed initializing DRM.\n");
1518 return ret;
1519}
1520
1521static void __exit vmwgfx_exit(void)
1522{
8410ea3b 1523 drm_pci_exit(&driver, &vmw_pci_driver);
fb1d9738
JB		 1524}
1525
1526module_init(vmwgfx_init);
1527module_exit(vmwgfx_exit);
1528
1529MODULE_AUTHOR("VMware Inc. and others");
1530MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1531MODULE_LICENSE("GPL and additional rights");
73558ead
TH		 1532MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1533 __stringify(VMWGFX_DRIVER_MINOR) "."
1534 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1535 "0");
Linux kernel - Deliverables
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