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vmwgfx: Fix up query processing
[deliverable/linux.git] / drivers / gpu / drm / vmwgfx / vmwgfx_drv.c
CommitLineData
fb1d9738
JB		 1/**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#include "drmP.h"
29#include "vmwgfx_drv.h"
30#include "ttm/ttm_placement.h"
31#include "ttm/ttm_bo_driver.h"
32#include "ttm/ttm_object.h"
33#include "ttm/ttm_module.h"
34
35#define VMWGFX_DRIVER_NAME "vmwgfx"
36#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
37#define VMWGFX_CHIP_SVGAII 0
38#define VMW_FB_RESERVATION 0
39
40/**
41 * Fully encoded drm commands. Might move to vmw_drm.h
42 */
43
44#define DRM_IOCTL_VMW_GET_PARAM \
45 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
46 struct drm_vmw_getparam_arg)
47#define DRM_IOCTL_VMW_ALLOC_DMABUF \
48 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
49 union drm_vmw_alloc_dmabuf_arg)
50#define DRM_IOCTL_VMW_UNREF_DMABUF \
51 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
52 struct drm_vmw_unref_dmabuf_arg)
53#define DRM_IOCTL_VMW_CURSOR_BYPASS \
54 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
55 struct drm_vmw_cursor_bypass_arg)
56
57#define DRM_IOCTL_VMW_CONTROL_STREAM \
58 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
59 struct drm_vmw_control_stream_arg)
60#define DRM_IOCTL_VMW_CLAIM_STREAM \
61 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
62 struct drm_vmw_stream_arg)
63#define DRM_IOCTL_VMW_UNREF_STREAM \
64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
65 struct drm_vmw_stream_arg)
66
67#define DRM_IOCTL_VMW_CREATE_CONTEXT \
68 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
69 struct drm_vmw_context_arg)
70#define DRM_IOCTL_VMW_UNREF_CONTEXT \
71 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
72 struct drm_vmw_context_arg)
73#define DRM_IOCTL_VMW_CREATE_SURFACE \
74 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
75 union drm_vmw_surface_create_arg)
76#define DRM_IOCTL_VMW_UNREF_SURFACE \
77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
78 struct drm_vmw_surface_arg)
79#define DRM_IOCTL_VMW_REF_SURFACE \
80 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
81 union drm_vmw_surface_reference_arg)
82#define DRM_IOCTL_VMW_EXECBUF \
83 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
84 struct drm_vmw_execbuf_arg)
ae2a1040
TH		 85#define DRM_IOCTL_VMW_GET_3D_CAP \
86 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
87 struct drm_vmw_get_3d_cap_arg)
fb1d9738
JB		 88#define DRM_IOCTL_VMW_FENCE_WAIT \
89 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
90 struct drm_vmw_fence_wait_arg)
ae2a1040
TH		 91#define DRM_IOCTL_VMW_FENCE_SIGNALED \
92 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
93 struct drm_vmw_fence_signaled_arg)
94#define DRM_IOCTL_VMW_FENCE_UNREF \
95 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
96 struct drm_vmw_fence_arg)
2fcd5a73
JB		 97#define DRM_IOCTL_VMW_PRESENT \
98 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
99 struct drm_vmw_present_arg)
100#define DRM_IOCTL_VMW_PRESENT_READBACK \
101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
102 struct drm_vmw_present_readback_arg)
fb1d9738
JB		 103
104/**
105 * The core DRM version of this macro doesn't account for
106 * DRM_COMMAND_BASE.
107 */
108
109#define VMW_IOCTL_DEF(ioctl, func, flags) \
1b2f1489 110 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
fb1d9738
JB		 111
112/**
113 * Ioctl definitions.
114 */
115
116static struct drm_ioctl_desc vmw_ioctls[] = {
1b2f1489 117 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
e1f78003 118 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 119 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
e1f78003 120 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 121 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
e1f78003 122 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 123 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
e1f78003
TH		 124 vmw_kms_cursor_bypass_ioctl,
125 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
fb1d9738 126
1b2f1489 127 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
e1f78003 128 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
1b2f1489 129 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
e1f78003 130 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
1b2f1489 131 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
e1f78003 132 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
fb1d9738 133
1b2f1489 134 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
e1f78003 135 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 136 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
e1f78003 137 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 138 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
e1f78003 139 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 140 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
e1f78003 141 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 142 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
e1f78003 143 DRM_AUTH | DRM_UNLOCKED),
1b2f1489 144 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
e1f78003 145 DRM_AUTH | DRM_UNLOCKED),
ae2a1040
TH		 146 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
147 DRM_AUTH | DRM_UNLOCKED),
148 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
149 vmw_fence_obj_signaled_ioctl,
150 DRM_AUTH | DRM_UNLOCKED),
151 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
d8bd19d2 152 DRM_AUTH | DRM_UNLOCKED),
f63f6a59
TH		 153 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
154 DRM_AUTH | DRM_UNLOCKED),
2fcd5a73
JB		 155
156 /* these allow direct access to the framebuffers mark as master only */
157 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
158 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
159 VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
160 vmw_present_readback_ioctl,
161 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
fb1d9738
JB		 162};
163
164static struct pci_device_id vmw_pci_id_list[] = {
165 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
166 {0, 0, 0}
167};
168
30c78bb8 169static int enable_fbdev;
fb1d9738
JB		 170
171static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
172static void vmw_master_init(struct vmw_master *);
d9f36a00
TH		 173static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
174 void *ptr);
fb1d9738 175
30c78bb8
TH		 176MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
177module_param_named(enable_fbdev, enable_fbdev, int, 0600);
178
fb1d9738
JB		 179static void vmw_print_capabilities(uint32_t capabilities)
180{
181 DRM_INFO("Capabilities:\n");
182 if (capabilities & SVGA_CAP_RECT_COPY)
183 DRM_INFO(" Rect copy.\n");
184 if (capabilities & SVGA_CAP_CURSOR)
185 DRM_INFO(" Cursor.\n");
186 if (capabilities & SVGA_CAP_CURSOR_BYPASS)
187 DRM_INFO(" Cursor bypass.\n");
188 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
189 DRM_INFO(" Cursor bypass 2.\n");
190 if (capabilities & SVGA_CAP_8BIT_EMULATION)
191 DRM_INFO(" 8bit emulation.\n");
192 if (capabilities & SVGA_CAP_ALPHA_CURSOR)
193 DRM_INFO(" Alpha cursor.\n");
194 if (capabilities & SVGA_CAP_3D)
195 DRM_INFO(" 3D.\n");
196 if (capabilities & SVGA_CAP_EXTENDED_FIFO)
197 DRM_INFO(" Extended Fifo.\n");
198 if (capabilities & SVGA_CAP_MULTIMON)
199 DRM_INFO(" Multimon.\n");
200 if (capabilities & SVGA_CAP_PITCHLOCK)
201 DRM_INFO(" Pitchlock.\n");
202 if (capabilities & SVGA_CAP_IRQMASK)
203 DRM_INFO(" Irq mask.\n");
204 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
205 DRM_INFO(" Display Topology.\n");
206 if (capabilities & SVGA_CAP_GMR)
207 DRM_INFO(" GMR.\n");
208 if (capabilities & SVGA_CAP_TRACES)
209 DRM_INFO(" Traces.\n");
dcca2862
TH		 210 if (capabilities & SVGA_CAP_GMR2)
211 DRM_INFO(" GMR2.\n");
212 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
213 DRM_INFO(" Screen Object 2.\n");
fb1d9738
JB		 214}
215
e2fa3a76
TH		 216
217/**
218 * vmw_execbuf_prepare_dummy_query - Initialize a query result structure at
219 * the start of a buffer object.
220 *
221 * @dev_priv: The device private structure.
222 *
223 * This function will idle the buffer using an uninterruptible wait, then
224 * map the first page and initialize a pending occlusion query result structure,
225 * Finally it will unmap the buffer.
226 *
227 * TODO: Since we're only mapping a single page, we should optimize the map
228 * to use kmap_atomic / iomap_atomic.
229 */
230static void vmw_dummy_query_bo_prepare(struct vmw_private *dev_priv)
231{
232 struct ttm_bo_kmap_obj map;
233 volatile SVGA3dQueryResult *result;
234 bool dummy;
235 int ret;
236 struct ttm_bo_device *bdev = &dev_priv->bdev;
237 struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
238
239 ttm_bo_reserve(bo, false, false, false, 0);
240 spin_lock(&bdev->fence_lock);
241 ret = ttm_bo_wait(bo, false, false, false, TTM_USAGE_READWRITE);
242 spin_unlock(&bdev->fence_lock);
243 if (unlikely(ret != 0))
244 (void) vmw_fallback_wait(dev_priv, false, true, 0, false,
245 10*HZ);
246
247 ret = ttm_bo_kmap(bo, 0, 1, &map);
248 if (likely(ret == 0)) {
249 result = ttm_kmap_obj_virtual(&map, &dummy);
250 result->totalSize = sizeof(*result);
251 result->state = SVGA3D_QUERYSTATE_PENDING;
252 result->result32 = 0xff;
253 ttm_bo_kunmap(&map);
254 } else
255 DRM_ERROR("Dummy query buffer map failed.\n");
256 ttm_bo_unreserve(bo);
257}
258
259
260/**
261 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
262 *
263 * @dev_priv: A device private structure.
264 *
265 * This function creates a small buffer object that holds the query
266 * result for dummy queries emitted as query barriers.
267 * No interruptible waits are done within this function.
268 *
269 * Returns an error if bo creation fails.
270 */
271static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
272{
273 return ttm_bo_create(&dev_priv->bdev,
274 PAGE_SIZE,
275 ttm_bo_type_device,
276 &vmw_vram_sys_placement,
277 0, 0, false, NULL,
278 &dev_priv->dummy_query_bo);
279}
280
281
fb1d9738
JB		 282static int vmw_request_device(struct vmw_private *dev_priv)
283{
284 int ret;
285
fb1d9738
JB		 286 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
287 if (unlikely(ret != 0)) {
288 DRM_ERROR("Unable to initialize FIFO.\n");
289 return ret;
290 }
ae2a1040 291 vmw_fence_fifo_up(dev_priv->fman);
e2fa3a76
TH		 292 ret = vmw_dummy_query_bo_create(dev_priv);
293 if (unlikely(ret != 0))
294 goto out_no_query_bo;
295 vmw_dummy_query_bo_prepare(dev_priv);
fb1d9738
JB		 296
297 return 0;
e2fa3a76
TH		 298
299out_no_query_bo:
300 vmw_fence_fifo_down(dev_priv->fman);
301 vmw_fifo_release(dev_priv, &dev_priv->fifo);
302 return ret;
fb1d9738
JB		 303}
304
305static void vmw_release_device(struct vmw_private *dev_priv)
306{
e2fa3a76
TH		 307 /*
308 * Previous destructions should've released
309 * the pinned bo.
310 */
311
312 BUG_ON(dev_priv->pinned_bo != NULL);
313
314 ttm_bo_unref(&dev_priv->dummy_query_bo);
ae2a1040 315 vmw_fence_fifo_down(dev_priv->fman);
fb1d9738 316 vmw_fifo_release(dev_priv, &dev_priv->fifo);
30c78bb8
TH		 317}
318
05730b32
TH		 319/**
320 * Increase the 3d resource refcount.
321 * If the count was prevously zero, initialize the fifo, switching to svga
322 * mode. Note that the master holds a ref as well, and may request an
323 * explicit switch to svga mode if fb is not running, using @unhide_svga.
324 */
325int vmw_3d_resource_inc(struct vmw_private *dev_priv,
326 bool unhide_svga)
30c78bb8
TH		 327{
328 int ret = 0;
329
330 mutex_lock(&dev_priv->release_mutex);
331 if (unlikely(dev_priv->num_3d_resources++ == 0)) {
332 ret = vmw_request_device(dev_priv);
333 if (unlikely(ret != 0))
334 --dev_priv->num_3d_resources;
05730b32
TH		 335 } else if (unhide_svga) {
336 mutex_lock(&dev_priv->hw_mutex);
337 vmw_write(dev_priv, SVGA_REG_ENABLE,
338 vmw_read(dev_priv, SVGA_REG_ENABLE) &
339 ~SVGA_REG_ENABLE_HIDE);
340 mutex_unlock(&dev_priv->hw_mutex);
30c78bb8 341 }
05730b32 342
30c78bb8
TH		 343 mutex_unlock(&dev_priv->release_mutex);
344 return ret;
fb1d9738
JB		 345}
346
05730b32
TH		 347/**
348 * Decrease the 3d resource refcount.
349 * If the count reaches zero, disable the fifo, switching to vga mode.
350 * Note that the master holds a refcount as well, and may request an
351 * explicit switch to vga mode when it releases its refcount to account
352 * for the situation of an X server vt switch to VGA with 3d resources
353 * active.
354 */
355void vmw_3d_resource_dec(struct vmw_private *dev_priv,
356 bool hide_svga)
30c78bb8
TH		 357{
358 int32_t n3d;
359
360 mutex_lock(&dev_priv->release_mutex);
361 if (unlikely(--dev_priv->num_3d_resources == 0))
362 vmw_release_device(dev_priv);
05730b32
TH		 363 else if (hide_svga) {
364 mutex_lock(&dev_priv->hw_mutex);
365 vmw_write(dev_priv, SVGA_REG_ENABLE,
366 vmw_read(dev_priv, SVGA_REG_ENABLE) |
367 SVGA_REG_ENABLE_HIDE);
368 mutex_unlock(&dev_priv->hw_mutex);
369 }
370
30c78bb8
TH		 371 n3d = (int32_t) dev_priv->num_3d_resources;
372 mutex_unlock(&dev_priv->release_mutex);
373
374 BUG_ON(n3d < 0);
375}
376
fb1d9738
JB		 377static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
378{
379 struct vmw_private *dev_priv;
380 int ret;
c188660f 381 uint32_t svga_id;
fb1d9738
JB		 382
383 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
384 if (unlikely(dev_priv == NULL)) {
385 DRM_ERROR("Failed allocating a device private struct.\n");
386 return -ENOMEM;
387 }
388 memset(dev_priv, 0, sizeof(*dev_priv));
389
390 dev_priv->dev = dev;
391 dev_priv->vmw_chipset = chipset;
6bcd8d3c 392 dev_priv->last_read_seqno = (uint32_t) -100;
fb1d9738
JB		 393 mutex_init(&dev_priv->hw_mutex);
394 mutex_init(&dev_priv->cmdbuf_mutex);
30c78bb8 395 mutex_init(&dev_priv->release_mutex);
fb1d9738
JB		 396 rwlock_init(&dev_priv->resource_lock);
397 idr_init(&dev_priv->context_idr);
398 idr_init(&dev_priv->surface_idr);
399 idr_init(&dev_priv->stream_idr);
fb1d9738
JB		 400 mutex_init(&dev_priv->init_mutex);
401 init_waitqueue_head(&dev_priv->fence_queue);
402 init_waitqueue_head(&dev_priv->fifo_queue);
4f73a96b 403 dev_priv->fence_queue_waiters = 0;
fb1d9738 404 atomic_set(&dev_priv->fifo_queue_waiters, 0);
fb1d9738
JB		 405
406 dev_priv->io_start = pci_resource_start(dev->pdev, 0);
407 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
408 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
409
30c78bb8
TH		 410 dev_priv->enable_fb = enable_fbdev;
411
fb1d9738 412 mutex_lock(&dev_priv->hw_mutex);
c188660f
PH		 413
414 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
415 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
416 if (svga_id != SVGA_ID_2) {
417 ret = -ENOSYS;
418 DRM_ERROR("Unsuported SVGA ID 0x%x\n", svga_id);
419 mutex_unlock(&dev_priv->hw_mutex);
420 goto out_err0;
421 }
422
fb1d9738
JB		 423 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
424
425 if (dev_priv->capabilities & SVGA_CAP_GMR) {
426 dev_priv->max_gmr_descriptors =
427 vmw_read(dev_priv,
428 SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
429 dev_priv->max_gmr_ids =
430 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
431 }
fb17f189
TH		 432 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
433 dev_priv->max_gmr_pages =
434 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
435 dev_priv->memory_size =
436 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
437 }
fb1d9738
JB		 438
439 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
440 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
441 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
442 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
443
444 mutex_unlock(&dev_priv->hw_mutex);
445
446 vmw_print_capabilities(dev_priv->capabilities);
447
448 if (dev_priv->capabilities & SVGA_CAP_GMR) {
449 DRM_INFO("Max GMR ids is %u\n",
450 (unsigned)dev_priv->max_gmr_ids);
451 DRM_INFO("Max GMR descriptors is %u\n",
452 (unsigned)dev_priv->max_gmr_descriptors);
453 }
fb17f189
TH		 454 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
455 DRM_INFO("Max number of GMR pages is %u\n",
456 (unsigned)dev_priv->max_gmr_pages);
457 DRM_INFO("Max dedicated hypervisor graphics memory is %u\n",
458 (unsigned)dev_priv->memory_size);
459 }
fb1d9738
JB		 460 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
461 dev_priv->vram_start, dev_priv->vram_size / 1024);
462 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
463 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
464
465 ret = vmw_ttm_global_init(dev_priv);
466 if (unlikely(ret != 0))
467 goto out_err0;
468
469
470 vmw_master_init(&dev_priv->fbdev_master);
471 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
472 dev_priv->active_master = &dev_priv->fbdev_master;
473
a2c06ee2 474
fb1d9738
JB		 475 ret = ttm_bo_device_init(&dev_priv->bdev,
476 dev_priv->bo_global_ref.ref.object,
477 &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET,
478 false);
479 if (unlikely(ret != 0)) {
480 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
481 goto out_err1;
482 }
483
484 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
485 (dev_priv->vram_size >> PAGE_SHIFT));
486 if (unlikely(ret != 0)) {
487 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
488 goto out_err2;
489 }
490
135cba0d
TH		 491 dev_priv->has_gmr = true;
492 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
493 dev_priv->max_gmr_ids) != 0) {
494 DRM_INFO("No GMR memory available. "
495 "Graphics memory resources are very limited.\n");
496 dev_priv->has_gmr = false;
497 }
498
fb1d9738
JB		 499 dev_priv->mmio_mtrr = drm_mtrr_add(dev_priv->mmio_start,
500 dev_priv->mmio_size, DRM_MTRR_WC);
501
502 dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
503 dev_priv->mmio_size);
504
505 if (unlikely(dev_priv->mmio_virt == NULL)) {
506 ret = -ENOMEM;
507 DRM_ERROR("Failed mapping MMIO.\n");
508 goto out_err3;
509 }
510
d7e1958d
JB		 511 /* Need mmio memory to check for fifo pitchlock cap. */
512 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
513 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
514 !vmw_fifo_have_pitchlock(dev_priv)) {
515 ret = -ENOSYS;
516 DRM_ERROR("Hardware has no pitchlock\n");
517 goto out_err4;
518 }
519
fb1d9738
JB		 520 dev_priv->tdev = ttm_object_device_init
521 (dev_priv->mem_global_ref.object, 12);
522
523 if (unlikely(dev_priv->tdev == NULL)) {
524 DRM_ERROR("Unable to initialize TTM object management.\n");
525 ret = -ENOMEM;
526 goto out_err4;
527 }
528
529 dev->dev_private = dev_priv;
530
fb1d9738
JB		 531 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
532 dev_priv->stealth = (ret != 0);
533 if (dev_priv->stealth) {
534 /**
535 * Request at least the mmio PCI resource.
536 */
537
538 DRM_INFO("It appears like vesafb is loaded. "
f2d12b8e 539 "Ignore above error if any.\n");
fb1d9738
JB		 540 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
541 if (unlikely(ret != 0)) {
542 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
543 goto out_no_device;
544 }
fb1d9738 545 }
ae2a1040
TH		 546
547 dev_priv->fman = vmw_fence_manager_init(dev_priv);
548 if (unlikely(dev_priv->fman == NULL))
549 goto out_no_fman;
56d1c78d
JB		 550
551 /* Need to start the fifo to check if we can do screen objects */
552 ret = vmw_3d_resource_inc(dev_priv, true);
553 if (unlikely(ret != 0))
554 goto out_no_fifo;
555 vmw_kms_save_vga(dev_priv);
56d1c78d
JB		 556
557 /* Start kms and overlay systems, needs fifo. */
7a1c2f6c
TH		 558 ret = vmw_kms_init(dev_priv);
559 if (unlikely(ret != 0))
560 goto out_no_kms;
f2d12b8e 561 vmw_overlay_init(dev_priv);
56d1c78d 562
01e81419
JB		 563 /* 3D Depends on Screen Objects being used. */
564 DRM_INFO("%s", vmw_fifo_have_3d(dev_priv) ?
565 "Detected device 3D availability.\n" :
566 "Detected no device 3D availability.\n");
567
56d1c78d 568 /* We might be done with the fifo now */
30c78bb8 569 if (dev_priv->enable_fb) {
30c78bb8 570 vmw_fb_init(dev_priv);
30c78bb8 571 } else {
56d1c78d
JB		 572 vmw_kms_restore_vga(dev_priv);
573 vmw_3d_resource_dec(dev_priv, true);
30c78bb8 574 }
fb1d9738 575
7a1c2f6c
TH		 576 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
577 ret = drm_irq_install(dev);
578 if (unlikely(ret != 0)) {
579 DRM_ERROR("Failed installing irq: %d\n", ret);
580 goto out_no_irq;
581 }
582 }
583
d9f36a00
TH		 584 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
585 register_pm_notifier(&dev_priv->pm_nb);
586
fb1d9738
JB		 587 return 0;
588
7a1c2f6c 589out_no_irq:
56d1c78d 590 if (dev_priv->enable_fb)
7a1c2f6c 591 vmw_fb_close(dev_priv);
56d1c78d
JB		 592 vmw_overlay_close(dev_priv);
593 vmw_kms_close(dev_priv);
594out_no_kms:
595 /* We still have a 3D resource reference held */
596 if (dev_priv->enable_fb) {
7a1c2f6c 597 vmw_kms_restore_vga(dev_priv);
05730b32 598 vmw_3d_resource_dec(dev_priv, false);
7a1c2f6c 599 }
30c78bb8 600out_no_fifo:
ae2a1040
TH		 601 vmw_fence_manager_takedown(dev_priv->fman);
602out_no_fman:
30c78bb8
TH		 603 if (dev_priv->stealth)
604 pci_release_region(dev->pdev, 2);
605 else
606 pci_release_regions(dev->pdev);
fb1d9738 607out_no_device:
fb1d9738
JB		 608 ttm_object_device_release(&dev_priv->tdev);
609out_err4:
610 iounmap(dev_priv->mmio_virt);
611out_err3:
612 drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
613 dev_priv->mmio_size, DRM_MTRR_WC);
135cba0d
TH		 614 if (dev_priv->has_gmr)
615 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
fb1d9738
JB		 616 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
617out_err2:
618 (void)ttm_bo_device_release(&dev_priv->bdev);
619out_err1:
620 vmw_ttm_global_release(dev_priv);
621out_err0:
fb1d9738
JB		 622 idr_destroy(&dev_priv->surface_idr);
623 idr_destroy(&dev_priv->context_idr);
624 idr_destroy(&dev_priv->stream_idr);
625 kfree(dev_priv);
626 return ret;
627}
628
629static int vmw_driver_unload(struct drm_device *dev)
630{
631 struct vmw_private *dev_priv = vmw_priv(dev);
632
d9f36a00
TH		 633 unregister_pm_notifier(&dev_priv->pm_nb);
634
be38ab6e
TH		 635 if (dev_priv->ctx.cmd_bounce)
636 vfree(dev_priv->ctx.cmd_bounce);
7a1c2f6c
TH		 637 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
638 drm_irq_uninstall(dev_priv->dev);
30c78bb8
TH		 639 if (dev_priv->enable_fb) {
640 vmw_fb_close(dev_priv);
641 vmw_kms_restore_vga(dev_priv);
05730b32 642 vmw_3d_resource_dec(dev_priv, false);
30c78bb8 643 }
f2d12b8e
TH		 644 vmw_kms_close(dev_priv);
645 vmw_overlay_close(dev_priv);
ae2a1040 646 vmw_fence_manager_takedown(dev_priv->fman);
f2d12b8e 647 if (dev_priv->stealth)
fb1d9738 648 pci_release_region(dev->pdev, 2);
f2d12b8e
TH		 649 else
650 pci_release_regions(dev->pdev);
651
fb1d9738
JB		 652 ttm_object_device_release(&dev_priv->tdev);
653 iounmap(dev_priv->mmio_virt);
654 drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
655 dev_priv->mmio_size, DRM_MTRR_WC);
135cba0d
TH		 656 if (dev_priv->has_gmr)
657 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
fb1d9738
JB		 658 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
659 (void)ttm_bo_device_release(&dev_priv->bdev);
660 vmw_ttm_global_release(dev_priv);
fb1d9738
JB		 661 idr_destroy(&dev_priv->surface_idr);
662 idr_destroy(&dev_priv->context_idr);
663 idr_destroy(&dev_priv->stream_idr);
664
665 kfree(dev_priv);
666
667 return 0;
668}
669
670static void vmw_postclose(struct drm_device *dev,
671 struct drm_file *file_priv)
672{
673 struct vmw_fpriv *vmw_fp;
674
675 vmw_fp = vmw_fpriv(file_priv);
676 ttm_object_file_release(&vmw_fp->tfile);
677 if (vmw_fp->locked_master)
678 drm_master_put(&vmw_fp->locked_master);
679 kfree(vmw_fp);
680}
681
682static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
683{
684 struct vmw_private *dev_priv = vmw_priv(dev);
685 struct vmw_fpriv *vmw_fp;
686 int ret = -ENOMEM;
687
688 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
689 if (unlikely(vmw_fp == NULL))
690 return ret;
691
692 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
693 if (unlikely(vmw_fp->tfile == NULL))
694 goto out_no_tfile;
695
696 file_priv->driver_priv = vmw_fp;
697
698 if (unlikely(dev_priv->bdev.dev_mapping == NULL))
699 dev_priv->bdev.dev_mapping =
700 file_priv->filp->f_path.dentry->d_inode->i_mapping;
701
702 return 0;
703
704out_no_tfile:
705 kfree(vmw_fp);
706 return ret;
707}
708
709static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
710 unsigned long arg)
711{
712 struct drm_file *file_priv = filp->private_data;
713 struct drm_device *dev = file_priv->minor->dev;
714 unsigned int nr = DRM_IOCTL_NR(cmd);
fb1d9738
JB		 715
716 /*
e1f78003 717 * Do extra checking on driver private ioctls.
fb1d9738
JB		 718 */
719
720 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
721 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
722 struct drm_ioctl_desc *ioctl =
723 &vmw_ioctls[nr - DRM_COMMAND_BASE];
724
2854eeda 725 if (unlikely(ioctl->cmd_drv != cmd)) {
fb1d9738
JB		 726 DRM_ERROR("Invalid command format, ioctl %d\n",
727 nr - DRM_COMMAND_BASE);
728 return -EINVAL;
729 }
fb1d9738
JB		 730 }
731
e1f78003 732 return drm_ioctl(filp, cmd, arg);
fb1d9738
JB		 733}
734
735static int vmw_firstopen(struct drm_device *dev)
736{
737 struct vmw_private *dev_priv = vmw_priv(dev);
738 dev_priv->is_opened = true;
739
740 return 0;
741}
742
743static void vmw_lastclose(struct drm_device *dev)
744{
745 struct vmw_private *dev_priv = vmw_priv(dev);
746 struct drm_crtc *crtc;
747 struct drm_mode_set set;
748 int ret;
749
750 /**
751 * Do nothing on the lastclose call from drm_unload.
752 */
753
754 if (!dev_priv->is_opened)
755 return;
756
757 dev_priv->is_opened = false;
758 set.x = 0;
759 set.y = 0;
760 set.fb = NULL;
761 set.mode = NULL;
762 set.connectors = NULL;
763 set.num_connectors = 0;
764
765 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
766 set.crtc = crtc;
767 ret = crtc->funcs->set_config(&set);
768 WARN_ON(ret != 0);
769 }
770
771}
772
773static void vmw_master_init(struct vmw_master *vmaster)
774{
775 ttm_lock_init(&vmaster->lock);
3a939a5e
TH		 776 INIT_LIST_HEAD(&vmaster->fb_surf);
777 mutex_init(&vmaster->fb_surf_mutex);
fb1d9738
JB		 778}
779
780static int vmw_master_create(struct drm_device *dev,
781 struct drm_master *master)
782{
783 struct vmw_master *vmaster;
784
fb1d9738
JB		 785 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
786 if (unlikely(vmaster == NULL))
787 return -ENOMEM;
788
3a939a5e 789 vmw_master_init(vmaster);
fb1d9738
JB		 790 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
791 master->driver_priv = vmaster;
792
793 return 0;
794}
795
796static void vmw_master_destroy(struct drm_device *dev,
797 struct drm_master *master)
798{
799 struct vmw_master *vmaster = vmw_master(master);
800
fb1d9738
JB		 801 master->driver_priv = NULL;
802 kfree(vmaster);
803}
804
805
806static int vmw_master_set(struct drm_device *dev,
807 struct drm_file *file_priv,
808 bool from_open)
809{
810 struct vmw_private *dev_priv = vmw_priv(dev);
811 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
812 struct vmw_master *active = dev_priv->active_master;
813 struct vmw_master *vmaster = vmw_master(file_priv->master);
814 int ret = 0;
815
30c78bb8 816 if (!dev_priv->enable_fb) {
05730b32 817 ret = vmw_3d_resource_inc(dev_priv, true);
30c78bb8
TH		 818 if (unlikely(ret != 0))
819 return ret;
820 vmw_kms_save_vga(dev_priv);
821 mutex_lock(&dev_priv->hw_mutex);
822 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
823 mutex_unlock(&dev_priv->hw_mutex);
824 }
825
fb1d9738
JB		 826 if (active) {
827 BUG_ON(active != &dev_priv->fbdev_master);
828 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
829 if (unlikely(ret != 0))
830 goto out_no_active_lock;
831
832 ttm_lock_set_kill(&active->lock, true, SIGTERM);
833 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
834 if (unlikely(ret != 0)) {
835 DRM_ERROR("Unable to clean VRAM on "
836 "master drop.\n");
837 }
838
839 dev_priv->active_master = NULL;
840 }
841
842 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
843 if (!from_open) {
844 ttm_vt_unlock(&vmaster->lock);
845 BUG_ON(vmw_fp->locked_master != file_priv->master);
846 drm_master_put(&vmw_fp->locked_master);
847 }
848
849 dev_priv->active_master = vmaster;
850
851 return 0;
852
853out_no_active_lock:
30c78bb8
TH		 854 if (!dev_priv->enable_fb) {
855 mutex_lock(&dev_priv->hw_mutex);
856 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
857 mutex_unlock(&dev_priv->hw_mutex);
858 vmw_kms_restore_vga(dev_priv);
05730b32 859 vmw_3d_resource_dec(dev_priv, true);
30c78bb8 860 }
fb1d9738
JB		 861 return ret;
862}
863
864static void vmw_master_drop(struct drm_device *dev,
865 struct drm_file *file_priv,
866 bool from_release)
867{
868 struct vmw_private *dev_priv = vmw_priv(dev);
869 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
870 struct vmw_master *vmaster = vmw_master(file_priv->master);
871 int ret;
872
fb1d9738
JB		 873 /**
874 * Make sure the master doesn't disappear while we have
875 * it locked.
876 */
877
878 vmw_fp->locked_master = drm_master_get(file_priv->master);
879 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
e2fa3a76
TH		 880 vmw_execbuf_release_pinned_bo(dev_priv, false, 0);
881
fb1d9738
JB		 882 if (unlikely((ret != 0))) {
883 DRM_ERROR("Unable to lock TTM at VT switch.\n");
884 drm_master_put(&vmw_fp->locked_master);
885 }
886
887 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
888
30c78bb8
TH		 889 if (!dev_priv->enable_fb) {
890 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
891 if (unlikely(ret != 0))
892 DRM_ERROR("Unable to clean VRAM on master drop.\n");
893 mutex_lock(&dev_priv->hw_mutex);
894 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
895 mutex_unlock(&dev_priv->hw_mutex);
896 vmw_kms_restore_vga(dev_priv);
05730b32 897 vmw_3d_resource_dec(dev_priv, true);
30c78bb8
TH		 898 }
899
fb1d9738
JB		 900 dev_priv->active_master = &dev_priv->fbdev_master;
901 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
902 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
903
30c78bb8
TH		 904 if (dev_priv->enable_fb)
905 vmw_fb_on(dev_priv);
fb1d9738
JB		 906}
907
908
909static void vmw_remove(struct pci_dev *pdev)
910{
911 struct drm_device *dev = pci_get_drvdata(pdev);
912
913 drm_put_dev(dev);
914}
915
d9f36a00
TH		 916static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
917 void *ptr)
918{
919 struct vmw_private *dev_priv =
920 container_of(nb, struct vmw_private, pm_nb);
921 struct vmw_master *vmaster = dev_priv->active_master;
922
923 switch (val) {
924 case PM_HIBERNATION_PREPARE:
925 case PM_SUSPEND_PREPARE:
926 ttm_suspend_lock(&vmaster->lock);
927
928 /**
929 * This empties VRAM and unbinds all GMR bindings.
930 * Buffer contents is moved to swappable memory.
931 */
e2fa3a76 932 vmw_execbuf_release_pinned_bo(dev_priv, false, 0);
d9f36a00 933 ttm_bo_swapout_all(&dev_priv->bdev);
094e0fa8 934
d9f36a00
TH		 935 break;
936 case PM_POST_HIBERNATION:
937 case PM_POST_SUSPEND:
094e0fa8 938 case PM_POST_RESTORE:
d9f36a00 939 ttm_suspend_unlock(&vmaster->lock);
094e0fa8 940
d9f36a00
TH		 941 break;
942 case PM_RESTORE_PREPARE:
943 break;
d9f36a00
TH		 944 default:
945 break;
946 }
947 return 0;
948}
949
950/**
951 * These might not be needed with the virtual SVGA device.
952 */
953
7fbd721a 954static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
d9f36a00 955{
094e0fa8
TH		 956 struct drm_device *dev = pci_get_drvdata(pdev);
957 struct vmw_private *dev_priv = vmw_priv(dev);
958
959 if (dev_priv->num_3d_resources != 0) {
960 DRM_INFO("Can't suspend or hibernate "
961 "while 3D resources are active.\n");
962 return -EBUSY;
963 }
964
d9f36a00
TH		 965 pci_save_state(pdev);
966 pci_disable_device(pdev);
967 pci_set_power_state(pdev, PCI_D3hot);
968 return 0;
969}
970
7fbd721a 971static int vmw_pci_resume(struct pci_dev *pdev)
d9f36a00
TH		 972{
973 pci_set_power_state(pdev, PCI_D0);
974 pci_restore_state(pdev);
975 return pci_enable_device(pdev);
976}
977
7fbd721a
TH		 978static int vmw_pm_suspend(struct device *kdev)
979{
980 struct pci_dev *pdev = to_pci_dev(kdev);
981 struct pm_message dummy;
982
983 dummy.event = 0;
984
985 return vmw_pci_suspend(pdev, dummy);
986}
987
988static int vmw_pm_resume(struct device *kdev)
989{
990 struct pci_dev *pdev = to_pci_dev(kdev);
991
992 return vmw_pci_resume(pdev);
993}
994
995static int vmw_pm_prepare(struct device *kdev)
996{
997 struct pci_dev *pdev = to_pci_dev(kdev);
998 struct drm_device *dev = pci_get_drvdata(pdev);
999 struct vmw_private *dev_priv = vmw_priv(dev);
1000
1001 /**
1002 * Release 3d reference held by fbdev and potentially
1003 * stop fifo.
1004 */
1005 dev_priv->suspended = true;
1006 if (dev_priv->enable_fb)
05730b32 1007 vmw_3d_resource_dec(dev_priv, true);
7fbd721a
TH		 1008
1009 if (dev_priv->num_3d_resources != 0) {
1010
1011 DRM_INFO("Can't suspend or hibernate "
1012 "while 3D resources are active.\n");
1013
1014 if (dev_priv->enable_fb)
05730b32 1015 vmw_3d_resource_inc(dev_priv, true);
7fbd721a
TH		 1016 dev_priv->suspended = false;
1017 return -EBUSY;
1018 }
1019
1020 return 0;
1021}
1022
1023static void vmw_pm_complete(struct device *kdev)
1024{
1025 struct pci_dev *pdev = to_pci_dev(kdev);
1026 struct drm_device *dev = pci_get_drvdata(pdev);
1027 struct vmw_private *dev_priv = vmw_priv(dev);
1028
1029 /**
1030 * Reclaim 3d reference held by fbdev and potentially
1031 * start fifo.
1032 */
1033 if (dev_priv->enable_fb)
05730b32 1034 vmw_3d_resource_inc(dev_priv, false);
7fbd721a
TH		 1035
1036 dev_priv->suspended = false;
1037}
1038
1039static const struct dev_pm_ops vmw_pm_ops = {
1040 .prepare = vmw_pm_prepare,
1041 .complete = vmw_pm_complete,
1042 .suspend = vmw_pm_suspend,
1043 .resume = vmw_pm_resume,
1044};
1045
fb1d9738
JB		 1046static struct drm_driver driver = {
1047 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1048 DRIVER_MODESET,
1049 .load = vmw_driver_load,
1050 .unload = vmw_driver_unload,
1051 .firstopen = vmw_firstopen,
1052 .lastclose = vmw_lastclose,
1053 .irq_preinstall = vmw_irq_preinstall,
1054 .irq_postinstall = vmw_irq_postinstall,
1055 .irq_uninstall = vmw_irq_uninstall,
1056 .irq_handler = vmw_irq_handler,
7a1c2f6c 1057 .get_vblank_counter = vmw_get_vblank_counter,
fb1d9738 1058 .reclaim_buffers_locked = NULL,
fb1d9738
JB		 1059 .ioctls = vmw_ioctls,
1060 .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
1061 .dma_quiescent = NULL, /*vmw_dma_quiescent, */
1062 .master_create = vmw_master_create,
1063 .master_destroy = vmw_master_destroy,
1064 .master_set = vmw_master_set,
1065 .master_drop = vmw_master_drop,
1066 .open = vmw_driver_open,
1067 .postclose = vmw_postclose,
1068 .fops = {
1069 .owner = THIS_MODULE,
1070 .open = drm_open,
1071 .release = drm_release,
1072 .unlocked_ioctl = vmw_unlocked_ioctl,
1073 .mmap = vmw_mmap,
1074 .poll = drm_poll,
1075 .fasync = drm_fasync,
1076#if defined(CONFIG_COMPAT)
1077 .compat_ioctl = drm_compat_ioctl,
1078#endif
dc880abe 1079 .llseek = noop_llseek,
7fbd721a 1080 },
fb1d9738
JB		 1081 .name = VMWGFX_DRIVER_NAME,
1082 .desc = VMWGFX_DRIVER_DESC,
1083 .date = VMWGFX_DRIVER_DATE,
1084 .major = VMWGFX_DRIVER_MAJOR,
1085 .minor = VMWGFX_DRIVER_MINOR,
1086 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1087};
1088
8410ea3b
DA		 1089static struct pci_driver vmw_pci_driver = {
1090 .name = VMWGFX_DRIVER_NAME,
1091 .id_table = vmw_pci_id_list,
1092 .probe = vmw_probe,
1093 .remove = vmw_remove,
1094 .driver = {
1095 .pm = &vmw_pm_ops
1096 }
1097};
1098
fb1d9738
JB		 1099static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1100{
dcdb1674 1101 return drm_get_pci_dev(pdev, ent, &driver);
fb1d9738
JB		 1102}
1103
1104static int __init vmwgfx_init(void)
1105{
1106 int ret;
8410ea3b 1107 ret = drm_pci_init(&driver, &vmw_pci_driver);
fb1d9738
JB		 1108 if (ret)
1109 DRM_ERROR("Failed initializing DRM.\n");
1110 return ret;
1111}
1112
1113static void __exit vmwgfx_exit(void)
1114{
8410ea3b 1115 drm_pci_exit(&driver, &vmw_pci_driver);
fb1d9738
JB		 1116}
1117
1118module_init(vmwgfx_init);
1119module_exit(vmwgfx_exit);
1120
1121MODULE_AUTHOR("VMware Inc. and others");
1122MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1123MODULE_LICENSE("GPL and additional rights");
73558ead
TH		 1124MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1125 __stringify(VMWGFX_DRIVER_MINOR) "."
1126 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1127 "0");
Linux kernel - Deliverables
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