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fb1d9738 JB |
1 | /************************************************************************** |
2 | * | |
3 | * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sub license, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial portions | |
16 | * of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | **************************************************************************/ | |
27 | ||
28 | #include "vmwgfx_drv.h" | |
29 | #include "drmP.h" | |
30 | #include "ttm/ttm_placement.h" | |
31 | ||
8e19a951 JB |
32 | bool vmw_fifo_have_3d(struct vmw_private *dev_priv) |
33 | { | |
34 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; | |
35 | uint32_t fifo_min, hwversion; | |
36 | ||
d7e1958d JB |
37 | if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) |
38 | return false; | |
39 | ||
8e19a951 JB |
40 | fifo_min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
41 | if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int)) | |
42 | return false; | |
43 | ||
44 | hwversion = ioread32(fifo_mem + SVGA_FIFO_3D_HWVERSION); | |
45 | if (hwversion == 0) | |
46 | return false; | |
47 | ||
b7b70024 | 48 | if (hwversion < SVGA3D_HWVERSION_WS8_B1) |
8e19a951 JB |
49 | return false; |
50 | ||
01e81419 JB |
51 | /* Non-Screen Object path does not support surfaces */ |
52 | if (!dev_priv->sou_priv) | |
53 | return false; | |
54 | ||
8e19a951 JB |
55 | return true; |
56 | } | |
57 | ||
d7e1958d JB |
58 | bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv) |
59 | { | |
60 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; | |
61 | uint32_t caps; | |
62 | ||
63 | if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) | |
64 | return false; | |
65 | ||
66 | caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES); | |
67 | if (caps & SVGA_FIFO_CAP_PITCHLOCK) | |
68 | return true; | |
69 | ||
70 | return false; | |
71 | } | |
72 | ||
fb1d9738 JB |
73 | int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) |
74 | { | |
75 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; | |
76 | uint32_t max; | |
77 | uint32_t min; | |
78 | uint32_t dummy; | |
fb1d9738 JB |
79 | |
80 | fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE; | |
81 | fifo->static_buffer = vmalloc(fifo->static_buffer_size); | |
82 | if (unlikely(fifo->static_buffer == NULL)) | |
83 | return -ENOMEM; | |
84 | ||
fb1d9738 JB |
85 | fifo->dynamic_buffer = NULL; |
86 | fifo->reserved_size = 0; | |
87 | fifo->using_bounce_buffer = false; | |
88 | ||
85b9e487 | 89 | mutex_init(&fifo->fifo_mutex); |
fb1d9738 JB |
90 | init_rwsem(&fifo->rwsem); |
91 | ||
92 | /* | |
93 | * Allow mapping the first page read-only to user-space. | |
94 | */ | |
95 | ||
96 | DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH)); | |
97 | DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT)); | |
98 | DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL)); | |
99 | ||
100 | mutex_lock(&dev_priv->hw_mutex); | |
101 | dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); | |
102 | dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); | |
30c78bb8 | 103 | dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); |
fb1d9738 JB |
104 | vmw_write(dev_priv, SVGA_REG_ENABLE, 1); |
105 | ||
106 | min = 4; | |
107 | if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO) | |
108 | min = vmw_read(dev_priv, SVGA_REG_MEM_REGS); | |
109 | min <<= 2; | |
110 | ||
111 | if (min < PAGE_SIZE) | |
112 | min = PAGE_SIZE; | |
113 | ||
114 | iowrite32(min, fifo_mem + SVGA_FIFO_MIN); | |
115 | iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX); | |
116 | wmb(); | |
117 | iowrite32(min, fifo_mem + SVGA_FIFO_NEXT_CMD); | |
118 | iowrite32(min, fifo_mem + SVGA_FIFO_STOP); | |
119 | iowrite32(0, fifo_mem + SVGA_FIFO_BUSY); | |
120 | mb(); | |
121 | ||
122 | vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); | |
123 | mutex_unlock(&dev_priv->hw_mutex); | |
124 | ||
125 | max = ioread32(fifo_mem + SVGA_FIFO_MAX); | |
126 | min = ioread32(fifo_mem + SVGA_FIFO_MIN); | |
127 | fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES); | |
128 | ||
129 | DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n", | |
130 | (unsigned int) max, | |
131 | (unsigned int) min, | |
132 | (unsigned int) fifo->capabilities); | |
133 | ||
6bcd8d3c TH |
134 | atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); |
135 | iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE); | |
136 | vmw_marker_queue_init(&fifo->marker_queue); | |
fb1d9738 | 137 | return vmw_fifo_send_fence(dev_priv, &dummy); |
fb1d9738 JB |
138 | } |
139 | ||
140 | void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason) | |
141 | { | |
142 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; | |
143 | ||
144 | mutex_lock(&dev_priv->hw_mutex); | |
145 | ||
146 | if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) { | |
147 | iowrite32(1, fifo_mem + SVGA_FIFO_BUSY); | |
148 | vmw_write(dev_priv, SVGA_REG_SYNC, reason); | |
149 | } | |
150 | ||
151 | mutex_unlock(&dev_priv->hw_mutex); | |
152 | } | |
153 | ||
154 | void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) | |
155 | { | |
156 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; | |
157 | ||
158 | mutex_lock(&dev_priv->hw_mutex); | |
159 | ||
160 | while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0) | |
161 | vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); | |
162 | ||
6bcd8d3c | 163 | dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE); |
fb1d9738 JB |
164 | |
165 | vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, | |
166 | dev_priv->config_done_state); | |
167 | vmw_write(dev_priv, SVGA_REG_ENABLE, | |
168 | dev_priv->enable_state); | |
30c78bb8 TH |
169 | vmw_write(dev_priv, SVGA_REG_TRACES, |
170 | dev_priv->traces_state); | |
fb1d9738 JB |
171 | |
172 | mutex_unlock(&dev_priv->hw_mutex); | |
6bcd8d3c | 173 | vmw_marker_queue_takedown(&fifo->marker_queue); |
fb1d9738 | 174 | |
fb1d9738 JB |
175 | if (likely(fifo->static_buffer != NULL)) { |
176 | vfree(fifo->static_buffer); | |
177 | fifo->static_buffer = NULL; | |
178 | } | |
179 | ||
180 | if (likely(fifo->dynamic_buffer != NULL)) { | |
181 | vfree(fifo->dynamic_buffer); | |
182 | fifo->dynamic_buffer = NULL; | |
183 | } | |
184 | } | |
185 | ||
186 | static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes) | |
187 | { | |
188 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; | |
189 | uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX); | |
190 | uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); | |
191 | uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN); | |
192 | uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP); | |
193 | ||
194 | return ((max - next_cmd) + (stop - min) <= bytes); | |
195 | } | |
196 | ||
197 | static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv, | |
198 | uint32_t bytes, bool interruptible, | |
199 | unsigned long timeout) | |
200 | { | |
201 | int ret = 0; | |
202 | unsigned long end_jiffies = jiffies + timeout; | |
203 | DEFINE_WAIT(__wait); | |
204 | ||
205 | DRM_INFO("Fifo wait noirq.\n"); | |
206 | ||
207 | for (;;) { | |
208 | prepare_to_wait(&dev_priv->fifo_queue, &__wait, | |
209 | (interruptible) ? | |
210 | TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
211 | if (!vmw_fifo_is_full(dev_priv, bytes)) | |
212 | break; | |
213 | if (time_after_eq(jiffies, end_jiffies)) { | |
214 | ret = -EBUSY; | |
215 | DRM_ERROR("SVGA device lockup.\n"); | |
216 | break; | |
217 | } | |
218 | schedule_timeout(1); | |
219 | if (interruptible && signal_pending(current)) { | |
3d3a5b32 | 220 | ret = -ERESTARTSYS; |
fb1d9738 JB |
221 | break; |
222 | } | |
223 | } | |
224 | finish_wait(&dev_priv->fifo_queue, &__wait); | |
225 | wake_up_all(&dev_priv->fifo_queue); | |
226 | DRM_INFO("Fifo noirq exit.\n"); | |
227 | return ret; | |
228 | } | |
229 | ||
230 | static int vmw_fifo_wait(struct vmw_private *dev_priv, | |
231 | uint32_t bytes, bool interruptible, | |
232 | unsigned long timeout) | |
233 | { | |
234 | long ret = 1L; | |
235 | unsigned long irq_flags; | |
236 | ||
237 | if (likely(!vmw_fifo_is_full(dev_priv, bytes))) | |
238 | return 0; | |
239 | ||
240 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL); | |
241 | if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) | |
242 | return vmw_fifo_wait_noirq(dev_priv, bytes, | |
243 | interruptible, timeout); | |
244 | ||
245 | mutex_lock(&dev_priv->hw_mutex); | |
246 | if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) { | |
247 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); | |
248 | outl(SVGA_IRQFLAG_FIFO_PROGRESS, | |
249 | dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); | |
250 | vmw_write(dev_priv, SVGA_REG_IRQMASK, | |
251 | vmw_read(dev_priv, SVGA_REG_IRQMASK) | | |
252 | SVGA_IRQFLAG_FIFO_PROGRESS); | |
253 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); | |
254 | } | |
255 | mutex_unlock(&dev_priv->hw_mutex); | |
256 | ||
257 | if (interruptible) | |
258 | ret = wait_event_interruptible_timeout | |
259 | (dev_priv->fifo_queue, | |
260 | !vmw_fifo_is_full(dev_priv, bytes), timeout); | |
261 | else | |
262 | ret = wait_event_timeout | |
263 | (dev_priv->fifo_queue, | |
264 | !vmw_fifo_is_full(dev_priv, bytes), timeout); | |
265 | ||
3d3a5b32 | 266 | if (unlikely(ret == 0)) |
fb1d9738 JB |
267 | ret = -EBUSY; |
268 | else if (likely(ret > 0)) | |
269 | ret = 0; | |
270 | ||
271 | mutex_lock(&dev_priv->hw_mutex); | |
272 | if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) { | |
273 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); | |
274 | vmw_write(dev_priv, SVGA_REG_IRQMASK, | |
275 | vmw_read(dev_priv, SVGA_REG_IRQMASK) & | |
276 | ~SVGA_IRQFLAG_FIFO_PROGRESS); | |
277 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); | |
278 | } | |
279 | mutex_unlock(&dev_priv->hw_mutex); | |
280 | ||
281 | return ret; | |
282 | } | |
283 | ||
de12d44f JB |
284 | /** |
285 | * Reserve @bytes number of bytes in the fifo. | |
286 | * | |
287 | * This function will return NULL (error) on two conditions: | |
288 | * If it timeouts waiting for fifo space, or if @bytes is larger than the | |
289 | * available fifo space. | |
290 | * | |
291 | * Returns: | |
292 | * Pointer to the fifo, or null on error (possible hardware hang). | |
293 | */ | |
fb1d9738 JB |
294 | void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes) |
295 | { | |
296 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; | |
297 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; | |
298 | uint32_t max; | |
299 | uint32_t min; | |
300 | uint32_t next_cmd; | |
301 | uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; | |
302 | int ret; | |
303 | ||
85b9e487 | 304 | mutex_lock(&fifo_state->fifo_mutex); |
fb1d9738 JB |
305 | max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
306 | min = ioread32(fifo_mem + SVGA_FIFO_MIN); | |
307 | next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); | |
308 | ||
309 | if (unlikely(bytes >= (max - min))) | |
310 | goto out_err; | |
311 | ||
312 | BUG_ON(fifo_state->reserved_size != 0); | |
313 | BUG_ON(fifo_state->dynamic_buffer != NULL); | |
314 | ||
315 | fifo_state->reserved_size = bytes; | |
316 | ||
317 | while (1) { | |
318 | uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP); | |
319 | bool need_bounce = false; | |
320 | bool reserve_in_place = false; | |
321 | ||
322 | if (next_cmd >= stop) { | |
323 | if (likely((next_cmd + bytes < max || | |
324 | (next_cmd + bytes == max && stop > min)))) | |
325 | reserve_in_place = true; | |
326 | ||
327 | else if (vmw_fifo_is_full(dev_priv, bytes)) { | |
328 | ret = vmw_fifo_wait(dev_priv, bytes, | |
329 | false, 3 * HZ); | |
330 | if (unlikely(ret != 0)) | |
331 | goto out_err; | |
332 | } else | |
333 | need_bounce = true; | |
334 | ||
335 | } else { | |
336 | ||
337 | if (likely((next_cmd + bytes < stop))) | |
338 | reserve_in_place = true; | |
339 | else { | |
340 | ret = vmw_fifo_wait(dev_priv, bytes, | |
341 | false, 3 * HZ); | |
342 | if (unlikely(ret != 0)) | |
343 | goto out_err; | |
344 | } | |
345 | } | |
346 | ||
347 | if (reserve_in_place) { | |
348 | if (reserveable || bytes <= sizeof(uint32_t)) { | |
349 | fifo_state->using_bounce_buffer = false; | |
350 | ||
351 | if (reserveable) | |
352 | iowrite32(bytes, fifo_mem + | |
353 | SVGA_FIFO_RESERVED); | |
354 | return fifo_mem + (next_cmd >> 2); | |
355 | } else { | |
356 | need_bounce = true; | |
357 | } | |
358 | } | |
359 | ||
360 | if (need_bounce) { | |
361 | fifo_state->using_bounce_buffer = true; | |
362 | if (bytes < fifo_state->static_buffer_size) | |
363 | return fifo_state->static_buffer; | |
364 | else { | |
365 | fifo_state->dynamic_buffer = vmalloc(bytes); | |
366 | return fifo_state->dynamic_buffer; | |
367 | } | |
368 | } | |
369 | } | |
370 | out_err: | |
371 | fifo_state->reserved_size = 0; | |
85b9e487 | 372 | mutex_unlock(&fifo_state->fifo_mutex); |
fb1d9738 JB |
373 | return NULL; |
374 | } | |
375 | ||
376 | static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state, | |
377 | __le32 __iomem *fifo_mem, | |
378 | uint32_t next_cmd, | |
379 | uint32_t max, uint32_t min, uint32_t bytes) | |
380 | { | |
381 | uint32_t chunk_size = max - next_cmd; | |
382 | uint32_t rest; | |
383 | uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? | |
384 | fifo_state->dynamic_buffer : fifo_state->static_buffer; | |
385 | ||
386 | if (bytes < chunk_size) | |
387 | chunk_size = bytes; | |
388 | ||
389 | iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED); | |
390 | mb(); | |
391 | memcpy_toio(fifo_mem + (next_cmd >> 2), buffer, chunk_size); | |
392 | rest = bytes - chunk_size; | |
393 | if (rest) | |
394 | memcpy_toio(fifo_mem + (min >> 2), buffer + (chunk_size >> 2), | |
395 | rest); | |
396 | } | |
397 | ||
398 | static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state, | |
399 | __le32 __iomem *fifo_mem, | |
400 | uint32_t next_cmd, | |
401 | uint32_t max, uint32_t min, uint32_t bytes) | |
402 | { | |
403 | uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? | |
404 | fifo_state->dynamic_buffer : fifo_state->static_buffer; | |
405 | ||
406 | while (bytes > 0) { | |
407 | iowrite32(*buffer++, fifo_mem + (next_cmd >> 2)); | |
408 | next_cmd += sizeof(uint32_t); | |
409 | if (unlikely(next_cmd == max)) | |
410 | next_cmd = min; | |
411 | mb(); | |
412 | iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); | |
413 | mb(); | |
414 | bytes -= sizeof(uint32_t); | |
415 | } | |
416 | } | |
417 | ||
418 | void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) | |
419 | { | |
420 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; | |
421 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; | |
422 | uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); | |
423 | uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX); | |
424 | uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN); | |
425 | bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; | |
426 | ||
427 | BUG_ON((bytes & 3) != 0); | |
428 | BUG_ON(bytes > fifo_state->reserved_size); | |
429 | ||
430 | fifo_state->reserved_size = 0; | |
431 | ||
432 | if (fifo_state->using_bounce_buffer) { | |
433 | if (reserveable) | |
434 | vmw_fifo_res_copy(fifo_state, fifo_mem, | |
435 | next_cmd, max, min, bytes); | |
436 | else | |
437 | vmw_fifo_slow_copy(fifo_state, fifo_mem, | |
438 | next_cmd, max, min, bytes); | |
439 | ||
440 | if (fifo_state->dynamic_buffer) { | |
441 | vfree(fifo_state->dynamic_buffer); | |
442 | fifo_state->dynamic_buffer = NULL; | |
443 | } | |
444 | ||
445 | } | |
446 | ||
85b9e487 | 447 | down_write(&fifo_state->rwsem); |
fb1d9738 JB |
448 | if (fifo_state->using_bounce_buffer || reserveable) { |
449 | next_cmd += bytes; | |
450 | if (next_cmd >= max) | |
451 | next_cmd -= max - min; | |
452 | mb(); | |
453 | iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); | |
454 | } | |
455 | ||
456 | if (reserveable) | |
457 | iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED); | |
458 | mb(); | |
fb1d9738 | 459 | up_write(&fifo_state->rwsem); |
85b9e487 TH |
460 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); |
461 | mutex_unlock(&fifo_state->fifo_mutex); | |
fb1d9738 JB |
462 | } |
463 | ||
6bcd8d3c | 464 | int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno) |
fb1d9738 JB |
465 | { |
466 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; | |
467 | struct svga_fifo_cmd_fence *cmd_fence; | |
468 | void *fm; | |
469 | int ret = 0; | |
470 | uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence); | |
471 | ||
472 | fm = vmw_fifo_reserve(dev_priv, bytes); | |
473 | if (unlikely(fm == NULL)) { | |
6bcd8d3c | 474 | *seqno = atomic_read(&dev_priv->marker_seq); |
fb1d9738 | 475 | ret = -ENOMEM; |
6bcd8d3c | 476 | (void)vmw_fallback_wait(dev_priv, false, true, *seqno, |
fb1d9738 JB |
477 | false, 3*HZ); |
478 | goto out_err; | |
479 | } | |
480 | ||
481 | do { | |
6bcd8d3c TH |
482 | *seqno = atomic_add_return(1, &dev_priv->marker_seq); |
483 | } while (*seqno == 0); | |
fb1d9738 JB |
484 | |
485 | if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) { | |
486 | ||
487 | /* | |
488 | * Don't request hardware to send a fence. The | |
489 | * waiting code in vmwgfx_irq.c will emulate this. | |
490 | */ | |
491 | ||
492 | vmw_fifo_commit(dev_priv, 0); | |
493 | return 0; | |
494 | } | |
495 | ||
496 | *(__le32 *) fm = cpu_to_le32(SVGA_CMD_FENCE); | |
497 | cmd_fence = (struct svga_fifo_cmd_fence *) | |
498 | ((unsigned long)fm + sizeof(__le32)); | |
499 | ||
6bcd8d3c | 500 | iowrite32(*seqno, &cmd_fence->fence); |
fb1d9738 | 501 | vmw_fifo_commit(dev_priv, bytes); |
6bcd8d3c TH |
502 | (void) vmw_marker_push(&fifo_state->marker_queue, *seqno); |
503 | vmw_update_seqno(dev_priv, fifo_state); | |
fb1d9738 JB |
504 | |
505 | out_err: | |
506 | return ret; | |
507 | } |