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fb1d9738 JB |
1 | /************************************************************************** |
2 | * | |
3 | * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sub license, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial portions | |
16 | * of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | **************************************************************************/ | |
27 | ||
28 | #include "vmwgfx_drv.h" | |
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/ttm/ttm_placement.h> | |
fb1d9738 | 31 | |
8e19a951 JB |
32 | bool vmw_fifo_have_3d(struct vmw_private *dev_priv) |
33 | { | |
b9eb1a61 | 34 | u32 __iomem *fifo_mem = dev_priv->mmio_virt; |
8e19a951 | 35 | uint32_t fifo_min, hwversion; |
ebd4c6f6 | 36 | const struct vmw_fifo_state *fifo = &dev_priv->fifo; |
8e19a951 | 37 | |
d8c08b2b TH |
38 | if (!(dev_priv->capabilities & SVGA_CAP_3D)) |
39 | return false; | |
40 | ||
41 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { | |
42 | uint32_t result; | |
43 | ||
44 | if (!dev_priv->has_mob) | |
45 | return false; | |
46 | ||
496eb6fd | 47 | spin_lock(&dev_priv->cap_lock); |
d8c08b2b TH |
48 | vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D); |
49 | result = vmw_read(dev_priv, SVGA_REG_DEV_CAP); | |
496eb6fd | 50 | spin_unlock(&dev_priv->cap_lock); |
d8c08b2b TH |
51 | |
52 | return (result != 0); | |
53 | } | |
54 | ||
d7e1958d JB |
55 | if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) |
56 | return false; | |
57 | ||
8e19a951 JB |
58 | fifo_min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
59 | if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int)) | |
60 | return false; | |
61 | ||
ebd4c6f6 TH |
62 | hwversion = ioread32(fifo_mem + |
63 | ((fifo->capabilities & | |
64 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ? | |
65 | SVGA_FIFO_3D_HWVERSION_REVISED : | |
66 | SVGA_FIFO_3D_HWVERSION)); | |
67 | ||
8e19a951 JB |
68 | if (hwversion == 0) |
69 | return false; | |
70 | ||
b7b70024 | 71 | if (hwversion < SVGA3D_HWVERSION_WS8_B1) |
8e19a951 JB |
72 | return false; |
73 | ||
c8261a96 SY |
74 | /* Legacy Display Unit does not support surfaces */ |
75 | if (dev_priv->active_display_unit == vmw_du_legacy) | |
01e81419 JB |
76 | return false; |
77 | ||
8e19a951 JB |
78 | return true; |
79 | } | |
80 | ||
d7e1958d JB |
81 | bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv) |
82 | { | |
b9eb1a61 | 83 | u32 __iomem *fifo_mem = dev_priv->mmio_virt; |
d7e1958d JB |
84 | uint32_t caps; |
85 | ||
86 | if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) | |
87 | return false; | |
88 | ||
89 | caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES); | |
90 | if (caps & SVGA_FIFO_CAP_PITCHLOCK) | |
91 | return true; | |
92 | ||
93 | return false; | |
94 | } | |
95 | ||
fb1d9738 JB |
96 | int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) |
97 | { | |
b9eb1a61 | 98 | u32 __iomem *fifo_mem = dev_priv->mmio_virt; |
fb1d9738 JB |
99 | uint32_t max; |
100 | uint32_t min; | |
fb1d9738 JB |
101 | |
102 | fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE; | |
103 | fifo->static_buffer = vmalloc(fifo->static_buffer_size); | |
104 | if (unlikely(fifo->static_buffer == NULL)) | |
105 | return -ENOMEM; | |
106 | ||
fb1d9738 JB |
107 | fifo->dynamic_buffer = NULL; |
108 | fifo->reserved_size = 0; | |
109 | fifo->using_bounce_buffer = false; | |
110 | ||
85b9e487 | 111 | mutex_init(&fifo->fifo_mutex); |
fb1d9738 JB |
112 | init_rwsem(&fifo->rwsem); |
113 | ||
fb1d9738 JB |
114 | DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH)); |
115 | DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT)); | |
116 | DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL)); | |
117 | ||
fb1d9738 JB |
118 | dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); |
119 | dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); | |
30c78bb8 | 120 | dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); |
153b3d5b TH |
121 | |
122 | vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE_HIDE); | |
123 | vmw_write(dev_priv, SVGA_REG_TRACES, 0); | |
fb1d9738 JB |
124 | |
125 | min = 4; | |
126 | if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO) | |
127 | min = vmw_read(dev_priv, SVGA_REG_MEM_REGS); | |
128 | min <<= 2; | |
129 | ||
130 | if (min < PAGE_SIZE) | |
131 | min = PAGE_SIZE; | |
132 | ||
133 | iowrite32(min, fifo_mem + SVGA_FIFO_MIN); | |
134 | iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX); | |
135 | wmb(); | |
136 | iowrite32(min, fifo_mem + SVGA_FIFO_NEXT_CMD); | |
137 | iowrite32(min, fifo_mem + SVGA_FIFO_STOP); | |
138 | iowrite32(0, fifo_mem + SVGA_FIFO_BUSY); | |
139 | mb(); | |
140 | ||
141 | vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); | |
fb1d9738 JB |
142 | |
143 | max = ioread32(fifo_mem + SVGA_FIFO_MAX); | |
144 | min = ioread32(fifo_mem + SVGA_FIFO_MIN); | |
145 | fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES); | |
146 | ||
147 | DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n", | |
148 | (unsigned int) max, | |
149 | (unsigned int) min, | |
150 | (unsigned int) fifo->capabilities); | |
151 | ||
6bcd8d3c TH |
152 | atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); |
153 | iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE); | |
154 | vmw_marker_queue_init(&fifo->marker_queue); | |
153b3d5b TH |
155 | |
156 | return 0; | |
fb1d9738 JB |
157 | } |
158 | ||
496eb6fd | 159 | void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason) |
fb1d9738 | 160 | { |
b9eb1a61 | 161 | u32 __iomem *fifo_mem = dev_priv->mmio_virt; |
496eb6fd TH |
162 | static DEFINE_SPINLOCK(ping_lock); |
163 | unsigned long irq_flags; | |
fb1d9738 | 164 | |
496eb6fd TH |
165 | /* |
166 | * The ping_lock is needed because we don't have an atomic | |
167 | * test-and-set of the SVGA_FIFO_BUSY register. | |
168 | */ | |
169 | spin_lock_irqsave(&ping_lock, irq_flags); | |
fb1d9738 JB |
170 | if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) { |
171 | iowrite32(1, fifo_mem + SVGA_FIFO_BUSY); | |
172 | vmw_write(dev_priv, SVGA_REG_SYNC, reason); | |
173 | } | |
496eb6fd | 174 | spin_unlock_irqrestore(&ping_lock, irq_flags); |
fb1d9738 JB |
175 | } |
176 | ||
177 | void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) | |
178 | { | |
b9eb1a61 | 179 | u32 __iomem *fifo_mem = dev_priv->mmio_virt; |
fb1d9738 | 180 | |
f01ea0c3 | 181 | vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); |
fb1d9738 | 182 | while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0) |
f01ea0c3 | 183 | ; |
fb1d9738 | 184 | |
6bcd8d3c | 185 | dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE); |
fb1d9738 JB |
186 | |
187 | vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, | |
188 | dev_priv->config_done_state); | |
189 | vmw_write(dev_priv, SVGA_REG_ENABLE, | |
190 | dev_priv->enable_state); | |
30c78bb8 TH |
191 | vmw_write(dev_priv, SVGA_REG_TRACES, |
192 | dev_priv->traces_state); | |
fb1d9738 | 193 | |
6bcd8d3c | 194 | vmw_marker_queue_takedown(&fifo->marker_queue); |
fb1d9738 | 195 | |
fb1d9738 JB |
196 | if (likely(fifo->static_buffer != NULL)) { |
197 | vfree(fifo->static_buffer); | |
198 | fifo->static_buffer = NULL; | |
199 | } | |
200 | ||
201 | if (likely(fifo->dynamic_buffer != NULL)) { | |
202 | vfree(fifo->dynamic_buffer); | |
203 | fifo->dynamic_buffer = NULL; | |
204 | } | |
205 | } | |
206 | ||
207 | static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes) | |
208 | { | |
b9eb1a61 | 209 | u32 __iomem *fifo_mem = dev_priv->mmio_virt; |
fb1d9738 JB |
210 | uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
211 | uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); | |
212 | uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN); | |
213 | uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP); | |
214 | ||
215 | return ((max - next_cmd) + (stop - min) <= bytes); | |
216 | } | |
217 | ||
218 | static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv, | |
219 | uint32_t bytes, bool interruptible, | |
220 | unsigned long timeout) | |
221 | { | |
222 | int ret = 0; | |
223 | unsigned long end_jiffies = jiffies + timeout; | |
224 | DEFINE_WAIT(__wait); | |
225 | ||
226 | DRM_INFO("Fifo wait noirq.\n"); | |
227 | ||
228 | for (;;) { | |
229 | prepare_to_wait(&dev_priv->fifo_queue, &__wait, | |
230 | (interruptible) ? | |
231 | TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
232 | if (!vmw_fifo_is_full(dev_priv, bytes)) | |
233 | break; | |
234 | if (time_after_eq(jiffies, end_jiffies)) { | |
235 | ret = -EBUSY; | |
236 | DRM_ERROR("SVGA device lockup.\n"); | |
237 | break; | |
238 | } | |
239 | schedule_timeout(1); | |
240 | if (interruptible && signal_pending(current)) { | |
3d3a5b32 | 241 | ret = -ERESTARTSYS; |
fb1d9738 JB |
242 | break; |
243 | } | |
244 | } | |
245 | finish_wait(&dev_priv->fifo_queue, &__wait); | |
246 | wake_up_all(&dev_priv->fifo_queue); | |
247 | DRM_INFO("Fifo noirq exit.\n"); | |
248 | return ret; | |
249 | } | |
250 | ||
251 | static int vmw_fifo_wait(struct vmw_private *dev_priv, | |
252 | uint32_t bytes, bool interruptible, | |
253 | unsigned long timeout) | |
254 | { | |
255 | long ret = 1L; | |
256 | unsigned long irq_flags; | |
257 | ||
258 | if (likely(!vmw_fifo_is_full(dev_priv, bytes))) | |
259 | return 0; | |
260 | ||
261 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL); | |
262 | if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) | |
263 | return vmw_fifo_wait_noirq(dev_priv, bytes, | |
264 | interruptible, timeout); | |
265 | ||
496eb6fd | 266 | spin_lock(&dev_priv->waiter_lock); |
fb1d9738 JB |
267 | if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) { |
268 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); | |
269 | outl(SVGA_IRQFLAG_FIFO_PROGRESS, | |
270 | dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); | |
57c5ee79 TH |
271 | dev_priv->irq_mask |= SVGA_IRQFLAG_FIFO_PROGRESS; |
272 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); | |
fb1d9738 JB |
273 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); |
274 | } | |
496eb6fd | 275 | spin_unlock(&dev_priv->waiter_lock); |
fb1d9738 JB |
276 | |
277 | if (interruptible) | |
278 | ret = wait_event_interruptible_timeout | |
279 | (dev_priv->fifo_queue, | |
280 | !vmw_fifo_is_full(dev_priv, bytes), timeout); | |
281 | else | |
282 | ret = wait_event_timeout | |
283 | (dev_priv->fifo_queue, | |
284 | !vmw_fifo_is_full(dev_priv, bytes), timeout); | |
285 | ||
3d3a5b32 | 286 | if (unlikely(ret == 0)) |
fb1d9738 JB |
287 | ret = -EBUSY; |
288 | else if (likely(ret > 0)) | |
289 | ret = 0; | |
290 | ||
496eb6fd | 291 | spin_lock(&dev_priv->waiter_lock); |
fb1d9738 JB |
292 | if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) { |
293 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); | |
57c5ee79 TH |
294 | dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS; |
295 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); | |
fb1d9738 JB |
296 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); |
297 | } | |
496eb6fd | 298 | spin_unlock(&dev_priv->waiter_lock); |
fb1d9738 JB |
299 | |
300 | return ret; | |
301 | } | |
302 | ||
de12d44f JB |
303 | /** |
304 | * Reserve @bytes number of bytes in the fifo. | |
305 | * | |
306 | * This function will return NULL (error) on two conditions: | |
307 | * If it timeouts waiting for fifo space, or if @bytes is larger than the | |
308 | * available fifo space. | |
309 | * | |
310 | * Returns: | |
311 | * Pointer to the fifo, or null on error (possible hardware hang). | |
312 | */ | |
3eab3d9e TH |
313 | static void *vmw_local_fifo_reserve(struct vmw_private *dev_priv, |
314 | uint32_t bytes) | |
fb1d9738 JB |
315 | { |
316 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; | |
b9eb1a61 | 317 | u32 __iomem *fifo_mem = dev_priv->mmio_virt; |
fb1d9738 JB |
318 | uint32_t max; |
319 | uint32_t min; | |
320 | uint32_t next_cmd; | |
321 | uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; | |
322 | int ret; | |
323 | ||
85b9e487 | 324 | mutex_lock(&fifo_state->fifo_mutex); |
fb1d9738 JB |
325 | max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
326 | min = ioread32(fifo_mem + SVGA_FIFO_MIN); | |
327 | next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); | |
328 | ||
329 | if (unlikely(bytes >= (max - min))) | |
330 | goto out_err; | |
331 | ||
332 | BUG_ON(fifo_state->reserved_size != 0); | |
333 | BUG_ON(fifo_state->dynamic_buffer != NULL); | |
334 | ||
335 | fifo_state->reserved_size = bytes; | |
336 | ||
337 | while (1) { | |
338 | uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP); | |
339 | bool need_bounce = false; | |
340 | bool reserve_in_place = false; | |
341 | ||
342 | if (next_cmd >= stop) { | |
343 | if (likely((next_cmd + bytes < max || | |
344 | (next_cmd + bytes == max && stop > min)))) | |
345 | reserve_in_place = true; | |
346 | ||
347 | else if (vmw_fifo_is_full(dev_priv, bytes)) { | |
348 | ret = vmw_fifo_wait(dev_priv, bytes, | |
349 | false, 3 * HZ); | |
350 | if (unlikely(ret != 0)) | |
351 | goto out_err; | |
352 | } else | |
353 | need_bounce = true; | |
354 | ||
355 | } else { | |
356 | ||
357 | if (likely((next_cmd + bytes < stop))) | |
358 | reserve_in_place = true; | |
359 | else { | |
360 | ret = vmw_fifo_wait(dev_priv, bytes, | |
361 | false, 3 * HZ); | |
362 | if (unlikely(ret != 0)) | |
363 | goto out_err; | |
364 | } | |
365 | } | |
366 | ||
367 | if (reserve_in_place) { | |
368 | if (reserveable || bytes <= sizeof(uint32_t)) { | |
369 | fifo_state->using_bounce_buffer = false; | |
370 | ||
371 | if (reserveable) | |
372 | iowrite32(bytes, fifo_mem + | |
373 | SVGA_FIFO_RESERVED); | |
b9eb1a61 TH |
374 | return (void __force *) (fifo_mem + |
375 | (next_cmd >> 2)); | |
fb1d9738 JB |
376 | } else { |
377 | need_bounce = true; | |
378 | } | |
379 | } | |
380 | ||
381 | if (need_bounce) { | |
382 | fifo_state->using_bounce_buffer = true; | |
383 | if (bytes < fifo_state->static_buffer_size) | |
384 | return fifo_state->static_buffer; | |
385 | else { | |
386 | fifo_state->dynamic_buffer = vmalloc(bytes); | |
387 | return fifo_state->dynamic_buffer; | |
388 | } | |
389 | } | |
390 | } | |
391 | out_err: | |
392 | fifo_state->reserved_size = 0; | |
85b9e487 | 393 | mutex_unlock(&fifo_state->fifo_mutex); |
3eab3d9e | 394 | |
fb1d9738 JB |
395 | return NULL; |
396 | } | |
397 | ||
3eab3d9e TH |
398 | void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes) |
399 | { | |
400 | void *ret; | |
401 | ||
402 | if (dev_priv->cman) | |
403 | ret = vmw_cmdbuf_reserve(dev_priv->cman, bytes, | |
404 | SVGA3D_INVALID_ID, false, NULL); | |
405 | else | |
406 | ret = vmw_local_fifo_reserve(dev_priv, bytes); | |
407 | if (IS_ERR_OR_NULL(ret)) { | |
408 | DRM_ERROR("Fifo reserve failure of %u bytes.\n", | |
409 | (unsigned) bytes); | |
410 | dump_stack(); | |
411 | return NULL; | |
412 | } | |
413 | ||
414 | return ret; | |
415 | } | |
416 | ||
fb1d9738 | 417 | static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state, |
b9eb1a61 | 418 | u32 __iomem *fifo_mem, |
fb1d9738 JB |
419 | uint32_t next_cmd, |
420 | uint32_t max, uint32_t min, uint32_t bytes) | |
421 | { | |
422 | uint32_t chunk_size = max - next_cmd; | |
423 | uint32_t rest; | |
424 | uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? | |
425 | fifo_state->dynamic_buffer : fifo_state->static_buffer; | |
426 | ||
427 | if (bytes < chunk_size) | |
428 | chunk_size = bytes; | |
429 | ||
430 | iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED); | |
431 | mb(); | |
432 | memcpy_toio(fifo_mem + (next_cmd >> 2), buffer, chunk_size); | |
433 | rest = bytes - chunk_size; | |
434 | if (rest) | |
435 | memcpy_toio(fifo_mem + (min >> 2), buffer + (chunk_size >> 2), | |
436 | rest); | |
437 | } | |
438 | ||
439 | static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state, | |
b9eb1a61 | 440 | u32 __iomem *fifo_mem, |
fb1d9738 JB |
441 | uint32_t next_cmd, |
442 | uint32_t max, uint32_t min, uint32_t bytes) | |
443 | { | |
444 | uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? | |
445 | fifo_state->dynamic_buffer : fifo_state->static_buffer; | |
446 | ||
447 | while (bytes > 0) { | |
448 | iowrite32(*buffer++, fifo_mem + (next_cmd >> 2)); | |
449 | next_cmd += sizeof(uint32_t); | |
450 | if (unlikely(next_cmd == max)) | |
451 | next_cmd = min; | |
452 | mb(); | |
453 | iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); | |
454 | mb(); | |
455 | bytes -= sizeof(uint32_t); | |
456 | } | |
457 | } | |
458 | ||
b9eb1a61 | 459 | static void vmw_local_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) |
fb1d9738 JB |
460 | { |
461 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; | |
b9eb1a61 | 462 | u32 __iomem *fifo_mem = dev_priv->mmio_virt; |
fb1d9738 JB |
463 | uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); |
464 | uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX); | |
465 | uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN); | |
466 | bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; | |
467 | ||
468 | BUG_ON((bytes & 3) != 0); | |
469 | BUG_ON(bytes > fifo_state->reserved_size); | |
470 | ||
471 | fifo_state->reserved_size = 0; | |
472 | ||
473 | if (fifo_state->using_bounce_buffer) { | |
474 | if (reserveable) | |
475 | vmw_fifo_res_copy(fifo_state, fifo_mem, | |
476 | next_cmd, max, min, bytes); | |
477 | else | |
478 | vmw_fifo_slow_copy(fifo_state, fifo_mem, | |
479 | next_cmd, max, min, bytes); | |
480 | ||
481 | if (fifo_state->dynamic_buffer) { | |
482 | vfree(fifo_state->dynamic_buffer); | |
483 | fifo_state->dynamic_buffer = NULL; | |
484 | } | |
485 | ||
486 | } | |
487 | ||
85b9e487 | 488 | down_write(&fifo_state->rwsem); |
fb1d9738 JB |
489 | if (fifo_state->using_bounce_buffer || reserveable) { |
490 | next_cmd += bytes; | |
491 | if (next_cmd >= max) | |
492 | next_cmd -= max - min; | |
493 | mb(); | |
494 | iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); | |
495 | } | |
496 | ||
497 | if (reserveable) | |
498 | iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED); | |
499 | mb(); | |
fb1d9738 | 500 | up_write(&fifo_state->rwsem); |
85b9e487 TH |
501 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); |
502 | mutex_unlock(&fifo_state->fifo_mutex); | |
fb1d9738 JB |
503 | } |
504 | ||
3eab3d9e TH |
505 | void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) |
506 | { | |
507 | if (dev_priv->cman) | |
508 | vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, false); | |
509 | else | |
510 | vmw_local_fifo_commit(dev_priv, bytes); | |
511 | } | |
512 | ||
513 | ||
514 | /** | |
515 | * vmw_fifo_commit_flush - Commit fifo space and flush any buffered commands. | |
516 | * | |
517 | * @dev_priv: Pointer to device private structure. | |
518 | * @bytes: Number of bytes to commit. | |
519 | */ | |
520 | static void vmw_fifo_commit_flush(struct vmw_private *dev_priv, uint32_t bytes) | |
521 | { | |
522 | if (dev_priv->cman) | |
523 | vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, true); | |
524 | else | |
525 | vmw_local_fifo_commit(dev_priv, bytes); | |
526 | } | |
527 | ||
528 | /** | |
529 | * vmw_fifo_flush - Flush any buffered commands and make sure command processing | |
530 | * starts. | |
531 | * | |
532 | * @dev_priv: Pointer to device private structure. | |
533 | * @interruptible: Whether to wait interruptible if function needs to sleep. | |
534 | */ | |
535 | int vmw_fifo_flush(struct vmw_private *dev_priv, bool interruptible) | |
536 | { | |
537 | might_sleep(); | |
538 | ||
539 | if (dev_priv->cman) | |
540 | return vmw_cmdbuf_cur_flush(dev_priv->cman, interruptible); | |
541 | else | |
542 | return 0; | |
543 | } | |
544 | ||
6bcd8d3c | 545 | int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno) |
fb1d9738 JB |
546 | { |
547 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; | |
548 | struct svga_fifo_cmd_fence *cmd_fence; | |
b9eb1a61 | 549 | u32 *fm; |
fb1d9738 | 550 | int ret = 0; |
b9eb1a61 | 551 | uint32_t bytes = sizeof(u32) + sizeof(*cmd_fence); |
fb1d9738 JB |
552 | |
553 | fm = vmw_fifo_reserve(dev_priv, bytes); | |
554 | if (unlikely(fm == NULL)) { | |
6bcd8d3c | 555 | *seqno = atomic_read(&dev_priv->marker_seq); |
fb1d9738 | 556 | ret = -ENOMEM; |
6bcd8d3c | 557 | (void)vmw_fallback_wait(dev_priv, false, true, *seqno, |
fb1d9738 JB |
558 | false, 3*HZ); |
559 | goto out_err; | |
560 | } | |
561 | ||
562 | do { | |
6bcd8d3c TH |
563 | *seqno = atomic_add_return(1, &dev_priv->marker_seq); |
564 | } while (*seqno == 0); | |
fb1d9738 JB |
565 | |
566 | if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) { | |
567 | ||
568 | /* | |
569 | * Don't request hardware to send a fence. The | |
570 | * waiting code in vmwgfx_irq.c will emulate this. | |
571 | */ | |
572 | ||
573 | vmw_fifo_commit(dev_priv, 0); | |
574 | return 0; | |
575 | } | |
576 | ||
b9eb1a61 TH |
577 | *fm++ = SVGA_CMD_FENCE; |
578 | cmd_fence = (struct svga_fifo_cmd_fence *) fm; | |
579 | cmd_fence->fence = *seqno; | |
3eab3d9e | 580 | vmw_fifo_commit_flush(dev_priv, bytes); |
6bcd8d3c TH |
581 | (void) vmw_marker_push(&fifo_state->marker_queue, *seqno); |
582 | vmw_update_seqno(dev_priv, fifo_state); | |
fb1d9738 JB |
583 | |
584 | out_err: | |
585 | return ret; | |
586 | } | |
e2fa3a76 TH |
587 | |
588 | /** | |
ddcda24e TH |
589 | * vmw_fifo_emit_dummy_legacy_query - emits a dummy query to the fifo using |
590 | * legacy query commands. | |
e2fa3a76 TH |
591 | * |
592 | * @dev_priv: The device private structure. | |
593 | * @cid: The hardware context id used for the query. | |
594 | * | |
ddcda24e | 595 | * See the vmw_fifo_emit_dummy_query documentation. |
e2fa3a76 | 596 | */ |
ddcda24e TH |
597 | static int vmw_fifo_emit_dummy_legacy_query(struct vmw_private *dev_priv, |
598 | uint32_t cid) | |
e2fa3a76 TH |
599 | { |
600 | /* | |
601 | * A query wait without a preceding query end will | |
602 | * actually finish all queries for this cid | |
603 | * without writing to the query result structure. | |
604 | */ | |
605 | ||
459d0fa7 | 606 | struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base; |
e2fa3a76 TH |
607 | struct { |
608 | SVGA3dCmdHeader header; | |
609 | SVGA3dCmdWaitForQuery body; | |
610 | } *cmd; | |
611 | ||
612 | cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd)); | |
613 | ||
614 | if (unlikely(cmd == NULL)) { | |
615 | DRM_ERROR("Out of fifo space for dummy query.\n"); | |
616 | return -ENOMEM; | |
617 | } | |
618 | ||
619 | cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY; | |
620 | cmd->header.size = sizeof(cmd->body); | |
621 | cmd->body.cid = cid; | |
622 | cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION; | |
623 | ||
624 | if (bo->mem.mem_type == TTM_PL_VRAM) { | |
625 | cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER; | |
626 | cmd->body.guestResult.offset = bo->offset; | |
627 | } else { | |
628 | cmd->body.guestResult.gmrId = bo->mem.start; | |
629 | cmd->body.guestResult.offset = 0; | |
630 | } | |
631 | ||
632 | vmw_fifo_commit(dev_priv, sizeof(*cmd)); | |
633 | ||
634 | return 0; | |
635 | } | |
ddcda24e TH |
636 | |
637 | /** | |
638 | * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using | |
639 | * guest-backed resource query commands. | |
640 | * | |
641 | * @dev_priv: The device private structure. | |
642 | * @cid: The hardware context id used for the query. | |
643 | * | |
644 | * See the vmw_fifo_emit_dummy_query documentation. | |
645 | */ | |
646 | static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv, | |
647 | uint32_t cid) | |
648 | { | |
649 | /* | |
650 | * A query wait without a preceding query end will | |
651 | * actually finish all queries for this cid | |
652 | * without writing to the query result structure. | |
653 | */ | |
654 | ||
459d0fa7 | 655 | struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base; |
ddcda24e TH |
656 | struct { |
657 | SVGA3dCmdHeader header; | |
658 | SVGA3dCmdWaitForGBQuery body; | |
659 | } *cmd; | |
660 | ||
661 | cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd)); | |
662 | ||
663 | if (unlikely(cmd == NULL)) { | |
664 | DRM_ERROR("Out of fifo space for dummy query.\n"); | |
665 | return -ENOMEM; | |
666 | } | |
667 | ||
668 | cmd->header.id = SVGA_3D_CMD_WAIT_FOR_GB_QUERY; | |
669 | cmd->header.size = sizeof(cmd->body); | |
670 | cmd->body.cid = cid; | |
671 | cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION; | |
672 | BUG_ON(bo->mem.mem_type != VMW_PL_MOB); | |
673 | cmd->body.mobid = bo->mem.start; | |
674 | cmd->body.offset = 0; | |
675 | ||
676 | vmw_fifo_commit(dev_priv, sizeof(*cmd)); | |
677 | ||
678 | return 0; | |
679 | } | |
680 | ||
681 | ||
682 | /** | |
683 | * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using | |
684 | * appropriate resource query commands. | |
685 | * | |
686 | * @dev_priv: The device private structure. | |
687 | * @cid: The hardware context id used for the query. | |
688 | * | |
689 | * This function is used to emit a dummy occlusion query with | |
690 | * no primitives rendered between query begin and query end. | |
691 | * It's used to provide a query barrier, in order to know that when | |
692 | * this query is finished, all preceding queries are also finished. | |
693 | * | |
694 | * A Query results structure should have been initialized at the start | |
695 | * of the dev_priv->dummy_query_bo buffer object. And that buffer object | |
696 | * must also be either reserved or pinned when this function is called. | |
697 | * | |
698 | * Returns -ENOMEM on failure to reserve fifo space. | |
699 | */ | |
700 | int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv, | |
701 | uint32_t cid) | |
702 | { | |
703 | if (dev_priv->has_mob) | |
704 | return vmw_fifo_emit_dummy_gb_query(dev_priv, cid); | |
705 | ||
706 | return vmw_fifo_emit_dummy_legacy_query(dev_priv, cid); | |
707 | } |