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fb1d9738 JB |
1 | /************************************************************************** |
2 | * | |
54fbde8a | 3 | * Copyright © 2009-2015 VMware, Inc., Palo Alto, CA., USA |
fb1d9738 JB |
4 | * All Rights Reserved. |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sub license, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial portions | |
16 | * of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | **************************************************************************/ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
fb1d9738 JB |
29 | #include "vmwgfx_drv.h" |
30 | ||
31 | #define VMW_FENCE_WRAP (1 << 24) | |
32 | ||
e9f0d76f | 33 | irqreturn_t vmw_irq_handler(int irq, void *arg) |
fb1d9738 JB |
34 | { |
35 | struct drm_device *dev = (struct drm_device *)arg; | |
36 | struct vmw_private *dev_priv = vmw_priv(dev); | |
57c5ee79 | 37 | uint32_t status, masked_status; |
fb1d9738 | 38 | |
fb1d9738 | 39 | status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); |
d2e8851a | 40 | masked_status = status & READ_ONCE(dev_priv->irq_mask); |
fb1d9738 | 41 | |
57c5ee79 TH |
42 | if (likely(status)) |
43 | outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); | |
ae2a1040 | 44 | |
d2e8851a | 45 | if (!status) |
57c5ee79 TH |
46 | return IRQ_NONE; |
47 | ||
48 | if (masked_status & (SVGA_IRQFLAG_ANY_FENCE | | |
49 | SVGA_IRQFLAG_FENCE_GOAL)) { | |
50 | vmw_fences_update(dev_priv->fman); | |
fb1d9738 | 51 | wake_up_all(&dev_priv->fence_queue); |
ae2a1040 | 52 | } |
57c5ee79 TH |
53 | |
54 | if (masked_status & SVGA_IRQFLAG_FIFO_PROGRESS) | |
fb1d9738 JB |
55 | wake_up_all(&dev_priv->fifo_queue); |
56 | ||
3eab3d9e TH |
57 | if (masked_status & (SVGA_IRQFLAG_COMMAND_BUFFER | |
58 | SVGA_IRQFLAG_ERROR)) | |
59 | vmw_cmdbuf_tasklet_schedule(dev_priv->cman); | |
fb1d9738 | 60 | |
57c5ee79 | 61 | return IRQ_HANDLED; |
fb1d9738 JB |
62 | } |
63 | ||
6bcd8d3c | 64 | static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno) |
fb1d9738 | 65 | { |
fb1d9738 | 66 | |
496eb6fd | 67 | return (vmw_read(dev_priv, SVGA_REG_BUSY) == 0); |
fb1d9738 JB |
68 | } |
69 | ||
6bcd8d3c | 70 | void vmw_update_seqno(struct vmw_private *dev_priv, |
1925d456 TH |
71 | struct vmw_fifo_state *fifo_state) |
72 | { | |
b76ff5ea TH |
73 | u32 *fifo_mem = dev_priv->mmio_virt; |
74 | uint32_t seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE); | |
1925d456 | 75 | |
6bcd8d3c TH |
76 | if (dev_priv->last_read_seqno != seqno) { |
77 | dev_priv->last_read_seqno = seqno; | |
78 | vmw_marker_pull(&fifo_state->marker_queue, seqno); | |
57c5ee79 | 79 | vmw_fences_update(dev_priv->fman); |
1925d456 TH |
80 | } |
81 | } | |
fb1d9738 | 82 | |
6bcd8d3c TH |
83 | bool vmw_seqno_passed(struct vmw_private *dev_priv, |
84 | uint32_t seqno) | |
fb1d9738 | 85 | { |
fb1d9738 JB |
86 | struct vmw_fifo_state *fifo_state; |
87 | bool ret; | |
88 | ||
6bcd8d3c | 89 | if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP)) |
fb1d9738 JB |
90 | return true; |
91 | ||
1925d456 | 92 | fifo_state = &dev_priv->fifo; |
6bcd8d3c TH |
93 | vmw_update_seqno(dev_priv, fifo_state); |
94 | if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP)) | |
fb1d9738 JB |
95 | return true; |
96 | ||
fb1d9738 | 97 | if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE) && |
6bcd8d3c | 98 | vmw_fifo_idle(dev_priv, seqno)) |
fb1d9738 JB |
99 | return true; |
100 | ||
fb1d9738 | 101 | /** |
6bcd8d3c | 102 | * Then check if the seqno is higher than what we've actually |
fb1d9738 JB |
103 | * emitted. Then the fence is stale and signaled. |
104 | */ | |
105 | ||
6bcd8d3c | 106 | ret = ((atomic_read(&dev_priv->marker_seq) - seqno) |
85b9e487 | 107 | > VMW_FENCE_WRAP); |
fb1d9738 JB |
108 | |
109 | return ret; | |
110 | } | |
111 | ||
112 | int vmw_fallback_wait(struct vmw_private *dev_priv, | |
113 | bool lazy, | |
114 | bool fifo_idle, | |
6bcd8d3c | 115 | uint32_t seqno, |
fb1d9738 JB |
116 | bool interruptible, |
117 | unsigned long timeout) | |
118 | { | |
119 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; | |
120 | ||
121 | uint32_t count = 0; | |
122 | uint32_t signal_seq; | |
123 | int ret; | |
124 | unsigned long end_jiffies = jiffies + timeout; | |
125 | bool (*wait_condition)(struct vmw_private *, uint32_t); | |
126 | DEFINE_WAIT(__wait); | |
127 | ||
128 | wait_condition = (fifo_idle) ? &vmw_fifo_idle : | |
6bcd8d3c | 129 | &vmw_seqno_passed; |
fb1d9738 JB |
130 | |
131 | /** | |
132 | * Block command submission while waiting for idle. | |
133 | */ | |
134 | ||
3eab3d9e | 135 | if (fifo_idle) { |
fb1d9738 | 136 | down_read(&fifo_state->rwsem); |
3eab3d9e TH |
137 | if (dev_priv->cman) { |
138 | ret = vmw_cmdbuf_idle(dev_priv->cman, interruptible, | |
139 | 10*HZ); | |
140 | if (ret) | |
141 | goto out_err; | |
142 | } | |
143 | } | |
144 | ||
6bcd8d3c | 145 | signal_seq = atomic_read(&dev_priv->marker_seq); |
fb1d9738 JB |
146 | ret = 0; |
147 | ||
148 | for (;;) { | |
149 | prepare_to_wait(&dev_priv->fence_queue, &__wait, | |
150 | (interruptible) ? | |
151 | TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
6bcd8d3c | 152 | if (wait_condition(dev_priv, seqno)) |
fb1d9738 JB |
153 | break; |
154 | if (time_after_eq(jiffies, end_jiffies)) { | |
155 | DRM_ERROR("SVGA device lockup.\n"); | |
156 | break; | |
157 | } | |
158 | if (lazy) | |
159 | schedule_timeout(1); | |
160 | else if ((++count & 0x0F) == 0) { | |
161 | /** | |
162 | * FIXME: Use schedule_hr_timeout here for | |
163 | * newer kernels and lower CPU utilization. | |
164 | */ | |
165 | ||
166 | __set_current_state(TASK_RUNNING); | |
167 | schedule(); | |
168 | __set_current_state((interruptible) ? | |
169 | TASK_INTERRUPTIBLE : | |
170 | TASK_UNINTERRUPTIBLE); | |
171 | } | |
172 | if (interruptible && signal_pending(current)) { | |
3d3a5b32 | 173 | ret = -ERESTARTSYS; |
fb1d9738 JB |
174 | break; |
175 | } | |
176 | } | |
177 | finish_wait(&dev_priv->fence_queue, &__wait); | |
178 | if (ret == 0 && fifo_idle) { | |
b76ff5ea TH |
179 | u32 *fifo_mem = dev_priv->mmio_virt; |
180 | ||
181 | vmw_mmio_write(signal_seq, fifo_mem + SVGA_FIFO_FENCE); | |
fb1d9738 JB |
182 | } |
183 | wake_up_all(&dev_priv->fence_queue); | |
3eab3d9e | 184 | out_err: |
fb1d9738 JB |
185 | if (fifo_idle) |
186 | up_read(&fifo_state->rwsem); | |
187 | ||
188 | return ret; | |
189 | } | |
190 | ||
d2e8851a TH |
191 | void vmw_generic_waiter_add(struct vmw_private *dev_priv, |
192 | u32 flag, int *waiter_count) | |
4f73a96b | 193 | { |
d2e8851a TH |
194 | spin_lock_bh(&dev_priv->waiter_lock); |
195 | if ((*waiter_count)++ == 0) { | |
196 | outl(flag, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); | |
197 | dev_priv->irq_mask |= flag; | |
57c5ee79 | 198 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); |
4f73a96b | 199 | } |
d2e8851a | 200 | spin_unlock_bh(&dev_priv->waiter_lock); |
4f73a96b TH |
201 | } |
202 | ||
d2e8851a TH |
203 | void vmw_generic_waiter_remove(struct vmw_private *dev_priv, |
204 | u32 flag, int *waiter_count) | |
4f73a96b | 205 | { |
d2e8851a TH |
206 | spin_lock_bh(&dev_priv->waiter_lock); |
207 | if (--(*waiter_count) == 0) { | |
208 | dev_priv->irq_mask &= ~flag; | |
57c5ee79 | 209 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); |
57c5ee79 | 210 | } |
d2e8851a | 211 | spin_unlock_bh(&dev_priv->waiter_lock); |
57c5ee79 TH |
212 | } |
213 | ||
d2e8851a TH |
214 | void vmw_seqno_waiter_add(struct vmw_private *dev_priv) |
215 | { | |
216 | vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_ANY_FENCE, | |
217 | &dev_priv->fence_queue_waiters); | |
218 | } | |
219 | ||
220 | void vmw_seqno_waiter_remove(struct vmw_private *dev_priv) | |
221 | { | |
222 | vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_ANY_FENCE, | |
223 | &dev_priv->fence_queue_waiters); | |
224 | } | |
57c5ee79 TH |
225 | |
226 | void vmw_goal_waiter_add(struct vmw_private *dev_priv) | |
227 | { | |
d2e8851a TH |
228 | vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_FENCE_GOAL, |
229 | &dev_priv->goal_queue_waiters); | |
57c5ee79 TH |
230 | } |
231 | ||
232 | void vmw_goal_waiter_remove(struct vmw_private *dev_priv) | |
233 | { | |
d2e8851a TH |
234 | vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_FENCE_GOAL, |
235 | &dev_priv->goal_queue_waiters); | |
4f73a96b TH |
236 | } |
237 | ||
6bcd8d3c TH |
238 | int vmw_wait_seqno(struct vmw_private *dev_priv, |
239 | bool lazy, uint32_t seqno, | |
240 | bool interruptible, unsigned long timeout) | |
fb1d9738 JB |
241 | { |
242 | long ret; | |
fb1d9738 JB |
243 | struct vmw_fifo_state *fifo = &dev_priv->fifo; |
244 | ||
6bcd8d3c | 245 | if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP)) |
fb1d9738 JB |
246 | return 0; |
247 | ||
6bcd8d3c | 248 | if (likely(vmw_seqno_passed(dev_priv, seqno))) |
fb1d9738 JB |
249 | return 0; |
250 | ||
251 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); | |
252 | ||
253 | if (!(fifo->capabilities & SVGA_FIFO_CAP_FENCE)) | |
6bcd8d3c | 254 | return vmw_fallback_wait(dev_priv, lazy, true, seqno, |
fb1d9738 JB |
255 | interruptible, timeout); |
256 | ||
257 | if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) | |
6bcd8d3c | 258 | return vmw_fallback_wait(dev_priv, lazy, false, seqno, |
fb1d9738 JB |
259 | interruptible, timeout); |
260 | ||
4f73a96b | 261 | vmw_seqno_waiter_add(dev_priv); |
fb1d9738 JB |
262 | |
263 | if (interruptible) | |
264 | ret = wait_event_interruptible_timeout | |
265 | (dev_priv->fence_queue, | |
6bcd8d3c | 266 | vmw_seqno_passed(dev_priv, seqno), |
fb1d9738 JB |
267 | timeout); |
268 | else | |
269 | ret = wait_event_timeout | |
270 | (dev_priv->fence_queue, | |
6bcd8d3c | 271 | vmw_seqno_passed(dev_priv, seqno), |
fb1d9738 JB |
272 | timeout); |
273 | ||
4f73a96b TH |
274 | vmw_seqno_waiter_remove(dev_priv); |
275 | ||
3d3a5b32 | 276 | if (unlikely(ret == 0)) |
fb1d9738 JB |
277 | ret = -EBUSY; |
278 | else if (likely(ret > 0)) | |
279 | ret = 0; | |
280 | ||
fb1d9738 JB |
281 | return ret; |
282 | } | |
283 | ||
284 | void vmw_irq_preinstall(struct drm_device *dev) | |
285 | { | |
286 | struct vmw_private *dev_priv = vmw_priv(dev); | |
287 | uint32_t status; | |
288 | ||
289 | if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) | |
290 | return; | |
291 | ||
fb1d9738 JB |
292 | status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); |
293 | outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); | |
294 | } | |
295 | ||
296 | int vmw_irq_postinstall(struct drm_device *dev) | |
297 | { | |
298 | return 0; | |
299 | } | |
300 | ||
301 | void vmw_irq_uninstall(struct drm_device *dev) | |
302 | { | |
303 | struct vmw_private *dev_priv = vmw_priv(dev); | |
304 | uint32_t status; | |
305 | ||
306 | if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) | |
307 | return; | |
308 | ||
fb1d9738 | 309 | vmw_write(dev_priv, SVGA_REG_IRQMASK, 0); |
fb1d9738 JB |
310 | |
311 | status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); | |
312 | outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); | |
313 | } |