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vmwgfx: Add present and readback ioctls
[deliverable/linux.git] / drivers / gpu / drm / vmwgfx / vmwgfx_kms.c
CommitLineData
fb1d9738
JB		 1/**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#include "vmwgfx_kms.h"
29
56d1c78d 30
fb1d9738
JB		 31/* Might need a hrtimer here? */
32#define VMWGFX_PRESENT_RATE ((HZ / 60 > 0) ? HZ / 60 : 1)
33
fb1d9738
JB		 34void vmw_display_unit_cleanup(struct vmw_display_unit *du)
35{
36 if (du->cursor_surface)
37 vmw_surface_unreference(&du->cursor_surface);
38 if (du->cursor_dmabuf)
39 vmw_dmabuf_unreference(&du->cursor_dmabuf);
40 drm_crtc_cleanup(&du->crtc);
41 drm_encoder_cleanup(&du->encoder);
42 drm_connector_cleanup(&du->connector);
43}
44
45/*
46 * Display Unit Cursor functions
47 */
48
49int vmw_cursor_update_image(struct vmw_private *dev_priv,
50 u32 *image, u32 width, u32 height,
51 u32 hotspotX, u32 hotspotY)
52{
53 struct {
54 u32 cmd;
55 SVGAFifoCmdDefineAlphaCursor cursor;
56 } *cmd;
57 u32 image_size = width * height * 4;
58 u32 cmd_size = sizeof(*cmd) + image_size;
59
60 if (!image)
61 return -EINVAL;
62
63 cmd = vmw_fifo_reserve(dev_priv, cmd_size);
64 if (unlikely(cmd == NULL)) {
65 DRM_ERROR("Fifo reserve failed.\n");
66 return -ENOMEM;
67 }
68
69 memset(cmd, 0, sizeof(*cmd));
70
71 memcpy(&cmd[1], image, image_size);
72
73 cmd->cmd = cpu_to_le32(SVGA_CMD_DEFINE_ALPHA_CURSOR);
74 cmd->cursor.id = cpu_to_le32(0);
75 cmd->cursor.width = cpu_to_le32(width);
76 cmd->cursor.height = cpu_to_le32(height);
77 cmd->cursor.hotspotX = cpu_to_le32(hotspotX);
78 cmd->cursor.hotspotY = cpu_to_le32(hotspotY);
79
80 vmw_fifo_commit(dev_priv, cmd_size);
81
82 return 0;
83}
84
85void vmw_cursor_update_position(struct vmw_private *dev_priv,
86 bool show, int x, int y)
87{
88 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
89 uint32_t count;
90
91 iowrite32(show ? 1 : 0, fifo_mem + SVGA_FIFO_CURSOR_ON);
92 iowrite32(x, fifo_mem + SVGA_FIFO_CURSOR_X);
93 iowrite32(y, fifo_mem + SVGA_FIFO_CURSOR_Y);
94 count = ioread32(fifo_mem + SVGA_FIFO_CURSOR_COUNT);
95 iowrite32(++count, fifo_mem + SVGA_FIFO_CURSOR_COUNT);
96}
97
98int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
99 uint32_t handle, uint32_t width, uint32_t height)
100{
101 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
102 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
103 struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
104 struct vmw_surface *surface = NULL;
105 struct vmw_dma_buffer *dmabuf = NULL;
106 int ret;
107
108 if (handle) {
7a73ba74
TH		 109 ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
110 handle, &surface);
fb1d9738
JB		 111 if (!ret) {
112 if (!surface->snooper.image) {
113 DRM_ERROR("surface not suitable for cursor\n");
114 return -EINVAL;
115 }
116 } else {
117 ret = vmw_user_dmabuf_lookup(tfile,
118 handle, &dmabuf);
119 if (ret) {
120 DRM_ERROR("failed to find surface or dmabuf: %i\n", ret);
121 return -EINVAL;
122 }
123 }
124 }
125
126 /* takedown old cursor */
127 if (du->cursor_surface) {
128 du->cursor_surface->snooper.crtc = NULL;
129 vmw_surface_unreference(&du->cursor_surface);
130 }
131 if (du->cursor_dmabuf)
132 vmw_dmabuf_unreference(&du->cursor_dmabuf);
133
134 /* setup new image */
135 if (surface) {
136 /* vmw_user_surface_lookup takes one reference */
137 du->cursor_surface = surface;
138
139 du->cursor_surface->snooper.crtc = crtc;
140 du->cursor_age = du->cursor_surface->snooper.age;
141 vmw_cursor_update_image(dev_priv, surface->snooper.image,
142 64, 64, du->hotspot_x, du->hotspot_y);
143 } else if (dmabuf) {
144 struct ttm_bo_kmap_obj map;
145 unsigned long kmap_offset;
146 unsigned long kmap_num;
147 void *virtual;
148 bool dummy;
149
150 /* vmw_user_surface_lookup takes one reference */
151 du->cursor_dmabuf = dmabuf;
152
153 kmap_offset = 0;
154 kmap_num = (64*64*4) >> PAGE_SHIFT;
155
156 ret = ttm_bo_reserve(&dmabuf->base, true, false, false, 0);
157 if (unlikely(ret != 0)) {
158 DRM_ERROR("reserve failed\n");
159 return -EINVAL;
160 }
161
162 ret = ttm_bo_kmap(&dmabuf->base, kmap_offset, kmap_num, &map);
163 if (unlikely(ret != 0))
164 goto err_unreserve;
165
166 virtual = ttm_kmap_obj_virtual(&map, &dummy);
167 vmw_cursor_update_image(dev_priv, virtual, 64, 64,
168 du->hotspot_x, du->hotspot_y);
169
170 ttm_bo_kunmap(&map);
171err_unreserve:
172 ttm_bo_unreserve(&dmabuf->base);
173
174 } else {
175 vmw_cursor_update_position(dev_priv, false, 0, 0);
176 return 0;
177 }
178
179 vmw_cursor_update_position(dev_priv, true, du->cursor_x, du->cursor_y);
180
181 return 0;
182}
183
184int vmw_du_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
185{
186 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
187 struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
188 bool shown = du->cursor_surface || du->cursor_dmabuf ? true : false;
189
190 du->cursor_x = x + crtc->x;
191 du->cursor_y = y + crtc->y;
192
193 vmw_cursor_update_position(dev_priv, shown,
194 du->cursor_x, du->cursor_y);
195
196 return 0;
197}
198
199void vmw_kms_cursor_snoop(struct vmw_surface *srf,
200 struct ttm_object_file *tfile,
201 struct ttm_buffer_object *bo,
202 SVGA3dCmdHeader *header)
203{
204 struct ttm_bo_kmap_obj map;
205 unsigned long kmap_offset;
206 unsigned long kmap_num;
207 SVGA3dCopyBox *box;
208 unsigned box_count;
209 void *virtual;
210 bool dummy;
211 struct vmw_dma_cmd {
212 SVGA3dCmdHeader header;
213 SVGA3dCmdSurfaceDMA dma;
214 } *cmd;
215 int ret;
216
217 cmd = container_of(header, struct vmw_dma_cmd, header);
218
219 /* No snooper installed */
220 if (!srf->snooper.image)
221 return;
222
223 if (cmd->dma.host.face != 0 || cmd->dma.host.mipmap != 0) {
224 DRM_ERROR("face and mipmap for cursors should never != 0\n");
225 return;
226 }
227
228 if (cmd->header.size < 64) {
229 DRM_ERROR("at least one full copy box must be given\n");
230 return;
231 }
232
233 box = (SVGA3dCopyBox *)&cmd[1];
234 box_count = (cmd->header.size - sizeof(SVGA3dCmdSurfaceDMA)) /
235 sizeof(SVGA3dCopyBox);
236
237 if (cmd->dma.guest.pitch != (64 * 4) ||
238 cmd->dma.guest.ptr.offset % PAGE_SIZE ||
239 box->x != 0 || box->y != 0 || box->z != 0 ||
240 box->srcx != 0 || box->srcy != 0 || box->srcz != 0 ||
241 box->w != 64 || box->h != 64 || box->d != 1 ||
242 box_count != 1) {
243 /* TODO handle none page aligned offsets */
244 /* TODO handle partial uploads and pitch != 256 */
245 /* TODO handle more then one copy (size != 64) */
25985edc 246 DRM_ERROR("lazy programmer, can't handle weird stuff\n");
fb1d9738
JB		 247 return;
248 }
249
250 kmap_offset = cmd->dma.guest.ptr.offset >> PAGE_SHIFT;
251 kmap_num = (64*64*4) >> PAGE_SHIFT;
252
253 ret = ttm_bo_reserve(bo, true, false, false, 0);
254 if (unlikely(ret != 0)) {
255 DRM_ERROR("reserve failed\n");
256 return;
257 }
258
259 ret = ttm_bo_kmap(bo, kmap_offset, kmap_num, &map);
260 if (unlikely(ret != 0))
261 goto err_unreserve;
262
263 virtual = ttm_kmap_obj_virtual(&map, &dummy);
264
265 memcpy(srf->snooper.image, virtual, 64*64*4);
266 srf->snooper.age++;
267
268 /* we can't call this function from this function since execbuf has
269 * reserved fifo space.
270 *
271 * if (srf->snooper.crtc)
272 * vmw_ldu_crtc_cursor_update_image(dev_priv,
273 * srf->snooper.image, 64, 64,
274 * du->hotspot_x, du->hotspot_y);
275 */
276
277 ttm_bo_kunmap(&map);
278err_unreserve:
279 ttm_bo_unreserve(bo);
280}
281
282void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv)
283{
284 struct drm_device *dev = dev_priv->dev;
285 struct vmw_display_unit *du;
286 struct drm_crtc *crtc;
287
288 mutex_lock(&dev->mode_config.mutex);
289
290 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
291 du = vmw_crtc_to_du(crtc);
292 if (!du->cursor_surface ||
293 du->cursor_age == du->cursor_surface->snooper.age)
294 continue;
295
296 du->cursor_age = du->cursor_surface->snooper.age;
297 vmw_cursor_update_image(dev_priv,
298 du->cursor_surface->snooper.image,
299 64, 64, du->hotspot_x, du->hotspot_y);
300 }
301
302 mutex_unlock(&dev->mode_config.mutex);
303}
304
305/*
306 * Generic framebuffer code
307 */
308
309int vmw_framebuffer_create_handle(struct drm_framebuffer *fb,
310 struct drm_file *file_priv,
311 unsigned int *handle)
312{
313 if (handle)
314 handle = 0;
315
316 return 0;
317}
318
319/*
320 * Surface framebuffer code
321 */
322
323#define vmw_framebuffer_to_vfbs(x) \
324 container_of(x, struct vmw_framebuffer_surface, base.base)
325
326struct vmw_framebuffer_surface {
327 struct vmw_framebuffer base;
328 struct vmw_surface *surface;
22ee861c 329 struct vmw_dma_buffer *buffer;
3a939a5e
TH		 330 struct list_head head;
331 struct drm_master *master;
fb1d9738
JB		 332};
333
334void vmw_framebuffer_surface_destroy(struct drm_framebuffer *framebuffer)
335{
3a939a5e 336 struct vmw_framebuffer_surface *vfbs =
fb1d9738 337 vmw_framebuffer_to_vfbs(framebuffer);
3a939a5e
TH		 338 struct vmw_master *vmaster = vmw_master(vfbs->master);
339
340
341 mutex_lock(&vmaster->fb_surf_mutex);
342 list_del(&vfbs->head);
343 mutex_unlock(&vmaster->fb_surf_mutex);
fb1d9738 344
3a939a5e 345 drm_master_put(&vfbs->master);
fb1d9738 346 drm_framebuffer_cleanup(framebuffer);
3a939a5e 347 vmw_surface_unreference(&vfbs->surface);
fb1d9738 348
3a939a5e 349 kfree(vfbs);
fb1d9738
JB		 350}
351
56d1c78d
JB		 352static int do_surface_dirty_sou(struct vmw_private *dev_priv,
353 struct vmw_framebuffer *framebuffer,
354 struct vmw_surface *surf,
355 unsigned flags, unsigned color,
356 struct drm_clip_rect *clips,
357 unsigned num_clips, int inc)
358{
359 int left = clips->x2, right = clips->x1;
360 int top = clips->y2, bottom = clips->y1;
361 size_t fifo_size;
362 int i;
363
364 struct {
365 SVGA3dCmdHeader header;
366 SVGA3dCmdBlitSurfaceToScreen body;
367 } *cmd;
368
369
370 fifo_size = sizeof(*cmd);
371 cmd = vmw_fifo_reserve(dev_priv, fifo_size);
372 if (unlikely(cmd == NULL)) {
373 DRM_ERROR("Fifo reserve failed.\n");
374 return -ENOMEM;
375 }
376
377 memset(cmd, 0, fifo_size);
378
379 cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
380 cmd->header.size = cpu_to_le32(sizeof(cmd->body));
381
382 cmd->body.srcImage.sid = cpu_to_le32(surf->res.id);
383 cmd->body.destScreenId = SVGA_ID_INVALID; /* virtual coords */
384
385 for (i = 0; i < num_clips; i++, clips += inc) {
386 left = min_t(int, left, (int)clips->x1);
387 right = max_t(int, right, (int)clips->x2);
388 top = min_t(int, top, (int)clips->y1);
389 bottom = max_t(int, bottom, (int)clips->y2);
390 }
391
392 cmd->body.srcRect.left = left;
393 cmd->body.srcRect.right = right;
394 cmd->body.srcRect.top = top;
395 cmd->body.srcRect.bottom = bottom;
396
397 cmd->body.destRect.left = left;
398 cmd->body.destRect.right = right;
399 cmd->body.destRect.top = top;
400 cmd->body.destRect.bottom = bottom;
401
402 vmw_fifo_commit(dev_priv, fifo_size);
403
5deb65cf
JB		 404 return 0;
405}
fb1d9738
JB		 406
407int vmw_framebuffer_surface_dirty(struct drm_framebuffer *framebuffer,
02b00162 408 struct drm_file *file_priv,
fb1d9738
JB		 409 unsigned flags, unsigned color,
410 struct drm_clip_rect *clips,
411 unsigned num_clips)
412{
413 struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
3a939a5e 414 struct vmw_master *vmaster = vmw_master(file_priv->master);
fb1d9738
JB		 415 struct vmw_framebuffer_surface *vfbs =
416 vmw_framebuffer_to_vfbs(framebuffer);
417 struct vmw_surface *surf = vfbs->surface;
418 struct drm_clip_rect norect;
5deb65cf 419 int ret, inc = 1;
fb1d9738 420
3a939a5e
TH		 421 if (unlikely(vfbs->master != file_priv->master))
422 return -EINVAL;
423
01e81419
JB		 424 /* Require ScreenObject support for 3D */
425 if (!dev_priv->sou_priv)
426 return -EINVAL;
427
3a939a5e
TH		 428 ret = ttm_read_lock(&vmaster->lock, true);
429 if (unlikely(ret != 0))
430 return ret;
431
fb1d9738
JB		 432 if (!num_clips) {
433 num_clips = 1;
434 clips = &norect;
435 norect.x1 = norect.y1 = 0;
436 norect.x2 = framebuffer->width;
437 norect.y2 = framebuffer->height;
438 } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
439 num_clips /= 2;
440 inc = 2; /* skip source rects */
441 }
442
01e81419
JB		 443 ret = do_surface_dirty_sou(dev_priv, &vfbs->base, surf,
444 flags, color,
445 clips, num_clips, inc);
fb1d9738 446
3a939a5e 447 ttm_read_unlock(&vmaster->lock);
fb1d9738
JB		 448 return 0;
449}
450
451static struct drm_framebuffer_funcs vmw_framebuffer_surface_funcs = {
452 .destroy = vmw_framebuffer_surface_destroy,
453 .dirty = vmw_framebuffer_surface_dirty,
454 .create_handle = vmw_framebuffer_create_handle,
455};
456
d3216a0c 457static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv,
3a939a5e 458 struct drm_file *file_priv,
d3216a0c
TH		 459 struct vmw_surface *surface,
460 struct vmw_framebuffer **out,
461 const struct drm_mode_fb_cmd
462 *mode_cmd)
fb1d9738
JB		 463
464{
465 struct drm_device *dev = dev_priv->dev;
466 struct vmw_framebuffer_surface *vfbs;
d3216a0c 467 enum SVGA3dSurfaceFormat format;
3a939a5e 468 struct vmw_master *vmaster = vmw_master(file_priv->master);
fb1d9738
JB		 469 int ret;
470
01e81419
JB		 471 /* 3D is only supported on HWv8 hosts which supports screen objects */
472 if (!dev_priv->sou_priv)
473 return -ENOSYS;
474
d3216a0c
TH		 475 /*
476 * Sanity checks.
477 */
478
479 if (unlikely(surface->mip_levels[0] != 1 ||
480 surface->num_sizes != 1 ||
481 surface->sizes[0].width < mode_cmd->width ||
482 surface->sizes[0].height < mode_cmd->height ||
483 surface->sizes[0].depth != 1)) {
484 DRM_ERROR("Incompatible surface dimensions "
485 "for requested mode.\n");
486 return -EINVAL;
487 }
488
489 switch (mode_cmd->depth) {
490 case 32:
491 format = SVGA3D_A8R8G8B8;
492 break;
493 case 24:
494 format = SVGA3D_X8R8G8B8;
495 break;
496 case 16:
497 format = SVGA3D_R5G6B5;
498 break;
499 case 15:
500 format = SVGA3D_A1R5G5B5;
501 break;
f01b7ba0
MD		 502 case 8:
503 format = SVGA3D_LUMINANCE8;
504 break;
d3216a0c
TH		 505 default:
506 DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
507 return -EINVAL;
508 }
509
510 if (unlikely(format != surface->format)) {
511 DRM_ERROR("Invalid surface format for requested mode.\n");
512 return -EINVAL;
513 }
514
fb1d9738
JB		 515 vfbs = kzalloc(sizeof(*vfbs), GFP_KERNEL);
516 if (!vfbs) {
517 ret = -ENOMEM;
518 goto out_err1;
519 }
520
521 ret = drm_framebuffer_init(dev, &vfbs->base.base,
522 &vmw_framebuffer_surface_funcs);
523 if (ret)
524 goto out_err2;
525
526 if (!vmw_surface_reference(surface)) {
527 DRM_ERROR("failed to reference surface %p\n", surface);
528 goto out_err3;
529 }
530
531 /* XXX get the first 3 from the surface info */
d3216a0c
TH		 532 vfbs->base.base.bits_per_pixel = mode_cmd->bpp;
533 vfbs->base.base.pitch = mode_cmd->pitch;
534 vfbs->base.base.depth = mode_cmd->depth;
535 vfbs->base.base.width = mode_cmd->width;
536 vfbs->base.base.height = mode_cmd->height;
fb1d9738 537 vfbs->surface = surface;
3a939a5e 538 vfbs->master = drm_master_get(file_priv->master);
3a939a5e
TH		 539
540 mutex_lock(&vmaster->fb_surf_mutex);
3a939a5e
TH		 541 list_add_tail(&vfbs->head, &vmaster->fb_surf);
542 mutex_unlock(&vmaster->fb_surf_mutex);
543
fb1d9738
JB		 544 *out = &vfbs->base;
545
546 return 0;
547
548out_err3:
549 drm_framebuffer_cleanup(&vfbs->base.base);
550out_err2:
551 kfree(vfbs);
552out_err1:
553 return ret;
554}
555
556/*
557 * Dmabuf framebuffer code
558 */
559
560#define vmw_framebuffer_to_vfbd(x) \
561 container_of(x, struct vmw_framebuffer_dmabuf, base.base)
562
563struct vmw_framebuffer_dmabuf {
564 struct vmw_framebuffer base;
565 struct vmw_dma_buffer *buffer;
56d1c78d 566 uint32_t handle;
fb1d9738
JB		 567};
568
569void vmw_framebuffer_dmabuf_destroy(struct drm_framebuffer *framebuffer)
570{
571 struct vmw_framebuffer_dmabuf *vfbd =
572 vmw_framebuffer_to_vfbd(framebuffer);
573
574 drm_framebuffer_cleanup(framebuffer);
575 vmw_dmabuf_unreference(&vfbd->buffer);
576
577 kfree(vfbd);
578}
579
5deb65cf
JB		 580static int do_dmabuf_dirty_ldu(struct vmw_private *dev_priv,
581 struct vmw_framebuffer *framebuffer,
582 struct vmw_dma_buffer *buffer,
583 unsigned flags, unsigned color,
584 struct drm_clip_rect *clips,
585 unsigned num_clips, int increment)
586{
587 size_t fifo_size;
588 int i;
589
590 struct {
591 uint32_t header;
592 SVGAFifoCmdUpdate body;
593 } *cmd;
594
595 fifo_size = sizeof(*cmd) * num_clips;
596 cmd = vmw_fifo_reserve(dev_priv, fifo_size);
597 if (unlikely(cmd == NULL)) {
598 DRM_ERROR("Fifo reserve failed.\n");
599 return -ENOMEM;
600 }
601
602 memset(cmd, 0, fifo_size);
603 for (i = 0; i < num_clips; i++, clips += increment) {
604 cmd[i].header = cpu_to_le32(SVGA_CMD_UPDATE);
605 cmd[i].body.x = cpu_to_le32(clips->x1);
606 cmd[i].body.y = cpu_to_le32(clips->y1);
607 cmd[i].body.width = cpu_to_le32(clips->x2 - clips->x1);
608 cmd[i].body.height = cpu_to_le32(clips->y2 - clips->y1);
609 }
610
611 vmw_fifo_commit(dev_priv, fifo_size);
612 return 0;
613}
614
56d1c78d
JB		 615static int do_dmabuf_dirty_sou(struct drm_file *file_priv,
616 struct vmw_private *dev_priv,
617 struct vmw_framebuffer *framebuffer,
618 struct vmw_dma_buffer *buffer,
619 unsigned flags, unsigned color,
620 struct drm_clip_rect *clips,
621 unsigned num_clips, int increment)
622{
623 struct vmw_framebuffer_dmabuf *vfbd =
624 vmw_framebuffer_to_vfbd(&framebuffer->base);
625 size_t fifo_size;
626 int i, ret;
627
628 struct {
629 uint32_t header;
630 SVGAFifoCmdDefineGMRFB body;
631 } *cmd;
632 struct {
633 uint32_t header;
634 SVGAFifoCmdBlitGMRFBToScreen body;
635 } *blits;
636
637 fifo_size = sizeof(*cmd) + sizeof(*blits) * num_clips;
638 cmd = kmalloc(fifo_size, GFP_KERNEL);
639 if (unlikely(cmd == NULL)) {
640 DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
641 return -ENOMEM;
642 }
643
644 memset(cmd, 0, fifo_size);
645 cmd->header = SVGA_CMD_DEFINE_GMRFB;
646 cmd->body.format.bitsPerPixel = framebuffer->base.bits_per_pixel;
647 cmd->body.format.colorDepth = framebuffer->base.depth;
648 cmd->body.format.reserved = 0;
649 cmd->body.bytesPerLine = framebuffer->base.pitch;
650 cmd->body.ptr.gmrId = vfbd->handle;
651 cmd->body.ptr.offset = 0;
652
653 blits = (void *)&cmd[1];
654 for (i = 0; i < num_clips; i++, clips += increment) {
655 blits[i].header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
656 blits[i].body.srcOrigin.x = clips->x1;
657 blits[i].body.srcOrigin.y = clips->y1;
658 blits[i].body.destRect.left = clips->x1;
659 blits[i].body.destRect.top = clips->y1;
660 blits[i].body.destRect.right = clips->x2;
661 blits[i].body.destRect.bottom = clips->y2;
662 }
663
664 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
665 fifo_size, 0, NULL);
666
667 kfree(cmd);
668
669 return ret;
670}
671
fb1d9738 672int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer,
02b00162 673 struct drm_file *file_priv,
fb1d9738
JB		 674 unsigned flags, unsigned color,
675 struct drm_clip_rect *clips,
676 unsigned num_clips)
677{
678 struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
3a939a5e 679 struct vmw_master *vmaster = vmw_master(file_priv->master);
5deb65cf
JB		 680 struct vmw_framebuffer_dmabuf *vfbd =
681 vmw_framebuffer_to_vfbd(framebuffer);
682 struct vmw_dma_buffer *dmabuf = vfbd->buffer;
fb1d9738 683 struct drm_clip_rect norect;
5deb65cf 684 int ret, increment = 1;
fb1d9738 685
3a939a5e
TH		 686 ret = ttm_read_lock(&vmaster->lock, true);
687 if (unlikely(ret != 0))
688 return ret;
689
df1c93ba 690 if (!num_clips) {
fb1d9738
JB		 691 num_clips = 1;
692 clips = &norect;
693 norect.x1 = norect.y1 = 0;
694 norect.x2 = framebuffer->width;
695 norect.y2 = framebuffer->height;
696 } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
697 num_clips /= 2;
698 increment = 2;
699 }
700
56d1c78d
JB		 701 if (dev_priv->ldu_priv) {
702 ret = do_dmabuf_dirty_ldu(dev_priv, &vfbd->base, dmabuf,
703 flags, color,
704 clips, num_clips, increment);
705 } else {
706 ret = do_dmabuf_dirty_sou(file_priv, dev_priv, &vfbd->base,
707 dmabuf, flags, color,
708 clips, num_clips, increment);
709 }
fb1d9738 710
3a939a5e 711 ttm_read_unlock(&vmaster->lock);
5deb65cf 712 return ret;
fb1d9738
JB		 713}
714
715static struct drm_framebuffer_funcs vmw_framebuffer_dmabuf_funcs = {
716 .destroy = vmw_framebuffer_dmabuf_destroy,
717 .dirty = vmw_framebuffer_dmabuf_dirty,
718 .create_handle = vmw_framebuffer_create_handle,
719};
720
497a3ff9
JB		 721/**
722 * Pin the dmabuffer to the start of vram.
723 */
fb1d9738
JB		 724static int vmw_framebuffer_dmabuf_pin(struct vmw_framebuffer *vfb)
725{
726 struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
727 struct vmw_framebuffer_dmabuf *vfbd =
728 vmw_framebuffer_to_vfbd(&vfb->base);
729 int ret;
730
56d1c78d
JB		 731 /* This code should not be used with screen objects */
732 BUG_ON(dev_priv->sou_priv);
d7e1958d 733
fb1d9738
JB		 734 vmw_overlay_pause_all(dev_priv);
735
d991ef03 736 ret = vmw_dmabuf_to_start_of_vram(dev_priv, vfbd->buffer, true, false);
fb1d9738 737
fb1d9738
JB		 738 vmw_overlay_resume_all(dev_priv);
739
316ab13a
JB		 740 WARN_ON(ret != 0);
741
fb1d9738
JB		 742 return 0;
743}
744
745static int vmw_framebuffer_dmabuf_unpin(struct vmw_framebuffer *vfb)
746{
747 struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
748 struct vmw_framebuffer_dmabuf *vfbd =
749 vmw_framebuffer_to_vfbd(&vfb->base);
750
751 if (!vfbd->buffer) {
752 WARN_ON(!vfbd->buffer);
753 return 0;
754 }
755
d991ef03 756 return vmw_dmabuf_unpin(dev_priv, vfbd->buffer, false);
fb1d9738
JB		 757}
758
d3216a0c
TH		 759static int vmw_kms_new_framebuffer_dmabuf(struct vmw_private *dev_priv,
760 struct vmw_dma_buffer *dmabuf,
761 struct vmw_framebuffer **out,
762 const struct drm_mode_fb_cmd
763 *mode_cmd)
fb1d9738
JB		 764
765{
766 struct drm_device *dev = dev_priv->dev;
767 struct vmw_framebuffer_dmabuf *vfbd;
d3216a0c 768 unsigned int requested_size;
fb1d9738
JB		 769 int ret;
770
d3216a0c
TH		 771 requested_size = mode_cmd->height * mode_cmd->pitch;
772 if (unlikely(requested_size > dmabuf->base.num_pages * PAGE_SIZE)) {
773 DRM_ERROR("Screen buffer object size is too small "
774 "for requested mode.\n");
775 return -EINVAL;
776 }
777
fb1d9738
JB		 778 vfbd = kzalloc(sizeof(*vfbd), GFP_KERNEL);
779 if (!vfbd) {
780 ret = -ENOMEM;
781 goto out_err1;
782 }
783
784 ret = drm_framebuffer_init(dev, &vfbd->base.base,
785 &vmw_framebuffer_dmabuf_funcs);
786 if (ret)
787 goto out_err2;
788
789 if (!vmw_dmabuf_reference(dmabuf)) {
790 DRM_ERROR("failed to reference dmabuf %p\n", dmabuf);
791 goto out_err3;
792 }
793
d3216a0c
TH		 794 vfbd->base.base.bits_per_pixel = mode_cmd->bpp;
795 vfbd->base.base.pitch = mode_cmd->pitch;
796 vfbd->base.base.depth = mode_cmd->depth;
797 vfbd->base.base.width = mode_cmd->width;
798 vfbd->base.base.height = mode_cmd->height;
56d1c78d
JB		 799 if (!dev_priv->sou_priv) {
800 vfbd->base.pin = vmw_framebuffer_dmabuf_pin;
801 vfbd->base.unpin = vmw_framebuffer_dmabuf_unpin;
802 }
2fcd5a73 803 vfbd->base.dmabuf = true;
fb1d9738 804 vfbd->buffer = dmabuf;
56d1c78d 805 vfbd->handle = mode_cmd->handle;
fb1d9738
JB		 806 *out = &vfbd->base;
807
808 return 0;
809
810out_err3:
811 drm_framebuffer_cleanup(&vfbd->base.base);
812out_err2:
813 kfree(vfbd);
814out_err1:
815 return ret;
816}
817
818/*
819 * Generic Kernel modesetting functions
820 */
821
822static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
823 struct drm_file *file_priv,
824 struct drm_mode_fb_cmd *mode_cmd)
825{
826 struct vmw_private *dev_priv = vmw_priv(dev);
827 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
828 struct vmw_framebuffer *vfb = NULL;
829 struct vmw_surface *surface = NULL;
830 struct vmw_dma_buffer *bo = NULL;
e133e737 831 u64 required_size;
fb1d9738
JB		 832 int ret;
833
d3216a0c
TH		 834 /**
835 * This code should be conditioned on Screen Objects not being used.
836 * If screen objects are used, we can allocate a GMR to hold the
837 * requested framebuffer.
838 */
839
840 required_size = mode_cmd->pitch * mode_cmd->height;
e133e737 841 if (unlikely(required_size > (u64) dev_priv->vram_size)) {
d3216a0c
TH		 842 DRM_ERROR("VRAM size is too small for requested mode.\n");
843 return NULL;
844 }
845
846 /**
847 * End conditioned code.
848 */
849
7a73ba74
TH		 850 ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
851 mode_cmd->handle, &surface);
fb1d9738
JB		 852 if (ret)
853 goto try_dmabuf;
854
5ffdb658
JB		 855 if (!surface->scanout)
856 goto err_not_scanout;
857
3a939a5e
TH		 858 ret = vmw_kms_new_framebuffer_surface(dev_priv, file_priv, surface,
859 &vfb, mode_cmd);
fb1d9738
JB		 860
861 /* vmw_user_surface_lookup takes one ref so does new_fb */
862 vmw_surface_unreference(&surface);
863
864 if (ret) {
865 DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
cce13ff7 866 return ERR_PTR(ret);
fb1d9738
JB		 867 }
868 return &vfb->base;
869
870try_dmabuf:
871 DRM_INFO("%s: trying buffer\n", __func__);
872
873 ret = vmw_user_dmabuf_lookup(tfile, mode_cmd->handle, &bo);
874 if (ret) {
875 DRM_ERROR("failed to find buffer: %i\n", ret);
cce13ff7 876 return ERR_PTR(-ENOENT);
fb1d9738
JB		 877 }
878
879 ret = vmw_kms_new_framebuffer_dmabuf(dev_priv, bo, &vfb,
d3216a0c 880 mode_cmd);
fb1d9738
JB		 881
882 /* vmw_user_dmabuf_lookup takes one ref so does new_fb */
883 vmw_dmabuf_unreference(&bo);
884
885 if (ret) {
886 DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
cce13ff7 887 return ERR_PTR(ret);
fb1d9738
JB		 888 }
889
890 return &vfb->base;
5ffdb658
JB		 891
892err_not_scanout:
893 DRM_ERROR("surface not marked as scanout\n");
894 /* vmw_user_surface_lookup takes one ref */
895 vmw_surface_unreference(&surface);
896
cce13ff7 897 return ERR_PTR(-EINVAL);
fb1d9738
JB		 898}
899
fb1d9738
JB		 900static struct drm_mode_config_funcs vmw_kms_funcs = {
901 .fb_create = vmw_kms_fb_create,
fb1d9738
JB		 902};
903
2fcd5a73
JB		 904int vmw_kms_present(struct vmw_private *dev_priv,
905 struct drm_file *file_priv,
906 struct vmw_framebuffer *vfb,
907 struct vmw_surface *surface,
908 uint32_t sid,
909 int32_t destX, int32_t destY,
910 struct drm_vmw_rect *clips,
911 uint32_t num_clips)
912{
913 size_t fifo_size;
914 int i, ret;
915
916 struct {
917 SVGA3dCmdHeader header;
918 SVGA3dCmdBlitSurfaceToScreen body;
919 } *cmd;
920 SVGASignedRect *blits;
921
922 BUG_ON(surface == NULL);
923 BUG_ON(!clips || !num_clips);
924
925 fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
926 cmd = kmalloc(fifo_size, GFP_KERNEL);
927 if (unlikely(cmd == NULL)) {
928 DRM_ERROR("Failed to allocate temporary fifo memory.\n");
929 return -ENOMEM;
930 }
931
932 memset(cmd, 0, fifo_size);
933
934 cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
935 cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
936
937 cmd->body.srcImage.sid = sid;
938 cmd->body.destScreenId = SVGA_ID_INVALID; /* virtual coords */
939
940 cmd->body.srcRect.left = 0;
941 cmd->body.srcRect.right = surface->sizes[0].width;
942 cmd->body.srcRect.top = 0;
943 cmd->body.srcRect.bottom = surface->sizes[0].height;
944
945 cmd->body.destRect.left = destX;
946 cmd->body.destRect.right = destX + surface->sizes[0].width;
947 cmd->body.destRect.top = destY;
948 cmd->body.destRect.bottom = destY + surface->sizes[0].height;
949
950 blits = (SVGASignedRect *)&cmd[1];
951 for (i = 0; i < num_clips; i++) {
952 blits[i].left = clips[i].x;
953 blits[i].right = clips[i].x + clips[i].w;
954 blits[i].top = clips[i].y;
955 blits[i].bottom = clips[i].y + clips[i].h;
956 }
957
958 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
959 fifo_size, 0, NULL);
960
961 kfree(cmd);
962
963 return ret;
964}
965
966int vmw_kms_readback(struct vmw_private *dev_priv,
967 struct drm_file *file_priv,
968 struct vmw_framebuffer *vfb,
969 struct drm_vmw_fence_rep __user *user_fence_rep,
970 struct drm_vmw_rect *clips,
971 uint32_t num_clips)
972{
973 struct vmw_framebuffer_dmabuf *vfbd =
974 vmw_framebuffer_to_vfbd(&vfb->base);
975 struct vmw_dma_buffer *dmabuf = vfbd->buffer;
976 struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
977 struct drm_crtc *crtc;
978 size_t fifo_size;
979 int i, k, ret, num_units, blits_pos;
980
981 struct {
982 uint32_t header;
983 SVGAFifoCmdDefineGMRFB body;
984 } *cmd;
985 struct {
986 uint32_t header;
987 SVGAFifoCmdBlitScreenToGMRFB body;
988 } *blits;
989
990 num_units = 0;
991 list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
992 if (crtc->fb != &vfb->base)
993 continue;
994 units[num_units++] = vmw_crtc_to_du(crtc);
995 }
996
997 BUG_ON(dmabuf == NULL);
998 BUG_ON(!clips || !num_clips);
999
1000 /* take a safe guess at fifo size */
1001 fifo_size = sizeof(*cmd) + sizeof(*blits) * num_clips * num_units;
1002 cmd = kmalloc(fifo_size, GFP_KERNEL);
1003 if (unlikely(cmd == NULL)) {
1004 DRM_ERROR("Failed to allocate temporary fifo memory.\n");
1005 return -ENOMEM;
1006 }
1007
1008 memset(cmd, 0, fifo_size);
1009 cmd->header = SVGA_CMD_DEFINE_GMRFB;
1010 cmd->body.format.bitsPerPixel = vfb->base.bits_per_pixel;
1011 cmd->body.format.colorDepth = vfb->base.depth;
1012 cmd->body.format.reserved = 0;
1013 cmd->body.bytesPerLine = vfb->base.pitch;
1014 cmd->body.ptr.gmrId = vfbd->handle;
1015 cmd->body.ptr.offset = 0;
1016
1017 blits = (void *)&cmd[1];
1018 blits_pos = 0;
1019 for (i = 0; i < num_units; i++) {
1020 struct drm_vmw_rect *c = clips;
1021 for (k = 0; k < num_clips; k++, c++) {
1022 /* transform clip coords to crtc origin based coords */
1023 int clip_x1 = c->x - units[i]->crtc.x;
1024 int clip_x2 = c->x - units[i]->crtc.x + c->w;
1025 int clip_y1 = c->y - units[i]->crtc.y;
1026 int clip_y2 = c->y - units[i]->crtc.y + c->h;
1027 int dest_x = c->x;
1028 int dest_y = c->y;
1029
1030 /* compensate for clipping, we negate
1031 * a negative number and add that.
1032 */
1033 if (clip_x1 < 0)
1034 dest_x += -clip_x1;
1035 if (clip_y1 < 0)
1036 dest_y += -clip_y1;
1037
1038 /* clip */
1039 clip_x1 = max(clip_x1, 0);
1040 clip_y1 = max(clip_y1, 0);
1041 clip_x2 = min(clip_x2, units[i]->crtc.mode.hdisplay);
1042 clip_y2 = min(clip_y2, units[i]->crtc.mode.vdisplay);
1043
1044 /* and cull any rects that misses the crtc */
1045 if (clip_x1 >= units[i]->crtc.mode.hdisplay ||
1046 clip_y1 >= units[i]->crtc.mode.vdisplay ||
1047 clip_x2 <= 0 || clip_y2 <= 0)
1048 continue;
1049
1050 blits[blits_pos].header = SVGA_CMD_BLIT_SCREEN_TO_GMRFB;
1051 blits[blits_pos].body.srcScreenId = units[i]->unit;
1052 blits[blits_pos].body.destOrigin.x = dest_x;
1053 blits[blits_pos].body.destOrigin.y = dest_y;
1054
1055 blits[blits_pos].body.srcRect.left = clip_x1;
1056 blits[blits_pos].body.srcRect.top = clip_y1;
1057 blits[blits_pos].body.srcRect.right = clip_x2;
1058 blits[blits_pos].body.srcRect.bottom = clip_y2;
1059 blits_pos++;
1060 }
1061 }
1062 /* reset size here and use calculated exact size from loops */
1063 fifo_size = sizeof(*cmd) + sizeof(*blits) * blits_pos;
1064
1065 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd, fifo_size,
1066 0, user_fence_rep);
1067
1068 kfree(cmd);
1069
1070 return ret;
1071}
1072
fb1d9738
JB		 1073int vmw_kms_init(struct vmw_private *dev_priv)
1074{
1075 struct drm_device *dev = dev_priv->dev;
1076 int ret;
1077
1078 drm_mode_config_init(dev);
1079 dev->mode_config.funcs = &vmw_kms_funcs;
3bef3572
JB		 1080 dev->mode_config.min_width = 1;
1081 dev->mode_config.min_height = 1;
7e71f8a5
JB		 1082 /* assumed largest fb size */
1083 dev->mode_config.max_width = 8192;
1084 dev->mode_config.max_height = 8192;
fb1d9738 1085
56d1c78d
JB		 1086 ret = vmw_kms_init_screen_object_display(dev_priv);
1087 if (ret) /* Fallback */
1088 (void)vmw_kms_init_legacy_display_system(dev_priv);
fb1d9738
JB		 1089
1090 return 0;
1091}
1092
1093int vmw_kms_close(struct vmw_private *dev_priv)
1094{
1095 /*
1096 * Docs says we should take the lock before calling this function
1097 * but since it destroys encoders and our destructor calls
1098 * drm_encoder_cleanup which takes the lock we deadlock.
1099 */
1100 drm_mode_config_cleanup(dev_priv->dev);
1101 vmw_kms_close_legacy_display_system(dev_priv);
1102 return 0;
1103}
1104
1105int vmw_kms_cursor_bypass_ioctl(struct drm_device *dev, void *data,
1106 struct drm_file *file_priv)
1107{
1108 struct drm_vmw_cursor_bypass_arg *arg = data;
1109 struct vmw_display_unit *du;
1110 struct drm_mode_object *obj;
1111 struct drm_crtc *crtc;
1112 int ret = 0;
1113
1114
1115 mutex_lock(&dev->mode_config.mutex);
1116 if (arg->flags & DRM_VMW_CURSOR_BYPASS_ALL) {
1117
1118 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1119 du = vmw_crtc_to_du(crtc);
1120 du->hotspot_x = arg->xhot;
1121 du->hotspot_y = arg->yhot;
1122 }
1123
1124 mutex_unlock(&dev->mode_config.mutex);
1125 return 0;
1126 }
1127
1128 obj = drm_mode_object_find(dev, arg->crtc_id, DRM_MODE_OBJECT_CRTC);
1129 if (!obj) {
1130 ret = -EINVAL;
1131 goto out;
1132 }
1133
1134 crtc = obj_to_crtc(obj);
1135 du = vmw_crtc_to_du(crtc);
1136
1137 du->hotspot_x = arg->xhot;
1138 du->hotspot_y = arg->yhot;
1139
1140out:
1141 mutex_unlock(&dev->mode_config.mutex);
1142
1143 return ret;
1144}
1145
0bef23f9 1146int vmw_kms_write_svga(struct vmw_private *vmw_priv,
d7e1958d 1147 unsigned width, unsigned height, unsigned pitch,
6558429b 1148 unsigned bpp, unsigned depth)
fb1d9738 1149{
d7e1958d
JB		 1150 if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
1151 vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);
1152 else if (vmw_fifo_have_pitchlock(vmw_priv))
1153 iowrite32(pitch, vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
1154 vmw_write(vmw_priv, SVGA_REG_WIDTH, width);
1155 vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);
6558429b 1156 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);
0bef23f9
MD		 1157
1158 if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) {
1159 DRM_ERROR("Invalid depth %u for %u bpp, host expects %u\n",
1160 depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH));
1161 return -EINVAL;
1162 }
1163
1164 return 0;
d7e1958d 1165}
fb1d9738 1166
d7e1958d
JB		 1167int vmw_kms_save_vga(struct vmw_private *vmw_priv)
1168{
7c4f7780
TH		 1169 struct vmw_vga_topology_state *save;
1170 uint32_t i;
1171
fb1d9738
JB		 1172 vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH);
1173 vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT);
7c4f7780 1174 vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL);
d7e1958d
JB		 1175 if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
1176 vmw_priv->vga_pitchlock =
7c4f7780 1177 vmw_read(vmw_priv, SVGA_REG_PITCHLOCK);
d7e1958d 1178 else if (vmw_fifo_have_pitchlock(vmw_priv))
7c4f7780
TH		 1179 vmw_priv->vga_pitchlock = ioread32(vmw_priv->mmio_virt +
1180 SVGA_FIFO_PITCHLOCK);
1181
1182 if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
1183 return 0;
fb1d9738 1184
7c4f7780
TH		 1185 vmw_priv->num_displays = vmw_read(vmw_priv,
1186 SVGA_REG_NUM_GUEST_DISPLAYS);
1187
029e50bf
TH		 1188 if (vmw_priv->num_displays == 0)
1189 vmw_priv->num_displays = 1;
1190
7c4f7780
TH		 1191 for (i = 0; i < vmw_priv->num_displays; ++i) {
1192 save = &vmw_priv->vga_save[i];
1193 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
1194 save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY);
1195 save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X);
1196 save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y);
1197 save->width = vmw_read(vmw_priv, SVGA_REG_DISPLAY_WIDTH);
1198 save->height = vmw_read(vmw_priv, SVGA_REG_DISPLAY_HEIGHT);
1199 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
30c78bb8
TH		 1200 if (i == 0 && vmw_priv->num_displays == 1 &&
1201 save->width == 0 && save->height == 0) {
1202
1203 /*
1204 * It should be fairly safe to assume that these
1205 * values are uninitialized.
1206 */
1207
1208 save->width = vmw_priv->vga_width - save->pos_x;
1209 save->height = vmw_priv->vga_height - save->pos_y;
1210 }
7c4f7780 1211 }
30c78bb8 1212
fb1d9738
JB		 1213 return 0;
1214}
1215
1216int vmw_kms_restore_vga(struct vmw_private *vmw_priv)
1217{
7c4f7780
TH		 1218 struct vmw_vga_topology_state *save;
1219 uint32_t i;
1220
fb1d9738
JB		 1221 vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width);
1222 vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height);
7c4f7780 1223 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp);
d7e1958d
JB		 1224 if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
1225 vmw_write(vmw_priv, SVGA_REG_PITCHLOCK,
1226 vmw_priv->vga_pitchlock);
1227 else if (vmw_fifo_have_pitchlock(vmw_priv))
1228 iowrite32(vmw_priv->vga_pitchlock,
1229 vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
fb1d9738 1230
7c4f7780
TH		 1231 if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
1232 return 0;
1233
1234 for (i = 0; i < vmw_priv->num_displays; ++i) {
1235 save = &vmw_priv->vga_save[i];
1236 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
1237 vmw_write(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY, save->primary);
1238 vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_X, save->pos_x);
1239 vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y, save->pos_y);
1240 vmw_write(vmw_priv, SVGA_REG_DISPLAY_WIDTH, save->width);
1241 vmw_write(vmw_priv, SVGA_REG_DISPLAY_HEIGHT, save->height);
1242 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
1243 }
1244
fb1d9738
JB		 1245 return 0;
1246}
d8bd19d2 1247
e133e737
TH		 1248bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,
1249 uint32_t pitch,
1250 uint32_t height)
1251{
1252 return ((u64) pitch * (u64) height) < (u64) dev_priv->vram_size;
1253}
1254
7a1c2f6c
TH		 1255u32 vmw_get_vblank_counter(struct drm_device *dev, int crtc)
1256{
1257 return 0;
1258}
626ab771
JB		 1259
1260
1261/*
1262 * Small shared kms functions.
1263 */
1264
1265int vmw_du_update_layout(struct vmw_private *dev_priv, unsigned num,
1266 struct drm_vmw_rect *rects)
1267{
1268 struct drm_device *dev = dev_priv->dev;
1269 struct vmw_display_unit *du;
1270 struct drm_connector *con;
1271 int i;
1272
1273 mutex_lock(&dev->mode_config.mutex);
1274
1275#if 0
1276 DRM_INFO("%s: new layout ", __func__);
1277 for (i = 0; i < (int)num; i++)
1278 DRM_INFO("(%i, %i %ux%u) ", rects[i].x, rects[i].y,
1279 rects[i].w, rects[i].h);
1280 DRM_INFO("\n");
1281#else
1282 (void)i;
1283#endif
1284
1285 list_for_each_entry(con, &dev->mode_config.connector_list, head) {
1286 du = vmw_connector_to_du(con);
1287 if (num > du->unit) {
1288 du->pref_width = rects[du->unit].w;
1289 du->pref_height = rects[du->unit].h;
1290 du->pref_active = true;
1291 } else {
1292 du->pref_width = 800;
1293 du->pref_height = 600;
1294 du->pref_active = false;
1295 }
1296 con->status = vmw_du_connector_detect(con, true);
1297 }
1298
1299 mutex_unlock(&dev->mode_config.mutex);
1300
1301 return 0;
1302}
1303
1304void vmw_du_crtc_save(struct drm_crtc *crtc)
1305{
1306}
1307
1308void vmw_du_crtc_restore(struct drm_crtc *crtc)
1309{
1310}
1311
1312void vmw_du_crtc_gamma_set(struct drm_crtc *crtc,
1313 u16 *r, u16 *g, u16 *b,
1314 uint32_t start, uint32_t size)
1315{
1316 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
1317 int i;
1318
1319 for (i = 0; i < size; i++) {
1320 DRM_DEBUG("%d r/g/b = 0x%04x / 0x%04x / 0x%04x\n", i,
1321 r[i], g[i], b[i]);
1322 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 0, r[i] >> 8);
1323 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 1, g[i] >> 8);
1324 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 2, b[i] >> 8);
1325 }
1326}
1327
1328void vmw_du_connector_dpms(struct drm_connector *connector, int mode)
1329{
1330}
1331
1332void vmw_du_connector_save(struct drm_connector *connector)
1333{
1334}
1335
1336void vmw_du_connector_restore(struct drm_connector *connector)
1337{
1338}
1339
1340enum drm_connector_status
1341vmw_du_connector_detect(struct drm_connector *connector, bool force)
1342{
1343 uint32_t num_displays;
1344 struct drm_device *dev = connector->dev;
1345 struct vmw_private *dev_priv = vmw_priv(dev);
1346
1347 mutex_lock(&dev_priv->hw_mutex);
1348 num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);
1349 mutex_unlock(&dev_priv->hw_mutex);
1350
1351 return ((vmw_connector_to_du(connector)->unit < num_displays) ?
1352 connector_status_connected : connector_status_disconnected);
1353}
1354
1355static struct drm_display_mode vmw_kms_connector_builtin[] = {
1356 /* 640x480@60Hz */
1357 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
1358 752, 800, 0, 480, 489, 492, 525, 0,
1359 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
1360 /* 800x600@60Hz */
1361 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
1362 968, 1056, 0, 600, 601, 605, 628, 0,
1363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1364 /* 1024x768@60Hz */
1365 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
1366 1184, 1344, 0, 768, 771, 777, 806, 0,
1367 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
1368 /* 1152x864@75Hz */
1369 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
1370 1344, 1600, 0, 864, 865, 868, 900, 0,
1371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1372 /* 1280x768@60Hz */
1373 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
1374 1472, 1664, 0, 768, 771, 778, 798, 0,
1375 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1376 /* 1280x800@60Hz */
1377 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
1378 1480, 1680, 0, 800, 803, 809, 831, 0,
1379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
1380 /* 1280x960@60Hz */
1381 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
1382 1488, 1800, 0, 960, 961, 964, 1000, 0,
1383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1384 /* 1280x1024@60Hz */
1385 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
1386 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
1387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1388 /* 1360x768@60Hz */
1389 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
1390 1536, 1792, 0, 768, 771, 777, 795, 0,
1391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1392 /* 1440x1050@60Hz */
1393 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
1394 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
1395 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1396 /* 1440x900@60Hz */
1397 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
1398 1672, 1904, 0, 900, 903, 909, 934, 0,
1399 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1400 /* 1600x1200@60Hz */
1401 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
1402 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1404 /* 1680x1050@60Hz */
1405 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
1406 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
1407 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1408 /* 1792x1344@60Hz */
1409 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
1410 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
1411 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1412 /* 1853x1392@60Hz */
1413 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
1414 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
1415 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1416 /* 1920x1200@60Hz */
1417 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
1418 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
1419 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1420 /* 1920x1440@60Hz */
1421 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
1422 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
1423 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1424 /* 2560x1600@60Hz */
1425 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
1426 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
1427 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1428 /* Terminate */
1429 { DRM_MODE("", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) },
1430};
1431
1432int vmw_du_connector_fill_modes(struct drm_connector *connector,
1433 uint32_t max_width, uint32_t max_height)
1434{
1435 struct vmw_display_unit *du = vmw_connector_to_du(connector);
1436 struct drm_device *dev = connector->dev;
1437 struct vmw_private *dev_priv = vmw_priv(dev);
1438 struct drm_display_mode *mode = NULL;
1439 struct drm_display_mode *bmode;
1440 struct drm_display_mode prefmode = { DRM_MODE("preferred",
1441 DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
1442 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1443 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)
1444 };
1445 int i;
1446
1447 /* Add preferred mode */
1448 {
1449 mode = drm_mode_duplicate(dev, &prefmode);
1450 if (!mode)
1451 return 0;
1452 mode->hdisplay = du->pref_width;
1453 mode->vdisplay = du->pref_height;
1454 mode->vrefresh = drm_mode_vrefresh(mode);
1455 if (vmw_kms_validate_mode_vram(dev_priv, mode->hdisplay * 2,
1456 mode->vdisplay)) {
1457 drm_mode_probed_add(connector, mode);
1458
1459 if (du->pref_mode) {
1460 list_del_init(&du->pref_mode->head);
1461 drm_mode_destroy(dev, du->pref_mode);
1462 }
1463
1464 du->pref_mode = mode;
1465 }
1466 }
1467
1468 for (i = 0; vmw_kms_connector_builtin[i].type != 0; i++) {
1469 bmode = &vmw_kms_connector_builtin[i];
1470 if (bmode->hdisplay > max_width ||
1471 bmode->vdisplay > max_height)
1472 continue;
1473
1474 if (!vmw_kms_validate_mode_vram(dev_priv, bmode->hdisplay * 2,
1475 bmode->vdisplay))
1476 continue;
1477
1478 mode = drm_mode_duplicate(dev, bmode);
1479 if (!mode)
1480 return 0;
1481 mode->vrefresh = drm_mode_vrefresh(mode);
1482
1483 drm_mode_probed_add(connector, mode);
1484 }
1485
1486 drm_mode_connector_list_update(connector);
1487
1488 return 1;
1489}
1490
1491int vmw_du_connector_set_property(struct drm_connector *connector,
1492 struct drm_property *property,
1493 uint64_t val)
1494{
1495 return 0;
1496}
Linux kernel - Deliverables
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