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drm: add an fb creation ioctl that takes a pixel format v5
[deliverable/linux.git] / drivers / gpu / drm / vmwgfx / vmwgfx_kms.c
CommitLineData
fb1d9738
JB		 1/**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#include "vmwgfx_kms.h"
29
56d1c78d 30
fb1d9738
JB		 31/* Might need a hrtimer here? */
32#define VMWGFX_PRESENT_RATE ((HZ / 60 > 0) ? HZ / 60 : 1)
33
fb1d9738
JB		 34void vmw_display_unit_cleanup(struct vmw_display_unit *du)
35{
36 if (du->cursor_surface)
37 vmw_surface_unreference(&du->cursor_surface);
38 if (du->cursor_dmabuf)
39 vmw_dmabuf_unreference(&du->cursor_dmabuf);
40 drm_crtc_cleanup(&du->crtc);
41 drm_encoder_cleanup(&du->encoder);
42 drm_connector_cleanup(&du->connector);
43}
44
45/*
46 * Display Unit Cursor functions
47 */
48
49int vmw_cursor_update_image(struct vmw_private *dev_priv,
50 u32 *image, u32 width, u32 height,
51 u32 hotspotX, u32 hotspotY)
52{
53 struct {
54 u32 cmd;
55 SVGAFifoCmdDefineAlphaCursor cursor;
56 } *cmd;
57 u32 image_size = width * height * 4;
58 u32 cmd_size = sizeof(*cmd) + image_size;
59
60 if (!image)
61 return -EINVAL;
62
63 cmd = vmw_fifo_reserve(dev_priv, cmd_size);
64 if (unlikely(cmd == NULL)) {
65 DRM_ERROR("Fifo reserve failed.\n");
66 return -ENOMEM;
67 }
68
69 memset(cmd, 0, sizeof(*cmd));
70
71 memcpy(&cmd[1], image, image_size);
72
73 cmd->cmd = cpu_to_le32(SVGA_CMD_DEFINE_ALPHA_CURSOR);
74 cmd->cursor.id = cpu_to_le32(0);
75 cmd->cursor.width = cpu_to_le32(width);
76 cmd->cursor.height = cpu_to_le32(height);
77 cmd->cursor.hotspotX = cpu_to_le32(hotspotX);
78 cmd->cursor.hotspotY = cpu_to_le32(hotspotY);
79
80 vmw_fifo_commit(dev_priv, cmd_size);
81
82 return 0;
83}
84
85void vmw_cursor_update_position(struct vmw_private *dev_priv,
86 bool show, int x, int y)
87{
88 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
89 uint32_t count;
90
91 iowrite32(show ? 1 : 0, fifo_mem + SVGA_FIFO_CURSOR_ON);
92 iowrite32(x, fifo_mem + SVGA_FIFO_CURSOR_X);
93 iowrite32(y, fifo_mem + SVGA_FIFO_CURSOR_Y);
94 count = ioread32(fifo_mem + SVGA_FIFO_CURSOR_COUNT);
95 iowrite32(++count, fifo_mem + SVGA_FIFO_CURSOR_COUNT);
96}
97
98int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
99 uint32_t handle, uint32_t width, uint32_t height)
100{
101 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
102 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
103 struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
104 struct vmw_surface *surface = NULL;
105 struct vmw_dma_buffer *dmabuf = NULL;
106 int ret;
107
108 if (handle) {
7a73ba74
TH		 109 ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
110 handle, &surface);
fb1d9738
JB		 111 if (!ret) {
112 if (!surface->snooper.image) {
113 DRM_ERROR("surface not suitable for cursor\n");
e5c8dbb8 114 vmw_surface_unreference(&surface);
fb1d9738
JB		 115 return -EINVAL;
116 }
117 } else {
118 ret = vmw_user_dmabuf_lookup(tfile,
119 handle, &dmabuf);
120 if (ret) {
121 DRM_ERROR("failed to find surface or dmabuf: %i\n", ret);
122 return -EINVAL;
123 }
124 }
125 }
126
127 /* takedown old cursor */
128 if (du->cursor_surface) {
129 du->cursor_surface->snooper.crtc = NULL;
130 vmw_surface_unreference(&du->cursor_surface);
131 }
132 if (du->cursor_dmabuf)
133 vmw_dmabuf_unreference(&du->cursor_dmabuf);
134
135 /* setup new image */
136 if (surface) {
137 /* vmw_user_surface_lookup takes one reference */
138 du->cursor_surface = surface;
139
140 du->cursor_surface->snooper.crtc = crtc;
141 du->cursor_age = du->cursor_surface->snooper.age;
142 vmw_cursor_update_image(dev_priv, surface->snooper.image,
143 64, 64, du->hotspot_x, du->hotspot_y);
144 } else if (dmabuf) {
145 struct ttm_bo_kmap_obj map;
146 unsigned long kmap_offset;
147 unsigned long kmap_num;
148 void *virtual;
149 bool dummy;
150
151 /* vmw_user_surface_lookup takes one reference */
152 du->cursor_dmabuf = dmabuf;
153
154 kmap_offset = 0;
155 kmap_num = (64*64*4) >> PAGE_SHIFT;
156
157 ret = ttm_bo_reserve(&dmabuf->base, true, false, false, 0);
158 if (unlikely(ret != 0)) {
159 DRM_ERROR("reserve failed\n");
160 return -EINVAL;
161 }
162
163 ret = ttm_bo_kmap(&dmabuf->base, kmap_offset, kmap_num, &map);
164 if (unlikely(ret != 0))
165 goto err_unreserve;
166
167 virtual = ttm_kmap_obj_virtual(&map, &dummy);
168 vmw_cursor_update_image(dev_priv, virtual, 64, 64,
169 du->hotspot_x, du->hotspot_y);
170
171 ttm_bo_kunmap(&map);
172err_unreserve:
173 ttm_bo_unreserve(&dmabuf->base);
174
175 } else {
176 vmw_cursor_update_position(dev_priv, false, 0, 0);
177 return 0;
178 }
179
da7653d6
TH		 180 vmw_cursor_update_position(dev_priv, true,
181 du->cursor_x + du->hotspot_x,
182 du->cursor_y + du->hotspot_y);
fb1d9738
JB		 183
184 return 0;
185}
186
187int vmw_du_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
188{
189 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
190 struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
191 bool shown = du->cursor_surface || du->cursor_dmabuf ? true : false;
192
193 du->cursor_x = x + crtc->x;
194 du->cursor_y = y + crtc->y;
195
196 vmw_cursor_update_position(dev_priv, shown,
da7653d6
TH		 197 du->cursor_x + du->hotspot_x,
198 du->cursor_y + du->hotspot_y);
fb1d9738
JB		 199
200 return 0;
201}
202
203void vmw_kms_cursor_snoop(struct vmw_surface *srf,
204 struct ttm_object_file *tfile,
205 struct ttm_buffer_object *bo,
206 SVGA3dCmdHeader *header)
207{
208 struct ttm_bo_kmap_obj map;
209 unsigned long kmap_offset;
210 unsigned long kmap_num;
211 SVGA3dCopyBox *box;
212 unsigned box_count;
213 void *virtual;
214 bool dummy;
215 struct vmw_dma_cmd {
216 SVGA3dCmdHeader header;
217 SVGA3dCmdSurfaceDMA dma;
218 } *cmd;
2ac86371 219 int i, ret;
fb1d9738
JB		 220
221 cmd = container_of(header, struct vmw_dma_cmd, header);
222
223 /* No snooper installed */
224 if (!srf->snooper.image)
225 return;
226
227 if (cmd->dma.host.face != 0 || cmd->dma.host.mipmap != 0) {
228 DRM_ERROR("face and mipmap for cursors should never != 0\n");
229 return;
230 }
231
232 if (cmd->header.size < 64) {
233 DRM_ERROR("at least one full copy box must be given\n");
234 return;
235 }
236
237 box = (SVGA3dCopyBox *)&cmd[1];
238 box_count = (cmd->header.size - sizeof(SVGA3dCmdSurfaceDMA)) /
239 sizeof(SVGA3dCopyBox);
240
2ac86371 241 if (cmd->dma.guest.ptr.offset % PAGE_SIZE ||
fb1d9738
JB		 242 box->x != 0 || box->y != 0 || box->z != 0 ||
243 box->srcx != 0 || box->srcy != 0 || box->srcz != 0 ||
2ac86371 244 box->d != 1 || box_count != 1) {
fb1d9738 245 /* TODO handle none page aligned offsets */
2ac86371
JB		 246 /* TODO handle more dst & src != 0 */
247 /* TODO handle more then one copy */
248 DRM_ERROR("Cant snoop dma request for cursor!\n");
249 DRM_ERROR("(%u, %u, %u) (%u, %u, %u) (%ux%ux%u) %u %u\n",
250 box->srcx, box->srcy, box->srcz,
251 box->x, box->y, box->z,
252 box->w, box->h, box->d, box_count,
253 cmd->dma.guest.ptr.offset);
fb1d9738
JB		 254 return;
255 }
256
257 kmap_offset = cmd->dma.guest.ptr.offset >> PAGE_SHIFT;
258 kmap_num = (64*64*4) >> PAGE_SHIFT;
259
260 ret = ttm_bo_reserve(bo, true, false, false, 0);
261 if (unlikely(ret != 0)) {
262 DRM_ERROR("reserve failed\n");
263 return;
264 }
265
266 ret = ttm_bo_kmap(bo, kmap_offset, kmap_num, &map);
267 if (unlikely(ret != 0))
268 goto err_unreserve;
269
270 virtual = ttm_kmap_obj_virtual(&map, &dummy);
271
2ac86371
JB		 272 if (box->w == 64 && cmd->dma.guest.pitch == 64*4) {
273 memcpy(srf->snooper.image, virtual, 64*64*4);
274 } else {
275 /* Image is unsigned pointer. */
276 for (i = 0; i < box->h; i++)
277 memcpy(srf->snooper.image + i * 64,
278 virtual + i * cmd->dma.guest.pitch,
279 box->w * 4);
280 }
281
fb1d9738
JB		 282 srf->snooper.age++;
283
284 /* we can't call this function from this function since execbuf has
285 * reserved fifo space.
286 *
287 * if (srf->snooper.crtc)
288 * vmw_ldu_crtc_cursor_update_image(dev_priv,
289 * srf->snooper.image, 64, 64,
290 * du->hotspot_x, du->hotspot_y);
291 */
292
293 ttm_bo_kunmap(&map);
294err_unreserve:
295 ttm_bo_unreserve(bo);
296}
297
298void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv)
299{
300 struct drm_device *dev = dev_priv->dev;
301 struct vmw_display_unit *du;
302 struct drm_crtc *crtc;
303
304 mutex_lock(&dev->mode_config.mutex);
305
306 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
307 du = vmw_crtc_to_du(crtc);
308 if (!du->cursor_surface ||
309 du->cursor_age == du->cursor_surface->snooper.age)
310 continue;
311
312 du->cursor_age = du->cursor_surface->snooper.age;
313 vmw_cursor_update_image(dev_priv,
314 du->cursor_surface->snooper.image,
315 64, 64, du->hotspot_x, du->hotspot_y);
316 }
317
318 mutex_unlock(&dev->mode_config.mutex);
319}
320
321/*
322 * Generic framebuffer code
323 */
324
325int vmw_framebuffer_create_handle(struct drm_framebuffer *fb,
326 struct drm_file *file_priv,
327 unsigned int *handle)
328{
329 if (handle)
330 handle = 0;
331
332 return 0;
333}
334
335/*
336 * Surface framebuffer code
337 */
338
339#define vmw_framebuffer_to_vfbs(x) \
340 container_of(x, struct vmw_framebuffer_surface, base.base)
341
342struct vmw_framebuffer_surface {
343 struct vmw_framebuffer base;
344 struct vmw_surface *surface;
22ee861c 345 struct vmw_dma_buffer *buffer;
3a939a5e
TH		 346 struct list_head head;
347 struct drm_master *master;
fb1d9738
JB		 348};
349
350void vmw_framebuffer_surface_destroy(struct drm_framebuffer *framebuffer)
351{
3a939a5e 352 struct vmw_framebuffer_surface *vfbs =
fb1d9738 353 vmw_framebuffer_to_vfbs(framebuffer);
3a939a5e
TH		 354 struct vmw_master *vmaster = vmw_master(vfbs->master);
355
356
357 mutex_lock(&vmaster->fb_surf_mutex);
358 list_del(&vfbs->head);
359 mutex_unlock(&vmaster->fb_surf_mutex);
fb1d9738 360
3a939a5e 361 drm_master_put(&vfbs->master);
fb1d9738 362 drm_framebuffer_cleanup(framebuffer);
3a939a5e 363 vmw_surface_unreference(&vfbs->surface);
90ff18bc 364 ttm_base_object_unref(&vfbs->base.user_obj);
fb1d9738 365
3a939a5e 366 kfree(vfbs);
fb1d9738
JB		 367}
368
56d1c78d 369static int do_surface_dirty_sou(struct vmw_private *dev_priv,
90ff18bc 370 struct drm_file *file_priv,
56d1c78d 371 struct vmw_framebuffer *framebuffer,
56d1c78d
JB		 372 unsigned flags, unsigned color,
373 struct drm_clip_rect *clips,
374 unsigned num_clips, int inc)
375{
c6ca8391
JB		 376 struct drm_clip_rect *clips_ptr;
377 struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
378 struct drm_crtc *crtc;
56d1c78d 379 size_t fifo_size;
c6ca8391
JB		 380 int i, num_units;
381 int ret = 0; /* silence warning */
382 int left, right, top, bottom;
56d1c78d
JB		 383
384 struct {
385 SVGA3dCmdHeader header;
386 SVGA3dCmdBlitSurfaceToScreen body;
387 } *cmd;
c6ca8391 388 SVGASignedRect *blits;
56d1c78d
JB		 389
390
c6ca8391
JB		 391 num_units = 0;
392 list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list,
393 head) {
394 if (crtc->fb != &framebuffer->base)
395 continue;
396 units[num_units++] = vmw_crtc_to_du(crtc);
397 }
398
c6ca8391
JB		 399 BUG_ON(!clips || !num_clips);
400
401 fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
90ff18bc 402 cmd = kzalloc(fifo_size, GFP_KERNEL);
56d1c78d 403 if (unlikely(cmd == NULL)) {
90ff18bc 404 DRM_ERROR("Temporary fifo memory alloc failed.\n");
56d1c78d
JB		 405 return -ENOMEM;
406 }
407
c6ca8391
JB		 408 left = clips->x1;
409 right = clips->x2;
410 top = clips->y1;
411 bottom = clips->y2;
412
413 clips_ptr = clips;
414 for (i = 1; i < num_clips; i++, clips_ptr += inc) {
415 left = min_t(int, left, (int)clips_ptr->x1);
416 right = max_t(int, right, (int)clips_ptr->x2);
417 top = min_t(int, top, (int)clips_ptr->y1);
418 bottom = max_t(int, bottom, (int)clips_ptr->y2);
56d1c78d
JB		 419 }
420
c6ca8391
JB		 421 /* only need to do this once */
422 memset(cmd, 0, fifo_size);
423 cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
424 cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
425
56d1c78d
JB		 426 cmd->body.srcRect.left = left;
427 cmd->body.srcRect.right = right;
428 cmd->body.srcRect.top = top;
429 cmd->body.srcRect.bottom = bottom;
430
c6ca8391
JB		 431 clips_ptr = clips;
432 blits = (SVGASignedRect *)&cmd[1];
433 for (i = 0; i < num_clips; i++, clips_ptr += inc) {
434 blits[i].left = clips_ptr->x1 - left;
435 blits[i].right = clips_ptr->x2 - left;
436 blits[i].top = clips_ptr->y1 - top;
437 blits[i].bottom = clips_ptr->y2 - top;
438 }
439
440 /* do per unit writing, reuse fifo for each */
441 for (i = 0; i < num_units; i++) {
442 struct vmw_display_unit *unit = units[i];
443 int clip_x1 = left - unit->crtc.x;
444 int clip_y1 = top - unit->crtc.y;
445 int clip_x2 = right - unit->crtc.x;
446 int clip_y2 = bottom - unit->crtc.y;
447
448 /* skip any crtcs that misses the clip region */
449 if (clip_x1 >= unit->crtc.mode.hdisplay ||
450 clip_y1 >= unit->crtc.mode.vdisplay ||
451 clip_x2 <= 0 || clip_y2 <= 0)
452 continue;
453
454 /* need to reset sid as it is changed by execbuf */
455 cmd->body.srcImage.sid = cpu_to_le32(framebuffer->user_handle);
456
457 cmd->body.destScreenId = unit->unit;
458
459 /*
460 * The blit command is a lot more resilient then the
461 * readback command when it comes to clip rects. So its
462 * okay to go out of bounds.
463 */
464
465 cmd->body.destRect.left = clip_x1;
466 cmd->body.destRect.right = clip_x2;
467 cmd->body.destRect.top = clip_y1;
468 cmd->body.destRect.bottom = clip_y2;
469
470
471 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
472 fifo_size, 0, NULL);
473
474 if (unlikely(ret != 0))
475 break;
476 }
56d1c78d 477
90ff18bc 478 kfree(cmd);
56d1c78d 479
90ff18bc 480 return ret;
5deb65cf 481}
fb1d9738
JB		 482
483int vmw_framebuffer_surface_dirty(struct drm_framebuffer *framebuffer,
02b00162 484 struct drm_file *file_priv,
fb1d9738
JB		 485 unsigned flags, unsigned color,
486 struct drm_clip_rect *clips,
487 unsigned num_clips)
488{
489 struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
3a939a5e 490 struct vmw_master *vmaster = vmw_master(file_priv->master);
fb1d9738
JB		 491 struct vmw_framebuffer_surface *vfbs =
492 vmw_framebuffer_to_vfbs(framebuffer);
fb1d9738 493 struct drm_clip_rect norect;
5deb65cf 494 int ret, inc = 1;
fb1d9738 495
3a939a5e
TH		 496 if (unlikely(vfbs->master != file_priv->master))
497 return -EINVAL;
498
01e81419
JB		 499 /* Require ScreenObject support for 3D */
500 if (!dev_priv->sou_priv)
501 return -EINVAL;
502
3a939a5e
TH		 503 ret = ttm_read_lock(&vmaster->lock, true);
504 if (unlikely(ret != 0))
505 return ret;
506
fb1d9738
JB		 507 if (!num_clips) {
508 num_clips = 1;
509 clips = &norect;
510 norect.x1 = norect.y1 = 0;
511 norect.x2 = framebuffer->width;
512 norect.y2 = framebuffer->height;
513 } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
514 num_clips /= 2;
515 inc = 2; /* skip source rects */
516 }
517
c5c42360 518 ret = do_surface_dirty_sou(dev_priv, file_priv, &vfbs->base,
01e81419
JB		 519 flags, color,
520 clips, num_clips, inc);
fb1d9738 521
3a939a5e 522 ttm_read_unlock(&vmaster->lock);
fb1d9738
JB		 523 return 0;
524}
525
526static struct drm_framebuffer_funcs vmw_framebuffer_surface_funcs = {
527 .destroy = vmw_framebuffer_surface_destroy,
528 .dirty = vmw_framebuffer_surface_dirty,
529 .create_handle = vmw_framebuffer_create_handle,
530};
531
d3216a0c 532static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv,
3a939a5e 533 struct drm_file *file_priv,
d3216a0c
TH		 534 struct vmw_surface *surface,
535 struct vmw_framebuffer **out,
536 const struct drm_mode_fb_cmd
537 *mode_cmd)
fb1d9738
JB		 538
539{
540 struct drm_device *dev = dev_priv->dev;
541 struct vmw_framebuffer_surface *vfbs;
d3216a0c 542 enum SVGA3dSurfaceFormat format;
3a939a5e 543 struct vmw_master *vmaster = vmw_master(file_priv->master);
fb1d9738
JB		 544 int ret;
545
01e81419
JB		 546 /* 3D is only supported on HWv8 hosts which supports screen objects */
547 if (!dev_priv->sou_priv)
548 return -ENOSYS;
549
d3216a0c
TH		 550 /*
551 * Sanity checks.
552 */
553
554 if (unlikely(surface->mip_levels[0] != 1 ||
555 surface->num_sizes != 1 ||
556 surface->sizes[0].width < mode_cmd->width ||
557 surface->sizes[0].height < mode_cmd->height ||
558 surface->sizes[0].depth != 1)) {
559 DRM_ERROR("Incompatible surface dimensions "
560 "for requested mode.\n");
561 return -EINVAL;
562 }
563
564 switch (mode_cmd->depth) {
565 case 32:
566 format = SVGA3D_A8R8G8B8;
567 break;
568 case 24:
569 format = SVGA3D_X8R8G8B8;
570 break;
571 case 16:
572 format = SVGA3D_R5G6B5;
573 break;
574 case 15:
575 format = SVGA3D_A1R5G5B5;
576 break;
f01b7ba0
MD		 577 case 8:
578 format = SVGA3D_LUMINANCE8;
579 break;
d3216a0c
TH		 580 default:
581 DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
582 return -EINVAL;
583 }
584
585 if (unlikely(format != surface->format)) {
586 DRM_ERROR("Invalid surface format for requested mode.\n");
587 return -EINVAL;
588 }
589
fb1d9738
JB		 590 vfbs = kzalloc(sizeof(*vfbs), GFP_KERNEL);
591 if (!vfbs) {
592 ret = -ENOMEM;
593 goto out_err1;
594 }
595
596 ret = drm_framebuffer_init(dev, &vfbs->base.base,
597 &vmw_framebuffer_surface_funcs);
598 if (ret)
599 goto out_err2;
600
601 if (!vmw_surface_reference(surface)) {
602 DRM_ERROR("failed to reference surface %p\n", surface);
603 goto out_err3;
604 }
605
606 /* XXX get the first 3 from the surface info */
d3216a0c
TH		 607 vfbs->base.base.bits_per_pixel = mode_cmd->bpp;
608 vfbs->base.base.pitch = mode_cmd->pitch;
609 vfbs->base.base.depth = mode_cmd->depth;
610 vfbs->base.base.width = mode_cmd->width;
611 vfbs->base.base.height = mode_cmd->height;
fb1d9738 612 vfbs->surface = surface;
90ff18bc 613 vfbs->base.user_handle = mode_cmd->handle;
3a939a5e 614 vfbs->master = drm_master_get(file_priv->master);
3a939a5e
TH		 615
616 mutex_lock(&vmaster->fb_surf_mutex);
3a939a5e
TH		 617 list_add_tail(&vfbs->head, &vmaster->fb_surf);
618 mutex_unlock(&vmaster->fb_surf_mutex);
619
fb1d9738
JB		 620 *out = &vfbs->base;
621
622 return 0;
623
624out_err3:
625 drm_framebuffer_cleanup(&vfbs->base.base);
626out_err2:
627 kfree(vfbs);
628out_err1:
629 return ret;
630}
631
632/*
633 * Dmabuf framebuffer code
634 */
635
636#define vmw_framebuffer_to_vfbd(x) \
637 container_of(x, struct vmw_framebuffer_dmabuf, base.base)
638
639struct vmw_framebuffer_dmabuf {
640 struct vmw_framebuffer base;
641 struct vmw_dma_buffer *buffer;
642};
643
644void vmw_framebuffer_dmabuf_destroy(struct drm_framebuffer *framebuffer)
645{
646 struct vmw_framebuffer_dmabuf *vfbd =
647 vmw_framebuffer_to_vfbd(framebuffer);
648
649 drm_framebuffer_cleanup(framebuffer);
650 vmw_dmabuf_unreference(&vfbd->buffer);
90ff18bc 651 ttm_base_object_unref(&vfbd->base.user_obj);
fb1d9738
JB		 652
653 kfree(vfbd);
654}
655
5deb65cf
JB		 656static int do_dmabuf_dirty_ldu(struct vmw_private *dev_priv,
657 struct vmw_framebuffer *framebuffer,
5deb65cf
JB		 658 unsigned flags, unsigned color,
659 struct drm_clip_rect *clips,
660 unsigned num_clips, int increment)
661{
662 size_t fifo_size;
663 int i;
664
665 struct {
666 uint32_t header;
667 SVGAFifoCmdUpdate body;
668 } *cmd;
669
670 fifo_size = sizeof(*cmd) * num_clips;
671 cmd = vmw_fifo_reserve(dev_priv, fifo_size);
672 if (unlikely(cmd == NULL)) {
673 DRM_ERROR("Fifo reserve failed.\n");
674 return -ENOMEM;
675 }
676
677 memset(cmd, 0, fifo_size);
678 for (i = 0; i < num_clips; i++, clips += increment) {
679 cmd[i].header = cpu_to_le32(SVGA_CMD_UPDATE);
680 cmd[i].body.x = cpu_to_le32(clips->x1);
681 cmd[i].body.y = cpu_to_le32(clips->y1);
682 cmd[i].body.width = cpu_to_le32(clips->x2 - clips->x1);
683 cmd[i].body.height = cpu_to_le32(clips->y2 - clips->y1);
684 }
685
686 vmw_fifo_commit(dev_priv, fifo_size);
687 return 0;
688}
689
c6ca8391
JB		 690static int do_dmabuf_define_gmrfb(struct drm_file *file_priv,
691 struct vmw_private *dev_priv,
692 struct vmw_framebuffer *framebuffer)
56d1c78d 693{
64fc9944 694 int depth = framebuffer->base.depth;
56d1c78d 695 size_t fifo_size;
c6ca8391 696 int ret;
56d1c78d
JB		 697
698 struct {
699 uint32_t header;
700 SVGAFifoCmdDefineGMRFB body;
701 } *cmd;
56d1c78d 702
64fc9944
JB		 703 /* Emulate RGBA support, contrary to svga_reg.h this is not
704 * supported by hosts. This is only a problem if we are reading
705 * this value later and expecting what we uploaded back.
706 */
707 if (depth == 32)
708 depth = 24;
709
c6ca8391 710 fifo_size = sizeof(*cmd);
56d1c78d
JB		 711 cmd = kmalloc(fifo_size, GFP_KERNEL);
712 if (unlikely(cmd == NULL)) {
713 DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
714 return -ENOMEM;
715 }
716
717 memset(cmd, 0, fifo_size);
718 cmd->header = SVGA_CMD_DEFINE_GMRFB;
719 cmd->body.format.bitsPerPixel = framebuffer->base.bits_per_pixel;
64fc9944 720 cmd->body.format.colorDepth = depth;
56d1c78d
JB		 721 cmd->body.format.reserved = 0;
722 cmd->body.bytesPerLine = framebuffer->base.pitch;
90ff18bc 723 cmd->body.ptr.gmrId = framebuffer->user_handle;
56d1c78d
JB		 724 cmd->body.ptr.offset = 0;
725
56d1c78d
JB		 726 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
727 fifo_size, 0, NULL);
728
729 kfree(cmd);
730
731 return ret;
732}
733
c6ca8391
JB		 734static int do_dmabuf_dirty_sou(struct drm_file *file_priv,
735 struct vmw_private *dev_priv,
736 struct vmw_framebuffer *framebuffer,
c6ca8391
JB		 737 unsigned flags, unsigned color,
738 struct drm_clip_rect *clips,
739 unsigned num_clips, int increment)
740{
741 struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
742 struct drm_clip_rect *clips_ptr;
743 int i, k, num_units, ret;
744 struct drm_crtc *crtc;
745 size_t fifo_size;
746
747 struct {
748 uint32_t header;
749 SVGAFifoCmdBlitGMRFBToScreen body;
750 } *blits;
751
752 ret = do_dmabuf_define_gmrfb(file_priv, dev_priv, framebuffer);
753 if (unlikely(ret != 0))
754 return ret; /* define_gmrfb prints warnings */
755
756 fifo_size = sizeof(*blits) * num_clips;
757 blits = kmalloc(fifo_size, GFP_KERNEL);
758 if (unlikely(blits == NULL)) {
759 DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
760 return -ENOMEM;
761 }
762
763 num_units = 0;
764 list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
765 if (crtc->fb != &framebuffer->base)
766 continue;
767 units[num_units++] = vmw_crtc_to_du(crtc);
768 }
769
770 for (k = 0; k < num_units; k++) {
771 struct vmw_display_unit *unit = units[k];
772 int hit_num = 0;
773
774 clips_ptr = clips;
775 for (i = 0; i < num_clips; i++, clips_ptr += increment) {
776 int clip_x1 = clips_ptr->x1 - unit->crtc.x;
777 int clip_y1 = clips_ptr->y1 - unit->crtc.y;
778 int clip_x2 = clips_ptr->x2 - unit->crtc.x;
779 int clip_y2 = clips_ptr->y2 - unit->crtc.y;
780
781 /* skip any crtcs that misses the clip region */
782 if (clip_x1 >= unit->crtc.mode.hdisplay ||
783 clip_y1 >= unit->crtc.mode.vdisplay ||
784 clip_x2 <= 0 || clip_y2 <= 0)
785 continue;
786
787 blits[hit_num].header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
788 blits[hit_num].body.destScreenId = unit->unit;
789 blits[hit_num].body.srcOrigin.x = clips_ptr->x1;
790 blits[hit_num].body.srcOrigin.y = clips_ptr->y1;
791 blits[hit_num].body.destRect.left = clip_x1;
792 blits[hit_num].body.destRect.top = clip_y1;
793 blits[hit_num].body.destRect.right = clip_x2;
794 blits[hit_num].body.destRect.bottom = clip_y2;
795 hit_num++;
796 }
797
798 /* no clips hit the crtc */
799 if (hit_num == 0)
800 continue;
801
802 fifo_size = sizeof(*blits) * hit_num;
803 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, blits,
804 fifo_size, 0, NULL);
805
806 if (unlikely(ret != 0))
807 break;
808 }
809
810 kfree(blits);
811
812 return ret;
813}
814
fb1d9738 815int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer,
02b00162 816 struct drm_file *file_priv,
fb1d9738
JB		 817 unsigned flags, unsigned color,
818 struct drm_clip_rect *clips,
819 unsigned num_clips)
820{
821 struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
3a939a5e 822 struct vmw_master *vmaster = vmw_master(file_priv->master);
5deb65cf
JB		 823 struct vmw_framebuffer_dmabuf *vfbd =
824 vmw_framebuffer_to_vfbd(framebuffer);
fb1d9738 825 struct drm_clip_rect norect;
5deb65cf 826 int ret, increment = 1;
fb1d9738 827
3a939a5e
TH		 828 ret = ttm_read_lock(&vmaster->lock, true);
829 if (unlikely(ret != 0))
830 return ret;
831
df1c93ba 832 if (!num_clips) {
fb1d9738
JB		 833 num_clips = 1;
834 clips = &norect;
835 norect.x1 = norect.y1 = 0;
836 norect.x2 = framebuffer->width;
837 norect.y2 = framebuffer->height;
838 } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
839 num_clips /= 2;
840 increment = 2;
841 }
842
56d1c78d 843 if (dev_priv->ldu_priv) {
c5c42360 844 ret = do_dmabuf_dirty_ldu(dev_priv, &vfbd->base,
56d1c78d
JB		 845 flags, color,
846 clips, num_clips, increment);
847 } else {
848 ret = do_dmabuf_dirty_sou(file_priv, dev_priv, &vfbd->base,
c5c42360 849 flags, color,
56d1c78d
JB		 850 clips, num_clips, increment);
851 }
fb1d9738 852
3a939a5e 853 ttm_read_unlock(&vmaster->lock);
5deb65cf 854 return ret;
fb1d9738
JB		 855}
856
857static struct drm_framebuffer_funcs vmw_framebuffer_dmabuf_funcs = {
858 .destroy = vmw_framebuffer_dmabuf_destroy,
859 .dirty = vmw_framebuffer_dmabuf_dirty,
860 .create_handle = vmw_framebuffer_create_handle,
861};
862
497a3ff9
JB		 863/**
864 * Pin the dmabuffer to the start of vram.
865 */
fb1d9738
JB		 866static int vmw_framebuffer_dmabuf_pin(struct vmw_framebuffer *vfb)
867{
868 struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
869 struct vmw_framebuffer_dmabuf *vfbd =
870 vmw_framebuffer_to_vfbd(&vfb->base);
871 int ret;
872
56d1c78d
JB		 873 /* This code should not be used with screen objects */
874 BUG_ON(dev_priv->sou_priv);
d7e1958d 875
fb1d9738
JB		 876 vmw_overlay_pause_all(dev_priv);
877
d991ef03 878 ret = vmw_dmabuf_to_start_of_vram(dev_priv, vfbd->buffer, true, false);
fb1d9738 879
fb1d9738
JB		 880 vmw_overlay_resume_all(dev_priv);
881
316ab13a
JB		 882 WARN_ON(ret != 0);
883
fb1d9738
JB		 884 return 0;
885}
886
887static int vmw_framebuffer_dmabuf_unpin(struct vmw_framebuffer *vfb)
888{
889 struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
890 struct vmw_framebuffer_dmabuf *vfbd =
891 vmw_framebuffer_to_vfbd(&vfb->base);
892
893 if (!vfbd->buffer) {
894 WARN_ON(!vfbd->buffer);
895 return 0;
896 }
897
d991ef03 898 return vmw_dmabuf_unpin(dev_priv, vfbd->buffer, false);
fb1d9738
JB		 899}
900
d3216a0c
TH		 901static int vmw_kms_new_framebuffer_dmabuf(struct vmw_private *dev_priv,
902 struct vmw_dma_buffer *dmabuf,
903 struct vmw_framebuffer **out,
904 const struct drm_mode_fb_cmd
905 *mode_cmd)
fb1d9738
JB		 906
907{
908 struct drm_device *dev = dev_priv->dev;
909 struct vmw_framebuffer_dmabuf *vfbd;
d3216a0c 910 unsigned int requested_size;
fb1d9738
JB		 911 int ret;
912
d3216a0c
TH		 913 requested_size = mode_cmd->height * mode_cmd->pitch;
914 if (unlikely(requested_size > dmabuf->base.num_pages * PAGE_SIZE)) {
915 DRM_ERROR("Screen buffer object size is too small "
916 "for requested mode.\n");
917 return -EINVAL;
918 }
919
c337ada7
JB		 920 /* Limited framebuffer color depth support for screen objects */
921 if (dev_priv->sou_priv) {
922 switch (mode_cmd->depth) {
923 case 32:
924 case 24:
925 /* Only support 32 bpp for 32 and 24 depth fbs */
926 if (mode_cmd->bpp == 32)
927 break;
928
929 DRM_ERROR("Invalid color depth/bbp: %d %d\n",
930 mode_cmd->depth, mode_cmd->bpp);
931 return -EINVAL;
932 case 16:
933 case 15:
934 /* Only support 16 bpp for 16 and 15 depth fbs */
935 if (mode_cmd->bpp == 16)
936 break;
937
938 DRM_ERROR("Invalid color depth/bbp: %d %d\n",
939 mode_cmd->depth, mode_cmd->bpp);
940 return -EINVAL;
941 default:
942 DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
943 return -EINVAL;
944 }
945 }
946
fb1d9738
JB		 947 vfbd = kzalloc(sizeof(*vfbd), GFP_KERNEL);
948 if (!vfbd) {
949 ret = -ENOMEM;
950 goto out_err1;
951 }
952
953 ret = drm_framebuffer_init(dev, &vfbd->base.base,
954 &vmw_framebuffer_dmabuf_funcs);
955 if (ret)
956 goto out_err2;
957
958 if (!vmw_dmabuf_reference(dmabuf)) {
959 DRM_ERROR("failed to reference dmabuf %p\n", dmabuf);
960 goto out_err3;
961 }
962
d3216a0c
TH		 963 vfbd->base.base.bits_per_pixel = mode_cmd->bpp;
964 vfbd->base.base.pitch = mode_cmd->pitch;
965 vfbd->base.base.depth = mode_cmd->depth;
966 vfbd->base.base.width = mode_cmd->width;
967 vfbd->base.base.height = mode_cmd->height;
56d1c78d
JB		 968 if (!dev_priv->sou_priv) {
969 vfbd->base.pin = vmw_framebuffer_dmabuf_pin;
970 vfbd->base.unpin = vmw_framebuffer_dmabuf_unpin;
971 }
2fcd5a73 972 vfbd->base.dmabuf = true;
fb1d9738 973 vfbd->buffer = dmabuf;
90ff18bc 974 vfbd->base.user_handle = mode_cmd->handle;
fb1d9738
JB		 975 *out = &vfbd->base;
976
977 return 0;
978
979out_err3:
980 drm_framebuffer_cleanup(&vfbd->base.base);
981out_err2:
982 kfree(vfbd);
983out_err1:
984 return ret;
985}
986
987/*
988 * Generic Kernel modesetting functions
989 */
990
991static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
992 struct drm_file *file_priv,
308e5bcb 993 struct drm_mode_fb_cmd2 *mode_cmd2)
fb1d9738
JB		 994{
995 struct vmw_private *dev_priv = vmw_priv(dev);
996 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
997 struct vmw_framebuffer *vfb = NULL;
998 struct vmw_surface *surface = NULL;
999 struct vmw_dma_buffer *bo = NULL;
90ff18bc 1000 struct ttm_base_object *user_obj;
308e5bcb 1001 struct drm_mode_fb_cmd mode_cmd;
e133e737 1002 u64 required_size;
fb1d9738
JB		 1003 int ret;
1004
308e5bcb
JB		 1005 mode_cmd.width = mode_cmd2->width;
1006 mode_cmd.height = mode_cmd2->height;
1007 mode_cmd.pitch = mode_cmd2->pitches[0];
1008 mode_cmd.handle = mode_cmd2->handles[0];
1009 drm_helper_get_fb_bpp_depth(mode_cmd2->pixel_format, &mode_cmd.depth,
1010 &mode_cmd.bpp);
1011
d3216a0c
TH		 1012 /**
1013 * This code should be conditioned on Screen Objects not being used.
1014 * If screen objects are used, we can allocate a GMR to hold the
1015 * requested framebuffer.
1016 */
1017
308e5bcb 1018 required_size = mode_cmd.pitch * mode_cmd.height;
e133e737 1019 if (unlikely(required_size > (u64) dev_priv->vram_size)) {
d3216a0c 1020 DRM_ERROR("VRAM size is too small for requested mode.\n");
d9826409 1021 return ERR_PTR(-ENOMEM);
d3216a0c
TH		 1022 }
1023
90ff18bc
TH		 1024 /*
1025 * Take a reference on the user object of the resource
1026 * backing the kms fb. This ensures that user-space handle
1027 * lookups on that resource will always work as long as
1028 * it's registered with a kms framebuffer. This is important,
1029 * since vmw_execbuf_process identifies resources in the
1030 * command stream using user-space handles.
1031 */
1032
308e5bcb 1033 user_obj = ttm_base_object_lookup(tfile, mode_cmd.handle);
90ff18bc
TH		 1034 if (unlikely(user_obj == NULL)) {
1035 DRM_ERROR("Could not locate requested kms frame buffer.\n");
1036 return ERR_PTR(-ENOENT);
1037 }
1038
d3216a0c
TH		 1039 /**
1040 * End conditioned code.
1041 */
1042
7a73ba74 1043 ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
308e5bcb 1044 mode_cmd.handle, &surface);
fb1d9738
JB		 1045 if (ret)
1046 goto try_dmabuf;
1047
5ffdb658
JB		 1048 if (!surface->scanout)
1049 goto err_not_scanout;
1050
3a939a5e 1051 ret = vmw_kms_new_framebuffer_surface(dev_priv, file_priv, surface,
308e5bcb 1052 &vfb, &mode_cmd);
fb1d9738
JB		 1053
1054 /* vmw_user_surface_lookup takes one ref so does new_fb */
1055 vmw_surface_unreference(&surface);
1056
1057 if (ret) {
1058 DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
90ff18bc 1059 ttm_base_object_unref(&user_obj);
cce13ff7 1060 return ERR_PTR(ret);
90ff18bc
TH		 1061 } else
1062 vfb->user_obj = user_obj;
fb1d9738
JB		 1063 return &vfb->base;
1064
1065try_dmabuf:
1066 DRM_INFO("%s: trying buffer\n", __func__);
1067
308e5bcb 1068 ret = vmw_user_dmabuf_lookup(tfile, mode_cmd.handle, &bo);
fb1d9738
JB		 1069 if (ret) {
1070 DRM_ERROR("failed to find buffer: %i\n", ret);
cce13ff7 1071 return ERR_PTR(-ENOENT);
fb1d9738
JB		 1072 }
1073
1074 ret = vmw_kms_new_framebuffer_dmabuf(dev_priv, bo, &vfb,
308e5bcb 1075 &mode_cmd);
fb1d9738
JB		 1076
1077 /* vmw_user_dmabuf_lookup takes one ref so does new_fb */
1078 vmw_dmabuf_unreference(&bo);
1079
1080 if (ret) {
1081 DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
90ff18bc 1082 ttm_base_object_unref(&user_obj);
cce13ff7 1083 return ERR_PTR(ret);
90ff18bc
TH		 1084 } else
1085 vfb->user_obj = user_obj;
fb1d9738
JB		 1086
1087 return &vfb->base;
5ffdb658
JB		 1088
1089err_not_scanout:
1090 DRM_ERROR("surface not marked as scanout\n");
1091 /* vmw_user_surface_lookup takes one ref */
1092 vmw_surface_unreference(&surface);
90ff18bc 1093 ttm_base_object_unref(&user_obj);
5ffdb658 1094
cce13ff7 1095 return ERR_PTR(-EINVAL);
fb1d9738
JB		 1096}
1097
fb1d9738
JB		 1098static struct drm_mode_config_funcs vmw_kms_funcs = {
1099 .fb_create = vmw_kms_fb_create,
fb1d9738
JB		 1100};
1101
2fcd5a73
JB		 1102int vmw_kms_present(struct vmw_private *dev_priv,
1103 struct drm_file *file_priv,
1104 struct vmw_framebuffer *vfb,
1105 struct vmw_surface *surface,
1106 uint32_t sid,
1107 int32_t destX, int32_t destY,
1108 struct drm_vmw_rect *clips,
1109 uint32_t num_clips)
1110{
c6ca8391
JB		 1111 struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
1112 struct drm_crtc *crtc;
2fcd5a73 1113 size_t fifo_size;
c6ca8391
JB		 1114 int i, k, num_units;
1115 int ret = 0; /* silence warning */
2fcd5a73
JB		 1116
1117 struct {
1118 SVGA3dCmdHeader header;
1119 SVGA3dCmdBlitSurfaceToScreen body;
1120 } *cmd;
1121 SVGASignedRect *blits;
1122
c6ca8391
JB		 1123 num_units = 0;
1124 list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
1125 if (crtc->fb != &vfb->base)
1126 continue;
1127 units[num_units++] = vmw_crtc_to_du(crtc);
1128 }
1129
2fcd5a73
JB		 1130 BUG_ON(surface == NULL);
1131 BUG_ON(!clips || !num_clips);
1132
1133 fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
1134 cmd = kmalloc(fifo_size, GFP_KERNEL);
1135 if (unlikely(cmd == NULL)) {
1136 DRM_ERROR("Failed to allocate temporary fifo memory.\n");
1137 return -ENOMEM;
1138 }
1139
c6ca8391 1140 /* only need to do this once */
2fcd5a73 1141 memset(cmd, 0, fifo_size);
2fcd5a73
JB		 1142 cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
1143 cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
1144
2fcd5a73
JB		 1145 cmd->body.srcRect.left = 0;
1146 cmd->body.srcRect.right = surface->sizes[0].width;
1147 cmd->body.srcRect.top = 0;
1148 cmd->body.srcRect.bottom = surface->sizes[0].height;
1149
2fcd5a73
JB		 1150 blits = (SVGASignedRect *)&cmd[1];
1151 for (i = 0; i < num_clips; i++) {
1152 blits[i].left = clips[i].x;
1153 blits[i].right = clips[i].x + clips[i].w;
1154 blits[i].top = clips[i].y;
1155 blits[i].bottom = clips[i].y + clips[i].h;
1156 }
1157
c6ca8391
JB		 1158 for (k = 0; k < num_units; k++) {
1159 struct vmw_display_unit *unit = units[k];
1160 int clip_x1 = destX - unit->crtc.x;
1161 int clip_y1 = destY - unit->crtc.y;
1162 int clip_x2 = clip_x1 + surface->sizes[0].width;
1163 int clip_y2 = clip_y1 + surface->sizes[0].height;
1164
1165 /* skip any crtcs that misses the clip region */
1166 if (clip_x1 >= unit->crtc.mode.hdisplay ||
1167 clip_y1 >= unit->crtc.mode.vdisplay ||
1168 clip_x2 <= 0 || clip_y2 <= 0)
1169 continue;
1170
1171 /* need to reset sid as it is changed by execbuf */
1172 cmd->body.srcImage.sid = sid;
1173
1174 cmd->body.destScreenId = unit->unit;
1175
1176 /*
1177 * The blit command is a lot more resilient then the
1178 * readback command when it comes to clip rects. So its
1179 * okay to go out of bounds.
1180 */
1181
1182 cmd->body.destRect.left = clip_x1;
1183 cmd->body.destRect.right = clip_x2;
1184 cmd->body.destRect.top = clip_y1;
1185 cmd->body.destRect.bottom = clip_y2;
1186
1187 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
1188 fifo_size, 0, NULL);
1189
1190 if (unlikely(ret != 0))
1191 break;
1192 }
2fcd5a73
JB		 1193
1194 kfree(cmd);
1195
1196 return ret;
1197}
1198
1199int vmw_kms_readback(struct vmw_private *dev_priv,
1200 struct drm_file *file_priv,
1201 struct vmw_framebuffer *vfb,
1202 struct drm_vmw_fence_rep __user *user_fence_rep,
1203 struct drm_vmw_rect *clips,
1204 uint32_t num_clips)
1205{
1206 struct vmw_framebuffer_dmabuf *vfbd =
1207 vmw_framebuffer_to_vfbd(&vfb->base);
1208 struct vmw_dma_buffer *dmabuf = vfbd->buffer;
1209 struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
1210 struct drm_crtc *crtc;
1211 size_t fifo_size;
1212 int i, k, ret, num_units, blits_pos;
1213
1214 struct {
1215 uint32_t header;
1216 SVGAFifoCmdDefineGMRFB body;
1217 } *cmd;
1218 struct {
1219 uint32_t header;
1220 SVGAFifoCmdBlitScreenToGMRFB body;
1221 } *blits;
1222
1223 num_units = 0;
1224 list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
1225 if (crtc->fb != &vfb->base)
1226 continue;
1227 units[num_units++] = vmw_crtc_to_du(crtc);
1228 }
1229
1230 BUG_ON(dmabuf == NULL);
1231 BUG_ON(!clips || !num_clips);
1232
1233 /* take a safe guess at fifo size */
1234 fifo_size = sizeof(*cmd) + sizeof(*blits) * num_clips * num_units;
1235 cmd = kmalloc(fifo_size, GFP_KERNEL);
1236 if (unlikely(cmd == NULL)) {
1237 DRM_ERROR("Failed to allocate temporary fifo memory.\n");
1238 return -ENOMEM;
1239 }
1240
1241 memset(cmd, 0, fifo_size);
1242 cmd->header = SVGA_CMD_DEFINE_GMRFB;
1243 cmd->body.format.bitsPerPixel = vfb->base.bits_per_pixel;
1244 cmd->body.format.colorDepth = vfb->base.depth;
1245 cmd->body.format.reserved = 0;
1246 cmd->body.bytesPerLine = vfb->base.pitch;
90ff18bc 1247 cmd->body.ptr.gmrId = vfb->user_handle;
2fcd5a73
JB		 1248 cmd->body.ptr.offset = 0;
1249
1250 blits = (void *)&cmd[1];
1251 blits_pos = 0;
1252 for (i = 0; i < num_units; i++) {
1253 struct drm_vmw_rect *c = clips;
1254 for (k = 0; k < num_clips; k++, c++) {
1255 /* transform clip coords to crtc origin based coords */
1256 int clip_x1 = c->x - units[i]->crtc.x;
1257 int clip_x2 = c->x - units[i]->crtc.x + c->w;
1258 int clip_y1 = c->y - units[i]->crtc.y;
1259 int clip_y2 = c->y - units[i]->crtc.y + c->h;
1260 int dest_x = c->x;
1261 int dest_y = c->y;
1262
1263 /* compensate for clipping, we negate
1264 * a negative number and add that.
1265 */
1266 if (clip_x1 < 0)
1267 dest_x += -clip_x1;
1268 if (clip_y1 < 0)
1269 dest_y += -clip_y1;
1270
1271 /* clip */
1272 clip_x1 = max(clip_x1, 0);
1273 clip_y1 = max(clip_y1, 0);
1274 clip_x2 = min(clip_x2, units[i]->crtc.mode.hdisplay);
1275 clip_y2 = min(clip_y2, units[i]->crtc.mode.vdisplay);
1276
1277 /* and cull any rects that misses the crtc */
1278 if (clip_x1 >= units[i]->crtc.mode.hdisplay ||
1279 clip_y1 >= units[i]->crtc.mode.vdisplay ||
1280 clip_x2 <= 0 || clip_y2 <= 0)
1281 continue;
1282
1283 blits[blits_pos].header = SVGA_CMD_BLIT_SCREEN_TO_GMRFB;
1284 blits[blits_pos].body.srcScreenId = units[i]->unit;
1285 blits[blits_pos].body.destOrigin.x = dest_x;
1286 blits[blits_pos].body.destOrigin.y = dest_y;
1287
1288 blits[blits_pos].body.srcRect.left = clip_x1;
1289 blits[blits_pos].body.srcRect.top = clip_y1;
1290 blits[blits_pos].body.srcRect.right = clip_x2;
1291 blits[blits_pos].body.srcRect.bottom = clip_y2;
1292 blits_pos++;
1293 }
1294 }
1295 /* reset size here and use calculated exact size from loops */
1296 fifo_size = sizeof(*cmd) + sizeof(*blits) * blits_pos;
1297
1298 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd, fifo_size,
1299 0, user_fence_rep);
1300
1301 kfree(cmd);
1302
1303 return ret;
1304}
1305
fb1d9738
JB		 1306int vmw_kms_init(struct vmw_private *dev_priv)
1307{
1308 struct drm_device *dev = dev_priv->dev;
1309 int ret;
1310
1311 drm_mode_config_init(dev);
1312 dev->mode_config.funcs = &vmw_kms_funcs;
3bef3572
JB		 1313 dev->mode_config.min_width = 1;
1314 dev->mode_config.min_height = 1;
7e71f8a5
JB		 1315 /* assumed largest fb size */
1316 dev->mode_config.max_width = 8192;
1317 dev->mode_config.max_height = 8192;
fb1d9738 1318
56d1c78d
JB		 1319 ret = vmw_kms_init_screen_object_display(dev_priv);
1320 if (ret) /* Fallback */
1321 (void)vmw_kms_init_legacy_display_system(dev_priv);
fb1d9738
JB		 1322
1323 return 0;
1324}
1325
1326int vmw_kms_close(struct vmw_private *dev_priv)
1327{
1328 /*
1329 * Docs says we should take the lock before calling this function
1330 * but since it destroys encoders and our destructor calls
1331 * drm_encoder_cleanup which takes the lock we deadlock.
1332 */
1333 drm_mode_config_cleanup(dev_priv->dev);
1334 vmw_kms_close_legacy_display_system(dev_priv);
1335 return 0;
1336}
1337
1338int vmw_kms_cursor_bypass_ioctl(struct drm_device *dev, void *data,
1339 struct drm_file *file_priv)
1340{
1341 struct drm_vmw_cursor_bypass_arg *arg = data;
1342 struct vmw_display_unit *du;
1343 struct drm_mode_object *obj;
1344 struct drm_crtc *crtc;
1345 int ret = 0;
1346
1347
1348 mutex_lock(&dev->mode_config.mutex);
1349 if (arg->flags & DRM_VMW_CURSOR_BYPASS_ALL) {
1350
1351 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1352 du = vmw_crtc_to_du(crtc);
1353 du->hotspot_x = arg->xhot;
1354 du->hotspot_y = arg->yhot;
1355 }
1356
1357 mutex_unlock(&dev->mode_config.mutex);
1358 return 0;
1359 }
1360
1361 obj = drm_mode_object_find(dev, arg->crtc_id, DRM_MODE_OBJECT_CRTC);
1362 if (!obj) {
1363 ret = -EINVAL;
1364 goto out;
1365 }
1366
1367 crtc = obj_to_crtc(obj);
1368 du = vmw_crtc_to_du(crtc);
1369
1370 du->hotspot_x = arg->xhot;
1371 du->hotspot_y = arg->yhot;
1372
1373out:
1374 mutex_unlock(&dev->mode_config.mutex);
1375
1376 return ret;
1377}
1378
0bef23f9 1379int vmw_kms_write_svga(struct vmw_private *vmw_priv,
d7e1958d 1380 unsigned width, unsigned height, unsigned pitch,
6558429b 1381 unsigned bpp, unsigned depth)
fb1d9738 1382{
d7e1958d
JB		 1383 if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
1384 vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);
1385 else if (vmw_fifo_have_pitchlock(vmw_priv))
1386 iowrite32(pitch, vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
1387 vmw_write(vmw_priv, SVGA_REG_WIDTH, width);
1388 vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);
6558429b 1389 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);
0bef23f9
MD		 1390
1391 if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) {
1392 DRM_ERROR("Invalid depth %u for %u bpp, host expects %u\n",
1393 depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH));
1394 return -EINVAL;
1395 }
1396
1397 return 0;
d7e1958d 1398}
fb1d9738 1399
d7e1958d
JB		 1400int vmw_kms_save_vga(struct vmw_private *vmw_priv)
1401{
7c4f7780
TH		 1402 struct vmw_vga_topology_state *save;
1403 uint32_t i;
1404
fb1d9738
JB		 1405 vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH);
1406 vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT);
7c4f7780 1407 vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL);
d7e1958d
JB		 1408 if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
1409 vmw_priv->vga_pitchlock =
7c4f7780 1410 vmw_read(vmw_priv, SVGA_REG_PITCHLOCK);
d7e1958d 1411 else if (vmw_fifo_have_pitchlock(vmw_priv))
7c4f7780
TH		 1412 vmw_priv->vga_pitchlock = ioread32(vmw_priv->mmio_virt +
1413 SVGA_FIFO_PITCHLOCK);
1414
1415 if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
1416 return 0;
fb1d9738 1417
7c4f7780
TH		 1418 vmw_priv->num_displays = vmw_read(vmw_priv,
1419 SVGA_REG_NUM_GUEST_DISPLAYS);
1420
029e50bf
TH		 1421 if (vmw_priv->num_displays == 0)
1422 vmw_priv->num_displays = 1;
1423
7c4f7780
TH		 1424 for (i = 0; i < vmw_priv->num_displays; ++i) {
1425 save = &vmw_priv->vga_save[i];
1426 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
1427 save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY);
1428 save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X);
1429 save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y);
1430 save->width = vmw_read(vmw_priv, SVGA_REG_DISPLAY_WIDTH);
1431 save->height = vmw_read(vmw_priv, SVGA_REG_DISPLAY_HEIGHT);
1432 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
30c78bb8
TH		 1433 if (i == 0 && vmw_priv->num_displays == 1 &&
1434 save->width == 0 && save->height == 0) {
1435
1436 /*
1437 * It should be fairly safe to assume that these
1438 * values are uninitialized.
1439 */
1440
1441 save->width = vmw_priv->vga_width - save->pos_x;
1442 save->height = vmw_priv->vga_height - save->pos_y;
1443 }
7c4f7780 1444 }
30c78bb8 1445
fb1d9738
JB		 1446 return 0;
1447}
1448
1449int vmw_kms_restore_vga(struct vmw_private *vmw_priv)
1450{
7c4f7780
TH		 1451 struct vmw_vga_topology_state *save;
1452 uint32_t i;
1453
fb1d9738
JB		 1454 vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width);
1455 vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height);
7c4f7780 1456 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp);
d7e1958d
JB		 1457 if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
1458 vmw_write(vmw_priv, SVGA_REG_PITCHLOCK,
1459 vmw_priv->vga_pitchlock);
1460 else if (vmw_fifo_have_pitchlock(vmw_priv))
1461 iowrite32(vmw_priv->vga_pitchlock,
1462 vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
fb1d9738 1463
7c4f7780
TH		 1464 if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
1465 return 0;
1466
1467 for (i = 0; i < vmw_priv->num_displays; ++i) {
1468 save = &vmw_priv->vga_save[i];
1469 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
1470 vmw_write(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY, save->primary);
1471 vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_X, save->pos_x);
1472 vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y, save->pos_y);
1473 vmw_write(vmw_priv, SVGA_REG_DISPLAY_WIDTH, save->width);
1474 vmw_write(vmw_priv, SVGA_REG_DISPLAY_HEIGHT, save->height);
1475 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
1476 }
1477
fb1d9738
JB		 1478 return 0;
1479}
d8bd19d2 1480
e133e737
TH		 1481bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,
1482 uint32_t pitch,
1483 uint32_t height)
1484{
1485 return ((u64) pitch * (u64) height) < (u64) dev_priv->vram_size;
1486}
1487
1c482ab3
JB		 1488
1489/**
1490 * Function called by DRM code called with vbl_lock held.
1491 */
7a1c2f6c
TH		 1492u32 vmw_get_vblank_counter(struct drm_device *dev, int crtc)
1493{
1494 return 0;
1495}
626ab771 1496
1c482ab3
JB		 1497/**
1498 * Function called by DRM code called with vbl_lock held.
1499 */
1500int vmw_enable_vblank(struct drm_device *dev, int crtc)
1501{
1502 return -ENOSYS;
1503}
1504
1505/**
1506 * Function called by DRM code called with vbl_lock held.
1507 */
1508void vmw_disable_vblank(struct drm_device *dev, int crtc)
1509{
1510}
1511
626ab771
JB		 1512
1513/*
1514 * Small shared kms functions.
1515 */
1516
1517int vmw_du_update_layout(struct vmw_private *dev_priv, unsigned num,
1518 struct drm_vmw_rect *rects)
1519{
1520 struct drm_device *dev = dev_priv->dev;
1521 struct vmw_display_unit *du;
1522 struct drm_connector *con;
626ab771
JB		 1523
1524 mutex_lock(&dev->mode_config.mutex);
1525
1526#if 0
6ea77d13
TH		 1527 {
1528 unsigned int i;
1529
1530 DRM_INFO("%s: new layout ", __func__);
1531 for (i = 0; i < num; i++)
1532 DRM_INFO("(%i, %i %ux%u) ", rects[i].x, rects[i].y,
1533 rects[i].w, rects[i].h);
1534 DRM_INFO("\n");
1535 }
626ab771
JB		 1536#endif
1537
1538 list_for_each_entry(con, &dev->mode_config.connector_list, head) {
1539 du = vmw_connector_to_du(con);
1540 if (num > du->unit) {
1541 du->pref_width = rects[du->unit].w;
1542 du->pref_height = rects[du->unit].h;
1543 du->pref_active = true;
cd2b89e7
TH		 1544 du->gui_x = rects[du->unit].x;
1545 du->gui_y = rects[du->unit].y;
626ab771
JB		 1546 } else {
1547 du->pref_width = 800;
1548 du->pref_height = 600;
1549 du->pref_active = false;
1550 }
1551 con->status = vmw_du_connector_detect(con, true);
1552 }
1553
1554 mutex_unlock(&dev->mode_config.mutex);
1555
1556 return 0;
1557}
1558
1559void vmw_du_crtc_save(struct drm_crtc *crtc)
1560{
1561}
1562
1563void vmw_du_crtc_restore(struct drm_crtc *crtc)
1564{
1565}
1566
1567void vmw_du_crtc_gamma_set(struct drm_crtc *crtc,
1568 u16 *r, u16 *g, u16 *b,
1569 uint32_t start, uint32_t size)
1570{
1571 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
1572 int i;
1573
1574 for (i = 0; i < size; i++) {
1575 DRM_DEBUG("%d r/g/b = 0x%04x / 0x%04x / 0x%04x\n", i,
1576 r[i], g[i], b[i]);
1577 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 0, r[i] >> 8);
1578 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 1, g[i] >> 8);
1579 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 2, b[i] >> 8);
1580 }
1581}
1582
1583void vmw_du_connector_dpms(struct drm_connector *connector, int mode)
1584{
1585}
1586
1587void vmw_du_connector_save(struct drm_connector *connector)
1588{
1589}
1590
1591void vmw_du_connector_restore(struct drm_connector *connector)
1592{
1593}
1594
1595enum drm_connector_status
1596vmw_du_connector_detect(struct drm_connector *connector, bool force)
1597{
1598 uint32_t num_displays;
1599 struct drm_device *dev = connector->dev;
1600 struct vmw_private *dev_priv = vmw_priv(dev);
cd2b89e7 1601 struct vmw_display_unit *du = vmw_connector_to_du(connector);
626ab771
JB		 1602
1603 mutex_lock(&dev_priv->hw_mutex);
1604 num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);
1605 mutex_unlock(&dev_priv->hw_mutex);
1606
cd2b89e7
TH		 1607 return ((vmw_connector_to_du(connector)->unit < num_displays &&
1608 du->pref_active) ?
626ab771
JB		 1609 connector_status_connected : connector_status_disconnected);
1610}
1611
1612static struct drm_display_mode vmw_kms_connector_builtin[] = {
1613 /* 640x480@60Hz */
1614 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
1615 752, 800, 0, 480, 489, 492, 525, 0,
1616 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
1617 /* 800x600@60Hz */
1618 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
1619 968, 1056, 0, 600, 601, 605, 628, 0,
1620 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1621 /* 1024x768@60Hz */
1622 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
1623 1184, 1344, 0, 768, 771, 777, 806, 0,
1624 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
1625 /* 1152x864@75Hz */
1626 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
1627 1344, 1600, 0, 864, 865, 868, 900, 0,
1628 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1629 /* 1280x768@60Hz */
1630 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
1631 1472, 1664, 0, 768, 771, 778, 798, 0,
1632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1633 /* 1280x800@60Hz */
1634 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
1635 1480, 1680, 0, 800, 803, 809, 831, 0,
1636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
1637 /* 1280x960@60Hz */
1638 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
1639 1488, 1800, 0, 960, 961, 964, 1000, 0,
1640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1641 /* 1280x1024@60Hz */
1642 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
1643 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
1644 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1645 /* 1360x768@60Hz */
1646 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
1647 1536, 1792, 0, 768, 771, 777, 795, 0,
1648 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1649 /* 1440x1050@60Hz */
1650 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
1651 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
1652 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1653 /* 1440x900@60Hz */
1654 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
1655 1672, 1904, 0, 900, 903, 909, 934, 0,
1656 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1657 /* 1600x1200@60Hz */
1658 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
1659 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
1660 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1661 /* 1680x1050@60Hz */
1662 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
1663 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
1664 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1665 /* 1792x1344@60Hz */
1666 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
1667 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
1668 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1669 /* 1853x1392@60Hz */
1670 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
1671 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
1672 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1673 /* 1920x1200@60Hz */
1674 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
1675 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
1676 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1677 /* 1920x1440@60Hz */
1678 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
1679 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
1680 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1681 /* 2560x1600@60Hz */
1682 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
1683 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
1684 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1685 /* Terminate */
1686 { DRM_MODE("", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) },
1687};
1688
1543b4dd
TH		 1689/**
1690 * vmw_guess_mode_timing - Provide fake timings for a
1691 * 60Hz vrefresh mode.
1692 *
1693 * @mode - Pointer to a struct drm_display_mode with hdisplay and vdisplay
1694 * members filled in.
1695 */
1696static void vmw_guess_mode_timing(struct drm_display_mode *mode)
1697{
1698 mode->hsync_start = mode->hdisplay + 50;
1699 mode->hsync_end = mode->hsync_start + 50;
1700 mode->htotal = mode->hsync_end + 50;
1701
1702 mode->vsync_start = mode->vdisplay + 50;
1703 mode->vsync_end = mode->vsync_start + 50;
1704 mode->vtotal = mode->vsync_end + 50;
1705
1706 mode->clock = (u32)mode->htotal * (u32)mode->vtotal / 100 * 6;
1707 mode->vrefresh = drm_mode_vrefresh(mode);
1708}
1709
1710
626ab771
JB		 1711int vmw_du_connector_fill_modes(struct drm_connector *connector,
1712 uint32_t max_width, uint32_t max_height)
1713{
1714 struct vmw_display_unit *du = vmw_connector_to_du(connector);
1715 struct drm_device *dev = connector->dev;
1716 struct vmw_private *dev_priv = vmw_priv(dev);
1717 struct drm_display_mode *mode = NULL;
1718 struct drm_display_mode *bmode;
1719 struct drm_display_mode prefmode = { DRM_MODE("preferred",
1720 DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
1721 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)
1723 };
1724 int i;
1725
1726 /* Add preferred mode */
1727 {
1728 mode = drm_mode_duplicate(dev, &prefmode);
1729 if (!mode)
1730 return 0;
1731 mode->hdisplay = du->pref_width;
1732 mode->vdisplay = du->pref_height;
1543b4dd 1733 vmw_guess_mode_timing(mode);
55bde5b2 1734
626ab771
JB		 1735 if (vmw_kms_validate_mode_vram(dev_priv, mode->hdisplay * 2,
1736 mode->vdisplay)) {
1737 drm_mode_probed_add(connector, mode);
55bde5b2
JB		 1738 } else {
1739 drm_mode_destroy(dev, mode);
1740 mode = NULL;
1741 }
626ab771 1742
55bde5b2
JB		 1743 if (du->pref_mode) {
1744 list_del_init(&du->pref_mode->head);
1745 drm_mode_destroy(dev, du->pref_mode);
626ab771 1746 }
55bde5b2
JB		 1747
1748 /* mode might be null here, this is intended */
1749 du->pref_mode = mode;
626ab771
JB		 1750 }
1751
1752 for (i = 0; vmw_kms_connector_builtin[i].type != 0; i++) {
1753 bmode = &vmw_kms_connector_builtin[i];
1754 if (bmode->hdisplay > max_width ||
1755 bmode->vdisplay > max_height)
1756 continue;
1757
1758 if (!vmw_kms_validate_mode_vram(dev_priv, bmode->hdisplay * 2,
1759 bmode->vdisplay))
1760 continue;
1761
1762 mode = drm_mode_duplicate(dev, bmode);
1763 if (!mode)
1764 return 0;
1765 mode->vrefresh = drm_mode_vrefresh(mode);
1766
1767 drm_mode_probed_add(connector, mode);
1768 }
1769
d41025c0
JB		 1770 /* Move the prefered mode first, help apps pick the right mode. */
1771 if (du->pref_mode)
1772 list_move(&du->pref_mode->head, &connector->probed_modes);
1773
626ab771
JB		 1774 drm_mode_connector_list_update(connector);
1775
1776 return 1;
1777}
1778
1779int vmw_du_connector_set_property(struct drm_connector *connector,
1780 struct drm_property *property,
1781 uint64_t val)
1782{
1783 return 0;
1784}
cd2b89e7
TH		 1785
1786
1787int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
1788 struct drm_file *file_priv)
1789{
1790 struct vmw_private *dev_priv = vmw_priv(dev);
1791 struct drm_vmw_update_layout_arg *arg =
1792 (struct drm_vmw_update_layout_arg *)data;
1793 struct vmw_master *vmaster = vmw_master(file_priv->master);
1794 void __user *user_rects;
1795 struct drm_vmw_rect *rects;
1796 unsigned rects_size;
1797 int ret;
1798 int i;
1799 struct drm_mode_config *mode_config = &dev->mode_config;
1800
1801 ret = ttm_read_lock(&vmaster->lock, true);
1802 if (unlikely(ret != 0))
1803 return ret;
1804
1805 if (!arg->num_outputs) {
1806 struct drm_vmw_rect def_rect = {0, 0, 800, 600};
1807 vmw_du_update_layout(dev_priv, 1, &def_rect);
1808 goto out_unlock;
1809 }
1810
1811 rects_size = arg->num_outputs * sizeof(struct drm_vmw_rect);
1812 rects = kzalloc(rects_size, GFP_KERNEL);
1813 if (unlikely(!rects)) {
1814 ret = -ENOMEM;
1815 goto out_unlock;
1816 }
1817
1818 user_rects = (void __user *)(unsigned long)arg->rects;
1819 ret = copy_from_user(rects, user_rects, rects_size);
1820 if (unlikely(ret != 0)) {
1821 DRM_ERROR("Failed to get rects.\n");
1822 ret = -EFAULT;
1823 goto out_free;
1824 }
1825
1826 for (i = 0; i < arg->num_outputs; ++i) {
1827 if (rects->x < 0 ||
1828 rects->y < 0 ||
1829 rects->x + rects->w > mode_config->max_width ||
1830 rects->y + rects->h > mode_config->max_height) {
1831 DRM_ERROR("Invalid GUI layout.\n");
1832 ret = -EINVAL;
1833 goto out_free;
1834 }
1835 }
1836
1837 vmw_du_update_layout(dev_priv, arg->num_outputs, rects);
1838
1839out_free:
1840 kfree(rects);
1841out_unlock:
1842 ttm_read_unlock(&vmaster->lock);
1843 return ret;
1844}
Linux kernel - Deliverables
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