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gpu: host1x: Expose syncpt and channel functionality
[deliverable/linux.git] / drivers / gpu / host1x / drm / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
61fd290d 11#include <linux/clk/tegra.h>
9eb9b220 12#include <linux/debugfs.h>
d8f4a9ed 13
692e6d7b 14#include "host1x_client.h"
de2ba664
AM		 15#include "dc.h"
16#include "drm.h"
17#include "gem.h"
d8f4a9ed 18
f34bc787
TR		 19struct tegra_plane {
20 struct drm_plane base;
21 unsigned int index;
d8f4a9ed
TR		 22};
23
f34bc787
TR		 24static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
25{
26 return container_of(plane, struct tegra_plane, base);
27}
28
29static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
30 struct drm_framebuffer *fb, int crtc_x,
31 int crtc_y, unsigned int crtc_w,
32 unsigned int crtc_h, uint32_t src_x,
33 uint32_t src_y, uint32_t src_w, uint32_t src_h)
34{
35 struct tegra_plane *p = to_tegra_plane(plane);
36 struct tegra_dc *dc = to_tegra_dc(crtc);
37 struct tegra_dc_window window;
38 unsigned int i;
39
40 memset(&window, 0, sizeof(window));
41 window.src.x = src_x >> 16;
42 window.src.y = src_y >> 16;
43 window.src.w = src_w >> 16;
44 window.src.h = src_h >> 16;
45 window.dst.x = crtc_x;
46 window.dst.y = crtc_y;
47 window.dst.w = crtc_w;
48 window.dst.h = crtc_h;
49 window.format = tegra_dc_format(fb->pixel_format);
50 window.bits_per_pixel = fb->bits_per_pixel;
51
52 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
de2ba664 53 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
f34bc787 54
de2ba664 55 window.base[i] = bo->paddr + fb->offsets[i];
f34bc787
TR		 56
57 /*
58 * Tegra doesn't support different strides for U and V planes
59 * so we display a warning if the user tries to display a
60 * framebuffer with such a configuration.
61 */
62 if (i >= 2) {
63 if (fb->pitches[i] != window.stride[1])
64 DRM_ERROR("unsupported UV-plane configuration\n");
65 } else {
66 window.stride[i] = fb->pitches[i];
67 }
68 }
69
70 return tegra_dc_setup_window(dc, p->index, &window);
71}
72
73static int tegra_plane_disable(struct drm_plane *plane)
74{
75 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
76 struct tegra_plane *p = to_tegra_plane(plane);
77 unsigned long value;
78
2678aeba
TR		 79 if (!plane->crtc)
80 return 0;
81
f34bc787
TR		 82 value = WINDOW_A_SELECT << p->index;
83 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
84
85 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
86 value &= ~WIN_ENABLE;
87 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
88
89 tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL);
90 tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL);
91
92 return 0;
93}
94
95static void tegra_plane_destroy(struct drm_plane *plane)
96{
97 tegra_plane_disable(plane);
98 drm_plane_cleanup(plane);
99}
100
101static const struct drm_plane_funcs tegra_plane_funcs = {
102 .update_plane = tegra_plane_update,
103 .disable_plane = tegra_plane_disable,
104 .destroy = tegra_plane_destroy,
105};
106
107static const uint32_t plane_formats[] = {
dbe4d9a7 108 DRM_FORMAT_XBGR8888,
f34bc787 109 DRM_FORMAT_XRGB8888,
dbe4d9a7 110 DRM_FORMAT_RGB565,
f34bc787
TR		 111 DRM_FORMAT_UYVY,
112 DRM_FORMAT_YUV420,
113 DRM_FORMAT_YUV422,
114};
115
116static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
117{
118 unsigned int i;
119 int err = 0;
120
121 for (i = 0; i < 2; i++) {
122 struct tegra_plane *plane;
123
124 plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
125 if (!plane)
126 return -ENOMEM;
127
128 plane->index = 1 + i;
129
130 err = drm_plane_init(drm, &plane->base, 1 << dc->pipe,
131 &tegra_plane_funcs, plane_formats,
132 ARRAY_SIZE(plane_formats), false);
133 if (err < 0)
134 return err;
135 }
136
137 return 0;
138}
139
23fb4740
TR		 140static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
141 struct drm_framebuffer *fb)
142{
ed683aea 143 unsigned int format = tegra_dc_format(fb->pixel_format);
de2ba664 144 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
23fb4740
TR		 145 unsigned long value;
146
147 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
148
149 value = fb->offsets[0] + y * fb->pitches[0] +
150 x * fb->bits_per_pixel / 8;
151
de2ba664 152 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR);
23fb4740 153 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
ed683aea 154 tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH);
23fb4740
TR		 155
156 value = GENERAL_UPDATE | WIN_A_UPDATE;
157 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
158
159 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
160 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
161
162 return 0;
163}
164
6e5ff998
TR		 165void tegra_dc_enable_vblank(struct tegra_dc *dc)
166{
167 unsigned long value, flags;
168
169 spin_lock_irqsave(&dc->lock, flags);
170
171 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
172 value |= VBLANK_INT;
173 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
174
175 spin_unlock_irqrestore(&dc->lock, flags);
176}
177
178void tegra_dc_disable_vblank(struct tegra_dc *dc)
179{
180 unsigned long value, flags;
181
182 spin_lock_irqsave(&dc->lock, flags);
183
184 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
185 value &= ~VBLANK_INT;
186 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
187
188 spin_unlock_irqrestore(&dc->lock, flags);
189}
190
3c03c46a
TR		 191static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
192{
193 struct drm_device *drm = dc->base.dev;
194 struct drm_crtc *crtc = &dc->base;
3c03c46a 195 unsigned long flags, base;
de2ba664 196 struct tegra_bo *bo;
3c03c46a
TR		 197
198 if (!dc->event)
199 return;
200
de2ba664 201 bo = tegra_fb_get_plane(crtc->fb, 0);
3c03c46a
TR		 202
203 /* check if new start address has been latched */
204 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
205 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
206 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
207
de2ba664 208 if (base == bo->paddr + crtc->fb->offsets[0]) {
3c03c46a
TR		 209 spin_lock_irqsave(&drm->event_lock, flags);
210 drm_send_vblank_event(drm, dc->pipe, dc->event);
211 drm_vblank_put(drm, dc->pipe);
212 dc->event = NULL;
213 spin_unlock_irqrestore(&drm->event_lock, flags);
214 }
215}
216
217void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
218{
219 struct tegra_dc *dc = to_tegra_dc(crtc);
220 struct drm_device *drm = crtc->dev;
221 unsigned long flags;
222
223 spin_lock_irqsave(&drm->event_lock, flags);
224
225 if (dc->event && dc->event->base.file_priv == file) {
226 dc->event->base.destroy(&dc->event->base);
227 drm_vblank_put(drm, dc->pipe);
228 dc->event = NULL;
229 }
230
231 spin_unlock_irqrestore(&drm->event_lock, flags);
232}
233
234static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
a5b6f74e 235 struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
3c03c46a
TR		 236{
237 struct tegra_dc *dc = to_tegra_dc(crtc);
238 struct drm_device *drm = crtc->dev;
239
240 if (dc->event)
241 return -EBUSY;
242
243 if (event) {
244 event->pipe = dc->pipe;
245 dc->event = event;
246 drm_vblank_get(drm, dc->pipe);
247 }
248
249 tegra_dc_set_base(dc, 0, 0, fb);
250 crtc->fb = fb;
251
252 return 0;
253}
254
d8f4a9ed 255static const struct drm_crtc_funcs tegra_crtc_funcs = {
3c03c46a 256 .page_flip = tegra_dc_page_flip,
d8f4a9ed
TR		 257 .set_config = drm_crtc_helper_set_config,
258 .destroy = drm_crtc_cleanup,
259};
260
f34bc787 261static void tegra_crtc_disable(struct drm_crtc *crtc)
d8f4a9ed 262{
f34bc787
TR		 263 struct drm_device *drm = crtc->dev;
264 struct drm_plane *plane;
265
266 list_for_each_entry(plane, &drm->mode_config.plane_list, head) {
267 if (plane->crtc == crtc) {
268 tegra_plane_disable(plane);
269 plane->crtc = NULL;
270
271 if (plane->fb) {
272 drm_framebuffer_unreference(plane->fb);
273 plane->fb = NULL;
274 }
275 }
276 }
d8f4a9ed
TR		 277}
278
279static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
280 const struct drm_display_mode *mode,
281 struct drm_display_mode *adjusted)
282{
283 return true;
284}
285
f34bc787 286static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
d8f4a9ed
TR		 287 unsigned int bpp)
288{
289 fixed20_12 outf = dfixed_init(out);
f34bc787 290 fixed20_12 inf = dfixed_init(in);
d8f4a9ed
TR		 291 u32 dda_inc;
292 int max;
293
294 if (v)
295 max = 15;
296 else {
297 switch (bpp) {
298 case 2:
299 max = 8;
300 break;
301
302 default:
303 WARN_ON_ONCE(1);
304 /* fallthrough */
305 case 4:
306 max = 4;
307 break;
308 }
309 }
310
311 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
312 inf.full -= dfixed_const(1);
313
314 dda_inc = dfixed_div(inf, outf);
315 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
316
317 return dda_inc;
318}
319
f34bc787 320static inline u32 compute_initial_dda(unsigned int in)
d8f4a9ed 321{
f34bc787
TR		 322 fixed20_12 inf = dfixed_init(in);
323 return dfixed_frac(inf);
d8f4a9ed
TR		 324}
325
326static int tegra_dc_set_timings(struct tegra_dc *dc,
327 struct drm_display_mode *mode)
328{
329 /* TODO: For HDMI compliance, h & v ref_to_sync should be set to 1 */
330 unsigned int h_ref_to_sync = 0;
331 unsigned int v_ref_to_sync = 0;
332 unsigned long value;
333
334 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
335
336 value = (v_ref_to_sync << 16) | h_ref_to_sync;
337 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
338
339 value = ((mode->vsync_end - mode->vsync_start) << 16) |
340 ((mode->hsync_end - mode->hsync_start) << 0);
341 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
342
d8f4a9ed
TR		 343 value = ((mode->vtotal - mode->vsync_end) << 16) |
344 ((mode->htotal - mode->hsync_end) << 0);
40495089
LS		 345 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
346
347 value = ((mode->vsync_start - mode->vdisplay) << 16) |
348 ((mode->hsync_start - mode->hdisplay) << 0);
d8f4a9ed
TR		 349 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
350
351 value = (mode->vdisplay << 16) | mode->hdisplay;
352 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
353
354 return 0;
355}
356
357static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
358 struct drm_display_mode *mode,
359 unsigned long *div)
360{
361 unsigned long pclk = mode->clock * 1000, rate;
362 struct tegra_dc *dc = to_tegra_dc(crtc);
363 struct tegra_output *output = NULL;
364 struct drm_encoder *encoder;
365 long err;
366
367 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
368 if (encoder->crtc == crtc) {
369 output = encoder_to_output(encoder);
370 break;
371 }
372
373 if (!output)
374 return -ENODEV;
375
376 /*
377 * This assumes that the display controller will divide its parent
378 * clock by 2 to generate the pixel clock.
379 */
380 err = tegra_output_setup_clock(output, dc->clk, pclk * 2);
381 if (err < 0) {
382 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
383 return err;
384 }
385
386 rate = clk_get_rate(dc->clk);
387 *div = (rate * 2 / pclk) - 2;
388
389 DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate, *div);
390
391 return 0;
392}
393
f34bc787
TR		 394static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
395{
396 switch (format) {
397 case WIN_COLOR_DEPTH_YCbCr422:
398 case WIN_COLOR_DEPTH_YUV422:
399 if (planar)
400 *planar = false;
401
402 return true;
403
404 case WIN_COLOR_DEPTH_YCbCr420P:
405 case WIN_COLOR_DEPTH_YUV420P:
406 case WIN_COLOR_DEPTH_YCbCr422P:
407 case WIN_COLOR_DEPTH_YUV422P:
408 case WIN_COLOR_DEPTH_YCbCr422R:
409 case WIN_COLOR_DEPTH_YUV422R:
410 case WIN_COLOR_DEPTH_YCbCr422RA:
411 case WIN_COLOR_DEPTH_YUV422RA:
412 if (planar)
413 *planar = true;
414
415 return true;
416 }
417
418 return false;
419}
420
421int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
422 const struct tegra_dc_window *window)
423{
424 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
425 unsigned long value;
426 bool yuv, planar;
427
428 /*
429 * For YUV planar modes, the number of bytes per pixel takes into
430 * account only the luma component and therefore is 1.
431 */
432 yuv = tegra_dc_format_is_yuv(window->format, &planar);
433 if (!yuv)
434 bpp = window->bits_per_pixel / 8;
435 else
436 bpp = planar ? 1 : 2;
437
438 value = WINDOW_A_SELECT << index;
439 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
440
441 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
442 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
443
444 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
445 tegra_dc_writel(dc, value, DC_WIN_POSITION);
446
447 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
448 tegra_dc_writel(dc, value, DC_WIN_SIZE);
449
450 h_offset = window->src.x * bpp;
451 v_offset = window->src.y;
452 h_size = window->src.w * bpp;
453 v_size = window->src.h;
454
455 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
456 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
457
458 /*
459 * For DDA computations the number of bytes per pixel for YUV planar
460 * modes needs to take into account all Y, U and V components.
461 */
462 if (yuv && planar)
463 bpp = 2;
464
465 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
466 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
467
468 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
469 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
470
471 h_dda = compute_initial_dda(window->src.x);
472 v_dda = compute_initial_dda(window->src.y);
473
474 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
475 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
476
477 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
478 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
479
480 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
481
482 if (yuv && planar) {
483 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
484 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
485 value = window->stride[1] << 16 | window->stride[0];
486 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
487 } else {
488 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
489 }
490
491 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
492 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
493
494 value = WIN_ENABLE;
495
496 if (yuv) {
497 /* setup default colorspace conversion coefficients */
498 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
499 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
500 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
501 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
502 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
503 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
504 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
505 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
506
507 value |= CSC_ENABLE;
84ff6b27 508 } else if (window->bits_per_pixel < 24) {
f34bc787
TR		 509 value |= COLOR_EXPAND;
510 }
511
512 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
513
514 /*
515 * Disable blending and assume Window A is the bottom-most window,
516 * Window C is the top-most window and Window B is in the middle.
517 */
518 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
519 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
520
521 switch (index) {
522 case 0:
523 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
524 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
525 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
526 break;
527
528 case 1:
529 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
530 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
531 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
532 break;
533
534 case 2:
535 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
536 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
537 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
538 break;
539 }
540
541 tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL);
542 tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL);
543
544 return 0;
545}
546
547unsigned int tegra_dc_format(uint32_t format)
548{
549 switch (format) {
dbe4d9a7
TR		 550 case DRM_FORMAT_XBGR8888:
551 return WIN_COLOR_DEPTH_R8G8B8A8;
552
f34bc787
TR		 553 case DRM_FORMAT_XRGB8888:
554 return WIN_COLOR_DEPTH_B8G8R8A8;
555
556 case DRM_FORMAT_RGB565:
557 return WIN_COLOR_DEPTH_B5G6R5;
558
559 case DRM_FORMAT_UYVY:
560 return WIN_COLOR_DEPTH_YCbCr422;
561
562 case DRM_FORMAT_YUV420:
563 return WIN_COLOR_DEPTH_YCbCr420P;
564
565 case DRM_FORMAT_YUV422:
566 return WIN_COLOR_DEPTH_YCbCr422P;
567
568 default:
569 break;
570 }
571
572 WARN(1, "unsupported pixel format %u, using default\n", format);
573 return WIN_COLOR_DEPTH_B8G8R8A8;
574}
575
d8f4a9ed
TR		 576static int tegra_crtc_mode_set(struct drm_crtc *crtc,
577 struct drm_display_mode *mode,
578 struct drm_display_mode *adjusted,
579 int x, int y, struct drm_framebuffer *old_fb)
580{
de2ba664 581 struct tegra_bo *bo = tegra_fb_get_plane(crtc->fb, 0);
d8f4a9ed 582 struct tegra_dc *dc = to_tegra_dc(crtc);
f34bc787 583 struct tegra_dc_window window;
d8f4a9ed
TR		 584 unsigned long div, value;
585 int err;
586
6e5ff998
TR		 587 drm_vblank_pre_modeset(crtc->dev, dc->pipe);
588
d8f4a9ed
TR		 589 err = tegra_crtc_setup_clk(crtc, mode, &div);
590 if (err) {
591 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
592 return err;
593 }
594
595 /* program display mode */
596 tegra_dc_set_timings(dc, mode);
597
598 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
599 tegra_dc_writel(dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
600
601 value = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY(1));
602 value &= ~LVS_OUTPUT_POLARITY_LOW;
603 value &= ~LHS_OUTPUT_POLARITY_LOW;
604 tegra_dc_writel(dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
605
606 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
607 DISP_ORDER_RED_BLUE;
608 tegra_dc_writel(dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
609
610 tegra_dc_writel(dc, 0x00010001, DC_DISP_SHIFT_CLOCK_OPTIONS);
611
612 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
613 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
614
615 /* setup window parameters */
f34bc787
TR		 616 memset(&window, 0, sizeof(window));
617 window.src.x = 0;
618 window.src.y = 0;
619 window.src.w = mode->hdisplay;
620 window.src.h = mode->vdisplay;
621 window.dst.x = 0;
622 window.dst.y = 0;
623 window.dst.w = mode->hdisplay;
624 window.dst.h = mode->vdisplay;
625 window.format = tegra_dc_format(crtc->fb->pixel_format);
626 window.bits_per_pixel = crtc->fb->bits_per_pixel;
627 window.stride[0] = crtc->fb->pitches[0];
de2ba664 628 window.base[0] = bo->paddr;
f34bc787
TR		 629
630 err = tegra_dc_setup_window(dc, 0, &window);
631 if (err < 0)
632 dev_err(dc->dev, "failed to enable root plane\n");
d8f4a9ed 633
d8f4a9ed
TR		 634 return 0;
635}
d8f4a9ed 636
23fb4740
TR		 637static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
638 struct drm_framebuffer *old_fb)
639{
640 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed 641
23fb4740 642 return tegra_dc_set_base(dc, x, y, crtc->fb);
d8f4a9ed
TR		 643}
644
645static void tegra_crtc_prepare(struct drm_crtc *crtc)
646{
647 struct tegra_dc *dc = to_tegra_dc(crtc);
648 unsigned int syncpt;
649 unsigned long value;
650
651 /* hardware initialization */
652 tegra_periph_reset_deassert(dc->clk);
653 usleep_range(10000, 20000);
654
655 if (dc->pipe)
656 syncpt = SYNCPT_VBLANK1;
657 else
658 syncpt = SYNCPT_VBLANK0;
659
660 /* initialize display controller */
661 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
662 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
663
664 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
665 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
666
667 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
668 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
669 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
670
671 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
672 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
673 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
674
675 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
676 value |= DISP_CTRL_MODE_C_DISPLAY;
677 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
678
679 /* initialize timer */
680 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
681 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
682 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
683
684 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
685 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
686 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
687
d8f4a9ed
TR		 688 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
689 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
6e5ff998
TR		 690
691 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
692 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
d8f4a9ed
TR		 693}
694
695static void tegra_crtc_commit(struct drm_crtc *crtc)
696{
697 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed
TR		 698 unsigned long value;
699
3b9e71ea
TR		 700 value = GENERAL_UPDATE | WIN_A_UPDATE;
701 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
d8f4a9ed 702
3b9e71ea 703 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
6e5ff998 704 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
d8f4a9ed 705
6e5ff998 706 drm_vblank_post_modeset(crtc->dev, dc->pipe);
d8f4a9ed
TR		 707}
708
709static void tegra_crtc_load_lut(struct drm_crtc *crtc)
710{
711}
712
713static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
f34bc787 714 .disable = tegra_crtc_disable,
d8f4a9ed
TR		 715 .mode_fixup = tegra_crtc_mode_fixup,
716 .mode_set = tegra_crtc_mode_set,
23fb4740 717 .mode_set_base = tegra_crtc_mode_set_base,
d8f4a9ed
TR		 718 .prepare = tegra_crtc_prepare,
719 .commit = tegra_crtc_commit,
720 .load_lut = tegra_crtc_load_lut,
721};
722
6e5ff998 723static irqreturn_t tegra_dc_irq(int irq, void *data)
d8f4a9ed
TR		 724{
725 struct tegra_dc *dc = data;
726 unsigned long status;
727
728 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
729 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
730
731 if (status & FRAME_END_INT) {
732 /*
733 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
734 */
735 }
736
737 if (status & VBLANK_INT) {
738 /*
739 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
740 */
741 drm_handle_vblank(dc->base.dev, dc->pipe);
3c03c46a 742 tegra_dc_finish_page_flip(dc);
d8f4a9ed
TR		 743 }
744
745 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
746 /*
747 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
748 */
749 }
750
751 return IRQ_HANDLED;
752}
753
754static int tegra_dc_show_regs(struct seq_file *s, void *data)
755{
756 struct drm_info_node *node = s->private;
757 struct tegra_dc *dc = node->info_ent->data;
758
759#define DUMP_REG(name) \
760 seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \
761 tegra_dc_readl(dc, name))
762
763 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
764 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
765 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
766 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
767 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
768 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
769 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
770 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
771 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
772 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
773 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
774 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
775 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
776 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
777 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
778 DUMP_REG(DC_CMD_SIGNAL_RAISE);
779 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
780 DUMP_REG(DC_CMD_INT_STATUS);
781 DUMP_REG(DC_CMD_INT_MASK);
782 DUMP_REG(DC_CMD_INT_ENABLE);
783 DUMP_REG(DC_CMD_INT_TYPE);
784 DUMP_REG(DC_CMD_INT_POLARITY);
785 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
786 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
787 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
788 DUMP_REG(DC_CMD_STATE_ACCESS);
789 DUMP_REG(DC_CMD_STATE_CONTROL);
790 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
791 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
792 DUMP_REG(DC_COM_CRC_CONTROL);
793 DUMP_REG(DC_COM_CRC_CHECKSUM);
794 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
795 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
796 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
797 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
798 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
799 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
800 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
801 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
802 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
803 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
804 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
805 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
806 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
807 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
808 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
809 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
810 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
811 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
812 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
813 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
814 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
815 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
816 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
817 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
818 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
819 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
820 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
821 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
822 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
823 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
824 DUMP_REG(DC_COM_SPI_CONTROL);
825 DUMP_REG(DC_COM_SPI_START_BYTE);
826 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
827 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
828 DUMP_REG(DC_COM_HSPI_CS_DC);
829 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
830 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
831 DUMP_REG(DC_COM_GPIO_CTRL);
832 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
833 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
834 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
835 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
836 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
837 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
838 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
839 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
840 DUMP_REG(DC_DISP_REF_TO_SYNC);
841 DUMP_REG(DC_DISP_SYNC_WIDTH);
842 DUMP_REG(DC_DISP_BACK_PORCH);
843 DUMP_REG(DC_DISP_ACTIVE);
844 DUMP_REG(DC_DISP_FRONT_PORCH);
845 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
846 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
847 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
848 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
849 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
850 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
851 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
852 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
853 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
854 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
855 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
856 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
857 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
858 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
859 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
860 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
861 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
862 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
863 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
864 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
865 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
866 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
867 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
868 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
869 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
870 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
871 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
872 DUMP_REG(DC_DISP_M0_CONTROL);
873 DUMP_REG(DC_DISP_M1_CONTROL);
874 DUMP_REG(DC_DISP_DI_CONTROL);
875 DUMP_REG(DC_DISP_PP_CONTROL);
876 DUMP_REG(DC_DISP_PP_SELECT_A);
877 DUMP_REG(DC_DISP_PP_SELECT_B);
878 DUMP_REG(DC_DISP_PP_SELECT_C);
879 DUMP_REG(DC_DISP_PP_SELECT_D);
880 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
881 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
882 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
883 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
884 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
885 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
886 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
887 DUMP_REG(DC_DISP_BORDER_COLOR);
888 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
889 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
890 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
891 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
892 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
893 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
894 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
895 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
896 DUMP_REG(DC_DISP_CURSOR_POSITION);
897 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
898 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
899 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
900 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
901 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
902 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
903 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
904 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
905 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
906 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
907 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
908 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
909 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
910 DUMP_REG(DC_DISP_SD_CONTROL);
911 DUMP_REG(DC_DISP_SD_CSC_COEFF);
912 DUMP_REG(DC_DISP_SD_LUT(0));
913 DUMP_REG(DC_DISP_SD_LUT(1));
914 DUMP_REG(DC_DISP_SD_LUT(2));
915 DUMP_REG(DC_DISP_SD_LUT(3));
916 DUMP_REG(DC_DISP_SD_LUT(4));
917 DUMP_REG(DC_DISP_SD_LUT(5));
918 DUMP_REG(DC_DISP_SD_LUT(6));
919 DUMP_REG(DC_DISP_SD_LUT(7));
920 DUMP_REG(DC_DISP_SD_LUT(8));
921 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
922 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
923 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
924 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
925 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
926 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
927 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
928 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
929 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
930 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
931 DUMP_REG(DC_DISP_SD_BL_TF(0));
932 DUMP_REG(DC_DISP_SD_BL_TF(1));
933 DUMP_REG(DC_DISP_SD_BL_TF(2));
934 DUMP_REG(DC_DISP_SD_BL_TF(3));
935 DUMP_REG(DC_DISP_SD_BL_CONTROL);
936 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
937 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
938 DUMP_REG(DC_WIN_WIN_OPTIONS);
939 DUMP_REG(DC_WIN_BYTE_SWAP);
940 DUMP_REG(DC_WIN_BUFFER_CONTROL);
941 DUMP_REG(DC_WIN_COLOR_DEPTH);
942 DUMP_REG(DC_WIN_POSITION);
943 DUMP_REG(DC_WIN_SIZE);
944 DUMP_REG(DC_WIN_PRESCALED_SIZE);
945 DUMP_REG(DC_WIN_H_INITIAL_DDA);
946 DUMP_REG(DC_WIN_V_INITIAL_DDA);
947 DUMP_REG(DC_WIN_DDA_INC);
948 DUMP_REG(DC_WIN_LINE_STRIDE);
949 DUMP_REG(DC_WIN_BUF_STRIDE);
950 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
951 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
952 DUMP_REG(DC_WIN_DV_CONTROL);
953 DUMP_REG(DC_WIN_BLEND_NOKEY);
954 DUMP_REG(DC_WIN_BLEND_1WIN);
955 DUMP_REG(DC_WIN_BLEND_2WIN_X);
956 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
f34bc787 957 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
d8f4a9ed
TR		 958 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
959 DUMP_REG(DC_WINBUF_START_ADDR);
960 DUMP_REG(DC_WINBUF_START_ADDR_NS);
961 DUMP_REG(DC_WINBUF_START_ADDR_U);
962 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
963 DUMP_REG(DC_WINBUF_START_ADDR_V);
964 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
965 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
966 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
967 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
968 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
969 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
970 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
971 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
972 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
973
974#undef DUMP_REG
975
976 return 0;
977}
978
979static struct drm_info_list debugfs_files[] = {
980 { "regs", tegra_dc_show_regs, 0, NULL },
981};
982
983static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
984{
985 unsigned int i;
986 char *name;
987 int err;
988
989 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
990 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
991 kfree(name);
992
993 if (!dc->debugfs)
994 return -ENOMEM;
995
996 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
997 GFP_KERNEL);
998 if (!dc->debugfs_files) {
999 err = -ENOMEM;
1000 goto remove;
1001 }
1002
1003 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1004 dc->debugfs_files[i].data = dc;
1005
1006 err = drm_debugfs_create_files(dc->debugfs_files,
1007 ARRAY_SIZE(debugfs_files),
1008 dc->debugfs, minor);
1009 if (err < 0)
1010 goto free;
1011
1012 dc->minor = minor;
1013
1014 return 0;
1015
1016free:
1017 kfree(dc->debugfs_files);
1018 dc->debugfs_files = NULL;
1019remove:
1020 debugfs_remove(dc->debugfs);
1021 dc->debugfs = NULL;
1022
1023 return err;
1024}
1025
1026static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1027{
1028 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1029 dc->minor);
1030 dc->minor = NULL;
1031
1032 kfree(dc->debugfs_files);
1033 dc->debugfs_files = NULL;
1034
1035 debugfs_remove(dc->debugfs);
1036 dc->debugfs = NULL;
1037
1038 return 0;
1039}
1040
53fa7f72 1041static int tegra_dc_init(struct host1x_client *client)
d8f4a9ed 1042{
53fa7f72
TR		 1043 struct tegra_drm_client *drm = to_tegra_drm_client(client);
1044 struct tegra_dc *dc = tegra_drm_client_to_dc(drm);
d8f4a9ed
TR		 1045 int err;
1046
53fa7f72 1047 dc->pipe = drm->drm->mode_config.num_crtc;
d8f4a9ed 1048
53fa7f72 1049 drm_crtc_init(drm->drm, &dc->base, &tegra_crtc_funcs);
d8f4a9ed
TR		 1050 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1051 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1052
53fa7f72 1053 err = tegra_dc_rgb_init(drm->drm, dc);
d8f4a9ed
TR		 1054 if (err < 0 && err != -ENODEV) {
1055 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1056 return err;
1057 }
1058
53fa7f72 1059 err = tegra_dc_add_planes(drm->drm, dc);
f34bc787
TR		 1060 if (err < 0)
1061 return err;
1062
d8f4a9ed 1063 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
53fa7f72 1064 err = tegra_dc_debugfs_init(dc, drm->drm->primary);
d8f4a9ed
TR		 1065 if (err < 0)
1066 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1067 }
1068
6e5ff998 1069 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
d8f4a9ed
TR		 1070 dev_name(dc->dev), dc);
1071 if (err < 0) {
1072 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1073 err);
1074 return err;
1075 }
1076
1077 return 0;
1078}
1079
53fa7f72 1080static int tegra_dc_exit(struct host1x_client *client)
d8f4a9ed 1081{
53fa7f72
TR		 1082 struct tegra_drm_client *drm = to_tegra_drm_client(client);
1083 struct tegra_dc *dc = tegra_drm_client_to_dc(drm);
d8f4a9ed
TR		 1084 int err;
1085
1086 devm_free_irq(dc->dev, dc->irq, dc);
1087
1088 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1089 err = tegra_dc_debugfs_exit(dc);
1090 if (err < 0)
1091 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1092 }
1093
1094 err = tegra_dc_rgb_exit(dc);
1095 if (err) {
1096 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1097 return err;
1098 }
1099
1100 return 0;
1101}
1102
1103static const struct host1x_client_ops dc_client_ops = {
53fa7f72
TR		 1104 .init = tegra_dc_init,
1105 .exit = tegra_dc_exit,
d8f4a9ed
TR		 1106};
1107
1108static int tegra_dc_probe(struct platform_device *pdev)
1109{
386a2a71 1110 struct tegra_drm *tegra = host1x_get_drm_data(pdev->dev.parent);
d8f4a9ed
TR		 1111 struct resource *regs;
1112 struct tegra_dc *dc;
1113 int err;
1114
1115 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1116 if (!dc)
1117 return -ENOMEM;
1118
6e5ff998 1119 spin_lock_init(&dc->lock);
d8f4a9ed
TR		 1120 INIT_LIST_HEAD(&dc->list);
1121 dc->dev = &pdev->dev;
1122
1123 dc->clk = devm_clk_get(&pdev->dev, NULL);
1124 if (IS_ERR(dc->clk)) {
1125 dev_err(&pdev->dev, "failed to get clock\n");
1126 return PTR_ERR(dc->clk);
1127 }
1128
1129 err = clk_prepare_enable(dc->clk);
1130 if (err < 0)
1131 return err;
1132
1133 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d4ed6025
TR		 1134 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1135 if (IS_ERR(dc->regs))
1136 return PTR_ERR(dc->regs);
d8f4a9ed
TR		 1137
1138 dc->irq = platform_get_irq(pdev, 0);
1139 if (dc->irq < 0) {
1140 dev_err(&pdev->dev, "failed to get IRQ\n");
1141 return -ENXIO;
1142 }
1143
53fa7f72
TR		 1144 INIT_LIST_HEAD(&dc->client.base.list);
1145 dc->client.base.ops = &dc_client_ops;
1146 dc->client.base.dev = &pdev->dev;
d8f4a9ed
TR		 1147
1148 err = tegra_dc_rgb_probe(dc);
1149 if (err < 0 && err != -ENODEV) {
1150 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1151 return err;
1152 }
1153
53fa7f72 1154 err = host1x_register_client(tegra, &dc->client.base);
d8f4a9ed
TR		 1155 if (err < 0) {
1156 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1157 err);
1158 return err;
1159 }
1160
1161 platform_set_drvdata(pdev, dc);
1162
1163 return 0;
1164}
1165
1166static int tegra_dc_remove(struct platform_device *pdev)
1167{
386a2a71 1168 struct tegra_drm *tegra = host1x_get_drm_data(pdev->dev.parent);
d8f4a9ed
TR		 1169 struct tegra_dc *dc = platform_get_drvdata(pdev);
1170 int err;
1171
53fa7f72 1172 err = host1x_unregister_client(tegra, &dc->client.base);
d8f4a9ed
TR		 1173 if (err < 0) {
1174 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1175 err);
1176 return err;
1177 }
1178
1179 clk_disable_unprepare(dc->clk);
1180
1181 return 0;
1182}
1183
1184static struct of_device_id tegra_dc_of_match[] = {
219e8153 1185 { .compatible = "nvidia,tegra30-dc", },
d8f4a9ed
TR		 1186 { .compatible = "nvidia,tegra20-dc", },
1187 { },
1188};
1189
1190struct platform_driver tegra_dc_driver = {
1191 .driver = {
1192 .name = "tegra-dc",
1193 .owner = THIS_MODULE,
1194 .of_match_table = tegra_dc_of_match,
1195 },
1196 .probe = tegra_dc_probe,
1197 .remove = tegra_dc_remove,
1198};
Linux kernel - Deliverables
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