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drm/tegra: Add gr2d device
[deliverable/linux.git] / drivers / gpu / host1x / drm / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
11#include <linux/debugfs.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
61fd290d 15#include <linux/clk/tegra.h>
d8f4a9ed 16
692e6d7b 17#include "host1x_client.h"
de2ba664
AM		 18#include "dc.h"
19#include "drm.h"
20#include "gem.h"
d8f4a9ed 21
f34bc787
TR		 22struct tegra_plane {
23 struct drm_plane base;
24 unsigned int index;
d8f4a9ed
TR		 25};
26
f34bc787
TR		 27static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
28{
29 return container_of(plane, struct tegra_plane, base);
30}
31
32static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
33 struct drm_framebuffer *fb, int crtc_x,
34 int crtc_y, unsigned int crtc_w,
35 unsigned int crtc_h, uint32_t src_x,
36 uint32_t src_y, uint32_t src_w, uint32_t src_h)
37{
38 struct tegra_plane *p = to_tegra_plane(plane);
39 struct tegra_dc *dc = to_tegra_dc(crtc);
40 struct tegra_dc_window window;
41 unsigned int i;
42
43 memset(&window, 0, sizeof(window));
44 window.src.x = src_x >> 16;
45 window.src.y = src_y >> 16;
46 window.src.w = src_w >> 16;
47 window.src.h = src_h >> 16;
48 window.dst.x = crtc_x;
49 window.dst.y = crtc_y;
50 window.dst.w = crtc_w;
51 window.dst.h = crtc_h;
52 window.format = tegra_dc_format(fb->pixel_format);
53 window.bits_per_pixel = fb->bits_per_pixel;
54
55 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
de2ba664 56 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
f34bc787 57
de2ba664 58 window.base[i] = bo->paddr + fb->offsets[i];
f34bc787
TR		 59
60 /*
61 * Tegra doesn't support different strides for U and V planes
62 * so we display a warning if the user tries to display a
63 * framebuffer with such a configuration.
64 */
65 if (i >= 2) {
66 if (fb->pitches[i] != window.stride[1])
67 DRM_ERROR("unsupported UV-plane configuration\n");
68 } else {
69 window.stride[i] = fb->pitches[i];
70 }
71 }
72
73 return tegra_dc_setup_window(dc, p->index, &window);
74}
75
76static int tegra_plane_disable(struct drm_plane *plane)
77{
78 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
79 struct tegra_plane *p = to_tegra_plane(plane);
80 unsigned long value;
81
82 value = WINDOW_A_SELECT << p->index;
83 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
84
85 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
86 value &= ~WIN_ENABLE;
87 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
88
89 tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL);
90 tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL);
91
92 return 0;
93}
94
95static void tegra_plane_destroy(struct drm_plane *plane)
96{
97 tegra_plane_disable(plane);
98 drm_plane_cleanup(plane);
99}
100
101static const struct drm_plane_funcs tegra_plane_funcs = {
102 .update_plane = tegra_plane_update,
103 .disable_plane = tegra_plane_disable,
104 .destroy = tegra_plane_destroy,
105};
106
107static const uint32_t plane_formats[] = {
108 DRM_FORMAT_XRGB8888,
109 DRM_FORMAT_UYVY,
110 DRM_FORMAT_YUV420,
111 DRM_FORMAT_YUV422,
112};
113
114static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
115{
116 unsigned int i;
117 int err = 0;
118
119 for (i = 0; i < 2; i++) {
120 struct tegra_plane *plane;
121
122 plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
123 if (!plane)
124 return -ENOMEM;
125
126 plane->index = 1 + i;
127
128 err = drm_plane_init(drm, &plane->base, 1 << dc->pipe,
129 &tegra_plane_funcs, plane_formats,
130 ARRAY_SIZE(plane_formats), false);
131 if (err < 0)
132 return err;
133 }
134
135 return 0;
136}
137
23fb4740
TR		 138static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
139 struct drm_framebuffer *fb)
140{
de2ba664 141 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
23fb4740
TR		 142 unsigned long value;
143
144 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
145
146 value = fb->offsets[0] + y * fb->pitches[0] +
147 x * fb->bits_per_pixel / 8;
148
de2ba664 149 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR);
23fb4740
TR		 150 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
151
152 value = GENERAL_UPDATE | WIN_A_UPDATE;
153 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
154
155 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
156 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
157
158 return 0;
159}
160
6e5ff998
TR		 161void tegra_dc_enable_vblank(struct tegra_dc *dc)
162{
163 unsigned long value, flags;
164
165 spin_lock_irqsave(&dc->lock, flags);
166
167 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
168 value |= VBLANK_INT;
169 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
170
171 spin_unlock_irqrestore(&dc->lock, flags);
172}
173
174void tegra_dc_disable_vblank(struct tegra_dc *dc)
175{
176 unsigned long value, flags;
177
178 spin_lock_irqsave(&dc->lock, flags);
179
180 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
181 value &= ~VBLANK_INT;
182 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
183
184 spin_unlock_irqrestore(&dc->lock, flags);
185}
186
3c03c46a
TR		 187static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
188{
189 struct drm_device *drm = dc->base.dev;
190 struct drm_crtc *crtc = &dc->base;
3c03c46a 191 unsigned long flags, base;
de2ba664 192 struct tegra_bo *bo;
3c03c46a
TR		 193
194 if (!dc->event)
195 return;
196
de2ba664 197 bo = tegra_fb_get_plane(crtc->fb, 0);
3c03c46a
TR		 198
199 /* check if new start address has been latched */
200 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
201 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
202 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
203
de2ba664 204 if (base == bo->paddr + crtc->fb->offsets[0]) {
3c03c46a
TR		 205 spin_lock_irqsave(&drm->event_lock, flags);
206 drm_send_vblank_event(drm, dc->pipe, dc->event);
207 drm_vblank_put(drm, dc->pipe);
208 dc->event = NULL;
209 spin_unlock_irqrestore(&drm->event_lock, flags);
210 }
211}
212
213void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
214{
215 struct tegra_dc *dc = to_tegra_dc(crtc);
216 struct drm_device *drm = crtc->dev;
217 unsigned long flags;
218
219 spin_lock_irqsave(&drm->event_lock, flags);
220
221 if (dc->event && dc->event->base.file_priv == file) {
222 dc->event->base.destroy(&dc->event->base);
223 drm_vblank_put(drm, dc->pipe);
224 dc->event = NULL;
225 }
226
227 spin_unlock_irqrestore(&drm->event_lock, flags);
228}
229
230static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
231 struct drm_pending_vblank_event *event)
232{
233 struct tegra_dc *dc = to_tegra_dc(crtc);
234 struct drm_device *drm = crtc->dev;
235
236 if (dc->event)
237 return -EBUSY;
238
239 if (event) {
240 event->pipe = dc->pipe;
241 dc->event = event;
242 drm_vblank_get(drm, dc->pipe);
243 }
244
245 tegra_dc_set_base(dc, 0, 0, fb);
246 crtc->fb = fb;
247
248 return 0;
249}
250
d8f4a9ed 251static const struct drm_crtc_funcs tegra_crtc_funcs = {
3c03c46a 252 .page_flip = tegra_dc_page_flip,
d8f4a9ed
TR		 253 .set_config = drm_crtc_helper_set_config,
254 .destroy = drm_crtc_cleanup,
255};
256
f34bc787 257static void tegra_crtc_disable(struct drm_crtc *crtc)
d8f4a9ed 258{
f34bc787
TR		 259 struct drm_device *drm = crtc->dev;
260 struct drm_plane *plane;
261
262 list_for_each_entry(plane, &drm->mode_config.plane_list, head) {
263 if (plane->crtc == crtc) {
264 tegra_plane_disable(plane);
265 plane->crtc = NULL;
266
267 if (plane->fb) {
268 drm_framebuffer_unreference(plane->fb);
269 plane->fb = NULL;
270 }
271 }
272 }
d8f4a9ed
TR		 273}
274
275static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
276 const struct drm_display_mode *mode,
277 struct drm_display_mode *adjusted)
278{
279 return true;
280}
281
f34bc787 282static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
d8f4a9ed
TR		 283 unsigned int bpp)
284{
285 fixed20_12 outf = dfixed_init(out);
f34bc787 286 fixed20_12 inf = dfixed_init(in);
d8f4a9ed
TR		 287 u32 dda_inc;
288 int max;
289
290 if (v)
291 max = 15;
292 else {
293 switch (bpp) {
294 case 2:
295 max = 8;
296 break;
297
298 default:
299 WARN_ON_ONCE(1);
300 /* fallthrough */
301 case 4:
302 max = 4;
303 break;
304 }
305 }
306
307 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
308 inf.full -= dfixed_const(1);
309
310 dda_inc = dfixed_div(inf, outf);
311 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
312
313 return dda_inc;
314}
315
f34bc787 316static inline u32 compute_initial_dda(unsigned int in)
d8f4a9ed 317{
f34bc787
TR		 318 fixed20_12 inf = dfixed_init(in);
319 return dfixed_frac(inf);
d8f4a9ed
TR		 320}
321
322static int tegra_dc_set_timings(struct tegra_dc *dc,
323 struct drm_display_mode *mode)
324{
325 /* TODO: For HDMI compliance, h & v ref_to_sync should be set to 1 */
326 unsigned int h_ref_to_sync = 0;
327 unsigned int v_ref_to_sync = 0;
328 unsigned long value;
329
330 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
331
332 value = (v_ref_to_sync << 16) | h_ref_to_sync;
333 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
334
335 value = ((mode->vsync_end - mode->vsync_start) << 16) |
336 ((mode->hsync_end - mode->hsync_start) << 0);
337 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
338
d8f4a9ed
TR		 339 value = ((mode->vtotal - mode->vsync_end) << 16) |
340 ((mode->htotal - mode->hsync_end) << 0);
40495089
LS		 341 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
342
343 value = ((mode->vsync_start - mode->vdisplay) << 16) |
344 ((mode->hsync_start - mode->hdisplay) << 0);
d8f4a9ed
TR		 345 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
346
347 value = (mode->vdisplay << 16) | mode->hdisplay;
348 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
349
350 return 0;
351}
352
353static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
354 struct drm_display_mode *mode,
355 unsigned long *div)
356{
357 unsigned long pclk = mode->clock * 1000, rate;
358 struct tegra_dc *dc = to_tegra_dc(crtc);
359 struct tegra_output *output = NULL;
360 struct drm_encoder *encoder;
361 long err;
362
363 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
364 if (encoder->crtc == crtc) {
365 output = encoder_to_output(encoder);
366 break;
367 }
368
369 if (!output)
370 return -ENODEV;
371
372 /*
373 * This assumes that the display controller will divide its parent
374 * clock by 2 to generate the pixel clock.
375 */
376 err = tegra_output_setup_clock(output, dc->clk, pclk * 2);
377 if (err < 0) {
378 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
379 return err;
380 }
381
382 rate = clk_get_rate(dc->clk);
383 *div = (rate * 2 / pclk) - 2;
384
385 DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate, *div);
386
387 return 0;
388}
389
f34bc787
TR		 390static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
391{
392 switch (format) {
393 case WIN_COLOR_DEPTH_YCbCr422:
394 case WIN_COLOR_DEPTH_YUV422:
395 if (planar)
396 *planar = false;
397
398 return true;
399
400 case WIN_COLOR_DEPTH_YCbCr420P:
401 case WIN_COLOR_DEPTH_YUV420P:
402 case WIN_COLOR_DEPTH_YCbCr422P:
403 case WIN_COLOR_DEPTH_YUV422P:
404 case WIN_COLOR_DEPTH_YCbCr422R:
405 case WIN_COLOR_DEPTH_YUV422R:
406 case WIN_COLOR_DEPTH_YCbCr422RA:
407 case WIN_COLOR_DEPTH_YUV422RA:
408 if (planar)
409 *planar = true;
410
411 return true;
412 }
413
414 return false;
415}
416
417int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
418 const struct tegra_dc_window *window)
419{
420 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
421 unsigned long value;
422 bool yuv, planar;
423
424 /*
425 * For YUV planar modes, the number of bytes per pixel takes into
426 * account only the luma component and therefore is 1.
427 */
428 yuv = tegra_dc_format_is_yuv(window->format, &planar);
429 if (!yuv)
430 bpp = window->bits_per_pixel / 8;
431 else
432 bpp = planar ? 1 : 2;
433
434 value = WINDOW_A_SELECT << index;
435 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
436
437 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
438 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
439
440 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
441 tegra_dc_writel(dc, value, DC_WIN_POSITION);
442
443 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
444 tegra_dc_writel(dc, value, DC_WIN_SIZE);
445
446 h_offset = window->src.x * bpp;
447 v_offset = window->src.y;
448 h_size = window->src.w * bpp;
449 v_size = window->src.h;
450
451 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
452 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
453
454 /*
455 * For DDA computations the number of bytes per pixel for YUV planar
456 * modes needs to take into account all Y, U and V components.
457 */
458 if (yuv && planar)
459 bpp = 2;
460
461 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
462 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
463
464 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
465 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
466
467 h_dda = compute_initial_dda(window->src.x);
468 v_dda = compute_initial_dda(window->src.y);
469
470 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
471 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
472
473 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
474 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
475
476 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
477
478 if (yuv && planar) {
479 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
480 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
481 value = window->stride[1] << 16 | window->stride[0];
482 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
483 } else {
484 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
485 }
486
487 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
488 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
489
490 value = WIN_ENABLE;
491
492 if (yuv) {
493 /* setup default colorspace conversion coefficients */
494 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
495 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
496 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
497 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
498 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
499 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
500 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
501 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
502
503 value |= CSC_ENABLE;
84ff6b27 504 } else if (window->bits_per_pixel < 24) {
f34bc787
TR		 505 value |= COLOR_EXPAND;
506 }
507
508 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
509
510 /*
511 * Disable blending and assume Window A is the bottom-most window,
512 * Window C is the top-most window and Window B is in the middle.
513 */
514 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
515 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
516
517 switch (index) {
518 case 0:
519 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
520 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
521 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
522 break;
523
524 case 1:
525 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
526 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
527 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
528 break;
529
530 case 2:
531 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
532 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
533 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
534 break;
535 }
536
537 tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL);
538 tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL);
539
540 return 0;
541}
542
543unsigned int tegra_dc_format(uint32_t format)
544{
545 switch (format) {
546 case DRM_FORMAT_XRGB8888:
547 return WIN_COLOR_DEPTH_B8G8R8A8;
548
549 case DRM_FORMAT_RGB565:
550 return WIN_COLOR_DEPTH_B5G6R5;
551
552 case DRM_FORMAT_UYVY:
553 return WIN_COLOR_DEPTH_YCbCr422;
554
555 case DRM_FORMAT_YUV420:
556 return WIN_COLOR_DEPTH_YCbCr420P;
557
558 case DRM_FORMAT_YUV422:
559 return WIN_COLOR_DEPTH_YCbCr422P;
560
561 default:
562 break;
563 }
564
565 WARN(1, "unsupported pixel format %u, using default\n", format);
566 return WIN_COLOR_DEPTH_B8G8R8A8;
567}
568
d8f4a9ed
TR		 569static int tegra_crtc_mode_set(struct drm_crtc *crtc,
570 struct drm_display_mode *mode,
571 struct drm_display_mode *adjusted,
572 int x, int y, struct drm_framebuffer *old_fb)
573{
de2ba664 574 struct tegra_bo *bo = tegra_fb_get_plane(crtc->fb, 0);
d8f4a9ed 575 struct tegra_dc *dc = to_tegra_dc(crtc);
f34bc787 576 struct tegra_dc_window window;
d8f4a9ed
TR		 577 unsigned long div, value;
578 int err;
579
6e5ff998
TR		 580 drm_vblank_pre_modeset(crtc->dev, dc->pipe);
581
d8f4a9ed
TR		 582 err = tegra_crtc_setup_clk(crtc, mode, &div);
583 if (err) {
584 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
585 return err;
586 }
587
588 /* program display mode */
589 tegra_dc_set_timings(dc, mode);
590
591 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
592 tegra_dc_writel(dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
593
594 value = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY(1));
595 value &= ~LVS_OUTPUT_POLARITY_LOW;
596 value &= ~LHS_OUTPUT_POLARITY_LOW;
597 tegra_dc_writel(dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
598
599 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
600 DISP_ORDER_RED_BLUE;
601 tegra_dc_writel(dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
602
603 tegra_dc_writel(dc, 0x00010001, DC_DISP_SHIFT_CLOCK_OPTIONS);
604
605 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
606 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
607
608 /* setup window parameters */
f34bc787
TR		 609 memset(&window, 0, sizeof(window));
610 window.src.x = 0;
611 window.src.y = 0;
612 window.src.w = mode->hdisplay;
613 window.src.h = mode->vdisplay;
614 window.dst.x = 0;
615 window.dst.y = 0;
616 window.dst.w = mode->hdisplay;
617 window.dst.h = mode->vdisplay;
618 window.format = tegra_dc_format(crtc->fb->pixel_format);
619 window.bits_per_pixel = crtc->fb->bits_per_pixel;
620 window.stride[0] = crtc->fb->pitches[0];
de2ba664 621 window.base[0] = bo->paddr;
f34bc787
TR		 622
623 err = tegra_dc_setup_window(dc, 0, &window);
624 if (err < 0)
625 dev_err(dc->dev, "failed to enable root plane\n");
d8f4a9ed 626
d8f4a9ed
TR		 627 return 0;
628}
d8f4a9ed 629
23fb4740
TR		 630static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
631 struct drm_framebuffer *old_fb)
632{
633 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed 634
23fb4740 635 return tegra_dc_set_base(dc, x, y, crtc->fb);
d8f4a9ed
TR		 636}
637
638static void tegra_crtc_prepare(struct drm_crtc *crtc)
639{
640 struct tegra_dc *dc = to_tegra_dc(crtc);
641 unsigned int syncpt;
642 unsigned long value;
643
644 /* hardware initialization */
645 tegra_periph_reset_deassert(dc->clk);
646 usleep_range(10000, 20000);
647
648 if (dc->pipe)
649 syncpt = SYNCPT_VBLANK1;
650 else
651 syncpt = SYNCPT_VBLANK0;
652
653 /* initialize display controller */
654 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
655 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
656
657 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
658 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
659
660 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
661 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
662 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
663
664 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
665 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
666 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
667
668 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
669 value |= DISP_CTRL_MODE_C_DISPLAY;
670 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
671
672 /* initialize timer */
673 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
674 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
675 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
676
677 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
678 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
679 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
680
d8f4a9ed
TR		 681 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
682 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
6e5ff998
TR		 683
684 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
685 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
d8f4a9ed
TR		 686}
687
688static void tegra_crtc_commit(struct drm_crtc *crtc)
689{
690 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed
TR		 691 unsigned long value;
692
3b9e71ea
TR		 693 value = GENERAL_UPDATE | WIN_A_UPDATE;
694 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
d8f4a9ed 695
3b9e71ea 696 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
6e5ff998 697 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
d8f4a9ed 698
6e5ff998 699 drm_vblank_post_modeset(crtc->dev, dc->pipe);
d8f4a9ed
TR		 700}
701
702static void tegra_crtc_load_lut(struct drm_crtc *crtc)
703{
704}
705
706static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
f34bc787 707 .disable = tegra_crtc_disable,
d8f4a9ed
TR		 708 .mode_fixup = tegra_crtc_mode_fixup,
709 .mode_set = tegra_crtc_mode_set,
23fb4740 710 .mode_set_base = tegra_crtc_mode_set_base,
d8f4a9ed
TR		 711 .prepare = tegra_crtc_prepare,
712 .commit = tegra_crtc_commit,
713 .load_lut = tegra_crtc_load_lut,
714};
715
6e5ff998 716static irqreturn_t tegra_dc_irq(int irq, void *data)
d8f4a9ed
TR		 717{
718 struct tegra_dc *dc = data;
719 unsigned long status;
720
721 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
722 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
723
724 if (status & FRAME_END_INT) {
725 /*
726 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
727 */
728 }
729
730 if (status & VBLANK_INT) {
731 /*
732 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
733 */
734 drm_handle_vblank(dc->base.dev, dc->pipe);
3c03c46a 735 tegra_dc_finish_page_flip(dc);
d8f4a9ed
TR		 736 }
737
738 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
739 /*
740 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
741 */
742 }
743
744 return IRQ_HANDLED;
745}
746
747static int tegra_dc_show_regs(struct seq_file *s, void *data)
748{
749 struct drm_info_node *node = s->private;
750 struct tegra_dc *dc = node->info_ent->data;
751
752#define DUMP_REG(name) \
753 seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \
754 tegra_dc_readl(dc, name))
755
756 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
757 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
758 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
759 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
760 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
761 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
762 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
763 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
764 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
765 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
766 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
767 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
768 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
769 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
770 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
771 DUMP_REG(DC_CMD_SIGNAL_RAISE);
772 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
773 DUMP_REG(DC_CMD_INT_STATUS);
774 DUMP_REG(DC_CMD_INT_MASK);
775 DUMP_REG(DC_CMD_INT_ENABLE);
776 DUMP_REG(DC_CMD_INT_TYPE);
777 DUMP_REG(DC_CMD_INT_POLARITY);
778 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
779 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
780 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
781 DUMP_REG(DC_CMD_STATE_ACCESS);
782 DUMP_REG(DC_CMD_STATE_CONTROL);
783 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
784 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
785 DUMP_REG(DC_COM_CRC_CONTROL);
786 DUMP_REG(DC_COM_CRC_CHECKSUM);
787 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
788 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
789 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
790 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
791 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
792 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
793 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
794 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
795 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
796 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
797 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
798 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
799 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
800 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
801 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
802 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
803 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
804 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
805 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
806 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
807 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
808 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
809 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
810 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
811 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
812 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
813 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
814 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
815 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
816 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
817 DUMP_REG(DC_COM_SPI_CONTROL);
818 DUMP_REG(DC_COM_SPI_START_BYTE);
819 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
820 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
821 DUMP_REG(DC_COM_HSPI_CS_DC);
822 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
823 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
824 DUMP_REG(DC_COM_GPIO_CTRL);
825 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
826 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
827 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
828 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
829 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
830 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
831 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
832 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
833 DUMP_REG(DC_DISP_REF_TO_SYNC);
834 DUMP_REG(DC_DISP_SYNC_WIDTH);
835 DUMP_REG(DC_DISP_BACK_PORCH);
836 DUMP_REG(DC_DISP_ACTIVE);
837 DUMP_REG(DC_DISP_FRONT_PORCH);
838 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
839 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
840 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
841 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
842 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
843 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
844 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
845 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
846 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
847 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
848 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
849 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
850 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
851 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
852 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
853 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
854 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
855 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
856 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
857 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
858 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
859 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
860 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
861 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
862 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
863 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
864 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
865 DUMP_REG(DC_DISP_M0_CONTROL);
866 DUMP_REG(DC_DISP_M1_CONTROL);
867 DUMP_REG(DC_DISP_DI_CONTROL);
868 DUMP_REG(DC_DISP_PP_CONTROL);
869 DUMP_REG(DC_DISP_PP_SELECT_A);
870 DUMP_REG(DC_DISP_PP_SELECT_B);
871 DUMP_REG(DC_DISP_PP_SELECT_C);
872 DUMP_REG(DC_DISP_PP_SELECT_D);
873 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
874 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
875 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
876 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
877 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
878 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
879 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
880 DUMP_REG(DC_DISP_BORDER_COLOR);
881 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
882 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
883 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
884 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
885 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
886 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
887 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
888 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
889 DUMP_REG(DC_DISP_CURSOR_POSITION);
890 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
891 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
892 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
893 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
894 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
895 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
896 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
897 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
898 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
899 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
900 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
901 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
902 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
903 DUMP_REG(DC_DISP_SD_CONTROL);
904 DUMP_REG(DC_DISP_SD_CSC_COEFF);
905 DUMP_REG(DC_DISP_SD_LUT(0));
906 DUMP_REG(DC_DISP_SD_LUT(1));
907 DUMP_REG(DC_DISP_SD_LUT(2));
908 DUMP_REG(DC_DISP_SD_LUT(3));
909 DUMP_REG(DC_DISP_SD_LUT(4));
910 DUMP_REG(DC_DISP_SD_LUT(5));
911 DUMP_REG(DC_DISP_SD_LUT(6));
912 DUMP_REG(DC_DISP_SD_LUT(7));
913 DUMP_REG(DC_DISP_SD_LUT(8));
914 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
915 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
916 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
917 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
918 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
919 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
920 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
921 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
922 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
923 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
924 DUMP_REG(DC_DISP_SD_BL_TF(0));
925 DUMP_REG(DC_DISP_SD_BL_TF(1));
926 DUMP_REG(DC_DISP_SD_BL_TF(2));
927 DUMP_REG(DC_DISP_SD_BL_TF(3));
928 DUMP_REG(DC_DISP_SD_BL_CONTROL);
929 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
930 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
931 DUMP_REG(DC_WIN_WIN_OPTIONS);
932 DUMP_REG(DC_WIN_BYTE_SWAP);
933 DUMP_REG(DC_WIN_BUFFER_CONTROL);
934 DUMP_REG(DC_WIN_COLOR_DEPTH);
935 DUMP_REG(DC_WIN_POSITION);
936 DUMP_REG(DC_WIN_SIZE);
937 DUMP_REG(DC_WIN_PRESCALED_SIZE);
938 DUMP_REG(DC_WIN_H_INITIAL_DDA);
939 DUMP_REG(DC_WIN_V_INITIAL_DDA);
940 DUMP_REG(DC_WIN_DDA_INC);
941 DUMP_REG(DC_WIN_LINE_STRIDE);
942 DUMP_REG(DC_WIN_BUF_STRIDE);
943 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
944 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
945 DUMP_REG(DC_WIN_DV_CONTROL);
946 DUMP_REG(DC_WIN_BLEND_NOKEY);
947 DUMP_REG(DC_WIN_BLEND_1WIN);
948 DUMP_REG(DC_WIN_BLEND_2WIN_X);
949 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
f34bc787 950 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
d8f4a9ed
TR		 951 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
952 DUMP_REG(DC_WINBUF_START_ADDR);
953 DUMP_REG(DC_WINBUF_START_ADDR_NS);
954 DUMP_REG(DC_WINBUF_START_ADDR_U);
955 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
956 DUMP_REG(DC_WINBUF_START_ADDR_V);
957 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
958 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
959 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
960 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
961 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
962 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
963 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
964 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
965 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
966
967#undef DUMP_REG
968
969 return 0;
970}
971
972static struct drm_info_list debugfs_files[] = {
973 { "regs", tegra_dc_show_regs, 0, NULL },
974};
975
976static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
977{
978 unsigned int i;
979 char *name;
980 int err;
981
982 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
983 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
984 kfree(name);
985
986 if (!dc->debugfs)
987 return -ENOMEM;
988
989 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
990 GFP_KERNEL);
991 if (!dc->debugfs_files) {
992 err = -ENOMEM;
993 goto remove;
994 }
995
996 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
997 dc->debugfs_files[i].data = dc;
998
999 err = drm_debugfs_create_files(dc->debugfs_files,
1000 ARRAY_SIZE(debugfs_files),
1001 dc->debugfs, minor);
1002 if (err < 0)
1003 goto free;
1004
1005 dc->minor = minor;
1006
1007 return 0;
1008
1009free:
1010 kfree(dc->debugfs_files);
1011 dc->debugfs_files = NULL;
1012remove:
1013 debugfs_remove(dc->debugfs);
1014 dc->debugfs = NULL;
1015
1016 return err;
1017}
1018
1019static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1020{
1021 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1022 dc->minor);
1023 dc->minor = NULL;
1024
1025 kfree(dc->debugfs_files);
1026 dc->debugfs_files = NULL;
1027
1028 debugfs_remove(dc->debugfs);
1029 dc->debugfs = NULL;
1030
1031 return 0;
1032}
1033
1034static int tegra_dc_drm_init(struct host1x_client *client,
1035 struct drm_device *drm)
1036{
1037 struct tegra_dc *dc = host1x_client_to_dc(client);
1038 int err;
1039
1040 dc->pipe = drm->mode_config.num_crtc;
1041
1042 drm_crtc_init(drm, &dc->base, &tegra_crtc_funcs);
1043 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1044 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1045
1046 err = tegra_dc_rgb_init(drm, dc);
1047 if (err < 0 && err != -ENODEV) {
1048 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1049 return err;
1050 }
1051
f34bc787
TR		 1052 err = tegra_dc_add_planes(drm, dc);
1053 if (err < 0)
1054 return err;
1055
d8f4a9ed
TR		 1056 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1057 err = tegra_dc_debugfs_init(dc, drm->primary);
1058 if (err < 0)
1059 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1060 }
1061
6e5ff998 1062 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
d8f4a9ed
TR		 1063 dev_name(dc->dev), dc);
1064 if (err < 0) {
1065 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1066 err);
1067 return err;
1068 }
1069
1070 return 0;
1071}
1072
1073static int tegra_dc_drm_exit(struct host1x_client *client)
1074{
1075 struct tegra_dc *dc = host1x_client_to_dc(client);
1076 int err;
1077
1078 devm_free_irq(dc->dev, dc->irq, dc);
1079
1080 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1081 err = tegra_dc_debugfs_exit(dc);
1082 if (err < 0)
1083 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1084 }
1085
1086 err = tegra_dc_rgb_exit(dc);
1087 if (err) {
1088 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1089 return err;
1090 }
1091
1092 return 0;
1093}
1094
1095static const struct host1x_client_ops dc_client_ops = {
1096 .drm_init = tegra_dc_drm_init,
1097 .drm_exit = tegra_dc_drm_exit,
1098};
1099
1100static int tegra_dc_probe(struct platform_device *pdev)
1101{
692e6d7b 1102 struct host1x_drm *host1x = host1x_get_drm_data(pdev->dev.parent);
d8f4a9ed
TR		 1103 struct resource *regs;
1104 struct tegra_dc *dc;
1105 int err;
1106
1107 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1108 if (!dc)
1109 return -ENOMEM;
1110
6e5ff998 1111 spin_lock_init(&dc->lock);
d8f4a9ed
TR		 1112 INIT_LIST_HEAD(&dc->list);
1113 dc->dev = &pdev->dev;
1114
1115 dc->clk = devm_clk_get(&pdev->dev, NULL);
1116 if (IS_ERR(dc->clk)) {
1117 dev_err(&pdev->dev, "failed to get clock\n");
1118 return PTR_ERR(dc->clk);
1119 }
1120
1121 err = clk_prepare_enable(dc->clk);
1122 if (err < 0)
1123 return err;
1124
1125 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1126 if (!regs) {
1127 dev_err(&pdev->dev, "failed to get registers\n");
1128 return -ENXIO;
1129 }
1130
d4ed6025
TR		 1131 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1132 if (IS_ERR(dc->regs))
1133 return PTR_ERR(dc->regs);
d8f4a9ed
TR		 1134
1135 dc->irq = platform_get_irq(pdev, 0);
1136 if (dc->irq < 0) {
1137 dev_err(&pdev->dev, "failed to get IRQ\n");
1138 return -ENXIO;
1139 }
1140
1141 INIT_LIST_HEAD(&dc->client.list);
1142 dc->client.ops = &dc_client_ops;
1143 dc->client.dev = &pdev->dev;
1144
1145 err = tegra_dc_rgb_probe(dc);
1146 if (err < 0 && err != -ENODEV) {
1147 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1148 return err;
1149 }
1150
1151 err = host1x_register_client(host1x, &dc->client);
1152 if (err < 0) {
1153 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1154 err);
1155 return err;
1156 }
1157
1158 platform_set_drvdata(pdev, dc);
1159
1160 return 0;
1161}
1162
1163static int tegra_dc_remove(struct platform_device *pdev)
1164{
692e6d7b 1165 struct host1x_drm *host1x = host1x_get_drm_data(pdev->dev.parent);
d8f4a9ed
TR		 1166 struct tegra_dc *dc = platform_get_drvdata(pdev);
1167 int err;
1168
1169 err = host1x_unregister_client(host1x, &dc->client);
1170 if (err < 0) {
1171 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1172 err);
1173 return err;
1174 }
1175
1176 clk_disable_unprepare(dc->clk);
1177
1178 return 0;
1179}
1180
1181static struct of_device_id tegra_dc_of_match[] = {
219e8153 1182 { .compatible = "nvidia,tegra30-dc", },
d8f4a9ed
TR		 1183 { .compatible = "nvidia,tegra20-dc", },
1184 { },
1185};
1186
1187struct platform_driver tegra_dc_driver = {
1188 .driver = {
1189 .name = "tegra-dc",
1190 .owner = THIS_MODULE,
1191 .of_match_table = tegra_dc_of_match,
1192 },
1193 .probe = tegra_dc_probe,
1194 .remove = tegra_dc_remove,
1195};
Linux kernel - Deliverables
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