[deliverable/linux.git] / drivers / gpu / host1x / mipi.c

/*
 * Copyright (C) 2013 NVIDIA Corporation
 *
 * Permission to use, copy, modify, distribute, and sell this software and its
 * documentation for any purpose is hereby granted without fee, provided that
 * the above copyright notice appear in all copies and that both that copyright
 * notice and this permission notice appear in supporting documentation, and
 * that the name of the copyright holders not be used in advertising or
 * publicity pertaining to distribution of the software without specific,
 * written prior permission.  The copyright holders make no representations
 * about the suitability of this software for any purpose.  It is provided "as
 * is" without express or implied warranty.
 *
 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
 * OF THIS SOFTWARE.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/host1x.h>
#include <linux/io.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include "dev.h"

#define MIPI_CAL_CTRL			0x00
#define MIPI_CAL_CTRL_NOISE_FILTER(x)	(((x) & 0xf) << 26)
#define MIPI_CAL_CTRL_PRESCALE(x)	(((x) & 0x3) << 24)
#define MIPI_CAL_CTRL_CLKEN_OVR		(1 << 4)
#define MIPI_CAL_CTRL_START		(1 << 0)

#define MIPI_CAL_AUTOCAL_CTRL		0x01

#define MIPI_CAL_STATUS			0x02
#define MIPI_CAL_STATUS_DONE		(1 << 16)
#define MIPI_CAL_STATUS_ACTIVE		(1 <<  0)

#define MIPI_CAL_CONFIG_CSIA		0x05
#define MIPI_CAL_CONFIG_CSIB		0x06
#define MIPI_CAL_CONFIG_CSIC		0x07
#define MIPI_CAL_CONFIG_CSID		0x08
#define MIPI_CAL_CONFIG_CSIE		0x09
#define MIPI_CAL_CONFIG_DSIA		0x0e
#define MIPI_CAL_CONFIG_DSIB		0x0f
#define MIPI_CAL_CONFIG_DSIC		0x10
#define MIPI_CAL_CONFIG_DSID		0x11

#define MIPI_CAL_CONFIG_DSIA_CLK	0x19
#define MIPI_CAL_CONFIG_DSIB_CLK	0x1a
#define MIPI_CAL_CONFIG_CSIAB_CLK	0x1b
#define MIPI_CAL_CONFIG_CSICD_CLK	0x1c
#define MIPI_CAL_CONFIG_CSIE_CLK	0x1d

/* for data and clock lanes */
#define MIPI_CAL_CONFIG_SELECT		(1 << 21)

/* for data lanes */
#define MIPI_CAL_CONFIG_HSPDOS(x)	(((x) & 0x1f) << 16)
#define MIPI_CAL_CONFIG_HSPUOS(x)	(((x) & 0x1f) <<  8)
#define MIPI_CAL_CONFIG_TERMOS(x)	(((x) & 0x1f) <<  0)

/* for clock lanes */
#define MIPI_CAL_CONFIG_HSCLKPDOSD(x)	(((x) & 0x1f) <<  8)
#define MIPI_CAL_CONFIG_HSCLKPUOSD(x)	(((x) & 0x1f) <<  0)

#define MIPI_CAL_BIAS_PAD_CFG0		0x16
#define MIPI_CAL_BIAS_PAD_PDVCLAMP	(1 << 1)
#define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF	(1 << 0)

#define MIPI_CAL_BIAS_PAD_CFG1		0x17
#define MIPI_CAL_BIAS_PAD_DRV_DN_REF(x) (((x) & 0x7) << 16)
#define MIPI_CAL_BIAS_PAD_DRV_UP_REF(x) (((x) & 0x7) << 8)

#define MIPI_CAL_BIAS_PAD_CFG2		0x18
#define MIPI_CAL_BIAS_PAD_VCLAMP(x)	(((x) & 0x7) << 16)
#define MIPI_CAL_BIAS_PAD_VAUXP(x)	(((x) & 0x7) << 4)
#define MIPI_CAL_BIAS_PAD_PDVREG	(1 << 1)

struct tegra_mipi_pad {
	unsigned long data;
	unsigned long clk;
};

struct tegra_mipi_soc {
	bool has_clk_lane;
	const struct tegra_mipi_pad *pads;
	unsigned int num_pads;

	bool clock_enable_override;
	bool needs_vclamp_ref;

	/* bias pad configuration settings */
	u8 pad_drive_down_ref;
	u8 pad_drive_up_ref;

	u8 pad_vclamp_level;
	u8 pad_vauxp_level;

	/* calibration settings for data lanes */
	u8 hspdos;
	u8 hspuos;
	u8 termos;

	/* calibration settings for clock lanes */
	u8 hsclkpdos;
	u8 hsclkpuos;
};

struct tegra_mipi {
	const struct tegra_mipi_soc *soc;
	void __iomem *regs;
	struct mutex lock;
	struct clk *clk;
};

struct tegra_mipi_device {
	struct platform_device *pdev;
	struct tegra_mipi *mipi;
	struct device *device;
	unsigned long pads;
};

static inline u32 tegra_mipi_readl(struct tegra_mipi *mipi,
				   unsigned long offset)
{
	return readl(mipi->regs + (offset << 2));
}

static inline void tegra_mipi_writel(struct tegra_mipi *mipi, u32 value,
				     unsigned long offset)
{
	writel(value, mipi->regs + (offset << 2));
}

struct tegra_mipi_device *tegra_mipi_request(struct device *device)
{
	struct device_node *np = device->of_node;
	struct tegra_mipi_device *dev;
	struct of_phandle_args args;
	int err;

	err = of_parse_phandle_with_args(np, "nvidia,mipi-calibrate",
					 "#nvidia,mipi-calibrate-cells", 0,
					 &args);
	if (err < 0)
		return ERR_PTR(err);

	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
	if (!dev) {
		err = -ENOMEM;
		goto out;
	}

	dev->pdev = of_find_device_by_node(args.np);
	if (!dev->pdev) {
		err = -ENODEV;
		goto free;
	}

	dev->mipi = platform_get_drvdata(dev->pdev);
	if (!dev->mipi) {
		err = -EPROBE_DEFER;
		goto put;
	}

	of_node_put(args.np);

	dev->pads = args.args[0];
	dev->device = device;

	return dev;

put:
	platform_device_put(dev->pdev);
free:
	kfree(dev);
out:
	of_node_put(args.np);
	return ERR_PTR(err);
}
EXPORT_SYMBOL(tegra_mipi_request);

void tegra_mipi_free(struct tegra_mipi_device *device)
{
	platform_device_put(device->pdev);
	kfree(device);
}
EXPORT_SYMBOL(tegra_mipi_free);

static int tegra_mipi_wait(struct tegra_mipi *mipi)
{
	unsigned long timeout = jiffies + msecs_to_jiffies(250);
	u32 value;

	while (time_before(jiffies, timeout)) {
		value = tegra_mipi_readl(mipi, MIPI_CAL_STATUS);
		if ((value & MIPI_CAL_STATUS_ACTIVE) == 0 &&
		    (value & MIPI_CAL_STATUS_DONE) != 0)
			return 0;

		usleep_range(10, 50);
	}

	return -ETIMEDOUT;
}

int tegra_mipi_calibrate(struct tegra_mipi_device *device)
{
	const struct tegra_mipi_soc *soc = device->mipi->soc;
	unsigned int i;
	u32 value;
	int err;

	err = clk_enable(device->mipi->clk);
	if (err < 0)
		return err;

	mutex_lock(&device->mipi->lock);

	value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG0);
	value &= ~MIPI_CAL_BIAS_PAD_PDVCLAMP;

	if (soc->needs_vclamp_ref)
		value |= MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;

	tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG0);

	value = MIPI_CAL_BIAS_PAD_DRV_DN_REF(soc->pad_drive_down_ref) |
		MIPI_CAL_BIAS_PAD_DRV_UP_REF(soc->pad_drive_up_ref);
	tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG1);

	value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2);
	value &= ~MIPI_CAL_BIAS_PAD_PDVREG;
	tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2);

	value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2);
	value &= ~MIPI_CAL_BIAS_PAD_VCLAMP(0x7);
	value &= ~MIPI_CAL_BIAS_PAD_VAUXP(0x7);
	value |= MIPI_CAL_BIAS_PAD_VCLAMP(soc->pad_vclamp_level);
	value |= MIPI_CAL_BIAS_PAD_VAUXP(soc->pad_vauxp_level);
	tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2);

	for (i = 0; i < soc->num_pads; i++) {
		u32 clk = 0, data = 0;

		if (device->pads & BIT(i)) {
			data = MIPI_CAL_CONFIG_SELECT |
			       MIPI_CAL_CONFIG_HSPDOS(soc->hspdos) |
			       MIPI_CAL_CONFIG_HSPUOS(soc->hspuos) |
			       MIPI_CAL_CONFIG_TERMOS(soc->termos);
			clk = MIPI_CAL_CONFIG_SELECT |
			      MIPI_CAL_CONFIG_HSCLKPDOSD(soc->hsclkpdos) |
			      MIPI_CAL_CONFIG_HSCLKPUOSD(soc->hsclkpuos);
		}

		tegra_mipi_writel(device->mipi, data, soc->pads[i].data);

		if (soc->has_clk_lane)
			tegra_mipi_writel(device->mipi, clk, soc->pads[i].clk);
	}

	value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
	value &= ~MIPI_CAL_CTRL_NOISE_FILTER(0xf);
	value &= ~MIPI_CAL_CTRL_PRESCALE(0x3);
	value |= MIPI_CAL_CTRL_NOISE_FILTER(0xa);
	value |= MIPI_CAL_CTRL_PRESCALE(0x2);

	if (!soc->clock_enable_override)
		value &= ~MIPI_CAL_CTRL_CLKEN_OVR;
	else
		value |= MIPI_CAL_CTRL_CLKEN_OVR;

	tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);

	/* clear any pending status bits */
	value = tegra_mipi_readl(device->mipi, MIPI_CAL_STATUS);
	tegra_mipi_writel(device->mipi, value, MIPI_CAL_STATUS);

	value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
	value |= MIPI_CAL_CTRL_START;
	tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);

	err = tegra_mipi_wait(device->mipi);

	mutex_unlock(&device->mipi->lock);
	clk_disable(device->mipi->clk);

	return err;
}
EXPORT_SYMBOL(tegra_mipi_calibrate);

static const struct tegra_mipi_pad tegra114_mipi_pads[] = {
	{ .data = MIPI_CAL_CONFIG_CSIA },
	{ .data = MIPI_CAL_CONFIG_CSIB },
	{ .data = MIPI_CAL_CONFIG_CSIC },
	{ .data = MIPI_CAL_CONFIG_CSID },
	{ .data = MIPI_CAL_CONFIG_CSIE },
	{ .data = MIPI_CAL_CONFIG_DSIA },
	{ .data = MIPI_CAL_CONFIG_DSIB },
	{ .data = MIPI_CAL_CONFIG_DSIC },
	{ .data = MIPI_CAL_CONFIG_DSID },
};

static const struct tegra_mipi_soc tegra114_mipi_soc = {
	.has_clk_lane = false,
	.pads = tegra114_mipi_pads,
	.num_pads = ARRAY_SIZE(tegra114_mipi_pads),
	.clock_enable_override = true,
	.needs_vclamp_ref = true,
	.pad_drive_down_ref = 0x2,
	.pad_drive_up_ref = 0x0,
	.pad_vclamp_level = 0x0,
	.pad_vauxp_level = 0x0,
	.hspdos = 0x0,
	.hspuos = 0x4,
	.termos = 0x5,
	.hsclkpdos = 0x0,
	.hsclkpuos = 0x4,
};

static const struct tegra_mipi_pad tegra124_mipi_pads[] = {
	{ .data = MIPI_CAL_CONFIG_CSIA, .clk = MIPI_CAL_CONFIG_CSIAB_CLK },
	{ .data = MIPI_CAL_CONFIG_CSIB, .clk = MIPI_CAL_CONFIG_CSIAB_CLK },
	{ .data = MIPI_CAL_CONFIG_CSIC, .clk = MIPI_CAL_CONFIG_CSICD_CLK },
	{ .data = MIPI_CAL_CONFIG_CSID, .clk = MIPI_CAL_CONFIG_CSICD_CLK },
	{ .data = MIPI_CAL_CONFIG_CSIE, .clk = MIPI_CAL_CONFIG_CSIE_CLK  },
	{ .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIA_CLK  },
	{ .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIB_CLK  },
};

static const struct tegra_mipi_soc tegra124_mipi_soc = {
	.has_clk_lane = true,
	.pads = tegra124_mipi_pads,
	.num_pads = ARRAY_SIZE(tegra124_mipi_pads),
	.clock_enable_override = true,
	.needs_vclamp_ref = true,
	.pad_drive_down_ref = 0x2,
	.pad_drive_up_ref = 0x0,
	.pad_vclamp_level = 0x0,
	.pad_vauxp_level = 0x0,
	.hspdos = 0x0,
	.hspuos = 0x0,
	.termos = 0x0,
	.hsclkpdos = 0x1,
	.hsclkpuos = 0x2,
};

static struct of_device_id tegra_mipi_of_match[] = {
	{ .compatible = "nvidia,tegra114-mipi", .data = &tegra114_mipi_soc },
	{ .compatible = "nvidia,tegra124-mipi", .data = &tegra124_mipi_soc },
	{ },
};

static int tegra_mipi_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	struct tegra_mipi *mipi;
	struct resource *res;
	int err;

	match = of_match_node(tegra_mipi_of_match, pdev->dev.of_node);
	if (!match)
		return -ENODEV;

	mipi = devm_kzalloc(&pdev->dev, sizeof(*mipi), GFP_KERNEL);
	if (!mipi)
		return -ENOMEM;

	mipi->soc = match->data;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mipi->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mipi->regs))
		return PTR_ERR(mipi->regs);

	mutex_init(&mipi->lock);

	mipi->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(mipi->clk)) {
		dev_err(&pdev->dev, "failed to get clock\n");
		return PTR_ERR(mipi->clk);
	}

	err = clk_prepare(mipi->clk);
	if (err < 0)
		return err;

	platform_set_drvdata(pdev, mipi);

	return 0;
}

static int tegra_mipi_remove(struct platform_device *pdev)
{
	struct tegra_mipi *mipi = platform_get_drvdata(pdev);

	clk_unprepare(mipi->clk);

	return 0;
}

struct platform_driver tegra_mipi_driver = {
	.driver = {
		.name = "tegra-mipi",
		.of_match_table = tegra_mipi_of_match,
	},
	.probe = tegra_mipi_probe,
	.remove = tegra_mipi_remove,
};
Commit	Line	Data
4de6a2d6 TR	1	/*
	2	* Copyright (C) 2013 NVIDIA Corporation
	3	*
	4	* Permission to use, copy, modify, distribute, and sell this software and its
	5	* documentation for any purpose is hereby granted without fee, provided that
	6	* the above copyright notice appear in all copies and that both that copyright
	7	* notice and this permission notice appear in supporting documentation, and
	8	* that the name of the copyright holders not be used in advertising or
	9	* publicity pertaining to distribution of the software without specific,
	10	* written prior permission. The copyright holders make no representations
	11	* about the suitability of this software for any purpose. It is provided "as
	12	* is" without express or implied warranty.
	13	*
	14	* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
	15	* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
	16	* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
	17	* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
	18	* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
	19	* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
	20	* OF THIS SOFTWARE.
	21	*/
	22
	23	#include <linux/clk.h>
	24	#include <linux/delay.h>
aef03d3f	25	#include <linux/host1x.h>
4de6a2d6 TR	26	#include <linux/io.h>
	27	#include <linux/of_platform.h>
	28	#include <linux/platform_device.h>
	29	#include <linux/slab.h>
	30
aef03d3f TR	31	#include "dev.h"
aef03d3f TR	32
4de6a2d6	33	#define MIPI_CAL_CTRL 0x00
83a3c223 TR	34	#define MIPI_CAL_CTRL_NOISE_FILTER(x) (((x) & 0xf) << 26)
	35	#define MIPI_CAL_CTRL_PRESCALE(x) (((x) & 0x3) << 24)
	36	#define MIPI_CAL_CTRL_CLKEN_OVR (1 << 4)
4de6a2d6 TR	37	#define MIPI_CAL_CTRL_START (1 << 0)
	38
	39	#define MIPI_CAL_AUTOCAL_CTRL 0x01
	40
	41	#define MIPI_CAL_STATUS 0x02
	42	#define MIPI_CAL_STATUS_DONE (1 << 16)
	43	#define MIPI_CAL_STATUS_ACTIVE (1 << 0)
	44
	45	#define MIPI_CAL_CONFIG_CSIA 0x05
	46	#define MIPI_CAL_CONFIG_CSIB 0x06
	47	#define MIPI_CAL_CONFIG_CSIC 0x07
	48	#define MIPI_CAL_CONFIG_CSID 0x08
	49	#define MIPI_CAL_CONFIG_CSIE 0x09
	50	#define MIPI_CAL_CONFIG_DSIA 0x0e
	51	#define MIPI_CAL_CONFIG_DSIB 0x0f
	52	#define MIPI_CAL_CONFIG_DSIC 0x10
	53	#define MIPI_CAL_CONFIG_DSID 0x11
	54
8ed5c062 TR	55	#define MIPI_CAL_CONFIG_DSIA_CLK 0x19
8ed5c062 TR	56	#define MIPI_CAL_CONFIG_DSIB_CLK 0x1a
08a15cc3 SP	57	#define MIPI_CAL_CONFIG_CSIAB_CLK 0x1b
	58	#define MIPI_CAL_CONFIG_CSICD_CLK 0x1c
	59	#define MIPI_CAL_CONFIG_CSIE_CLK 0x1d
	60
	61	/* for data and clock lanes */
4de6a2d6	62	#define MIPI_CAL_CONFIG_SELECT (1 << 21)
08a15cc3 SP	63
08a15cc3 SP	64	/* for data lanes */
4de6a2d6 TR	65	#define MIPI_CAL_CONFIG_HSPDOS(x) (((x) & 0x1f) << 16)
	66	#define MIPI_CAL_CONFIG_HSPUOS(x) (((x) & 0x1f) << 8)
	67	#define MIPI_CAL_CONFIG_TERMOS(x) (((x) & 0x1f) << 0)
	68
08a15cc3 SP	69	/* for clock lanes */
	70	#define MIPI_CAL_CONFIG_HSCLKPDOSD(x) (((x) & 0x1f) << 8)
	71	#define MIPI_CAL_CONFIG_HSCLKPUOSD(x) (((x) & 0x1f) << 0)
	72
4de6a2d6 TR	73	#define MIPI_CAL_BIAS_PAD_CFG0 0x16
	74	#define MIPI_CAL_BIAS_PAD_PDVCLAMP (1 << 1)
	75	#define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF (1 << 0)
	76
	77	#define MIPI_CAL_BIAS_PAD_CFG1 0x17
b298e98e	78	#define MIPI_CAL_BIAS_PAD_DRV_DN_REF(x) (((x) & 0x7) << 16)
83a3c223	79	#define MIPI_CAL_BIAS_PAD_DRV_UP_REF(x) (((x) & 0x7) << 8)
4de6a2d6 TR	80
4de6a2d6 TR	81	#define MIPI_CAL_BIAS_PAD_CFG2 0x18
83a3c223 TR	82	#define MIPI_CAL_BIAS_PAD_VCLAMP(x) (((x) & 0x7) << 16)
83a3c223 TR	83	#define MIPI_CAL_BIAS_PAD_VAUXP(x) (((x) & 0x7) << 4)
4de6a2d6 TR	84	#define MIPI_CAL_BIAS_PAD_PDVREG (1 << 1)
4de6a2d6 TR	85
08a15cc3 SP	86	struct tegra_mipi_pad {
	87	unsigned long data;
	88	unsigned long clk;
	89	};
	90
	91	struct tegra_mipi_soc {
	92	bool has_clk_lane;
	93	const struct tegra_mipi_pad *pads;
	94	unsigned int num_pads;
83a3c223 TR	95
	96	bool clock_enable_override;
	97	bool needs_vclamp_ref;
	98
	99	/* bias pad configuration settings */
	100	u8 pad_drive_down_ref;
	101	u8 pad_drive_up_ref;
	102
	103	u8 pad_vclamp_level;
	104	u8 pad_vauxp_level;
	105
	106	/* calibration settings for data lanes */
	107	u8 hspdos;
	108	u8 hspuos;
	109	u8 termos;
	110
	111	/* calibration settings for clock lanes */
	112	u8 hsclkpdos;
	113	u8 hsclkpuos;
4de6a2d6 TR	114	};
	115
	116	struct tegra_mipi {
08a15cc3	117	const struct tegra_mipi_soc *soc;
4de6a2d6 TR	118	void __iomem *regs;
	119	struct mutex lock;
	120	struct clk *clk;
	121	};
	122
	123	struct tegra_mipi_device {
	124	struct platform_device *pdev;
	125	struct tegra_mipi *mipi;
	126	struct device *device;
	127	unsigned long pads;
	128	};
	129
57b17ae7 TR	130	static inline u32 tegra_mipi_readl(struct tegra_mipi *mipi,
57b17ae7 TR	131	unsigned long offset)
4de6a2d6	132	{
57b17ae7	133	return readl(mipi->regs + (offset << 2));
4de6a2d6 TR	134	}
4de6a2d6 TR	135
57b17ae7 TR	136	static inline void tegra_mipi_writel(struct tegra_mipi *mipi, u32 value,
57b17ae7 TR	137	unsigned long offset)
4de6a2d6	138	{
57b17ae7	139	writel(value, mipi->regs + (offset << 2));
4de6a2d6 TR	140	}
	141
	142	struct tegra_mipi_device tegra_mipi_request(struct device device)
	143	{
	144	struct device_node *np = device->of_node;
	145	struct tegra_mipi_device *dev;
	146	struct of_phandle_args args;
	147	int err;
	148
	149	err = of_parse_phandle_with_args(np, "nvidia,mipi-calibrate",
	150	"#nvidia,mipi-calibrate-cells", 0,
	151	&args);
	152	if (err < 0)
	153	return ERR_PTR(err);
	154
	155	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
	156	if (!dev) {
4de6a2d6 TR	157	err = -ENOMEM;
	158	goto out;
	159	}
	160
	161	dev->pdev = of_find_device_by_node(args.np);
	162	if (!dev->pdev) {
4de6a2d6 TR	163	err = -ENODEV;
	164	goto free;
	165	}
	166
4de6a2d6 TR	167	dev->mipi = platform_get_drvdata(dev->pdev);
	168	if (!dev->mipi) {
	169	err = -EPROBE_DEFER;
08a15cc3	170	goto put;
4de6a2d6 TR	171	}
4de6a2d6 TR	172
08a15cc3 SP	173	of_node_put(args.np);
08a15cc3 SP	174
4de6a2d6 TR	175	dev->pads = args.args[0];
	176	dev->device = device;
	177
	178	return dev;
	179
08a15cc3	180	put:
4de6a2d6 TR	181	platform_device_put(dev->pdev);
	182	free:
	183	kfree(dev);
	184	out:
08a15cc3	185	of_node_put(args.np);
4de6a2d6 TR	186	return ERR_PTR(err);
	187	}
	188	EXPORT_SYMBOL(tegra_mipi_request);
	189
	190	void tegra_mipi_free(struct tegra_mipi_device *device)
	191	{
	192	platform_device_put(device->pdev);
	193	kfree(device);
	194	}
	195	EXPORT_SYMBOL(tegra_mipi_free);
	196
	197	static int tegra_mipi_wait(struct tegra_mipi *mipi)
	198	{
	199	unsigned long timeout = jiffies + msecs_to_jiffies(250);
57b17ae7	200	u32 value;
4de6a2d6 TR	201
	202	while (time_before(jiffies, timeout)) {
	203	value = tegra_mipi_readl(mipi, MIPI_CAL_STATUS);
	204	if ((value & MIPI_CAL_STATUS_ACTIVE) == 0 &&
	205	(value & MIPI_CAL_STATUS_DONE) != 0)
	206	return 0;
	207
	208	usleep_range(10, 50);
	209	}
	210
	211	return -ETIMEDOUT;
	212	}
	213
	214	int tegra_mipi_calibrate(struct tegra_mipi_device *device)
	215	{
08a15cc3	216	const struct tegra_mipi_soc *soc = device->mipi->soc;
4de6a2d6	217	unsigned int i;
57b17ae7	218	u32 value;
4de6a2d6 TR	219	int err;
	220
	221	err = clk_enable(device->mipi->clk);
	222	if (err < 0)
	223	return err;
	224
	225	mutex_lock(&device->mipi->lock);
	226
	227	value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG0);
	228	value &= ~MIPI_CAL_BIAS_PAD_PDVCLAMP;
83a3c223 TR	229
	230	if (soc->needs_vclamp_ref)
	231	value \|= MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
	232
4de6a2d6 TR	233	tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
4de6a2d6 TR	234
83a3c223 TR	235	value = MIPI_CAL_BIAS_PAD_DRV_DN_REF(soc->pad_drive_down_ref) \|
	236	MIPI_CAL_BIAS_PAD_DRV_UP_REF(soc->pad_drive_up_ref);
	237	tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG1);
b298e98e	238
4de6a2d6 TR	239	value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2);
	240	value &= ~MIPI_CAL_BIAS_PAD_PDVREG;
	241	tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
	242
83a3c223 TR	243	value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2);
	244	value &= ~MIPI_CAL_BIAS_PAD_VCLAMP(0x7);
	245	value &= ~MIPI_CAL_BIAS_PAD_VAUXP(0x7);
	246	value \|= MIPI_CAL_BIAS_PAD_VCLAMP(soc->pad_vclamp_level);
	247	value \|= MIPI_CAL_BIAS_PAD_VAUXP(soc->pad_vauxp_level);
	248	tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
	249
08a15cc3 SP	250	for (i = 0; i < soc->num_pads; i++) {
	251	u32 clk = 0, data = 0;
	252
	253	if (device->pads & BIT(i)) {
	254	data = MIPI_CAL_CONFIG_SELECT \|
83a3c223 TR	255	MIPI_CAL_CONFIG_HSPDOS(soc->hspdos) \|
	256	MIPI_CAL_CONFIG_HSPUOS(soc->hspuos) \|
	257	MIPI_CAL_CONFIG_TERMOS(soc->termos);
08a15cc3	258	clk = MIPI_CAL_CONFIG_SELECT \|
83a3c223 TR	259	MIPI_CAL_CONFIG_HSCLKPDOSD(soc->hsclkpdos) \|
83a3c223 TR	260	MIPI_CAL_CONFIG_HSCLKPUOSD(soc->hsclkpuos);
08a15cc3 SP	261	}
	262
	263	tegra_mipi_writel(device->mipi, data, soc->pads[i].data);
4de6a2d6	264
08a15cc3 SP	265	if (soc->has_clk_lane)
08a15cc3 SP	266	tegra_mipi_writel(device->mipi, clk, soc->pads[i].clk);
4de6a2d6 TR	267	}
4de6a2d6 TR	268
83a3c223 TR	269	value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
	270	value &= ~MIPI_CAL_CTRL_NOISE_FILTER(0xf);
	271	value &= ~MIPI_CAL_CTRL_PRESCALE(0x3);
	272	value \|= MIPI_CAL_CTRL_NOISE_FILTER(0xa);
	273	value \|= MIPI_CAL_CTRL_PRESCALE(0x2);
	274
	275	if (!soc->clock_enable_override)
	276	value &= ~MIPI_CAL_CTRL_CLKEN_OVR;
	277	else
	278	value \|= MIPI_CAL_CTRL_CLKEN_OVR;
	279
	280	tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
	281
2ed264bf TR	282	/* clear any pending status bits */
	283	value = tegra_mipi_readl(device->mipi, MIPI_CAL_STATUS);
	284	tegra_mipi_writel(device->mipi, value, MIPI_CAL_STATUS);
	285
26f7a92a SP	286	value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
	287	value \|= MIPI_CAL_CTRL_START;
	288	tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
4de6a2d6 TR	289
	290	err = tegra_mipi_wait(device->mipi);
	291
	292	mutex_unlock(&device->mipi->lock);
	293	clk_disable(device->mipi->clk);
	294
	295	return err;
	296	}
	297	EXPORT_SYMBOL(tegra_mipi_calibrate);
	298
08a15cc3 SP	299	static const struct tegra_mipi_pad tegra114_mipi_pads[] = {
	300	{ .data = MIPI_CAL_CONFIG_CSIA },
	301	{ .data = MIPI_CAL_CONFIG_CSIB },
	302	{ .data = MIPI_CAL_CONFIG_CSIC },
	303	{ .data = MIPI_CAL_CONFIG_CSID },
	304	{ .data = MIPI_CAL_CONFIG_CSIE },
	305	{ .data = MIPI_CAL_CONFIG_DSIA },
	306	{ .data = MIPI_CAL_CONFIG_DSIB },
	307	{ .data = MIPI_CAL_CONFIG_DSIC },
	308	{ .data = MIPI_CAL_CONFIG_DSID },
	309	};
	310
	311	static const struct tegra_mipi_soc tegra114_mipi_soc = {
	312	.has_clk_lane = false,
	313	.pads = tegra114_mipi_pads,
	314	.num_pads = ARRAY_SIZE(tegra114_mipi_pads),
83a3c223 TR	315	.clock_enable_override = true,
	316	.needs_vclamp_ref = true,
	317	.pad_drive_down_ref = 0x2,
	318	.pad_drive_up_ref = 0x0,
	319	.pad_vclamp_level = 0x0,
	320	.pad_vauxp_level = 0x0,
	321	.hspdos = 0x0,
	322	.hspuos = 0x4,
	323	.termos = 0x5,
	324	.hsclkpdos = 0x0,
	325	.hsclkpuos = 0x4,
08a15cc3 SP	326	};
	327
	328	static const struct tegra_mipi_pad tegra124_mipi_pads[] = {
	329	{ .data = MIPI_CAL_CONFIG_CSIA, .clk = MIPI_CAL_CONFIG_CSIAB_CLK },
	330	{ .data = MIPI_CAL_CONFIG_CSIB, .clk = MIPI_CAL_CONFIG_CSIAB_CLK },
	331	{ .data = MIPI_CAL_CONFIG_CSIC, .clk = MIPI_CAL_CONFIG_CSICD_CLK },
	332	{ .data = MIPI_CAL_CONFIG_CSID, .clk = MIPI_CAL_CONFIG_CSICD_CLK },
8ed5c062 TR	333	{ .data = MIPI_CAL_CONFIG_CSIE, .clk = MIPI_CAL_CONFIG_CSIE_CLK },
	334	{ .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIA_CLK },
	335	{ .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIB_CLK },
08a15cc3 SP	336	};
	337
	338	static const struct tegra_mipi_soc tegra124_mipi_soc = {
	339	.has_clk_lane = true,
	340	.pads = tegra124_mipi_pads,
	341	.num_pads = ARRAY_SIZE(tegra124_mipi_pads),
83a3c223 TR	342	.clock_enable_override = true,
	343	.needs_vclamp_ref = true,
	344	.pad_drive_down_ref = 0x2,
	345	.pad_drive_up_ref = 0x0,
	346	.pad_vclamp_level = 0x0,
	347	.pad_vauxp_level = 0x0,
	348	.hspdos = 0x0,
	349	.hspuos = 0x0,
	350	.termos = 0x0,
	351	.hsclkpdos = 0x1,
	352	.hsclkpuos = 0x2,
08a15cc3 SP	353	};
	354
	355	static struct of_device_id tegra_mipi_of_match[] = {
	356	{ .compatible = "nvidia,tegra114-mipi", .data = &tegra114_mipi_soc },
	357	{ .compatible = "nvidia,tegra124-mipi", .data = &tegra124_mipi_soc },
	358	{ },
	359	};
	360
4de6a2d6 TR	361	static int tegra_mipi_probe(struct platform_device *pdev)
4de6a2d6 TR	362	{
08a15cc3	363	const struct of_device_id *match;
4de6a2d6 TR	364	struct tegra_mipi *mipi;
	365	struct resource *res;
	366	int err;
	367
08a15cc3 SP	368	match = of_match_node(tegra_mipi_of_match, pdev->dev.of_node);
	369	if (!match)
	370	return -ENODEV;
	371
4de6a2d6 TR	372	mipi = devm_kzalloc(&pdev->dev, sizeof(*mipi), GFP_KERNEL);
	373	if (!mipi)
	374	return -ENOMEM;
	375
08a15cc3 SP	376	mipi->soc = match->data;
08a15cc3 SP	377
4de6a2d6 TR	378	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	379	mipi->regs = devm_ioremap_resource(&pdev->dev, res);
	380	if (IS_ERR(mipi->regs))
	381	return PTR_ERR(mipi->regs);
	382
	383	mutex_init(&mipi->lock);
	384
	385	mipi->clk = devm_clk_get(&pdev->dev, NULL);
	386	if (IS_ERR(mipi->clk)) {
	387	dev_err(&pdev->dev, "failed to get clock\n");
	388	return PTR_ERR(mipi->clk);
	389	}
	390
	391	err = clk_prepare(mipi->clk);
	392	if (err < 0)
	393	return err;
	394
	395	platform_set_drvdata(pdev, mipi);
	396
	397	return 0;
	398	}
	399
	400	static int tegra_mipi_remove(struct platform_device *pdev)
	401	{
	402	struct tegra_mipi *mipi = platform_get_drvdata(pdev);
	403
	404	clk_unprepare(mipi->clk);
	405
	406	return 0;
	407	}
	408
4de6a2d6 TR	409	struct platform_driver tegra_mipi_driver = {
	410	.driver = {
	411	.name = "tegra-mipi",
	412	.of_match_table = tegra_mipi_of_match,
	413	},
	414	.probe = tegra_mipi_probe,
	415	.remove = tegra_mipi_remove,
	416	};