Commit | Line | Data |
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4de6a2d6 TR |
1 | /* |
2 | * Copyright (C) 2013 NVIDIA Corporation | |
3 | * | |
4 | * Permission to use, copy, modify, distribute, and sell this software and its | |
5 | * documentation for any purpose is hereby granted without fee, provided that | |
6 | * the above copyright notice appear in all copies and that both that copyright | |
7 | * notice and this permission notice appear in supporting documentation, and | |
8 | * that the name of the copyright holders not be used in advertising or | |
9 | * publicity pertaining to distribution of the software without specific, | |
10 | * written prior permission. The copyright holders make no representations | |
11 | * about the suitability of this software for any purpose. It is provided "as | |
12 | * is" without express or implied warranty. | |
13 | * | |
14 | * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, | |
15 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO | |
16 | * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR | |
17 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, | |
18 | * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER | |
19 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE | |
20 | * OF THIS SOFTWARE. | |
21 | */ | |
22 | ||
23 | #include <linux/clk.h> | |
24 | #include <linux/delay.h> | |
aef03d3f | 25 | #include <linux/host1x.h> |
4de6a2d6 TR |
26 | #include <linux/io.h> |
27 | #include <linux/of_platform.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/slab.h> | |
30 | ||
aef03d3f TR |
31 | #include "dev.h" |
32 | ||
4de6a2d6 | 33 | #define MIPI_CAL_CTRL 0x00 |
83a3c223 TR |
34 | #define MIPI_CAL_CTRL_NOISE_FILTER(x) (((x) & 0xf) << 26) |
35 | #define MIPI_CAL_CTRL_PRESCALE(x) (((x) & 0x3) << 24) | |
36 | #define MIPI_CAL_CTRL_CLKEN_OVR (1 << 4) | |
4de6a2d6 TR |
37 | #define MIPI_CAL_CTRL_START (1 << 0) |
38 | ||
39 | #define MIPI_CAL_AUTOCAL_CTRL 0x01 | |
40 | ||
41 | #define MIPI_CAL_STATUS 0x02 | |
42 | #define MIPI_CAL_STATUS_DONE (1 << 16) | |
43 | #define MIPI_CAL_STATUS_ACTIVE (1 << 0) | |
44 | ||
45 | #define MIPI_CAL_CONFIG_CSIA 0x05 | |
46 | #define MIPI_CAL_CONFIG_CSIB 0x06 | |
47 | #define MIPI_CAL_CONFIG_CSIC 0x07 | |
48 | #define MIPI_CAL_CONFIG_CSID 0x08 | |
49 | #define MIPI_CAL_CONFIG_CSIE 0x09 | |
50 | #define MIPI_CAL_CONFIG_DSIA 0x0e | |
51 | #define MIPI_CAL_CONFIG_DSIB 0x0f | |
52 | #define MIPI_CAL_CONFIG_DSIC 0x10 | |
53 | #define MIPI_CAL_CONFIG_DSID 0x11 | |
54 | ||
8ed5c062 TR |
55 | #define MIPI_CAL_CONFIG_DSIA_CLK 0x19 |
56 | #define MIPI_CAL_CONFIG_DSIB_CLK 0x1a | |
08a15cc3 SP |
57 | #define MIPI_CAL_CONFIG_CSIAB_CLK 0x1b |
58 | #define MIPI_CAL_CONFIG_CSICD_CLK 0x1c | |
59 | #define MIPI_CAL_CONFIG_CSIE_CLK 0x1d | |
60 | ||
61 | /* for data and clock lanes */ | |
4de6a2d6 | 62 | #define MIPI_CAL_CONFIG_SELECT (1 << 21) |
08a15cc3 SP |
63 | |
64 | /* for data lanes */ | |
4de6a2d6 TR |
65 | #define MIPI_CAL_CONFIG_HSPDOS(x) (((x) & 0x1f) << 16) |
66 | #define MIPI_CAL_CONFIG_HSPUOS(x) (((x) & 0x1f) << 8) | |
67 | #define MIPI_CAL_CONFIG_TERMOS(x) (((x) & 0x1f) << 0) | |
68 | ||
08a15cc3 SP |
69 | /* for clock lanes */ |
70 | #define MIPI_CAL_CONFIG_HSCLKPDOSD(x) (((x) & 0x1f) << 8) | |
71 | #define MIPI_CAL_CONFIG_HSCLKPUOSD(x) (((x) & 0x1f) << 0) | |
72 | ||
4de6a2d6 TR |
73 | #define MIPI_CAL_BIAS_PAD_CFG0 0x16 |
74 | #define MIPI_CAL_BIAS_PAD_PDVCLAMP (1 << 1) | |
75 | #define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF (1 << 0) | |
76 | ||
77 | #define MIPI_CAL_BIAS_PAD_CFG1 0x17 | |
b298e98e | 78 | #define MIPI_CAL_BIAS_PAD_DRV_DN_REF(x) (((x) & 0x7) << 16) |
83a3c223 | 79 | #define MIPI_CAL_BIAS_PAD_DRV_UP_REF(x) (((x) & 0x7) << 8) |
4de6a2d6 TR |
80 | |
81 | #define MIPI_CAL_BIAS_PAD_CFG2 0x18 | |
83a3c223 TR |
82 | #define MIPI_CAL_BIAS_PAD_VCLAMP(x) (((x) & 0x7) << 16) |
83 | #define MIPI_CAL_BIAS_PAD_VAUXP(x) (((x) & 0x7) << 4) | |
4de6a2d6 TR |
84 | #define MIPI_CAL_BIAS_PAD_PDVREG (1 << 1) |
85 | ||
08a15cc3 SP |
86 | struct tegra_mipi_pad { |
87 | unsigned long data; | |
88 | unsigned long clk; | |
89 | }; | |
90 | ||
91 | struct tegra_mipi_soc { | |
92 | bool has_clk_lane; | |
93 | const struct tegra_mipi_pad *pads; | |
94 | unsigned int num_pads; | |
83a3c223 TR |
95 | |
96 | bool clock_enable_override; | |
97 | bool needs_vclamp_ref; | |
98 | ||
99 | /* bias pad configuration settings */ | |
100 | u8 pad_drive_down_ref; | |
101 | u8 pad_drive_up_ref; | |
102 | ||
103 | u8 pad_vclamp_level; | |
104 | u8 pad_vauxp_level; | |
105 | ||
106 | /* calibration settings for data lanes */ | |
107 | u8 hspdos; | |
108 | u8 hspuos; | |
109 | u8 termos; | |
110 | ||
111 | /* calibration settings for clock lanes */ | |
112 | u8 hsclkpdos; | |
113 | u8 hsclkpuos; | |
4de6a2d6 TR |
114 | }; |
115 | ||
116 | struct tegra_mipi { | |
08a15cc3 | 117 | const struct tegra_mipi_soc *soc; |
4de6a2d6 TR |
118 | void __iomem *regs; |
119 | struct mutex lock; | |
120 | struct clk *clk; | |
121 | }; | |
122 | ||
123 | struct tegra_mipi_device { | |
124 | struct platform_device *pdev; | |
125 | struct tegra_mipi *mipi; | |
126 | struct device *device; | |
127 | unsigned long pads; | |
128 | }; | |
129 | ||
57b17ae7 TR |
130 | static inline u32 tegra_mipi_readl(struct tegra_mipi *mipi, |
131 | unsigned long offset) | |
4de6a2d6 | 132 | { |
57b17ae7 | 133 | return readl(mipi->regs + (offset << 2)); |
4de6a2d6 TR |
134 | } |
135 | ||
57b17ae7 TR |
136 | static inline void tegra_mipi_writel(struct tegra_mipi *mipi, u32 value, |
137 | unsigned long offset) | |
4de6a2d6 | 138 | { |
57b17ae7 | 139 | writel(value, mipi->regs + (offset << 2)); |
4de6a2d6 TR |
140 | } |
141 | ||
142 | struct tegra_mipi_device *tegra_mipi_request(struct device *device) | |
143 | { | |
144 | struct device_node *np = device->of_node; | |
145 | struct tegra_mipi_device *dev; | |
146 | struct of_phandle_args args; | |
147 | int err; | |
148 | ||
149 | err = of_parse_phandle_with_args(np, "nvidia,mipi-calibrate", | |
150 | "#nvidia,mipi-calibrate-cells", 0, | |
151 | &args); | |
152 | if (err < 0) | |
153 | return ERR_PTR(err); | |
154 | ||
155 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
156 | if (!dev) { | |
4de6a2d6 TR |
157 | err = -ENOMEM; |
158 | goto out; | |
159 | } | |
160 | ||
161 | dev->pdev = of_find_device_by_node(args.np); | |
162 | if (!dev->pdev) { | |
4de6a2d6 TR |
163 | err = -ENODEV; |
164 | goto free; | |
165 | } | |
166 | ||
4de6a2d6 TR |
167 | dev->mipi = platform_get_drvdata(dev->pdev); |
168 | if (!dev->mipi) { | |
169 | err = -EPROBE_DEFER; | |
08a15cc3 | 170 | goto put; |
4de6a2d6 TR |
171 | } |
172 | ||
08a15cc3 SP |
173 | of_node_put(args.np); |
174 | ||
4de6a2d6 TR |
175 | dev->pads = args.args[0]; |
176 | dev->device = device; | |
177 | ||
178 | return dev; | |
179 | ||
08a15cc3 | 180 | put: |
4de6a2d6 TR |
181 | platform_device_put(dev->pdev); |
182 | free: | |
183 | kfree(dev); | |
184 | out: | |
08a15cc3 | 185 | of_node_put(args.np); |
4de6a2d6 TR |
186 | return ERR_PTR(err); |
187 | } | |
188 | EXPORT_SYMBOL(tegra_mipi_request); | |
189 | ||
190 | void tegra_mipi_free(struct tegra_mipi_device *device) | |
191 | { | |
192 | platform_device_put(device->pdev); | |
193 | kfree(device); | |
194 | } | |
195 | EXPORT_SYMBOL(tegra_mipi_free); | |
196 | ||
197 | static int tegra_mipi_wait(struct tegra_mipi *mipi) | |
198 | { | |
199 | unsigned long timeout = jiffies + msecs_to_jiffies(250); | |
57b17ae7 | 200 | u32 value; |
4de6a2d6 TR |
201 | |
202 | while (time_before(jiffies, timeout)) { | |
203 | value = tegra_mipi_readl(mipi, MIPI_CAL_STATUS); | |
204 | if ((value & MIPI_CAL_STATUS_ACTIVE) == 0 && | |
205 | (value & MIPI_CAL_STATUS_DONE) != 0) | |
206 | return 0; | |
207 | ||
208 | usleep_range(10, 50); | |
209 | } | |
210 | ||
211 | return -ETIMEDOUT; | |
212 | } | |
213 | ||
214 | int tegra_mipi_calibrate(struct tegra_mipi_device *device) | |
215 | { | |
08a15cc3 | 216 | const struct tegra_mipi_soc *soc = device->mipi->soc; |
4de6a2d6 | 217 | unsigned int i; |
57b17ae7 | 218 | u32 value; |
4de6a2d6 TR |
219 | int err; |
220 | ||
221 | err = clk_enable(device->mipi->clk); | |
222 | if (err < 0) | |
223 | return err; | |
224 | ||
225 | mutex_lock(&device->mipi->lock); | |
226 | ||
227 | value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG0); | |
228 | value &= ~MIPI_CAL_BIAS_PAD_PDVCLAMP; | |
83a3c223 TR |
229 | |
230 | if (soc->needs_vclamp_ref) | |
231 | value |= MIPI_CAL_BIAS_PAD_E_VCLAMP_REF; | |
232 | ||
4de6a2d6 TR |
233 | tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG0); |
234 | ||
83a3c223 TR |
235 | value = MIPI_CAL_BIAS_PAD_DRV_DN_REF(soc->pad_drive_down_ref) | |
236 | MIPI_CAL_BIAS_PAD_DRV_UP_REF(soc->pad_drive_up_ref); | |
237 | tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG1); | |
b298e98e | 238 | |
4de6a2d6 TR |
239 | value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2); |
240 | value &= ~MIPI_CAL_BIAS_PAD_PDVREG; | |
241 | tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2); | |
242 | ||
83a3c223 TR |
243 | value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2); |
244 | value &= ~MIPI_CAL_BIAS_PAD_VCLAMP(0x7); | |
245 | value &= ~MIPI_CAL_BIAS_PAD_VAUXP(0x7); | |
246 | value |= MIPI_CAL_BIAS_PAD_VCLAMP(soc->pad_vclamp_level); | |
247 | value |= MIPI_CAL_BIAS_PAD_VAUXP(soc->pad_vauxp_level); | |
248 | tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2); | |
249 | ||
08a15cc3 SP |
250 | for (i = 0; i < soc->num_pads; i++) { |
251 | u32 clk = 0, data = 0; | |
252 | ||
253 | if (device->pads & BIT(i)) { | |
254 | data = MIPI_CAL_CONFIG_SELECT | | |
83a3c223 TR |
255 | MIPI_CAL_CONFIG_HSPDOS(soc->hspdos) | |
256 | MIPI_CAL_CONFIG_HSPUOS(soc->hspuos) | | |
257 | MIPI_CAL_CONFIG_TERMOS(soc->termos); | |
08a15cc3 | 258 | clk = MIPI_CAL_CONFIG_SELECT | |
83a3c223 TR |
259 | MIPI_CAL_CONFIG_HSCLKPDOSD(soc->hsclkpdos) | |
260 | MIPI_CAL_CONFIG_HSCLKPUOSD(soc->hsclkpuos); | |
08a15cc3 SP |
261 | } |
262 | ||
263 | tegra_mipi_writel(device->mipi, data, soc->pads[i].data); | |
4de6a2d6 | 264 | |
08a15cc3 SP |
265 | if (soc->has_clk_lane) |
266 | tegra_mipi_writel(device->mipi, clk, soc->pads[i].clk); | |
4de6a2d6 TR |
267 | } |
268 | ||
83a3c223 TR |
269 | value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL); |
270 | value &= ~MIPI_CAL_CTRL_NOISE_FILTER(0xf); | |
271 | value &= ~MIPI_CAL_CTRL_PRESCALE(0x3); | |
272 | value |= MIPI_CAL_CTRL_NOISE_FILTER(0xa); | |
273 | value |= MIPI_CAL_CTRL_PRESCALE(0x2); | |
274 | ||
275 | if (!soc->clock_enable_override) | |
276 | value &= ~MIPI_CAL_CTRL_CLKEN_OVR; | |
277 | else | |
278 | value |= MIPI_CAL_CTRL_CLKEN_OVR; | |
279 | ||
280 | tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); | |
281 | ||
26f7a92a SP |
282 | value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL); |
283 | value |= MIPI_CAL_CTRL_START; | |
284 | tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); | |
4de6a2d6 TR |
285 | |
286 | err = tegra_mipi_wait(device->mipi); | |
287 | ||
288 | mutex_unlock(&device->mipi->lock); | |
289 | clk_disable(device->mipi->clk); | |
290 | ||
291 | return err; | |
292 | } | |
293 | EXPORT_SYMBOL(tegra_mipi_calibrate); | |
294 | ||
08a15cc3 SP |
295 | static const struct tegra_mipi_pad tegra114_mipi_pads[] = { |
296 | { .data = MIPI_CAL_CONFIG_CSIA }, | |
297 | { .data = MIPI_CAL_CONFIG_CSIB }, | |
298 | { .data = MIPI_CAL_CONFIG_CSIC }, | |
299 | { .data = MIPI_CAL_CONFIG_CSID }, | |
300 | { .data = MIPI_CAL_CONFIG_CSIE }, | |
301 | { .data = MIPI_CAL_CONFIG_DSIA }, | |
302 | { .data = MIPI_CAL_CONFIG_DSIB }, | |
303 | { .data = MIPI_CAL_CONFIG_DSIC }, | |
304 | { .data = MIPI_CAL_CONFIG_DSID }, | |
305 | }; | |
306 | ||
307 | static const struct tegra_mipi_soc tegra114_mipi_soc = { | |
308 | .has_clk_lane = false, | |
309 | .pads = tegra114_mipi_pads, | |
310 | .num_pads = ARRAY_SIZE(tegra114_mipi_pads), | |
83a3c223 TR |
311 | .clock_enable_override = true, |
312 | .needs_vclamp_ref = true, | |
313 | .pad_drive_down_ref = 0x2, | |
314 | .pad_drive_up_ref = 0x0, | |
315 | .pad_vclamp_level = 0x0, | |
316 | .pad_vauxp_level = 0x0, | |
317 | .hspdos = 0x0, | |
318 | .hspuos = 0x4, | |
319 | .termos = 0x5, | |
320 | .hsclkpdos = 0x0, | |
321 | .hsclkpuos = 0x4, | |
08a15cc3 SP |
322 | }; |
323 | ||
324 | static const struct tegra_mipi_pad tegra124_mipi_pads[] = { | |
325 | { .data = MIPI_CAL_CONFIG_CSIA, .clk = MIPI_CAL_CONFIG_CSIAB_CLK }, | |
326 | { .data = MIPI_CAL_CONFIG_CSIB, .clk = MIPI_CAL_CONFIG_CSIAB_CLK }, | |
327 | { .data = MIPI_CAL_CONFIG_CSIC, .clk = MIPI_CAL_CONFIG_CSICD_CLK }, | |
328 | { .data = MIPI_CAL_CONFIG_CSID, .clk = MIPI_CAL_CONFIG_CSICD_CLK }, | |
8ed5c062 TR |
329 | { .data = MIPI_CAL_CONFIG_CSIE, .clk = MIPI_CAL_CONFIG_CSIE_CLK }, |
330 | { .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIA_CLK }, | |
331 | { .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIB_CLK }, | |
08a15cc3 SP |
332 | }; |
333 | ||
334 | static const struct tegra_mipi_soc tegra124_mipi_soc = { | |
335 | .has_clk_lane = true, | |
336 | .pads = tegra124_mipi_pads, | |
337 | .num_pads = ARRAY_SIZE(tegra124_mipi_pads), | |
83a3c223 TR |
338 | .clock_enable_override = true, |
339 | .needs_vclamp_ref = true, | |
340 | .pad_drive_down_ref = 0x2, | |
341 | .pad_drive_up_ref = 0x0, | |
342 | .pad_vclamp_level = 0x0, | |
343 | .pad_vauxp_level = 0x0, | |
344 | .hspdos = 0x0, | |
345 | .hspuos = 0x0, | |
346 | .termos = 0x0, | |
347 | .hsclkpdos = 0x1, | |
348 | .hsclkpuos = 0x2, | |
08a15cc3 SP |
349 | }; |
350 | ||
351 | static struct of_device_id tegra_mipi_of_match[] = { | |
352 | { .compatible = "nvidia,tegra114-mipi", .data = &tegra114_mipi_soc }, | |
353 | { .compatible = "nvidia,tegra124-mipi", .data = &tegra124_mipi_soc }, | |
354 | { }, | |
355 | }; | |
356 | ||
4de6a2d6 TR |
357 | static int tegra_mipi_probe(struct platform_device *pdev) |
358 | { | |
08a15cc3 | 359 | const struct of_device_id *match; |
4de6a2d6 TR |
360 | struct tegra_mipi *mipi; |
361 | struct resource *res; | |
362 | int err; | |
363 | ||
08a15cc3 SP |
364 | match = of_match_node(tegra_mipi_of_match, pdev->dev.of_node); |
365 | if (!match) | |
366 | return -ENODEV; | |
367 | ||
4de6a2d6 TR |
368 | mipi = devm_kzalloc(&pdev->dev, sizeof(*mipi), GFP_KERNEL); |
369 | if (!mipi) | |
370 | return -ENOMEM; | |
371 | ||
08a15cc3 SP |
372 | mipi->soc = match->data; |
373 | ||
4de6a2d6 TR |
374 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
375 | mipi->regs = devm_ioremap_resource(&pdev->dev, res); | |
376 | if (IS_ERR(mipi->regs)) | |
377 | return PTR_ERR(mipi->regs); | |
378 | ||
379 | mutex_init(&mipi->lock); | |
380 | ||
381 | mipi->clk = devm_clk_get(&pdev->dev, NULL); | |
382 | if (IS_ERR(mipi->clk)) { | |
383 | dev_err(&pdev->dev, "failed to get clock\n"); | |
384 | return PTR_ERR(mipi->clk); | |
385 | } | |
386 | ||
387 | err = clk_prepare(mipi->clk); | |
388 | if (err < 0) | |
389 | return err; | |
390 | ||
391 | platform_set_drvdata(pdev, mipi); | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
396 | static int tegra_mipi_remove(struct platform_device *pdev) | |
397 | { | |
398 | struct tegra_mipi *mipi = platform_get_drvdata(pdev); | |
399 | ||
400 | clk_unprepare(mipi->clk); | |
401 | ||
402 | return 0; | |
403 | } | |
404 | ||
4de6a2d6 TR |
405 | struct platform_driver tegra_mipi_driver = { |
406 | .driver = { | |
407 | .name = "tegra-mipi", | |
408 | .of_match_table = tegra_mipi_of_match, | |
409 | }, | |
410 | .probe = tegra_mipi_probe, | |
411 | .remove = tegra_mipi_remove, | |
412 | }; |