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gpu: ipu-v3: add support for RGBX8888 and RGBA8888 pixel formats
[deliverable/linux.git] / drivers / gpu / ipu-v3 / ipu-cpmem.c
CommitLineData
7d2691da
SL		 1/*
2 * Copyright (C) 2012 Mentor Graphics Inc.
3 * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12#include <linux/types.h>
13#include <linux/bitrev.h>
14#include <linux/io.h>
15#include <drm/drm_fourcc.h>
16#include "ipu-prv.h"
17
18struct ipu_cpmem_word {
19 u32 data[5];
20 u32 res[3];
21};
22
23struct ipu_ch_param {
24 struct ipu_cpmem_word word[2];
25};
26
27struct ipu_cpmem {
28 struct ipu_ch_param __iomem *base;
29 u32 module;
30 spinlock_t lock;
31 int use_count;
32 struct ipu_soc *ipu;
33};
34
35#define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size))
36
37#define IPU_FIELD_UBO IPU_CPMEM_WORD(0, 46, 22)
38#define IPU_FIELD_VBO IPU_CPMEM_WORD(0, 68, 22)
39#define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4)
40#define IPU_FIELD_RDRW IPU_CPMEM_WORD(0, 94, 1)
41#define IPU_FIELD_SO IPU_CPMEM_WORD(0, 113, 1)
42#define IPU_FIELD_SLY IPU_CPMEM_WORD(1, 102, 14)
43#define IPU_FIELD_SLUV IPU_CPMEM_WORD(1, 128, 14)
44
45#define IPU_FIELD_XV IPU_CPMEM_WORD(0, 0, 10)
46#define IPU_FIELD_YV IPU_CPMEM_WORD(0, 10, 9)
47#define IPU_FIELD_XB IPU_CPMEM_WORD(0, 19, 13)
48#define IPU_FIELD_YB IPU_CPMEM_WORD(0, 32, 12)
49#define IPU_FIELD_NSB_B IPU_CPMEM_WORD(0, 44, 1)
50#define IPU_FIELD_CF IPU_CPMEM_WORD(0, 45, 1)
51#define IPU_FIELD_SX IPU_CPMEM_WORD(0, 46, 12)
52#define IPU_FIELD_SY IPU_CPMEM_WORD(0, 58, 11)
53#define IPU_FIELD_NS IPU_CPMEM_WORD(0, 69, 10)
54#define IPU_FIELD_SDX IPU_CPMEM_WORD(0, 79, 7)
55#define IPU_FIELD_SM IPU_CPMEM_WORD(0, 86, 10)
56#define IPU_FIELD_SCC IPU_CPMEM_WORD(0, 96, 1)
57#define IPU_FIELD_SCE IPU_CPMEM_WORD(0, 97, 1)
58#define IPU_FIELD_SDY IPU_CPMEM_WORD(0, 98, 7)
59#define IPU_FIELD_SDRX IPU_CPMEM_WORD(0, 105, 1)
60#define IPU_FIELD_SDRY IPU_CPMEM_WORD(0, 106, 1)
61#define IPU_FIELD_BPP IPU_CPMEM_WORD(0, 107, 3)
62#define IPU_FIELD_DEC_SEL IPU_CPMEM_WORD(0, 110, 2)
63#define IPU_FIELD_DIM IPU_CPMEM_WORD(0, 112, 1)
64#define IPU_FIELD_BNDM IPU_CPMEM_WORD(0, 114, 3)
65#define IPU_FIELD_BM IPU_CPMEM_WORD(0, 117, 2)
66#define IPU_FIELD_ROT IPU_CPMEM_WORD(0, 119, 1)
c42d37ca 67#define IPU_FIELD_ROT_HF_VF IPU_CPMEM_WORD(0, 119, 3)
7d2691da
SL		 68#define IPU_FIELD_HF IPU_CPMEM_WORD(0, 120, 1)
69#define IPU_FIELD_VF IPU_CPMEM_WORD(0, 121, 1)
70#define IPU_FIELD_THE IPU_CPMEM_WORD(0, 122, 1)
71#define IPU_FIELD_CAP IPU_CPMEM_WORD(0, 123, 1)
72#define IPU_FIELD_CAE IPU_CPMEM_WORD(0, 124, 1)
73#define IPU_FIELD_FW IPU_CPMEM_WORD(0, 125, 13)
74#define IPU_FIELD_FH IPU_CPMEM_WORD(0, 138, 12)
75#define IPU_FIELD_EBA0 IPU_CPMEM_WORD(1, 0, 29)
76#define IPU_FIELD_EBA1 IPU_CPMEM_WORD(1, 29, 29)
77#define IPU_FIELD_ILO IPU_CPMEM_WORD(1, 58, 20)
78#define IPU_FIELD_NPB IPU_CPMEM_WORD(1, 78, 7)
79#define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4)
80#define IPU_FIELD_ALU IPU_CPMEM_WORD(1, 89, 1)
81#define IPU_FIELD_ALBM IPU_CPMEM_WORD(1, 90, 3)
82#define IPU_FIELD_ID IPU_CPMEM_WORD(1, 93, 2)
83#define IPU_FIELD_TH IPU_CPMEM_WORD(1, 95, 7)
84#define IPU_FIELD_SL IPU_CPMEM_WORD(1, 102, 14)
85#define IPU_FIELD_WID0 IPU_CPMEM_WORD(1, 116, 3)
86#define IPU_FIELD_WID1 IPU_CPMEM_WORD(1, 119, 3)
87#define IPU_FIELD_WID2 IPU_CPMEM_WORD(1, 122, 3)
88#define IPU_FIELD_WID3 IPU_CPMEM_WORD(1, 125, 3)
89#define IPU_FIELD_OFS0 IPU_CPMEM_WORD(1, 128, 5)
90#define IPU_FIELD_OFS1 IPU_CPMEM_WORD(1, 133, 5)
91#define IPU_FIELD_OFS2 IPU_CPMEM_WORD(1, 138, 5)
92#define IPU_FIELD_OFS3 IPU_CPMEM_WORD(1, 143, 5)
93#define IPU_FIELD_SXYS IPU_CPMEM_WORD(1, 148, 1)
94#define IPU_FIELD_CRE IPU_CPMEM_WORD(1, 149, 1)
95#define IPU_FIELD_DEC_SEL2 IPU_CPMEM_WORD(1, 150, 1)
96
97static inline struct ipu_ch_param __iomem *
98ipu_get_cpmem(struct ipuv3_channel *ch)
99{
100 struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv;
101
102 return cpmem->base + ch->num;
103}
104
105static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v)
106{
107 struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch);
108 u32 bit = (wbs >> 8) % 160;
109 u32 size = wbs & 0xff;
110 u32 word = (wbs >> 8) / 160;
111 u32 i = bit / 32;
112 u32 ofs = bit % 32;
113 u32 mask = (1 << size) - 1;
114 u32 val;
115
116 pr_debug("%s %d %d %d\n", __func__, word, bit , size);
117
118 val = readl(&base->word[word].data[i]);
119 val &= ~(mask << ofs);
120 val |= v << ofs;
121 writel(val, &base->word[word].data[i]);
122
123 if ((bit + size - 1) / 32 > i) {
124 val = readl(&base->word[word].data[i + 1]);
125 val &= ~(mask >> (ofs ? (32 - ofs) : 0));
126 val |= v >> (ofs ? (32 - ofs) : 0);
127 writel(val, &base->word[word].data[i + 1]);
128 }
129}
130
131static u32 ipu_ch_param_read_field(struct ipuv3_channel *ch, u32 wbs)
132{
133 struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch);
134 u32 bit = (wbs >> 8) % 160;
135 u32 size = wbs & 0xff;
136 u32 word = (wbs >> 8) / 160;
137 u32 i = bit / 32;
138 u32 ofs = bit % 32;
139 u32 mask = (1 << size) - 1;
140 u32 val = 0;
141
142 pr_debug("%s %d %d %d\n", __func__, word, bit , size);
143
144 val = (readl(&base->word[word].data[i]) >> ofs) & mask;
145
146 if ((bit + size - 1) / 32 > i) {
147 u32 tmp;
148
149 tmp = readl(&base->word[word].data[i + 1]);
150 tmp &= mask >> (ofs ? (32 - ofs) : 0);
151 val |= tmp << (ofs ? (32 - ofs) : 0);
152 }
153
154 return val;
155}
156
157/*
158 * The V4L2 spec defines packed RGB formats in memory byte order, which from
159 * point of view of the IPU corresponds to little-endian words with the first
160 * component in the least significant bits.
161 * The DRM pixel formats and IPU internal representation are ordered the other
162 * way around, with the first named component ordered at the most significant
163 * bits. Further, V4L2 formats are not well defined:
164 * http://linuxtv.org/downloads/v4l-dvb-apis/packed-rgb.html
165 * We choose the interpretation which matches GStreamer behavior.
166 */
167static int v4l2_pix_fmt_to_drm_fourcc(u32 pixelformat)
168{
169 switch (pixelformat) {
170 case V4L2_PIX_FMT_RGB565:
171 /*
172 * Here we choose the 'corrected' interpretation of RGBP, a
173 * little-endian 16-bit word with the red component at the most
174 * significant bits:
175 * g[2:0]b[4:0] r[4:0]g[5:3] <=> [16:0] R:G:B
176 */
177 return DRM_FORMAT_RGB565;
178 case V4L2_PIX_FMT_BGR24:
179 /* B G R <=> [24:0] R:G:B */
180 return DRM_FORMAT_RGB888;
181 case V4L2_PIX_FMT_RGB24:
182 /* R G B <=> [24:0] B:G:R */
183 return DRM_FORMAT_BGR888;
184 case V4L2_PIX_FMT_BGR32:
185 /* B G R A <=> [32:0] A:B:G:R */
186 return DRM_FORMAT_XRGB8888;
187 case V4L2_PIX_FMT_RGB32:
188 /* R G B A <=> [32:0] A:B:G:R */
189 return DRM_FORMAT_XBGR8888;
190 case V4L2_PIX_FMT_UYVY:
191 return DRM_FORMAT_UYVY;
192 case V4L2_PIX_FMT_YUYV:
193 return DRM_FORMAT_YUYV;
194 case V4L2_PIX_FMT_YUV420:
195 return DRM_FORMAT_YUV420;
9a34cef0
SL		 196 case V4L2_PIX_FMT_YUV422P:
197 return DRM_FORMAT_YUV422;
7d2691da
SL		 198 case V4L2_PIX_FMT_YVU420:
199 return DRM_FORMAT_YVU420;
9a34cef0
SL		 200 case V4L2_PIX_FMT_NV12:
201 return DRM_FORMAT_NV12;
202 case V4L2_PIX_FMT_NV16:
203 return DRM_FORMAT_NV16;
7d2691da
SL		 204 }
205
206 return -EINVAL;
207}
208
209void ipu_cpmem_zero(struct ipuv3_channel *ch)
210{
211 struct ipu_ch_param __iomem *p = ipu_get_cpmem(ch);
212 void __iomem *base = p;
213 int i;
214
215 for (i = 0; i < sizeof(*p) / sizeof(u32); i++)
216 writel(0, base + i * sizeof(u32));
217}
218EXPORT_SYMBOL_GPL(ipu_cpmem_zero);
219
220void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres)
221{
222 ipu_ch_param_write_field(ch, IPU_FIELD_FW, xres - 1);
223 ipu_ch_param_write_field(ch, IPU_FIELD_FH, yres - 1);
224}
225EXPORT_SYMBOL_GPL(ipu_cpmem_set_resolution);
226
227void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride)
228{
229 ipu_ch_param_write_field(ch, IPU_FIELD_SLY, stride - 1);
230}
231EXPORT_SYMBOL_GPL(ipu_cpmem_set_stride);
232
233void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch)
234{
235 struct ipu_soc *ipu = ch->ipu;
236 u32 val;
237
238 if (ipu->ipu_type == IPUV3EX)
239 ipu_ch_param_write_field(ch, IPU_FIELD_ID, 1);
240
241 val = ipu_idmac_read(ipu, IDMAC_CHA_PRI(ch->num));
242 val |= 1 << (ch->num % 32);
243 ipu_idmac_write(ipu, val, IDMAC_CHA_PRI(ch->num));
244};
245EXPORT_SYMBOL_GPL(ipu_cpmem_set_high_priority);
246
247void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf)
248{
249 if (bufnum)
250 ipu_ch_param_write_field(ch, IPU_FIELD_EBA1, buf >> 3);
251 else
252 ipu_ch_param_write_field(ch, IPU_FIELD_EBA0, buf >> 3);
253}
254EXPORT_SYMBOL_GPL(ipu_cpmem_set_buffer);
255
256void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride)
257{
258 ipu_ch_param_write_field(ch, IPU_FIELD_SO, 1);
259 ipu_ch_param_write_field(ch, IPU_FIELD_ILO, stride / 8);
260 ipu_ch_param_write_field(ch, IPU_FIELD_SLY, (stride * 2) - 1);
261};
262EXPORT_SYMBOL_GPL(ipu_cpmem_interlaced_scan);
263
555f0e66
SL		 264void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id)
265{
266 id &= 0x3;
267 ipu_ch_param_write_field(ch, IPU_FIELD_ID, id);
268}
269EXPORT_SYMBOL_GPL(ipu_cpmem_set_axi_id);
270
7d2691da
SL		 271void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize)
272{
273 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, burstsize - 1);
274};
275EXPORT_SYMBOL_GPL(ipu_cpmem_set_burstsize);
276
9b9da0be
SL		 277void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch)
278{
279 ipu_ch_param_write_field(ch, IPU_FIELD_BM, 1);
280}
281EXPORT_SYMBOL_GPL(ipu_cpmem_set_block_mode);
282
c42d37ca
SL		 283void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
284 enum ipu_rotate_mode rot)
285{
286 u32 temp_rot = bitrev8(rot) >> 5;
287
288 ipu_ch_param_write_field(ch, IPU_FIELD_ROT_HF_VF, temp_rot);
289}
290EXPORT_SYMBOL_GPL(ipu_cpmem_set_rotation);
291
7d2691da
SL		 292int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
293 const struct ipu_rgb *rgb)
294{
295 int bpp = 0, npb = 0, ro, go, bo, to;
296
297 ro = rgb->bits_per_pixel - rgb->red.length - rgb->red.offset;
298 go = rgb->bits_per_pixel - rgb->green.length - rgb->green.offset;
299 bo = rgb->bits_per_pixel - rgb->blue.length - rgb->blue.offset;
300 to = rgb->bits_per_pixel - rgb->transp.length - rgb->transp.offset;
301
302 ipu_ch_param_write_field(ch, IPU_FIELD_WID0, rgb->red.length - 1);
303 ipu_ch_param_write_field(ch, IPU_FIELD_OFS0, ro);
304 ipu_ch_param_write_field(ch, IPU_FIELD_WID1, rgb->green.length - 1);
305 ipu_ch_param_write_field(ch, IPU_FIELD_OFS1, go);
306 ipu_ch_param_write_field(ch, IPU_FIELD_WID2, rgb->blue.length - 1);
307 ipu_ch_param_write_field(ch, IPU_FIELD_OFS2, bo);
308
309 if (rgb->transp.length) {
310 ipu_ch_param_write_field(ch, IPU_FIELD_WID3,
311 rgb->transp.length - 1);
312 ipu_ch_param_write_field(ch, IPU_FIELD_OFS3, to);
313 } else {
314 ipu_ch_param_write_field(ch, IPU_FIELD_WID3, 7);
315 ipu_ch_param_write_field(ch, IPU_FIELD_OFS3,
316 rgb->bits_per_pixel);
317 }
318
319 switch (rgb->bits_per_pixel) {
320 case 32:
321 bpp = 0;
322 npb = 15;
323 break;
324 case 24:
325 bpp = 1;
326 npb = 19;
327 break;
328 case 16:
329 bpp = 3;
330 npb = 31;
331 break;
332 case 8:
333 bpp = 5;
334 npb = 63;
335 break;
336 default:
337 return -EINVAL;
338 }
339 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp);
340 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb);
341 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 7); /* rgb mode */
342
343 return 0;
344}
345EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_rgb);
346
347int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width)
348{
349 int bpp = 0, npb = 0;
350
351 switch (width) {
352 case 32:
353 bpp = 0;
354 npb = 15;
355 break;
356 case 24:
357 bpp = 1;
358 npb = 19;
359 break;
360 case 16:
361 bpp = 3;
362 npb = 31;
363 break;
364 case 8:
365 bpp = 5;
366 npb = 63;
367 break;
368 default:
369 return -EINVAL;
370 }
371
372 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp);
373 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb);
374 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 6); /* raw mode */
375
376 return 0;
377}
378EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_passthrough);
379
380void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format)
381{
382 switch (pixel_format) {
383 case V4L2_PIX_FMT_UYVY:
384 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */
385 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA);/* pix fmt */
386 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */
387 break;
388 case V4L2_PIX_FMT_YUYV:
389 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */
390 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8);/* pix fmt */
391 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */
392 break;
393 }
394}
395EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_interleaved);
396
397void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
398 u32 pixel_format, int stride,
399 int u_offset, int v_offset)
400{
401 switch (pixel_format) {
402 case V4L2_PIX_FMT_YUV420:
9a34cef0 403 case V4L2_PIX_FMT_YUV422P:
7d2691da
SL		 404 ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1);
405 ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8);
406 ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8);
407 break;
408 case V4L2_PIX_FMT_YVU420:
409 ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1);
410 ipu_ch_param_write_field(ch, IPU_FIELD_UBO, v_offset / 8);
411 ipu_ch_param_write_field(ch, IPU_FIELD_VBO, u_offset / 8);
412 break;
9a34cef0
SL		 413 case V4L2_PIX_FMT_NV12:
414 case V4L2_PIX_FMT_NV16:
415 ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, stride - 1);
416 ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8);
417 ipu_ch_param_write_field(ch, IPU_FIELD_VBO, u_offset / 8);
418 break;
7d2691da
SL		 419 }
420}
421EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full);
422
423void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
424 u32 pixel_format, int stride, int height)
425{
426 int u_offset, v_offset;
427 int uv_stride = 0;
428
429 switch (pixel_format) {
430 case V4L2_PIX_FMT_YUV420:
431 case V4L2_PIX_FMT_YVU420:
432 uv_stride = stride / 2;
433 u_offset = stride * height;
434 v_offset = u_offset + (uv_stride * height / 2);
435 ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride,
436 u_offset, v_offset);
437 break;
9a34cef0
SL		 438 case V4L2_PIX_FMT_YUV422P:
439 uv_stride = stride / 2;
440 u_offset = stride * height;
441 v_offset = u_offset + (uv_stride * height);
442 ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride,
443 u_offset, v_offset);
444 break;
445 case V4L2_PIX_FMT_NV12:
446 case V4L2_PIX_FMT_NV16:
447 u_offset = stride * height;
448 ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride,
449 u_offset, 0);
450 break;
7d2691da
SL		 451 }
452}
453EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar);
454
067f4aa4 455static const struct ipu_rgb def_xrgb_32 = {
7d2691da
SL		 456 .red = { .offset = 16, .length = 8, },
457 .green = { .offset = 8, .length = 8, },
458 .blue = { .offset = 0, .length = 8, },
459 .transp = { .offset = 24, .length = 8, },
460 .bits_per_pixel = 32,
461};
462
067f4aa4 463static const struct ipu_rgb def_xbgr_32 = {
7d2691da
SL		 464 .red = { .offset = 0, .length = 8, },
465 .green = { .offset = 8, .length = 8, },
466 .blue = { .offset = 16, .length = 8, },
467 .transp = { .offset = 24, .length = 8, },
468 .bits_per_pixel = 32,
469};
470
067f4aa4
PZ		 471static const struct ipu_rgb def_rgbx_32 = {
472 .red = { .offset = 24, .length = 8, },
473 .green = { .offset = 16, .length = 8, },
474 .blue = { .offset = 8, .length = 8, },
475 .transp = { .offset = 0, .length = 8, },
476 .bits_per_pixel = 32,
477};
478
479static const struct ipu_rgb def_bgrx_32 = {
480 .red = { .offset = 8, .length = 8, },
481 .green = { .offset = 16, .length = 8, },
482 .blue = { .offset = 24, .length = 8, },
483 .transp = { .offset = 0, .length = 8, },
484 .bits_per_pixel = 32,
485};
486
7d2691da
SL		 487static const struct ipu_rgb def_rgb_24 = {
488 .red = { .offset = 16, .length = 8, },
489 .green = { .offset = 8, .length = 8, },
490 .blue = { .offset = 0, .length = 8, },
491 .transp = { .offset = 0, .length = 0, },
492 .bits_per_pixel = 24,
493};
494
495static const struct ipu_rgb def_bgr_24 = {
496 .red = { .offset = 0, .length = 8, },
497 .green = { .offset = 8, .length = 8, },
498 .blue = { .offset = 16, .length = 8, },
499 .transp = { .offset = 0, .length = 0, },
500 .bits_per_pixel = 24,
501};
502
503static const struct ipu_rgb def_rgb_16 = {
504 .red = { .offset = 11, .length = 5, },
505 .green = { .offset = 5, .length = 6, },
506 .blue = { .offset = 0, .length = 5, },
507 .transp = { .offset = 0, .length = 0, },
508 .bits_per_pixel = 16,
509};
510
511static const struct ipu_rgb def_bgr_16 = {
512 .red = { .offset = 0, .length = 5, },
513 .green = { .offset = 5, .length = 6, },
514 .blue = { .offset = 11, .length = 5, },
515 .transp = { .offset = 0, .length = 0, },
516 .bits_per_pixel = 16,
517};
518
0cb8b757
PZ		 519static const struct ipu_rgb def_argb_16 = {
520 .red = { .offset = 10, .length = 5, },
521 .green = { .offset = 5, .length = 5, },
522 .blue = { .offset = 0, .length = 5, },
523 .transp = { .offset = 15, .length = 1, },
524 .bits_per_pixel = 16,
525};
526
527static const struct ipu_rgb def_abgr_16 = {
528 .red = { .offset = 0, .length = 5, },
529 .green = { .offset = 5, .length = 5, },
530 .blue = { .offset = 10, .length = 5, },
531 .transp = { .offset = 15, .length = 1, },
532 .bits_per_pixel = 16,
533};
534
535static const struct ipu_rgb def_rgba_16 = {
536 .red = { .offset = 11, .length = 5, },
537 .green = { .offset = 6, .length = 5, },
538 .blue = { .offset = 1, .length = 5, },
539 .transp = { .offset = 0, .length = 1, },
540 .bits_per_pixel = 16,
541};
542
543static const struct ipu_rgb def_bgra_16 = {
544 .red = { .offset = 1, .length = 5, },
545 .green = { .offset = 6, .length = 5, },
546 .blue = { .offset = 11, .length = 5, },
547 .transp = { .offset = 0, .length = 1, },
548 .bits_per_pixel = 16,
549};
550
7d2691da 551#define Y_OFFSET(pix, x, y) ((x) + pix->width * (y))
9a34cef0
SL		 552#define U_OFFSET(pix, x, y) ((pix->width * pix->height) + \
553 (pix->width * (y) / 4) + (x) / 2)
554#define V_OFFSET(pix, x, y) ((pix->width * pix->height) + \
555 (pix->width * pix->height / 4) + \
556 (pix->width * (y) / 4) + (x) / 2)
557#define U2_OFFSET(pix, x, y) ((pix->width * pix->height) + \
558 (pix->width * (y) / 2) + (x) / 2)
559#define V2_OFFSET(pix, x, y) ((pix->width * pix->height) + \
560 (pix->width * pix->height / 2) + \
561 (pix->width * (y) / 2) + (x) / 2)
562#define UV_OFFSET(pix, x, y) ((pix->width * pix->height) + \
563 (pix->width * (y) / 2) + (x))
564#define UV2_OFFSET(pix, x, y) ((pix->width * pix->height) + \
565 (pix->width * y) + (x))
7d2691da
SL		 566
567int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc)
568{
569 switch (drm_fourcc) {
570 case DRM_FORMAT_YUV420:
571 case DRM_FORMAT_YVU420:
572 /* pix format */
573 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 2);
574 /* burst size */
575 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
576 break;
9a34cef0
SL		 577 case DRM_FORMAT_YUV422:
578 case DRM_FORMAT_YVU422:
579 /* pix format */
580 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 1);
581 /* burst size */
582 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
583 break;
584 case DRM_FORMAT_NV12:
585 /* pix format */
586 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 4);
587 /* burst size */
588 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
589 break;
590 case DRM_FORMAT_NV16:
591 /* pix format */
592 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 3);
593 /* burst size */
594 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
595 break;
7d2691da
SL		 596 case DRM_FORMAT_UYVY:
597 /* bits/pixel */
598 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3);
599 /* pix format */
600 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA);
601 /* burst size */
602 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
603 break;
604 case DRM_FORMAT_YUYV:
605 /* bits/pixel */
606 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3);
607 /* pix format */
608 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8);
609 /* burst size */
610 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
611 break;
612 case DRM_FORMAT_ABGR8888:
613 case DRM_FORMAT_XBGR8888:
067f4aa4 614 ipu_cpmem_set_format_rgb(ch, &def_xbgr_32);
7d2691da
SL		 615 break;
616 case DRM_FORMAT_ARGB8888:
617 case DRM_FORMAT_XRGB8888:
067f4aa4
PZ		 618 ipu_cpmem_set_format_rgb(ch, &def_xrgb_32);
619 break;
620 case DRM_FORMAT_RGBA8888:
621 case DRM_FORMAT_RGBX8888:
622 ipu_cpmem_set_format_rgb(ch, &def_rgbx_32);
623 break;
624 case DRM_FORMAT_BGRA8888:
625 case DRM_FORMAT_BGRX8888:
626 ipu_cpmem_set_format_rgb(ch, &def_bgrx_32);
7d2691da
SL		 627 break;
628 case DRM_FORMAT_BGR888:
629 ipu_cpmem_set_format_rgb(ch, &def_bgr_24);
630 break;
631 case DRM_FORMAT_RGB888:
632 ipu_cpmem_set_format_rgb(ch, &def_rgb_24);
633 break;
634 case DRM_FORMAT_RGB565:
635 ipu_cpmem_set_format_rgb(ch, &def_rgb_16);
636 break;
637 case DRM_FORMAT_BGR565:
638 ipu_cpmem_set_format_rgb(ch, &def_bgr_16);
639 break;
0cb8b757
PZ		 640 case DRM_FORMAT_ARGB1555:
641 ipu_cpmem_set_format_rgb(ch, &def_argb_16);
642 break;
643 case DRM_FORMAT_ABGR1555:
644 ipu_cpmem_set_format_rgb(ch, &def_abgr_16);
645 break;
646 case DRM_FORMAT_RGBA5551:
647 ipu_cpmem_set_format_rgb(ch, &def_rgba_16);
648 break;
649 case DRM_FORMAT_BGRA5551:
650 ipu_cpmem_set_format_rgb(ch, &def_bgra_16);
651 break;
7d2691da
SL		 652 default:
653 return -EINVAL;
654 }
655
656 return 0;
657}
658EXPORT_SYMBOL_GPL(ipu_cpmem_set_fmt);
659
660int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image)
661{
662 struct v4l2_pix_format *pix = &image->pix;
9a34cef0 663 int offset, u_offset, v_offset;
7d2691da
SL		 664
665 pr_debug("%s: resolution: %dx%d stride: %d\n",
666 __func__, pix->width, pix->height,
667 pix->bytesperline);
668
669 ipu_cpmem_set_resolution(ch, image->rect.width, image->rect.height);
670 ipu_cpmem_set_stride(ch, pix->bytesperline);
671
672 ipu_cpmem_set_fmt(ch, v4l2_pix_fmt_to_drm_fourcc(pix->pixelformat));
673
674 switch (pix->pixelformat) {
675 case V4L2_PIX_FMT_YUV420:
676 case V4L2_PIX_FMT_YVU420:
9a34cef0 677 offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
7d2691da 678 u_offset = U_OFFSET(pix, image->rect.left,
9a34cef0 679 image->rect.top) - offset;
7d2691da 680 v_offset = V_OFFSET(pix, image->rect.left,
9a34cef0
SL		 681 image->rect.top) - offset;
682
683 ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat,
684 pix->bytesperline,
685 u_offset, v_offset);
686 break;
687 case V4L2_PIX_FMT_YUV422P:
688 offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
689 u_offset = U2_OFFSET(pix, image->rect.left,
690 image->rect.top) - offset;
691 v_offset = V2_OFFSET(pix, image->rect.left,
692 image->rect.top) - offset;
693
694 ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat,
695 pix->bytesperline,
696 u_offset, v_offset);
697 break;
698 case V4L2_PIX_FMT_NV12:
699 offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
700 u_offset = UV_OFFSET(pix, image->rect.left,
701 image->rect.top) - offset;
702 v_offset = 0;
7d2691da
SL		 703
704 ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat,
9a34cef0
SL		 705 pix->bytesperline,
706 u_offset, v_offset);
707 break;
708 case V4L2_PIX_FMT_NV16:
709 offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
710 u_offset = UV2_OFFSET(pix, image->rect.left,
711 image->rect.top) - offset;
712 v_offset = 0;
713
714 ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat,
715 pix->bytesperline,
716 u_offset, v_offset);
7d2691da
SL		 717 break;
718 case V4L2_PIX_FMT_UYVY:
719 case V4L2_PIX_FMT_YUYV:
2094b603
SL		 720 case V4L2_PIX_FMT_RGB565:
721 offset = image->rect.left * 2 +
722 image->rect.top * pix->bytesperline;
7d2691da
SL		 723 break;
724 case V4L2_PIX_FMT_RGB32:
725 case V4L2_PIX_FMT_BGR32:
2094b603
SL		 726 offset = image->rect.left * 4 +
727 image->rect.top * pix->bytesperline;
7d2691da
SL		 728 break;
729 case V4L2_PIX_FMT_RGB24:
730 case V4L2_PIX_FMT_BGR24:
2094b603
SL		 731 offset = image->rect.left * 3 +
732 image->rect.top * pix->bytesperline;
7d2691da
SL		 733 break;
734 default:
735 return -EINVAL;
736 }
737
9a34cef0
SL		 738 ipu_cpmem_set_buffer(ch, 0, image->phys0 + offset);
739 ipu_cpmem_set_buffer(ch, 1, image->phys1 + offset);
740
7d2691da
SL		 741 return 0;
742}
743EXPORT_SYMBOL_GPL(ipu_cpmem_set_image);
744
60c04456
SL		 745void ipu_cpmem_dump(struct ipuv3_channel *ch)
746{
747 struct ipu_ch_param __iomem *p = ipu_get_cpmem(ch);
748 struct ipu_soc *ipu = ch->ipu;
749 int chno = ch->num;
750
751 dev_dbg(ipu->dev, "ch %d word 0 - %08X %08X %08X %08X %08X\n", chno,
752 readl(&p->word[0].data[0]),
753 readl(&p->word[0].data[1]),
754 readl(&p->word[0].data[2]),
755 readl(&p->word[0].data[3]),
756 readl(&p->word[0].data[4]));
757 dev_dbg(ipu->dev, "ch %d word 1 - %08X %08X %08X %08X %08X\n", chno,
758 readl(&p->word[1].data[0]),
759 readl(&p->word[1].data[1]),
760 readl(&p->word[1].data[2]),
761 readl(&p->word[1].data[3]),
762 readl(&p->word[1].data[4]));
763 dev_dbg(ipu->dev, "PFS 0x%x, ",
764 ipu_ch_param_read_field(ch, IPU_FIELD_PFS));
765 dev_dbg(ipu->dev, "BPP 0x%x, ",
766 ipu_ch_param_read_field(ch, IPU_FIELD_BPP));
767 dev_dbg(ipu->dev, "NPB 0x%x\n",
768 ipu_ch_param_read_field(ch, IPU_FIELD_NPB));
769
770 dev_dbg(ipu->dev, "FW %d, ",
771 ipu_ch_param_read_field(ch, IPU_FIELD_FW));
772 dev_dbg(ipu->dev, "FH %d, ",
773 ipu_ch_param_read_field(ch, IPU_FIELD_FH));
774 dev_dbg(ipu->dev, "EBA0 0x%x\n",
775 ipu_ch_param_read_field(ch, IPU_FIELD_EBA0) << 3);
776 dev_dbg(ipu->dev, "EBA1 0x%x\n",
777 ipu_ch_param_read_field(ch, IPU_FIELD_EBA1) << 3);
778 dev_dbg(ipu->dev, "Stride %d\n",
779 ipu_ch_param_read_field(ch, IPU_FIELD_SL));
780 dev_dbg(ipu->dev, "scan_order %d\n",
781 ipu_ch_param_read_field(ch, IPU_FIELD_SO));
782 dev_dbg(ipu->dev, "uv_stride %d\n",
783 ipu_ch_param_read_field(ch, IPU_FIELD_SLUV));
784 dev_dbg(ipu->dev, "u_offset 0x%x\n",
785 ipu_ch_param_read_field(ch, IPU_FIELD_UBO) << 3);
786 dev_dbg(ipu->dev, "v_offset 0x%x\n",
787 ipu_ch_param_read_field(ch, IPU_FIELD_VBO) << 3);
788
789 dev_dbg(ipu->dev, "Width0 %d+1, ",
790 ipu_ch_param_read_field(ch, IPU_FIELD_WID0));
791 dev_dbg(ipu->dev, "Width1 %d+1, ",
792 ipu_ch_param_read_field(ch, IPU_FIELD_WID1));
793 dev_dbg(ipu->dev, "Width2 %d+1, ",
794 ipu_ch_param_read_field(ch, IPU_FIELD_WID2));
795 dev_dbg(ipu->dev, "Width3 %d+1, ",
796 ipu_ch_param_read_field(ch, IPU_FIELD_WID3));
797 dev_dbg(ipu->dev, "Offset0 %d, ",
798 ipu_ch_param_read_field(ch, IPU_FIELD_OFS0));
799 dev_dbg(ipu->dev, "Offset1 %d, ",
800 ipu_ch_param_read_field(ch, IPU_FIELD_OFS1));
801 dev_dbg(ipu->dev, "Offset2 %d, ",
802 ipu_ch_param_read_field(ch, IPU_FIELD_OFS2));
803 dev_dbg(ipu->dev, "Offset3 %d\n",
804 ipu_ch_param_read_field(ch, IPU_FIELD_OFS3));
805}
806EXPORT_SYMBOL_GPL(ipu_cpmem_dump);
807
7d2691da
SL		 808int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base)
809{
810 struct ipu_cpmem *cpmem;
811
812 cpmem = devm_kzalloc(dev, sizeof(*cpmem), GFP_KERNEL);
813 if (!cpmem)
814 return -ENOMEM;
815
816 ipu->cpmem_priv = cpmem;
817
818 spin_lock_init(&cpmem->lock);
819 cpmem->base = devm_ioremap(dev, base, SZ_128K);
820 if (!cpmem->base)
821 return -ENOMEM;
822
823 dev_dbg(dev, "CPMEM base: 0x%08lx remapped to %p\n",
824 base, cpmem->base);
825 cpmem->ipu = ipu;
826
827 return 0;
828}
829
830void ipu_cpmem_exit(struct ipu_soc *ipu)
831{
832}
Linux kernel - Deliverables
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