[deliverable/linux.git] / drivers / gpu / ipu-v3 / ipu-cpmem.c

/*
 * Copyright (C) 2012 Mentor Graphics Inc.
 * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */
#include <linux/types.h>
#include <linux/bitrev.h>
#include <linux/io.h>
#include <drm/drm_fourcc.h>
#include "ipu-prv.h"

struct ipu_cpmem_word {
	u32 data[5];
	u32 res[3];
};

struct ipu_ch_param {
	struct ipu_cpmem_word word[2];
};

struct ipu_cpmem {
	struct ipu_ch_param __iomem *base;
	u32 module;
	spinlock_t lock;
	int use_count;
	struct ipu_soc *ipu;
};

#define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size))

#define IPU_FIELD_UBO		IPU_CPMEM_WORD(0, 46, 22)
#define IPU_FIELD_VBO		IPU_CPMEM_WORD(0, 68, 22)
#define IPU_FIELD_IOX		IPU_CPMEM_WORD(0, 90, 4)
#define IPU_FIELD_RDRW		IPU_CPMEM_WORD(0, 94, 1)
#define IPU_FIELD_SO		IPU_CPMEM_WORD(0, 113, 1)
#define IPU_FIELD_SLY		IPU_CPMEM_WORD(1, 102, 14)
#define IPU_FIELD_SLUV		IPU_CPMEM_WORD(1, 128, 14)

#define IPU_FIELD_XV		IPU_CPMEM_WORD(0, 0, 10)
#define IPU_FIELD_YV		IPU_CPMEM_WORD(0, 10, 9)
#define IPU_FIELD_XB		IPU_CPMEM_WORD(0, 19, 13)
#define IPU_FIELD_YB		IPU_CPMEM_WORD(0, 32, 12)
#define IPU_FIELD_NSB_B		IPU_CPMEM_WORD(0, 44, 1)
#define IPU_FIELD_CF		IPU_CPMEM_WORD(0, 45, 1)
#define IPU_FIELD_SX		IPU_CPMEM_WORD(0, 46, 12)
#define IPU_FIELD_SY		IPU_CPMEM_WORD(0, 58, 11)
#define IPU_FIELD_NS		IPU_CPMEM_WORD(0, 69, 10)
#define IPU_FIELD_SDX		IPU_CPMEM_WORD(0, 79, 7)
#define IPU_FIELD_SM		IPU_CPMEM_WORD(0, 86, 10)
#define IPU_FIELD_SCC		IPU_CPMEM_WORD(0, 96, 1)
#define IPU_FIELD_SCE		IPU_CPMEM_WORD(0, 97, 1)
#define IPU_FIELD_SDY		IPU_CPMEM_WORD(0, 98, 7)
#define IPU_FIELD_SDRX		IPU_CPMEM_WORD(0, 105, 1)
#define IPU_FIELD_SDRY		IPU_CPMEM_WORD(0, 106, 1)
#define IPU_FIELD_BPP		IPU_CPMEM_WORD(0, 107, 3)
#define IPU_FIELD_DEC_SEL	IPU_CPMEM_WORD(0, 110, 2)
#define IPU_FIELD_DIM		IPU_CPMEM_WORD(0, 112, 1)
#define IPU_FIELD_BNDM		IPU_CPMEM_WORD(0, 114, 3)
#define IPU_FIELD_BM		IPU_CPMEM_WORD(0, 117, 2)
#define IPU_FIELD_ROT		IPU_CPMEM_WORD(0, 119, 1)
#define IPU_FIELD_HF		IPU_CPMEM_WORD(0, 120, 1)
#define IPU_FIELD_VF		IPU_CPMEM_WORD(0, 121, 1)
#define IPU_FIELD_THE		IPU_CPMEM_WORD(0, 122, 1)
#define IPU_FIELD_CAP		IPU_CPMEM_WORD(0, 123, 1)
#define IPU_FIELD_CAE		IPU_CPMEM_WORD(0, 124, 1)
#define IPU_FIELD_FW		IPU_CPMEM_WORD(0, 125, 13)
#define IPU_FIELD_FH		IPU_CPMEM_WORD(0, 138, 12)
#define IPU_FIELD_EBA0		IPU_CPMEM_WORD(1, 0, 29)
#define IPU_FIELD_EBA1		IPU_CPMEM_WORD(1, 29, 29)
#define IPU_FIELD_ILO		IPU_CPMEM_WORD(1, 58, 20)
#define IPU_FIELD_NPB		IPU_CPMEM_WORD(1, 78, 7)
#define IPU_FIELD_PFS		IPU_CPMEM_WORD(1, 85, 4)
#define IPU_FIELD_ALU		IPU_CPMEM_WORD(1, 89, 1)
#define IPU_FIELD_ALBM		IPU_CPMEM_WORD(1, 90, 3)
#define IPU_FIELD_ID		IPU_CPMEM_WORD(1, 93, 2)
#define IPU_FIELD_TH		IPU_CPMEM_WORD(1, 95, 7)
#define IPU_FIELD_SL		IPU_CPMEM_WORD(1, 102, 14)
#define IPU_FIELD_WID0		IPU_CPMEM_WORD(1, 116, 3)
#define IPU_FIELD_WID1		IPU_CPMEM_WORD(1, 119, 3)
#define IPU_FIELD_WID2		IPU_CPMEM_WORD(1, 122, 3)
#define IPU_FIELD_WID3		IPU_CPMEM_WORD(1, 125, 3)
#define IPU_FIELD_OFS0		IPU_CPMEM_WORD(1, 128, 5)
#define IPU_FIELD_OFS1		IPU_CPMEM_WORD(1, 133, 5)
#define IPU_FIELD_OFS2		IPU_CPMEM_WORD(1, 138, 5)
#define IPU_FIELD_OFS3		IPU_CPMEM_WORD(1, 143, 5)
#define IPU_FIELD_SXYS		IPU_CPMEM_WORD(1, 148, 1)
#define IPU_FIELD_CRE		IPU_CPMEM_WORD(1, 149, 1)
#define IPU_FIELD_DEC_SEL2	IPU_CPMEM_WORD(1, 150, 1)

static inline struct ipu_ch_param __iomem *
ipu_get_cpmem(struct ipuv3_channel *ch)
{
	struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv;

	return cpmem->base + ch->num;
}

static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v)
{
	struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch);
	u32 bit = (wbs >> 8) % 160;
	u32 size = wbs & 0xff;
	u32 word = (wbs >> 8) / 160;
	u32 i = bit / 32;
	u32 ofs = bit % 32;
	u32 mask = (1 << size) - 1;
	u32 val;

	pr_debug("%s %d %d %d\n", __func__, word, bit , size);

	val = readl(&base->word[word].data[i]);
	val &= ~(mask << ofs);
	val |= v << ofs;
	writel(val, &base->word[word].data[i]);

	if ((bit + size - 1) / 32 > i) {
		val = readl(&base->word[word].data[i + 1]);
		val &= ~(mask >> (ofs ? (32 - ofs) : 0));
		val |= v >> (ofs ? (32 - ofs) : 0);
		writel(val, &base->word[word].data[i + 1]);
	}
}

static u32 ipu_ch_param_read_field(struct ipuv3_channel *ch, u32 wbs)
{
	struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch);
	u32 bit = (wbs >> 8) % 160;
	u32 size = wbs & 0xff;
	u32 word = (wbs >> 8) / 160;
	u32 i = bit / 32;
	u32 ofs = bit % 32;
	u32 mask = (1 << size) - 1;
	u32 val = 0;

	pr_debug("%s %d %d %d\n", __func__, word, bit , size);

	val = (readl(&base->word[word].data[i]) >> ofs) & mask;

	if ((bit + size - 1) / 32 > i) {
		u32 tmp;

		tmp = readl(&base->word[word].data[i + 1]);
		tmp &= mask >> (ofs ? (32 - ofs) : 0);
		val |= tmp << (ofs ? (32 - ofs) : 0);
	}

	return val;
}

/*
 * The V4L2 spec defines packed RGB formats in memory byte order, which from
 * point of view of the IPU corresponds to little-endian words with the first
 * component in the least significant bits.
 * The DRM pixel formats and IPU internal representation are ordered the other
 * way around, with the first named component ordered at the most significant
 * bits. Further, V4L2 formats are not well defined:
 *     http://linuxtv.org/downloads/v4l-dvb-apis/packed-rgb.html
 * We choose the interpretation which matches GStreamer behavior.
 */
static int v4l2_pix_fmt_to_drm_fourcc(u32 pixelformat)
{
	switch (pixelformat) {
	case V4L2_PIX_FMT_RGB565:
		/*
		 * Here we choose the 'corrected' interpretation of RGBP, a
		 * little-endian 16-bit word with the red component at the most
		 * significant bits:
		 * g[2:0]b[4:0] r[4:0]g[5:3] <=> [16:0] R:G:B
		 */
		return DRM_FORMAT_RGB565;
	case V4L2_PIX_FMT_BGR24:
		/* B G R <=> [24:0] R:G:B */
		return DRM_FORMAT_RGB888;
	case V4L2_PIX_FMT_RGB24:
		/* R G B <=> [24:0] B:G:R */
		return DRM_FORMAT_BGR888;
	case V4L2_PIX_FMT_BGR32:
		/* B G R A <=> [32:0] A:B:G:R */
		return DRM_FORMAT_XRGB8888;
	case V4L2_PIX_FMT_RGB32:
		/* R G B A <=> [32:0] A:B:G:R */
		return DRM_FORMAT_XBGR8888;
	case V4L2_PIX_FMT_UYVY:
		return DRM_FORMAT_UYVY;
	case V4L2_PIX_FMT_YUYV:
		return DRM_FORMAT_YUYV;
	case V4L2_PIX_FMT_YUV420:
		return DRM_FORMAT_YUV420;
	case V4L2_PIX_FMT_YVU420:
		return DRM_FORMAT_YVU420;
	}

	return -EINVAL;
}

void ipu_cpmem_zero(struct ipuv3_channel *ch)
{
	struct ipu_ch_param __iomem *p = ipu_get_cpmem(ch);
	void __iomem *base = p;
	int i;

	for (i = 0; i < sizeof(*p) / sizeof(u32); i++)
		writel(0, base + i * sizeof(u32));
}
EXPORT_SYMBOL_GPL(ipu_cpmem_zero);

void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres)
{
	ipu_ch_param_write_field(ch, IPU_FIELD_FW, xres - 1);
	ipu_ch_param_write_field(ch, IPU_FIELD_FH, yres - 1);
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_resolution);

void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride)
{
	ipu_ch_param_write_field(ch, IPU_FIELD_SLY, stride - 1);
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_stride);

void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch)
{
	struct ipu_soc *ipu = ch->ipu;
	u32 val;

	if (ipu->ipu_type == IPUV3EX)
		ipu_ch_param_write_field(ch, IPU_FIELD_ID, 1);

	val = ipu_idmac_read(ipu, IDMAC_CHA_PRI(ch->num));
	val |= 1 << (ch->num % 32);
	ipu_idmac_write(ipu, val, IDMAC_CHA_PRI(ch->num));
};
EXPORT_SYMBOL_GPL(ipu_cpmem_set_high_priority);

void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf)
{
	if (bufnum)
		ipu_ch_param_write_field(ch, IPU_FIELD_EBA1, buf >> 3);
	else
		ipu_ch_param_write_field(ch, IPU_FIELD_EBA0, buf >> 3);
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_buffer);

void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride)
{
	ipu_ch_param_write_field(ch, IPU_FIELD_SO, 1);
	ipu_ch_param_write_field(ch, IPU_FIELD_ILO, stride / 8);
	ipu_ch_param_write_field(ch, IPU_FIELD_SLY, (stride * 2) - 1);
};
EXPORT_SYMBOL_GPL(ipu_cpmem_interlaced_scan);

void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize)
{
	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, burstsize - 1);
};
EXPORT_SYMBOL_GPL(ipu_cpmem_set_burstsize);

void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch)
{
	ipu_ch_param_write_field(ch, IPU_FIELD_BM, 1);
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_block_mode);

int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
			     const struct ipu_rgb *rgb)
{
	int bpp = 0, npb = 0, ro, go, bo, to;

	ro = rgb->bits_per_pixel - rgb->red.length - rgb->red.offset;
	go = rgb->bits_per_pixel - rgb->green.length - rgb->green.offset;
	bo = rgb->bits_per_pixel - rgb->blue.length - rgb->blue.offset;
	to = rgb->bits_per_pixel - rgb->transp.length - rgb->transp.offset;

	ipu_ch_param_write_field(ch, IPU_FIELD_WID0, rgb->red.length - 1);
	ipu_ch_param_write_field(ch, IPU_FIELD_OFS0, ro);
	ipu_ch_param_write_field(ch, IPU_FIELD_WID1, rgb->green.length - 1);
	ipu_ch_param_write_field(ch, IPU_FIELD_OFS1, go);
	ipu_ch_param_write_field(ch, IPU_FIELD_WID2, rgb->blue.length - 1);
	ipu_ch_param_write_field(ch, IPU_FIELD_OFS2, bo);

	if (rgb->transp.length) {
		ipu_ch_param_write_field(ch, IPU_FIELD_WID3,
				rgb->transp.length - 1);
		ipu_ch_param_write_field(ch, IPU_FIELD_OFS3, to);
	} else {
		ipu_ch_param_write_field(ch, IPU_FIELD_WID3, 7);
		ipu_ch_param_write_field(ch, IPU_FIELD_OFS3,
				rgb->bits_per_pixel);
	}

	switch (rgb->bits_per_pixel) {
	case 32:
		bpp = 0;
		npb = 15;
		break;
	case 24:
		bpp = 1;
		npb = 19;
		break;
	case 16:
		bpp = 3;
		npb = 31;
		break;
	case 8:
		bpp = 5;
		npb = 63;
		break;
	default:
		return -EINVAL;
	}
	ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp);
	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb);
	ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 7); /* rgb mode */

	return 0;
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_rgb);

int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width)
{
	int bpp = 0, npb = 0;

	switch (width) {
	case 32:
		bpp = 0;
		npb = 15;
		break;
	case 24:
		bpp = 1;
		npb = 19;
		break;
	case 16:
		bpp = 3;
		npb = 31;
		break;
	case 8:
		bpp = 5;
		npb = 63;
		break;
	default:
		return -EINVAL;
	}

	ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp);
	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb);
	ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 6); /* raw mode */

	return 0;
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_passthrough);

void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format)
{
	switch (pixel_format) {
	case V4L2_PIX_FMT_UYVY:
		ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */
		ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA);/* pix fmt */
		ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */
		break;
	case V4L2_PIX_FMT_YUYV:
		ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */
		ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8);/* pix fmt */
		ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */
		break;
	}
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_interleaved);

void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
				   u32 pixel_format, int stride,
				   int u_offset, int v_offset)
{
	switch (pixel_format) {
	case V4L2_PIX_FMT_YUV420:
		ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1);
		ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8);
		ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8);
		break;
	case V4L2_PIX_FMT_YVU420:
		ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1);
		ipu_ch_param_write_field(ch, IPU_FIELD_UBO, v_offset / 8);
		ipu_ch_param_write_field(ch, IPU_FIELD_VBO, u_offset / 8);
		break;
	}
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full);

void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
			      u32 pixel_format, int stride, int height)
{
	int u_offset, v_offset;
	int uv_stride = 0;

	switch (pixel_format) {
	case V4L2_PIX_FMT_YUV420:
	case V4L2_PIX_FMT_YVU420:
		uv_stride = stride / 2;
		u_offset = stride * height;
		v_offset = u_offset + (uv_stride * height / 2);
		ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride,
					      u_offset, v_offset);
		break;
	}
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar);

static const struct ipu_rgb def_rgb_32 = {
	.red	= { .offset = 16, .length = 8, },
	.green	= { .offset =  8, .length = 8, },
	.blue	= { .offset =  0, .length = 8, },
	.transp = { .offset = 24, .length = 8, },
	.bits_per_pixel = 32,
};

static const struct ipu_rgb def_bgr_32 = {
	.red	= { .offset =  0, .length = 8, },
	.green	= { .offset =  8, .length = 8, },
	.blue	= { .offset = 16, .length = 8, },
	.transp = { .offset = 24, .length = 8, },
	.bits_per_pixel = 32,
};

static const struct ipu_rgb def_rgb_24 = {
	.red	= { .offset = 16, .length = 8, },
	.green	= { .offset =  8, .length = 8, },
	.blue	= { .offset =  0, .length = 8, },
	.transp = { .offset =  0, .length = 0, },
	.bits_per_pixel = 24,
};

static const struct ipu_rgb def_bgr_24 = {
	.red	= { .offset =  0, .length = 8, },
	.green	= { .offset =  8, .length = 8, },
	.blue	= { .offset = 16, .length = 8, },
	.transp = { .offset =  0, .length = 0, },
	.bits_per_pixel = 24,
};

static const struct ipu_rgb def_rgb_16 = {
	.red	= { .offset = 11, .length = 5, },
	.green	= { .offset =  5, .length = 6, },
	.blue	= { .offset =  0, .length = 5, },
	.transp = { .offset =  0, .length = 0, },
	.bits_per_pixel = 16,
};

static const struct ipu_rgb def_bgr_16 = {
	.red	= { .offset =  0, .length = 5, },
	.green	= { .offset =  5, .length = 6, },
	.blue	= { .offset = 11, .length = 5, },
	.transp = { .offset =  0, .length = 0, },
	.bits_per_pixel = 16,
};

#define Y_OFFSET(pix, x, y)	((x) + pix->width * (y))
#define U_OFFSET(pix, x, y)	((pix->width * pix->height) + \
					(pix->width * (y) / 4) + (x) / 2)
#define V_OFFSET(pix, x, y)	((pix->width * pix->height) + \
					(pix->width * pix->height / 4) + \
					(pix->width * (y) / 4) + (x) / 2)

int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc)
{
	switch (drm_fourcc) {
	case DRM_FORMAT_YUV420:
	case DRM_FORMAT_YVU420:
		/* pix format */
		ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 2);
		/* burst size */
		ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
		break;
	case DRM_FORMAT_UYVY:
		/* bits/pixel */
		ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3);
		/* pix format */
		ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA);
		/* burst size */
		ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
		break;
	case DRM_FORMAT_YUYV:
		/* bits/pixel */
		ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3);
		/* pix format */
		ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8);
		/* burst size */
		ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
		break;
	case DRM_FORMAT_ABGR8888:
	case DRM_FORMAT_XBGR8888:
		ipu_cpmem_set_format_rgb(ch, &def_bgr_32);
		break;
	case DRM_FORMAT_ARGB8888:
	case DRM_FORMAT_XRGB8888:
		ipu_cpmem_set_format_rgb(ch, &def_rgb_32);
		break;
	case DRM_FORMAT_BGR888:
		ipu_cpmem_set_format_rgb(ch, &def_bgr_24);
		break;
	case DRM_FORMAT_RGB888:
		ipu_cpmem_set_format_rgb(ch, &def_rgb_24);
		break;
	case DRM_FORMAT_RGB565:
		ipu_cpmem_set_format_rgb(ch, &def_rgb_16);
		break;
	case DRM_FORMAT_BGR565:
		ipu_cpmem_set_format_rgb(ch, &def_bgr_16);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_fmt);

int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image)
{
	struct v4l2_pix_format *pix = &image->pix;
	int y_offset, u_offset, v_offset;

	pr_debug("%s: resolution: %dx%d stride: %d\n",
		 __func__, pix->width, pix->height,
		 pix->bytesperline);

	ipu_cpmem_set_resolution(ch, image->rect.width, image->rect.height);
	ipu_cpmem_set_stride(ch, pix->bytesperline);

	ipu_cpmem_set_fmt(ch, v4l2_pix_fmt_to_drm_fourcc(pix->pixelformat));

	switch (pix->pixelformat) {
	case V4L2_PIX_FMT_YUV420:
	case V4L2_PIX_FMT_YVU420:
		y_offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
		u_offset = U_OFFSET(pix, image->rect.left,
				    image->rect.top) - y_offset;
		v_offset = V_OFFSET(pix, image->rect.left,
				    image->rect.top) - y_offset;

		ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat,
				pix->bytesperline, u_offset, v_offset);
		ipu_cpmem_set_buffer(ch, 0, image->phys + y_offset);
		break;
	case V4L2_PIX_FMT_UYVY:
	case V4L2_PIX_FMT_YUYV:
		ipu_cpmem_set_buffer(ch, 0, image->phys +
				     image->rect.left * 2 +
				     image->rect.top * image->pix.bytesperline);
		break;
	case V4L2_PIX_FMT_RGB32:
	case V4L2_PIX_FMT_BGR32:
		ipu_cpmem_set_buffer(ch, 0, image->phys +
				     image->rect.left * 4 +
				     image->rect.top * image->pix.bytesperline);
		break;
	case V4L2_PIX_FMT_RGB565:
		ipu_cpmem_set_buffer(ch, 0, image->phys +
				     image->rect.left * 2 +
				     image->rect.top * image->pix.bytesperline);
		break;
	case V4L2_PIX_FMT_RGB24:
	case V4L2_PIX_FMT_BGR24:
		ipu_cpmem_set_buffer(ch, 0, image->phys +
				     image->rect.left * 3 +
				     image->rect.top * image->pix.bytesperline);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_image);

int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base)
{
	struct ipu_cpmem *cpmem;

	cpmem = devm_kzalloc(dev, sizeof(*cpmem), GFP_KERNEL);
	if (!cpmem)
		return -ENOMEM;

	ipu->cpmem_priv = cpmem;

	spin_lock_init(&cpmem->lock);
	cpmem->base = devm_ioremap(dev, base, SZ_128K);
	if (!cpmem->base)
		return -ENOMEM;

	dev_dbg(dev, "CPMEM base: 0x%08lx remapped to %p\n",
		base, cpmem->base);
	cpmem->ipu = ipu;

	return 0;
}

void ipu_cpmem_exit(struct ipu_soc *ipu)
{
}
Commit	Line	Data
7d2691da SL	1	/*
	2	* Copyright (C) 2012 Mentor Graphics Inc.
	3	* Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12	#include <linux/types.h>
	13	#include <linux/bitrev.h>
	14	#include <linux/io.h>
	15	#include <drm/drm_fourcc.h>
	16	#include "ipu-prv.h"
	17
	18	struct ipu_cpmem_word {
	19	u32 data[5];
	20	u32 res[3];
	21	};
	22
	23	struct ipu_ch_param {
	24	struct ipu_cpmem_word word[2];
	25	};
	26
	27	struct ipu_cpmem {
	28	struct ipu_ch_param __iomem *base;
	29	u32 module;
	30	spinlock_t lock;
	31	int use_count;
	32	struct ipu_soc *ipu;
	33	};
	34
	35	#define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) \| (size))
	36
	37	#define IPU_FIELD_UBO IPU_CPMEM_WORD(0, 46, 22)
	38	#define IPU_FIELD_VBO IPU_CPMEM_WORD(0, 68, 22)
	39	#define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4)
	40	#define IPU_FIELD_RDRW IPU_CPMEM_WORD(0, 94, 1)
	41	#define IPU_FIELD_SO IPU_CPMEM_WORD(0, 113, 1)
	42	#define IPU_FIELD_SLY IPU_CPMEM_WORD(1, 102, 14)
	43	#define IPU_FIELD_SLUV IPU_CPMEM_WORD(1, 128, 14)
	44
	45	#define IPU_FIELD_XV IPU_CPMEM_WORD(0, 0, 10)
	46	#define IPU_FIELD_YV IPU_CPMEM_WORD(0, 10, 9)
	47	#define IPU_FIELD_XB IPU_CPMEM_WORD(0, 19, 13)
	48	#define IPU_FIELD_YB IPU_CPMEM_WORD(0, 32, 12)
	49	#define IPU_FIELD_NSB_B IPU_CPMEM_WORD(0, 44, 1)
	50	#define IPU_FIELD_CF IPU_CPMEM_WORD(0, 45, 1)
	51	#define IPU_FIELD_SX IPU_CPMEM_WORD(0, 46, 12)
	52	#define IPU_FIELD_SY IPU_CPMEM_WORD(0, 58, 11)
	53	#define IPU_FIELD_NS IPU_CPMEM_WORD(0, 69, 10)
	54	#define IPU_FIELD_SDX IPU_CPMEM_WORD(0, 79, 7)
	55	#define IPU_FIELD_SM IPU_CPMEM_WORD(0, 86, 10)
	56	#define IPU_FIELD_SCC IPU_CPMEM_WORD(0, 96, 1)
	57	#define IPU_FIELD_SCE IPU_CPMEM_WORD(0, 97, 1)
	58	#define IPU_FIELD_SDY IPU_CPMEM_WORD(0, 98, 7)
	59	#define IPU_FIELD_SDRX IPU_CPMEM_WORD(0, 105, 1)
	60	#define IPU_FIELD_SDRY IPU_CPMEM_WORD(0, 106, 1)
	61	#define IPU_FIELD_BPP IPU_CPMEM_WORD(0, 107, 3)
	62	#define IPU_FIELD_DEC_SEL IPU_CPMEM_WORD(0, 110, 2)
	63	#define IPU_FIELD_DIM IPU_CPMEM_WORD(0, 112, 1)
	64	#define IPU_FIELD_BNDM IPU_CPMEM_WORD(0, 114, 3)
65	#define IPU_FIELD_BM IPU_CPMEM_WORD(0, 117, 2)
66	#define IPU_FIELD_ROT IPU_CPMEM_WORD(0, 119, 1)
67	#define IPU_FIELD_HF IPU_CPMEM_WORD(0, 120, 1)
68	#define IPU_FIELD_VF IPU_CPMEM_WORD(0, 121, 1)
69	#define IPU_FIELD_THE IPU_CPMEM_WORD(0, 122, 1)
70	#define IPU_FIELD_CAP IPU_CPMEM_WORD(0, 123, 1)
71	#define IPU_FIELD_CAE IPU_CPMEM_WORD(0, 124, 1)
72	#define IPU_FIELD_FW IPU_CPMEM_WORD(0, 125, 13)
73	#define IPU_FIELD_FH IPU_CPMEM_WORD(0, 138, 12)
74	#define IPU_FIELD_EBA0 IPU_CPMEM_WORD(1, 0, 29)
75	#define IPU_FIELD_EBA1 IPU_CPMEM_WORD(1, 29, 29)
76	#define IPU_FIELD_ILO IPU_CPMEM_WORD(1, 58, 20)
77	#define IPU_FIELD_NPB IPU_CPMEM_WORD(1, 78, 7)
78	#define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4)
79	#define IPU_FIELD_ALU IPU_CPMEM_WORD(1, 89, 1)
80	#define IPU_FIELD_ALBM IPU_CPMEM_WORD(1, 90, 3)
81	#define IPU_FIELD_ID IPU_CPMEM_WORD(1, 93, 2)
82	#define IPU_FIELD_TH IPU_CPMEM_WORD(1, 95, 7)
83	#define IPU_FIELD_SL IPU_CPMEM_WORD(1, 102, 14)
84	#define IPU_FIELD_WID0 IPU_CPMEM_WORD(1, 116, 3)
85	#define IPU_FIELD_WID1 IPU_CPMEM_WORD(1, 119, 3)
86	#define IPU_FIELD_WID2 IPU_CPMEM_WORD(1, 122, 3)
87	#define IPU_FIELD_WID3 IPU_CPMEM_WORD(1, 125, 3)
88	#define IPU_FIELD_OFS0 IPU_CPMEM_WORD(1, 128, 5)
89	#define IPU_FIELD_OFS1 IPU_CPMEM_WORD(1, 133, 5)
90	#define IPU_FIELD_OFS2 IPU_CPMEM_WORD(1, 138, 5)
91	#define IPU_FIELD_OFS3 IPU_CPMEM_WORD(1, 143, 5)
92	#define IPU_FIELD_SXYS IPU_CPMEM_WORD(1, 148, 1)
93	#define IPU_FIELD_CRE IPU_CPMEM_WORD(1, 149, 1)
94	#define IPU_FIELD_DEC_SEL2 IPU_CPMEM_WORD(1, 150, 1)
95
96	static inline struct ipu_ch_param __iomem *
97	ipu_get_cpmem(struct ipuv3_channel *ch)
98	{
99	struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv;
100
101	return cpmem->base + ch->num;
102	}
103
104	static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v)
105	{
106	struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch);
107	u32 bit = (wbs >> 8) % 160;
108	u32 size = wbs & 0xff;
109	u32 word = (wbs >> 8) / 160;
110	u32 i = bit / 32;
111	u32 ofs = bit % 32;
112	u32 mask = (1 << size) - 1;
113	u32 val;
114
115	pr_debug("%s %d %d %d\n", __func__, word, bit , size);
116
117	val = readl(&base->word[word].data[i]);
118	val &= ~(mask << ofs);
119	val \|= v << ofs;
120	writel(val, &base->word[word].data[i]);
121
122	if ((bit + size - 1) / 32 > i) {
123	val = readl(&base->word[word].data[i + 1]);
124	val &= ~(mask >> (ofs ? (32 - ofs) : 0));
125	val \|= v >> (ofs ? (32 - ofs) : 0);
126	writel(val, &base->word[word].data[i + 1]);
127	}
128	}
129
130	static u32 ipu_ch_param_read_field(struct ipuv3_channel *ch, u32 wbs)
131	{
132	struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch);
133	u32 bit = (wbs >> 8) % 160;
134	u32 size = wbs & 0xff;
135	u32 word = (wbs >> 8) / 160;
136	u32 i = bit / 32;
137	u32 ofs = bit % 32;
138	u32 mask = (1 << size) - 1;
139	u32 val = 0;
140
141	pr_debug("%s %d %d %d\n", __func__, word, bit , size);
142
143	val = (readl(&base->word[word].data[i]) >> ofs) & mask;
144
145	if ((bit + size - 1) / 32 > i) {
146	u32 tmp;
147
148	tmp = readl(&base->word[word].data[i + 1]);
149	tmp &= mask >> (ofs ? (32 - ofs) : 0);
150	val \|= tmp << (ofs ? (32 - ofs) : 0);
151	}
152
153	return val;
154	}
155
156	/*
157	* The V4L2 spec defines packed RGB formats in memory byte order, which from
158	* point of view of the IPU corresponds to little-endian words with the first
159	* component in the least significant bits.
160	* The DRM pixel formats and IPU internal representation are ordered the other
161	* way around, with the first named component ordered at the most significant
162	* bits. Further, V4L2 formats are not well defined:
163	* http://linuxtv.org/downloads/v4l-dvb-apis/packed-rgb.html
164	* We choose the interpretation which matches GStreamer behavior.
165	*/
166	static int v4l2_pix_fmt_to_drm_fourcc(u32 pixelformat)
167	{
168	switch (pixelformat) {
169	case V4L2_PIX_FMT_RGB565:
170	/*
171	* Here we choose the 'corrected' interpretation of RGBP, a
172	* little-endian 16-bit word with the red component at the most
173	* significant bits:
174	* g[2:0]b[4:0] r[4:0]g[5:3] <=> [16:0] R:G:B
175	*/
176	return DRM_FORMAT_RGB565;
177	case V4L2_PIX_FMT_BGR24:
178	/* B G R <=> [24:0] R:G:B */
179	return DRM_FORMAT_RGB888;
180	case V4L2_PIX_FMT_RGB24:
181	/* R G B <=> [24:0] B:G:R */
182	return DRM_FORMAT_BGR888;
183	case V4L2_PIX_FMT_BGR32:
184	/* B G R A <=> [32:0] A:B:G:R */
185	return DRM_FORMAT_XRGB8888;
186	case V4L2_PIX_FMT_RGB32:
187	/* R G B A <=> [32:0] A:B:G:R */
188	return DRM_FORMAT_XBGR8888;
189	case V4L2_PIX_FMT_UYVY:
190	return DRM_FORMAT_UYVY;
191	case V4L2_PIX_FMT_YUYV:
192	return DRM_FORMAT_YUYV;
193	case V4L2_PIX_FMT_YUV420:
194	return DRM_FORMAT_YUV420;
195	case V4L2_PIX_FMT_YVU420:
196	return DRM_FORMAT_YVU420;
197	}
198
199	return -EINVAL;
200	}
201
202	void ipu_cpmem_zero(struct ipuv3_channel *ch)
203	{
204	struct ipu_ch_param __iomem *p = ipu_get_cpmem(ch);
205	void __iomem *base = p;
206	int i;
207
208	for (i = 0; i < sizeof(*p) / sizeof(u32); i++)
209	writel(0, base + i * sizeof(u32));
210	}
211	EXPORT_SYMBOL_GPL(ipu_cpmem_zero);
212
213	void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres)
214	{
215	ipu_ch_param_write_field(ch, IPU_FIELD_FW, xres - 1);
216	ipu_ch_param_write_field(ch, IPU_FIELD_FH, yres - 1);
217	}
218	EXPORT_SYMBOL_GPL(ipu_cpmem_set_resolution);
219
220	void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride)
221	{
222	ipu_ch_param_write_field(ch, IPU_FIELD_SLY, stride - 1);
223	}
224	EXPORT_SYMBOL_GPL(ipu_cpmem_set_stride);
225
226	void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch)
227	{
228	struct ipu_soc *ipu = ch->ipu;
229	u32 val;
230
231	if (ipu->ipu_type == IPUV3EX)
232	ipu_ch_param_write_field(ch, IPU_FIELD_ID, 1);
233
234	val = ipu_idmac_read(ipu, IDMAC_CHA_PRI(ch->num));
235	val \|= 1 << (ch->num % 32);
236	ipu_idmac_write(ipu, val, IDMAC_CHA_PRI(ch->num));
237	};
238	EXPORT_SYMBOL_GPL(ipu_cpmem_set_high_priority);
239
240	void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf)
241	{
242	if (bufnum)
243	ipu_ch_param_write_field(ch, IPU_FIELD_EBA1, buf >> 3);
244	else
245	ipu_ch_param_write_field(ch, IPU_FIELD_EBA0, buf >> 3);
246	}
247	EXPORT_SYMBOL_GPL(ipu_cpmem_set_buffer);
248
249	void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride)
250	{
251	ipu_ch_param_write_field(ch, IPU_FIELD_SO, 1);
252	ipu_ch_param_write_field(ch, IPU_FIELD_ILO, stride / 8);
253	ipu_ch_param_write_field(ch, IPU_FIELD_SLY, (stride * 2) - 1);
254	};
255	EXPORT_SYMBOL_GPL(ipu_cpmem_interlaced_scan);
256
257	void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize)
258	{
259	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, burstsize - 1);
260	};
261	EXPORT_SYMBOL_GPL(ipu_cpmem_set_burstsize);
262
9b9da0be SL	263	void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch)
	264	{
	265	ipu_ch_param_write_field(ch, IPU_FIELD_BM, 1);
	266	}
	267	EXPORT_SYMBOL_GPL(ipu_cpmem_set_block_mode);
	268
7d2691da SL	269	int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
	270	const struct ipu_rgb *rgb)
	271	{
	272	int bpp = 0, npb = 0, ro, go, bo, to;
	273
	274	ro = rgb->bits_per_pixel - rgb->red.length - rgb->red.offset;
	275	go = rgb->bits_per_pixel - rgb->green.length - rgb->green.offset;
	276	bo = rgb->bits_per_pixel - rgb->blue.length - rgb->blue.offset;
	277	to = rgb->bits_per_pixel - rgb->transp.length - rgb->transp.offset;
	278
	279	ipu_ch_param_write_field(ch, IPU_FIELD_WID0, rgb->red.length - 1);
	280	ipu_ch_param_write_field(ch, IPU_FIELD_OFS0, ro);
	281	ipu_ch_param_write_field(ch, IPU_FIELD_WID1, rgb->green.length - 1);
	282	ipu_ch_param_write_field(ch, IPU_FIELD_OFS1, go);
	283	ipu_ch_param_write_field(ch, IPU_FIELD_WID2, rgb->blue.length - 1);
	284	ipu_ch_param_write_field(ch, IPU_FIELD_OFS2, bo);
	285
	286	if (rgb->transp.length) {
	287	ipu_ch_param_write_field(ch, IPU_FIELD_WID3,
	288	rgb->transp.length - 1);
	289	ipu_ch_param_write_field(ch, IPU_FIELD_OFS3, to);
	290	} else {
	291	ipu_ch_param_write_field(ch, IPU_FIELD_WID3, 7);
	292	ipu_ch_param_write_field(ch, IPU_FIELD_OFS3,
	293	rgb->bits_per_pixel);
	294	}
	295
	296	switch (rgb->bits_per_pixel) {
	297	case 32:
	298	bpp = 0;
	299	npb = 15;
	300	break;
	301	case 24:
	302	bpp = 1;
	303	npb = 19;
	304	break;
	305	case 16:
	306	bpp = 3;
	307	npb = 31;
	308	break;
	309	case 8:
	310	bpp = 5;
	311	npb = 63;
	312	break;
	313	default:
	314	return -EINVAL;
	315	}
	316	ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp);
	317	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb);
	318	ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 7); /* rgb mode */
	319
	320	return 0;
	321	}
	322	EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_rgb);
	323
	324	int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width)
	325	{
	326	int bpp = 0, npb = 0;
	327
	328	switch (width) {
	329	case 32:
	330	bpp = 0;
	331	npb = 15;
	332	break;
333	case 24:
334	bpp = 1;
335	npb = 19;
336	break;
337	case 16:
338	bpp = 3;
339	npb = 31;
340	break;
341	case 8:
342	bpp = 5;
343	npb = 63;
344	break;
345	default:
346	return -EINVAL;
347	}
348
349	ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp);
350	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb);
351	ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 6); /* raw mode */
352
353	return 0;
354	}
355	EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_passthrough);
356
357	void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format)
358	{
359	switch (pixel_format) {
360	case V4L2_PIX_FMT_UYVY:
361	ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */
362	ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA);/* pix fmt */
363	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */
364	break;
365	case V4L2_PIX_FMT_YUYV:
366	ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */
367	ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8);/* pix fmt */
368	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */
369	break;
370	}
371	}
372	EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_interleaved);
373
374	void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
375	u32 pixel_format, int stride,
376	int u_offset, int v_offset)
377	{
378	switch (pixel_format) {
379	case V4L2_PIX_FMT_YUV420:
380	ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1);
381	ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8);
382	ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8);
383	break;
384	case V4L2_PIX_FMT_YVU420:
385	ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1);
386	ipu_ch_param_write_field(ch, IPU_FIELD_UBO, v_offset / 8);
387	ipu_ch_param_write_field(ch, IPU_FIELD_VBO, u_offset / 8);
388	break;
389	}
390	}
391	EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full);
392
393	void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
394	u32 pixel_format, int stride, int height)
395	{
396	int u_offset, v_offset;
397	int uv_stride = 0;
398
399	switch (pixel_format) {
400	case V4L2_PIX_FMT_YUV420:
401	case V4L2_PIX_FMT_YVU420:
402	uv_stride = stride / 2;
403	u_offset = stride * height;
404	v_offset = u_offset + (uv_stride * height / 2);
405	ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride,
406	u_offset, v_offset);
407	break;
408	}
409	}
410	EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar);
411
412	static const struct ipu_rgb def_rgb_32 = {
413	.red = { .offset = 16, .length = 8, },
414	.green = { .offset = 8, .length = 8, },
415	.blue = { .offset = 0, .length = 8, },
416	.transp = { .offset = 24, .length = 8, },
417	.bits_per_pixel = 32,
418	};
419
420	static const struct ipu_rgb def_bgr_32 = {
421	.red = { .offset = 0, .length = 8, },
422	.green = { .offset = 8, .length = 8, },
423	.blue = { .offset = 16, .length = 8, },
424	.transp = { .offset = 24, .length = 8, },
425	.bits_per_pixel = 32,
426	};
427
428	static const struct ipu_rgb def_rgb_24 = {
429	.red = { .offset = 16, .length = 8, },
430	.green = { .offset = 8, .length = 8, },
431	.blue = { .offset = 0, .length = 8, },
432	.transp = { .offset = 0, .length = 0, },
433	.bits_per_pixel = 24,
434	};
435
436	static const struct ipu_rgb def_bgr_24 = {
437	.red = { .offset = 0, .length = 8, },
438	.green = { .offset = 8, .length = 8, },
439	.blue = { .offset = 16, .length = 8, },
440	.transp = { .offset = 0, .length = 0, },
441	.bits_per_pixel = 24,
442	};
443
444	static const struct ipu_rgb def_rgb_16 = {
445	.red = { .offset = 11, .length = 5, },
446	.green = { .offset = 5, .length = 6, },
447	.blue = { .offset = 0, .length = 5, },
448	.transp = { .offset = 0, .length = 0, },
449	.bits_per_pixel = 16,
450	};
451
452	static const struct ipu_rgb def_bgr_16 = {
453	.red = { .offset = 0, .length = 5, },
454	.green = { .offset = 5, .length = 6, },
455	.blue = { .offset = 11, .length = 5, },
456	.transp = { .offset = 0, .length = 0, },
457	.bits_per_pixel = 16,
458	};
459
460	#define Y_OFFSET(pix, x, y) ((x) + pix->width * (y))
461	#define U_OFFSET(pix, x, y) ((pix->width * pix->height) + \
462	(pix->width * (y) / 4) + (x) / 2)
463	#define V_OFFSET(pix, x, y) ((pix->width * pix->height) + \
464	(pix->width * pix->height / 4) + \
465	(pix->width * (y) / 4) + (x) / 2)
466
467	int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc)
468	{
469	switch (drm_fourcc) {
470	case DRM_FORMAT_YUV420:
471	case DRM_FORMAT_YVU420:
472	/* pix format */
473	ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 2);
474	/* burst size */
475	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
476	break;
477	case DRM_FORMAT_UYVY:
478	/* bits/pixel */
479	ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3);
480	/* pix format */
481	ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA);
482	/* burst size */
483	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
484	break;
485	case DRM_FORMAT_YUYV:
486	/* bits/pixel */
487	ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3);
488	/* pix format */
489	ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8);
490	/* burst size */
491	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
492	break;
493	case DRM_FORMAT_ABGR8888:
494	case DRM_FORMAT_XBGR8888:
495	ipu_cpmem_set_format_rgb(ch, &def_bgr_32);
496	break;
497	case DRM_FORMAT_ARGB8888:
498	case DRM_FORMAT_XRGB8888:
499	ipu_cpmem_set_format_rgb(ch, &def_rgb_32);
500	break;
501	case DRM_FORMAT_BGR888:
502	ipu_cpmem_set_format_rgb(ch, &def_bgr_24);
503	break;
504	case DRM_FORMAT_RGB888:
505	ipu_cpmem_set_format_rgb(ch, &def_rgb_24);
506	break;
507	case DRM_FORMAT_RGB565:
508	ipu_cpmem_set_format_rgb(ch, &def_rgb_16);
509	break;
510	case DRM_FORMAT_BGR565:
511	ipu_cpmem_set_format_rgb(ch, &def_bgr_16);
512	break;
513	default:
514	return -EINVAL;
515	}
516
517	return 0;
518	}
519	EXPORT_SYMBOL_GPL(ipu_cpmem_set_fmt);
520
521	int ipu_cpmem_set_image(struct ipuv3_channel ch, struct ipu_image image)
522	{
523	struct v4l2_pix_format *pix = &image->pix;
524	int y_offset, u_offset, v_offset;
525
526	pr_debug("%s: resolution: %dx%d stride: %d\n",
527	__func__, pix->width, pix->height,
528	pix->bytesperline);
529
530	ipu_cpmem_set_resolution(ch, image->rect.width, image->rect.height);
531	ipu_cpmem_set_stride(ch, pix->bytesperline);
532
533	ipu_cpmem_set_fmt(ch, v4l2_pix_fmt_to_drm_fourcc(pix->pixelformat));
534
535	switch (pix->pixelformat) {
536	case V4L2_PIX_FMT_YUV420:
537	case V4L2_PIX_FMT_YVU420:
538	y_offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
539	u_offset = U_OFFSET(pix, image->rect.left,
540	image->rect.top) - y_offset;
541	v_offset = V_OFFSET(pix, image->rect.left,
542	image->rect.top) - y_offset;
543
544	ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat,
545	pix->bytesperline, u_offset, v_offset);
546	ipu_cpmem_set_buffer(ch, 0, image->phys + y_offset);
547	break;
548	case V4L2_PIX_FMT_UYVY:
549	case V4L2_PIX_FMT_YUYV:
550	ipu_cpmem_set_buffer(ch, 0, image->phys +
551	image->rect.left * 2 +
552	image->rect.top * image->pix.bytesperline);
553	break;
554	case V4L2_PIX_FMT_RGB32:
555	case V4L2_PIX_FMT_BGR32:
556	ipu_cpmem_set_buffer(ch, 0, image->phys +
557	image->rect.left * 4 +
558	image->rect.top * image->pix.bytesperline);
559	break;
560	case V4L2_PIX_FMT_RGB565:
561	ipu_cpmem_set_buffer(ch, 0, image->phys +
562	image->rect.left * 2 +
563	image->rect.top * image->pix.bytesperline);
564	break;
565	case V4L2_PIX_FMT_RGB24:
566	case V4L2_PIX_FMT_BGR24:
567	ipu_cpmem_set_buffer(ch, 0, image->phys +
568	image->rect.left * 3 +
569	image->rect.top * image->pix.bytesperline);
570	break;
571	default:
572	return -EINVAL;
573	}
574
575	return 0;
576	}
577	EXPORT_SYMBOL_GPL(ipu_cpmem_set_image);
578
579	int ipu_cpmem_init(struct ipu_soc ipu, struct device dev, unsigned long base)
580	{
581	struct ipu_cpmem *cpmem;
582
583	cpmem = devm_kzalloc(dev, sizeof(*cpmem), GFP_KERNEL);
584	if (!cpmem)
585	return -ENOMEM;
586
587	ipu->cpmem_priv = cpmem;
588
589	spin_lock_init(&cpmem->lock);
590	cpmem->base = devm_ioremap(dev, base, SZ_128K);
591	if (!cpmem->base)
592	return -ENOMEM;
593
594	dev_dbg(dev, "CPMEM base: 0x%08lx remapped to %p\n",
595	base, cpmem->base);
596	cpmem->ipu = ipu;
597
598	return 0;
599	}
600
601	void ipu_cpmem_exit(struct ipu_soc *ipu)
602	{
603	}