[deliverable/linux.git] / drivers / gpu / ipu-v3 / ipu-dc.c

/*
 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 */

#include <linux/export.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>

#include <video/imx-ipu-v3.h>
#include "ipu-prv.h"

#define DC_MAP_CONF_PTR(n)	(0x108 + ((n) & ~0x1) * 2)
#define DC_MAP_CONF_VAL(n)	(0x144 + ((n) & ~0x1) * 2)

#define DC_EVT_NF		0
#define DC_EVT_NL		1
#define DC_EVT_EOF		2
#define DC_EVT_NFIELD		3
#define DC_EVT_EOL		4
#define DC_EVT_EOFIELD		5
#define DC_EVT_NEW_ADDR		6
#define DC_EVT_NEW_CHAN		7
#define DC_EVT_NEW_DATA		8

#define DC_EVT_NEW_ADDR_W_0	0
#define DC_EVT_NEW_ADDR_W_1	1
#define DC_EVT_NEW_CHAN_W_0	2
#define DC_EVT_NEW_CHAN_W_1	3
#define DC_EVT_NEW_DATA_W_0	4
#define DC_EVT_NEW_DATA_W_1	5
#define DC_EVT_NEW_ADDR_R_0	6
#define DC_EVT_NEW_ADDR_R_1	7
#define DC_EVT_NEW_CHAN_R_0	8
#define DC_EVT_NEW_CHAN_R_1	9
#define DC_EVT_NEW_DATA_R_0	10
#define DC_EVT_NEW_DATA_R_1	11

#define DC_WR_CH_CONF		0x0
#define DC_WR_CH_ADDR		0x4
#define DC_RL_CH(evt)		(8 + ((evt) & ~0x1) * 2)

#define DC_GEN			0xd4
#define DC_DISP_CONF1(disp)	(0xd8 + (disp) * 4)
#define DC_DISP_CONF2(disp)	(0xe8 + (disp) * 4)
#define DC_STAT			0x1c8

#define WROD(lf)		(0x18 | ((lf) << 1))
#define WRG			0x01
#define WCLK			0xc9

#define SYNC_WAVE 0
#define NULL_WAVE (-1)

#define DC_GEN_SYNC_1_6_SYNC	(2 << 1)
#define DC_GEN_SYNC_PRIORITY_1	(1 << 7)

#define DC_WR_CH_CONF_WORD_SIZE_8		(0 << 0)
#define DC_WR_CH_CONF_WORD_SIZE_16		(1 << 0)
#define DC_WR_CH_CONF_WORD_SIZE_24		(2 << 0)
#define DC_WR_CH_CONF_WORD_SIZE_32		(3 << 0)
#define DC_WR_CH_CONF_DISP_ID_PARALLEL(i)	(((i) & 0x1) << 3)
#define DC_WR_CH_CONF_DISP_ID_SERIAL		(2 << 3)
#define DC_WR_CH_CONF_DISP_ID_ASYNC		(3 << 4)
#define DC_WR_CH_CONF_FIELD_MODE		(1 << 9)
#define DC_WR_CH_CONF_PROG_TYPE_NORMAL		(4 << 5)
#define DC_WR_CH_CONF_PROG_TYPE_MASK		(7 << 5)
#define DC_WR_CH_CONF_PROG_DI_ID		(1 << 2)
#define DC_WR_CH_CONF_PROG_DISP_ID(i)		(((i) & 0x1) << 3)

#define IPU_DC_NUM_CHANNELS	10

struct ipu_dc_priv;

enum ipu_dc_map {
	IPU_DC_MAP_RGB24,
	IPU_DC_MAP_RGB565,
	IPU_DC_MAP_GBR24, /* TVEv2 */
	IPU_DC_MAP_BGR666,
	IPU_DC_MAP_LVDS666,
	IPU_DC_MAP_BGR24,
};

struct ipu_dc {
	/* The display interface number assigned to this dc channel */
	unsigned int		di;
	void __iomem		*base;
	struct ipu_dc_priv	*priv;
	int			chno;
	bool			in_use;
};

struct ipu_dc_priv {
	void __iomem		*dc_reg;
	void __iomem		*dc_tmpl_reg;
	struct ipu_soc		*ipu;
	struct device		*dev;
	struct ipu_dc		channels[IPU_DC_NUM_CHANNELS];
	struct mutex		mutex;
	struct completion	comp;
	int			dc_irq;
	int			dp_irq;
	int			use_count;
};

static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
{
	u32 reg;

	reg = readl(dc->base + DC_RL_CH(event));
	reg &= ~(0xffff << (16 * (event & 0x1)));
	reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
	writel(reg, dc->base + DC_RL_CH(event));
}

static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
		int map, int wave, int glue, int sync, int stop)
{
	struct ipu_dc_priv *priv = dc->priv;
	u32 reg1, reg2;

	if (opcode == WCLK) {
		reg1 = (operand << 20) & 0xfff00000;
		reg2 = operand >> 12 | opcode << 1 | stop << 9;
	} else if (opcode == WRG) {
		reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000);
		reg2 = operand >> 17 | opcode << 7 | stop << 9;
	} else {
		reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000);
		reg2 = operand >> 12 | opcode << 4 | stop << 9;
	}
	writel(reg1, priv->dc_tmpl_reg + word * 8);
	writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
}

static int ipu_bus_format_to_map(u32 fmt)
{
	switch (fmt) {
	case MEDIA_BUS_FMT_RGB888_1X24:
		return IPU_DC_MAP_RGB24;
	case MEDIA_BUS_FMT_RGB565_1X16:
		return IPU_DC_MAP_RGB565;
	case MEDIA_BUS_FMT_GBR888_1X24:
		return IPU_DC_MAP_GBR24;
	case MEDIA_BUS_FMT_RGB666_1X18:
		return IPU_DC_MAP_BGR666;
	case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
		return IPU_DC_MAP_LVDS666;
	case MEDIA_BUS_FMT_BGR888_1X24:
		return IPU_DC_MAP_BGR24;
	default:
		return -EINVAL;
	}
}

int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
		u32 bus_format, u32 width)
{
	struct ipu_dc_priv *priv = dc->priv;
	int addr, sync;
	u32 reg = 0;
	int map;

	dc->di = ipu_di_get_num(di);

	map = ipu_bus_format_to_map(bus_format);
	if (map < 0) {
		dev_dbg(priv->dev, "IPU_DISP: No MAP\n");
		return map;
	}

	/*
	 * In interlaced mode we need more counters to create the asymmetric
	 * per-field VSYNC signals. The pixel active signal synchronising DC
	 * to DI moves to signal generator #6 (see ipu-di.c). In progressive
	 * mode counter #5 is used.
	 */
	sync = interlaced ? 6 : 5;

	/* Reserve 5 microcode template words for each DI */
	if (dc->di)
		addr = 5;
	else
		addr = 0;

	if (interlaced) {
		dc_link_event(dc, DC_EVT_NL, addr, 3);
		dc_link_event(dc, DC_EVT_EOL, addr, 2);
		dc_link_event(dc, DC_EVT_NEW_DATA, addr, 1);

		/* Init template microcode */
		dc_write_tmpl(dc, addr, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);
	} else {
		dc_link_event(dc, DC_EVT_NL, addr + 2, 3);
		dc_link_event(dc, DC_EVT_EOL, addr + 3, 2);
		dc_link_event(dc, DC_EVT_NEW_DATA, addr + 1, 1);

		/* Init template microcode */
		dc_write_tmpl(dc, addr + 2, WROD(0), 0, map, SYNC_WAVE, 8, sync, 1);
		dc_write_tmpl(dc, addr + 3, WROD(0), 0, map, SYNC_WAVE, 4, sync, 0);
		dc_write_tmpl(dc, addr + 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
		dc_write_tmpl(dc, addr + 1, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);
	}

	dc_link_event(dc, DC_EVT_NF, 0, 0);
	dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
	dc_link_event(dc, DC_EVT_EOF, 0, 0);
	dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
	dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
	dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);

	reg = readl(dc->base + DC_WR_CH_CONF);
	if (interlaced)
		reg |= DC_WR_CH_CONF_FIELD_MODE;
	else
		reg &= ~DC_WR_CH_CONF_FIELD_MODE;
	writel(reg, dc->base + DC_WR_CH_CONF);

	writel(0x0, dc->base + DC_WR_CH_ADDR);
	writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));

	return 0;
}
EXPORT_SYMBOL_GPL(ipu_dc_init_sync);

void ipu_dc_enable(struct ipu_soc *ipu)
{
	struct ipu_dc_priv *priv = ipu->dc_priv;

	mutex_lock(&priv->mutex);

	if (!priv->use_count)
		ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);

	priv->use_count++;

	mutex_unlock(&priv->mutex);
}
EXPORT_SYMBOL_GPL(ipu_dc_enable);

void ipu_dc_enable_channel(struct ipu_dc *dc)
{
	int di;
	u32 reg;

	di = dc->di;

	reg = readl(dc->base + DC_WR_CH_CONF);
	reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
	writel(reg, dc->base + DC_WR_CH_CONF);
}
EXPORT_SYMBOL_GPL(ipu_dc_enable_channel);

static irqreturn_t dc_irq_handler(int irq, void *dev_id)
{
	struct ipu_dc *dc = dev_id;
	u32 reg;

	reg = readl(dc->base + DC_WR_CH_CONF);
	reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
	writel(reg, dc->base + DC_WR_CH_CONF);

	/* The Freescale BSP kernel clears DIx_COUNTER_RELEASE here */

	complete(&dc->priv->comp);
	return IRQ_HANDLED;
}

void ipu_dc_disable_channel(struct ipu_dc *dc)
{
	struct ipu_dc_priv *priv = dc->priv;
	int irq;
	unsigned long ret;
	u32 val;

	/* TODO: Handle MEM_FG_SYNC differently from MEM_BG_SYNC */
	if (dc->chno == 1)
		irq = priv->dc_irq;
	else if (dc->chno == 5)
		irq = priv->dp_irq;
	else
		return;

	init_completion(&priv->comp);
	enable_irq(irq);
	ret = wait_for_completion_timeout(&priv->comp, msecs_to_jiffies(50));
	disable_irq(irq);
	if (ret == 0) {
		dev_warn(priv->dev, "DC stop timeout after 50 ms\n");

		val = readl(dc->base + DC_WR_CH_CONF);
		val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
		writel(val, dc->base + DC_WR_CH_CONF);
	}
}
EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);

void ipu_dc_disable(struct ipu_soc *ipu)
{
	struct ipu_dc_priv *priv = ipu->dc_priv;

	mutex_lock(&priv->mutex);

	priv->use_count--;
	if (!priv->use_count)
		ipu_module_disable(priv->ipu, IPU_CONF_DC_EN);

	if (priv->use_count < 0)
		priv->use_count = 0;

	mutex_unlock(&priv->mutex);
}
EXPORT_SYMBOL_GPL(ipu_dc_disable);

static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
		int byte_num, int offset, int mask)
{
	int ptr = map * 3 + byte_num;
	u32 reg;

	reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
	reg &= ~(0xffff << (16 * (ptr & 0x1)));
	reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
	writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));

	reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
	reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));
	reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
	writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
}

static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map)
{
	u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));

	writel(reg & ~(0xffff << (16 * (map & 0x1))),
		     priv->dc_reg + DC_MAP_CONF_PTR(map));
}

struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel)
{
	struct ipu_dc_priv *priv = ipu->dc_priv;
	struct ipu_dc *dc;

	if (channel >= IPU_DC_NUM_CHANNELS)
		return ERR_PTR(-ENODEV);

	dc = &priv->channels[channel];

	mutex_lock(&priv->mutex);

	if (dc->in_use) {
		mutex_unlock(&priv->mutex);
		return ERR_PTR(-EBUSY);
	}

	dc->in_use = true;

	mutex_unlock(&priv->mutex);

	return dc;
}
EXPORT_SYMBOL_GPL(ipu_dc_get);

void ipu_dc_put(struct ipu_dc *dc)
{
	struct ipu_dc_priv *priv = dc->priv;

	mutex_lock(&priv->mutex);
	dc->in_use = false;
	mutex_unlock(&priv->mutex);
}
EXPORT_SYMBOL_GPL(ipu_dc_put);

int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
		unsigned long base, unsigned long template_base)
{
	struct ipu_dc_priv *priv;
	static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c,
		0x78, 0, 0x94, 0xb4};
	int i, ret;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	mutex_init(&priv->mutex);

	priv->dev = dev;
	priv->ipu = ipu;
	priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE);
	priv->dc_tmpl_reg = devm_ioremap(dev, template_base, PAGE_SIZE);
	if (!priv->dc_reg || !priv->dc_tmpl_reg)
		return -ENOMEM;

	for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) {
		priv->channels[i].chno = i;
		priv->channels[i].priv = priv;
		priv->channels[i].base = priv->dc_reg + channel_offsets[i];
	}

	priv->dc_irq = ipu_map_irq(ipu, IPU_IRQ_DC_FC_1);
	if (!priv->dc_irq)
		return -EINVAL;
	ret = devm_request_irq(dev, priv->dc_irq, dc_irq_handler, 0, NULL,
			       &priv->channels[1]);
	if (ret < 0)
		return ret;
	disable_irq(priv->dc_irq);
	priv->dp_irq = ipu_map_irq(ipu, IPU_IRQ_DP_SF_END);
	if (!priv->dp_irq)
		return -EINVAL;
	ret = devm_request_irq(dev, priv->dp_irq, dc_irq_handler, 0, NULL,
			       &priv->channels[5]);
	if (ret < 0)
		return ret;
	disable_irq(priv->dp_irq);

	writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(1) |
			DC_WR_CH_CONF_PROG_DI_ID,
			priv->channels[1].base + DC_WR_CH_CONF);
	writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(0),
			priv->channels[5].base + DC_WR_CH_CONF);

	writel(DC_GEN_SYNC_1_6_SYNC | DC_GEN_SYNC_PRIORITY_1,
		priv->dc_reg + DC_GEN);

	ipu->dc_priv = priv;

	dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",
			base, template_base);

	/* rgb24 */
	ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24);
	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */
	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */
	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */

	/* rgb565 */
	ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565);
	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */
	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */
	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */

	/* gbr24 */
	ipu_dc_map_clear(priv, IPU_DC_MAP_GBR24);
	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */
	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */
	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */

	/* bgr666 */
	ipu_dc_map_clear(priv, IPU_DC_MAP_BGR666);
	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */
	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */
	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */

	/* lvds666 */
	ipu_dc_map_clear(priv, IPU_DC_MAP_LVDS666);
	ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 0, 5, 0xfc); /* blue */
	ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 1, 13, 0xfc); /* green */
	ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 2, 21, 0xfc); /* red */

	/* bgr24 */
	ipu_dc_map_clear(priv, IPU_DC_MAP_BGR24);
	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 2, 7, 0xff); /* red */
	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */
	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */

	return 0;
}

void ipu_dc_exit(struct ipu_soc *ipu)
{
}
Commit	Line	Data
aecfbdb1 SH	1	/*
	2	* Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
	3	* Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful, but
	11	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	12	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	13	* for more details.
	14	*/
	15
	16	#include <linux/export.h>
	17	#include <linux/module.h>
	18	#include <linux/types.h>
	19	#include <linux/errno.h>
	20	#include <linux/delay.h>
1dee9a9e	21	#include <linux/interrupt.h>
aecfbdb1 SH	22	#include <linux/io.h>
aecfbdb1 SH	23
39b9004d	24	#include <video/imx-ipu-v3.h>
aecfbdb1 SH	25	#include "ipu-prv.h"
	26
	27	#define DC_MAP_CONF_PTR(n) (0x108 + ((n) & ~0x1) * 2)
	28	#define DC_MAP_CONF_VAL(n) (0x144 + ((n) & ~0x1) * 2)
	29
	30	#define DC_EVT_NF 0
	31	#define DC_EVT_NL 1
	32	#define DC_EVT_EOF 2
	33	#define DC_EVT_NFIELD 3
	34	#define DC_EVT_EOL 4
	35	#define DC_EVT_EOFIELD 5
	36	#define DC_EVT_NEW_ADDR 6
	37	#define DC_EVT_NEW_CHAN 7
	38	#define DC_EVT_NEW_DATA 8
	39
	40	#define DC_EVT_NEW_ADDR_W_0 0
	41	#define DC_EVT_NEW_ADDR_W_1 1
	42	#define DC_EVT_NEW_CHAN_W_0 2
	43	#define DC_EVT_NEW_CHAN_W_1 3
	44	#define DC_EVT_NEW_DATA_W_0 4
	45	#define DC_EVT_NEW_DATA_W_1 5
	46	#define DC_EVT_NEW_ADDR_R_0 6
	47	#define DC_EVT_NEW_ADDR_R_1 7
	48	#define DC_EVT_NEW_CHAN_R_0 8
	49	#define DC_EVT_NEW_CHAN_R_1 9
	50	#define DC_EVT_NEW_DATA_R_0 10
	51	#define DC_EVT_NEW_DATA_R_1 11
	52
	53	#define DC_WR_CH_CONF 0x0
	54	#define DC_WR_CH_ADDR 0x4
	55	#define DC_RL_CH(evt) (8 + ((evt) & ~0x1) * 2)
	56
	57	#define DC_GEN 0xd4
	58	#define DC_DISP_CONF1(disp) (0xd8 + (disp) * 4)
	59	#define DC_DISP_CONF2(disp) (0xe8 + (disp) * 4)
	60	#define DC_STAT 0x1c8
	61
	62	#define WROD(lf) (0x18 \| ((lf) << 1))
	63	#define WRG 0x01
85eacb06	64	#define WCLK 0xc9
aecfbdb1 SH	65
aecfbdb1 SH	66	#define SYNC_WAVE 0
85eacb06	67	#define NULL_WAVE (-1)
aecfbdb1 SH	68
	69	#define DC_GEN_SYNC_1_6_SYNC (2 << 1)
	70	#define DC_GEN_SYNC_PRIORITY_1 (1 << 7)
	71
	72	#define DC_WR_CH_CONF_WORD_SIZE_8 (0 << 0)
	73	#define DC_WR_CH_CONF_WORD_SIZE_16 (1 << 0)
	74	#define DC_WR_CH_CONF_WORD_SIZE_24 (2 << 0)
	75	#define DC_WR_CH_CONF_WORD_SIZE_32 (3 << 0)
	76	#define DC_WR_CH_CONF_DISP_ID_PARALLEL(i) (((i) & 0x1) << 3)
	77	#define DC_WR_CH_CONF_DISP_ID_SERIAL (2 << 3)
	78	#define DC_WR_CH_CONF_DISP_ID_ASYNC (3 << 4)
	79	#define DC_WR_CH_CONF_FIELD_MODE (1 << 9)
	80	#define DC_WR_CH_CONF_PROG_TYPE_NORMAL (4 << 5)
	81	#define DC_WR_CH_CONF_PROG_TYPE_MASK (7 << 5)
	82	#define DC_WR_CH_CONF_PROG_DI_ID (1 << 2)
	83	#define DC_WR_CH_CONF_PROG_DISP_ID(i) (((i) & 0x1) << 3)
	84
	85	#define IPU_DC_NUM_CHANNELS 10
	86
	87	struct ipu_dc_priv;
	88
	89	enum ipu_dc_map {
	90	IPU_DC_MAP_RGB24,
	91	IPU_DC_MAP_RGB565,
eeb14ec8	92	IPU_DC_MAP_GBR24, /* TVEv2 */
7d0a66c0	93	IPU_DC_MAP_BGR666,
9e74d292	94	IPU_DC_MAP_LVDS666,
0b186416	95	IPU_DC_MAP_BGR24,
aecfbdb1 SH	96	};
	97
	98	struct ipu_dc {
	99	/* The display interface number assigned to this dc channel */
	100	unsigned int di;
	101	void __iomem *base;
	102	struct ipu_dc_priv *priv;
	103	int chno;
	104	bool in_use;
	105	};
	106
	107	struct ipu_dc_priv {
	108	void __iomem *dc_reg;
	109	void __iomem *dc_tmpl_reg;
	110	struct ipu_soc *ipu;
	111	struct device *dev;
	112	struct ipu_dc channels[IPU_DC_NUM_CHANNELS];
	113	struct mutex mutex;
1dee9a9e PZ	114	struct completion comp;
	115	int dc_irq;
	116	int dp_irq;
f853f3da	117	int use_count;
aecfbdb1 SH	118	};
	119
	120	static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
	121	{
	122	u32 reg;
	123
	124	reg = readl(dc->base + DC_RL_CH(event));
	125	reg &= ~(0xffff << (16 * (event & 0x1)));
	126	reg \|= ((addr << 8) \| priority) << (16 * (event & 0x1));
	127	writel(reg, dc->base + DC_RL_CH(event));
	128	}
	129
	130	static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
85eacb06	131	int map, int wave, int glue, int sync, int stop)
aecfbdb1 SH	132	{
aecfbdb1 SH	133	struct ipu_dc_priv *priv = dc->priv;
85eacb06 PZ	134	u32 reg1, reg2;
	135
	136	if (opcode == WCLK) {
	137	reg1 = (operand << 20) & 0xfff00000;
	138	reg2 = operand >> 12 \| opcode << 1 \| stop << 9;
	139	} else if (opcode == WRG) {
	140	reg1 = sync \| glue << 4 \| ++wave << 11 \| ((operand << 15) & 0xffff8000);
	141	reg2 = operand >> 17 \| opcode << 7 \| stop << 9;
	142	} else {
	143	reg1 = sync \| glue << 4 \| ++wave << 11 \| ++map << 15 \| ((operand << 20) & 0xfff00000);
	144	reg2 = operand >> 12 \| opcode << 4 \| stop << 9;
	145	}
	146	writel(reg1, priv->dc_tmpl_reg + word * 8);
	147	writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
aecfbdb1 SH	148	}
aecfbdb1 SH	149
a7c6e76f	150	static int ipu_bus_format_to_map(u32 fmt)
aecfbdb1 SH	151	{
aecfbdb1 SH	152	switch (fmt) {
a7c6e76f	153	case MEDIA_BUS_FMT_RGB888_1X24:
aecfbdb1	154	return IPU_DC_MAP_RGB24;
a7c6e76f	155	case MEDIA_BUS_FMT_RGB565_1X16:
aecfbdb1	156	return IPU_DC_MAP_RGB565;
a7c6e76f	157	case MEDIA_BUS_FMT_GBR888_1X24:
eeb14ec8	158	return IPU_DC_MAP_GBR24;
a7c6e76f	159	case MEDIA_BUS_FMT_RGB666_1X18:
7d0a66c0	160	return IPU_DC_MAP_BGR666;
a7c6e76f	161	case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
9e74d292	162	return IPU_DC_MAP_LVDS666;
a7c6e76f	163	case MEDIA_BUS_FMT_BGR888_1X24:
0b186416	164	return IPU_DC_MAP_BGR24;
aecfbdb1 SH	165	default:
	166	return -EINVAL;
	167	}
	168	}
	169
	170	int ipu_dc_init_sync(struct ipu_dc dc, struct ipu_di di, bool interlaced,
2872c807	171	u32 bus_format, u32 width)
aecfbdb1 SH	172	{
aecfbdb1 SH	173	struct ipu_dc_priv *priv = dc->priv;
86bdb09f	174	int addr, sync;
df2da9a3 DC	175	u32 reg = 0;
df2da9a3 DC	176	int map;
aecfbdb1 SH	177
	178	dc->di = ipu_di_get_num(di);
	179
2872c807	180	map = ipu_bus_format_to_map(bus_format);
aecfbdb1 SH	181	if (map < 0) {
aecfbdb1 SH	182	dev_dbg(priv->dev, "IPU_DISP: No MAP\n");
df2da9a3	183	return map;
aecfbdb1 SH	184	}
aecfbdb1 SH	185
86bdb09f PZ	186	/*
	187	* In interlaced mode we need more counters to create the asymmetric
	188	* per-field VSYNC signals. The pixel active signal synchronising DC
	189	* to DI moves to signal generator #6 (see ipu-di.c). In progressive
	190	* mode counter #5 is used.
	191	*/
	192	sync = interlaced ? 6 : 5;
	193
	194	/* Reserve 5 microcode template words for each DI */
	195	if (dc->di)
	196	addr = 5;
	197	else
	198	addr = 0;
aefa627f	199
86bdb09f	200	if (interlaced) {
aefa627f RK	201	dc_link_event(dc, DC_EVT_NL, addr, 3);
	202	dc_link_event(dc, DC_EVT_EOL, addr, 2);
	203	dc_link_event(dc, DC_EVT_NEW_DATA, addr, 1);
aecfbdb1 SH	204
aecfbdb1 SH	205	/* Init template microcode */
86bdb09f	206	dc_write_tmpl(dc, addr, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);
aecfbdb1	207	} else {
86bdb09f PZ	208	dc_link_event(dc, DC_EVT_NL, addr + 2, 3);
	209	dc_link_event(dc, DC_EVT_EOL, addr + 3, 2);
	210	dc_link_event(dc, DC_EVT_NEW_DATA, addr + 1, 1);
	211
	212	/* Init template microcode */
	213	dc_write_tmpl(dc, addr + 2, WROD(0), 0, map, SYNC_WAVE, 8, sync, 1);
	214	dc_write_tmpl(dc, addr + 3, WROD(0), 0, map, SYNC_WAVE, 4, sync, 0);
	215	dc_write_tmpl(dc, addr + 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
	216	dc_write_tmpl(dc, addr + 1, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);
aecfbdb1	217	}
86bdb09f	218
aecfbdb1 SH	219	dc_link_event(dc, DC_EVT_NF, 0, 0);
	220	dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
	221	dc_link_event(dc, DC_EVT_EOF, 0, 0);
	222	dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
	223	dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
	224	dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);
	225
	226	reg = readl(dc->base + DC_WR_CH_CONF);
	227	if (interlaced)
	228	reg \|= DC_WR_CH_CONF_FIELD_MODE;
	229	else
	230	reg &= ~DC_WR_CH_CONF_FIELD_MODE;
	231	writel(reg, dc->base + DC_WR_CH_CONF);
	232
	233	writel(0x0, dc->base + DC_WR_CH_ADDR);
	234	writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));
	235
aecfbdb1 SH	236	return 0;
	237	}
	238	EXPORT_SYMBOL_GPL(ipu_dc_init_sync);
	239
1e6d486b PZ	240	void ipu_dc_enable(struct ipu_soc *ipu)
1e6d486b PZ	241	{
f853f3da SL	242	struct ipu_dc_priv *priv = ipu->dc_priv;
	243
	244	mutex_lock(&priv->mutex);
	245
	246	if (!priv->use_count)
	247	ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);
	248
	249	priv->use_count++;
	250
	251	mutex_unlock(&priv->mutex);
1e6d486b PZ	252	}
	253	EXPORT_SYMBOL_GPL(ipu_dc_enable);
	254
aecfbdb1 SH	255	void ipu_dc_enable_channel(struct ipu_dc *dc)
	256	{
	257	int di;
	258	u32 reg;
	259
	260	di = dc->di;
	261
	262	reg = readl(dc->base + DC_WR_CH_CONF);
	263	reg \|= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
	264	writel(reg, dc->base + DC_WR_CH_CONF);
	265	}
	266	EXPORT_SYMBOL_GPL(ipu_dc_enable_channel);
	267
1dee9a9e PZ	268	static irqreturn_t dc_irq_handler(int irq, void *dev_id)
	269	{
	270	struct ipu_dc *dc = dev_id;
	271	u32 reg;
	272
	273	reg = readl(dc->base + DC_WR_CH_CONF);
	274	reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
	275	writel(reg, dc->base + DC_WR_CH_CONF);
	276
	277	/* The Freescale BSP kernel clears DIx_COUNTER_RELEASE here */
	278
	279	complete(&dc->priv->comp);
	280	return IRQ_HANDLED;
	281	}
	282
aecfbdb1 SH	283	void ipu_dc_disable_channel(struct ipu_dc *dc)
	284	{
	285	struct ipu_dc_priv *priv = dc->priv;
af7537d3 NMG	286	int irq;
af7537d3 NMG	287	unsigned long ret;
aecfbdb1	288	u32 val;
aecfbdb1	289
1dee9a9e	290	/* TODO: Handle MEM_FG_SYNC differently from MEM_BG_SYNC */
aecfbdb1	291	if (dc->chno == 1)
1dee9a9e	292	irq = priv->dc_irq;
aecfbdb1	293	else if (dc->chno == 5)
1dee9a9e	294	irq = priv->dp_irq;
aecfbdb1 SH	295	else
	296	return;
	297
1dee9a9e PZ	298	init_completion(&priv->comp);
	299	enable_irq(irq);
	300	ret = wait_for_completion_timeout(&priv->comp, msecs_to_jiffies(50));
	301	disable_irq(irq);
af7537d3	302	if (ret == 0) {
1dee9a9e	303	dev_warn(priv->dev, "DC stop timeout after 50 ms\n");
aecfbdb1	304
1dee9a9e PZ	305	val = readl(dc->base + DC_WR_CH_CONF);
	306	val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
	307	writel(val, dc->base + DC_WR_CH_CONF);
aecfbdb1	308	}
aecfbdb1 SH	309	}
	310	EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);
	311
1e6d486b PZ	312	void ipu_dc_disable(struct ipu_soc *ipu)
1e6d486b PZ	313	{
f853f3da SL	314	struct ipu_dc_priv *priv = ipu->dc_priv;
	315
	316	mutex_lock(&priv->mutex);
	317
	318	priv->use_count--;
	319	if (!priv->use_count)
	320	ipu_module_disable(priv->ipu, IPU_CONF_DC_EN);
	321
	322	if (priv->use_count < 0)
	323	priv->use_count = 0;
	324
	325	mutex_unlock(&priv->mutex);
1e6d486b PZ	326	}
	327	EXPORT_SYMBOL_GPL(ipu_dc_disable);
	328
aecfbdb1 SH	329	static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
	330	int byte_num, int offset, int mask)
	331	{
	332	int ptr = map * 3 + byte_num;
	333	u32 reg;
	334
	335	reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
	336	reg &= ~(0xffff << (16 * (ptr & 0x1)));
	337	reg \|= ((offset << 8) \| mask) << (16 * (ptr & 0x1));
	338	writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));
	339
	340	reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
	341	reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));
	342	reg \|= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
	343	writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
	344	}
	345
	346	static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map)
	347	{
	348	u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
	349
	350	writel(reg & ~(0xffff << (16 * (map & 0x1))),
	351	priv->dc_reg + DC_MAP_CONF_PTR(map));
	352	}
	353
	354	struct ipu_dc ipu_dc_get(struct ipu_soc ipu, int channel)
	355	{
	356	struct ipu_dc_priv *priv = ipu->dc_priv;
	357	struct ipu_dc *dc;
	358
	359	if (channel >= IPU_DC_NUM_CHANNELS)
	360	return ERR_PTR(-ENODEV);
	361
	362	dc = &priv->channels[channel];
	363
	364	mutex_lock(&priv->mutex);
	365
	366	if (dc->in_use) {
	367	mutex_unlock(&priv->mutex);
	368	return ERR_PTR(-EBUSY);
	369	}
	370
89bc5be7	371	dc->in_use = true;
aecfbdb1 SH	372
	373	mutex_unlock(&priv->mutex);
	374
	375	return dc;
	376	}
	377	EXPORT_SYMBOL_GPL(ipu_dc_get);
	378
	379	void ipu_dc_put(struct ipu_dc *dc)
	380	{
	381	struct ipu_dc_priv *priv = dc->priv;
	382
	383	mutex_lock(&priv->mutex);
89bc5be7	384	dc->in_use = false;
aecfbdb1 SH	385	mutex_unlock(&priv->mutex);
	386	}
	387	EXPORT_SYMBOL_GPL(ipu_dc_put);
	388
	389	int ipu_dc_init(struct ipu_soc ipu, struct device dev,
	390	unsigned long base, unsigned long template_base)
	391	{
	392	struct ipu_dc_priv *priv;
	393	static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c,
	394	0x78, 0, 0x94, 0xb4};
1dee9a9e	395	int i, ret;
aecfbdb1 SH	396
	397	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	398	if (!priv)
	399	return -ENOMEM;
	400
	401	mutex_init(&priv->mutex);
	402
	403	priv->dev = dev;
	404	priv->ipu = ipu;
	405	priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE);
	406	priv->dc_tmpl_reg = devm_ioremap(dev, template_base, PAGE_SIZE);
	407	if (!priv->dc_reg \|\| !priv->dc_tmpl_reg)
	408	return -ENOMEM;
	409
	410	for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) {
	411	priv->channels[i].chno = i;
	412	priv->channels[i].priv = priv;
	413	priv->channels[i].base = priv->dc_reg + channel_offsets[i];
	414	}
	415
1dee9a9e PZ	416	priv->dc_irq = ipu_map_irq(ipu, IPU_IRQ_DC_FC_1);
	417	if (!priv->dc_irq)
	418	return -EINVAL;
	419	ret = devm_request_irq(dev, priv->dc_irq, dc_irq_handler, 0, NULL,
	420	&priv->channels[1]);
	421	if (ret < 0)
	422	return ret;
	423	disable_irq(priv->dc_irq);
	424	priv->dp_irq = ipu_map_irq(ipu, IPU_IRQ_DP_SF_END);
	425	if (!priv->dp_irq)
	426	return -EINVAL;
	427	ret = devm_request_irq(dev, priv->dp_irq, dc_irq_handler, 0, NULL,
	428	&priv->channels[5]);
	429	if (ret < 0)
	430	return ret;
	431	disable_irq(priv->dp_irq);
	432
aecfbdb1 SH	433	writel(DC_WR_CH_CONF_WORD_SIZE_24 \| DC_WR_CH_CONF_DISP_ID_PARALLEL(1) \|
	434	DC_WR_CH_CONF_PROG_DI_ID,
	435	priv->channels[1].base + DC_WR_CH_CONF);
	436	writel(DC_WR_CH_CONF_WORD_SIZE_24 \| DC_WR_CH_CONF_DISP_ID_PARALLEL(0),
	437	priv->channels[5].base + DC_WR_CH_CONF);
	438
838201aa ASC	439	writel(DC_GEN_SYNC_1_6_SYNC \| DC_GEN_SYNC_PRIORITY_1,
838201aa ASC	440	priv->dc_reg + DC_GEN);
aecfbdb1 SH	441
	442	ipu->dc_priv = priv;
	443
	444	dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",
	445	base, template_base);
	446
	447	/* rgb24 */
	448	ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24);
	449	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */
	450	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */
	451	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */
	452
	453	/* rgb565 */
	454	ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565);
	455	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */
	456	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */
	457	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */
	458
eeb14ec8 PZ	459	/* gbr24 */
	460	ipu_dc_map_clear(priv, IPU_DC_MAP_GBR24);
	461	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */
	462	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */
	463	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */
	464
7d0a66c0 MV	465	/* bgr666 */
	466	ipu_dc_map_clear(priv, IPU_DC_MAP_BGR666);
	467	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */
	468	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */
	469	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */
	470
9e74d292 ERB	471	/* lvds666 */
	472	ipu_dc_map_clear(priv, IPU_DC_MAP_LVDS666);
	473	ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 0, 5, 0xfc); /* blue */
	474	ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 1, 13, 0xfc); /* green */
	475	ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 2, 21, 0xfc); /* red */
	476
0b186416 PZ	477	/* bgr24 */
	478	ipu_dc_map_clear(priv, IPU_DC_MAP_BGR24);
	479	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 2, 7, 0xff); /* red */
	480	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */
	481	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */
	482
aecfbdb1 SH	483	return 0;
	484	}
	485
	486	void ipu_dc_exit(struct ipu_soc *ipu)
	487	{
	488	}