[deliverable/linux.git] / drivers / gpu / ipu-v3 / ipu-dmfc.c

/*
 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 */
#include <linux/export.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/io.h>

#include <video/imx-ipu-v3.h>
#include "ipu-prv.h"

#define DMFC_RD_CHAN		0x0000
#define DMFC_WR_CHAN		0x0004
#define DMFC_WR_CHAN_DEF	0x0008
#define DMFC_DP_CHAN		0x000c
#define DMFC_DP_CHAN_DEF	0x0010
#define DMFC_GENERAL1		0x0014
#define DMFC_GENERAL2		0x0018
#define DMFC_IC_CTRL		0x001c
#define DMFC_WR_CHAN_ALT	0x0020
#define DMFC_WR_CHAN_DEF_ALT	0x0024
#define DMFC_DP_CHAN_ALT	0x0028
#define DMFC_DP_CHAN_DEF_ALT	0x002c
#define DMFC_GENERAL1_ALT	0x0030
#define DMFC_STAT		0x0034

#define DMFC_WR_CHAN_1_28		0
#define DMFC_WR_CHAN_2_41		8
#define DMFC_WR_CHAN_1C_42		16
#define DMFC_WR_CHAN_2C_43		24

#define DMFC_DP_CHAN_5B_23		0
#define DMFC_DP_CHAN_5F_27		8
#define DMFC_DP_CHAN_6B_24		16
#define DMFC_DP_CHAN_6F_29		24

struct dmfc_channel_data {
	int		ipu_channel;
	unsigned long	channel_reg;
	unsigned long	shift;
	unsigned	eot_shift;
	unsigned	max_fifo_lines;
};

static const struct dmfc_channel_data dmfcdata[] = {
	{
		.ipu_channel	= IPUV3_CHANNEL_MEM_BG_SYNC,
		.channel_reg	= DMFC_DP_CHAN,
		.shift		= DMFC_DP_CHAN_5B_23,
		.eot_shift	= 20,
		.max_fifo_lines	= 3,
	}, {
		.ipu_channel	= 24,
		.channel_reg	= DMFC_DP_CHAN,
		.shift		= DMFC_DP_CHAN_6B_24,
		.eot_shift	= 22,
		.max_fifo_lines	= 1,
	}, {
		.ipu_channel	= IPUV3_CHANNEL_MEM_FG_SYNC,
		.channel_reg	= DMFC_DP_CHAN,
		.shift		= DMFC_DP_CHAN_5F_27,
		.eot_shift	= 21,
		.max_fifo_lines	= 2,
	}, {
		.ipu_channel	= IPUV3_CHANNEL_MEM_DC_SYNC,
		.channel_reg	= DMFC_WR_CHAN,
		.shift		= DMFC_WR_CHAN_1_28,
		.eot_shift	= 16,
		.max_fifo_lines	= 2,
	}, {
		.ipu_channel	= 29,
		.channel_reg	= DMFC_DP_CHAN,
		.shift		= DMFC_DP_CHAN_6F_29,
		.eot_shift	= 23,
		.max_fifo_lines	= 1,
	},
};

#define DMFC_NUM_CHANNELS	ARRAY_SIZE(dmfcdata)

struct ipu_dmfc_priv;

struct dmfc_channel {
	unsigned			slots;
	struct ipu_soc			*ipu;
	struct ipu_dmfc_priv		*priv;
	const struct dmfc_channel_data	*data;
};

struct ipu_dmfc_priv {
	struct ipu_soc *ipu;
	struct device *dev;
	struct dmfc_channel channels[DMFC_NUM_CHANNELS];
	struct mutex mutex;
	void __iomem *base;
	int use_count;
};

int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc)
{
	struct ipu_dmfc_priv *priv = dmfc->priv;
	mutex_lock(&priv->mutex);

	if (!priv->use_count)
		ipu_module_enable(priv->ipu, IPU_CONF_DMFC_EN);

	priv->use_count++;

	mutex_unlock(&priv->mutex);

	return 0;
}
EXPORT_SYMBOL_GPL(ipu_dmfc_enable_channel);

static void ipu_dmfc_wait_fifos(struct ipu_dmfc_priv *priv)
{
	unsigned long timeout = jiffies + msecs_to_jiffies(1000);

	while ((readl(priv->base + DMFC_STAT) & 0x02fff000) != 0x02fff000) {
		if (time_after(jiffies, timeout)) {
			dev_warn(priv->dev,
				 "Timeout waiting for DMFC FIFOs to clear\n");
			break;
		}
		cpu_relax();
	}
}

void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc)
{
	struct ipu_dmfc_priv *priv = dmfc->priv;

	mutex_lock(&priv->mutex);

	priv->use_count--;

	if (!priv->use_count) {
		ipu_dmfc_wait_fifos(priv);
		ipu_module_disable(priv->ipu, IPU_CONF_DMFC_EN);
	}

	if (priv->use_count < 0)
		priv->use_count = 0;

	mutex_unlock(&priv->mutex);
}
EXPORT_SYMBOL_GPL(ipu_dmfc_disable_channel);

void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width)
{
	struct ipu_dmfc_priv *priv = dmfc->priv;
	u32 dmfc_gen1;

	mutex_lock(&priv->mutex);

	dmfc_gen1 = readl(priv->base + DMFC_GENERAL1);

	if ((dmfc->slots * 64 * 4) / width > dmfc->data->max_fifo_lines)
		dmfc_gen1 |= 1 << dmfc->data->eot_shift;
	else
		dmfc_gen1 &= ~(1 << dmfc->data->eot_shift);

	writel(dmfc_gen1, priv->base + DMFC_GENERAL1);

	mutex_unlock(&priv->mutex);
}
EXPORT_SYMBOL_GPL(ipu_dmfc_config_wait4eot);

struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipu_channel)
{
	struct ipu_dmfc_priv *priv = ipu->dmfc_priv;
	int i;

	for (i = 0; i < DMFC_NUM_CHANNELS; i++)
		if (dmfcdata[i].ipu_channel == ipu_channel)
			return &priv->channels[i];
	return ERR_PTR(-ENODEV);
}
EXPORT_SYMBOL_GPL(ipu_dmfc_get);

void ipu_dmfc_put(struct dmfc_channel *dmfc)
{
}
EXPORT_SYMBOL_GPL(ipu_dmfc_put);

int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
		struct clk *ipu_clk)
{
	struct ipu_dmfc_priv *priv;
	int i;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->base = devm_ioremap(dev, base, PAGE_SIZE);
	if (!priv->base)
		return -ENOMEM;

	priv->dev = dev;
	priv->ipu = ipu;
	mutex_init(&priv->mutex);

	ipu->dmfc_priv = priv;

	for (i = 0; i < DMFC_NUM_CHANNELS; i++) {
		priv->channels[i].priv = priv;
		priv->channels[i].ipu = ipu;
		priv->channels[i].data = &dmfcdata[i];

		if (dmfcdata[i].ipu_channel == IPUV3_CHANNEL_MEM_BG_SYNC ||
		    dmfcdata[i].ipu_channel == IPUV3_CHANNEL_MEM_FG_SYNC ||
		    dmfcdata[i].ipu_channel == IPUV3_CHANNEL_MEM_DC_SYNC)
			priv->channels[i].slots = 2;
	}

	writel(0x00000050, priv->base + DMFC_WR_CHAN);
	writel(0x00005654, priv->base + DMFC_DP_CHAN);
	writel(0x202020f6, priv->base + DMFC_WR_CHAN_DEF);
	writel(0x2020f6f6, priv->base + DMFC_DP_CHAN_DEF);
	writel(0x00000003, priv->base + DMFC_GENERAL1);

	return 0;
}

void ipu_dmfc_exit(struct ipu_soc *ipu)
{
}
Commit	Line	Data
aecfbdb1 SH	1	/*
	2	* Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
	3	* Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful, but
	11	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	12	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	13	* for more details.
	14	*/
	15	#include <linux/export.h>
	16	#include <linux/types.h>
	17	#include <linux/errno.h>
	18	#include <linux/io.h>
	19
39b9004d	20	#include <video/imx-ipu-v3.h>
aecfbdb1 SH	21	#include "ipu-prv.h"
	22
	23	#define DMFC_RD_CHAN 0x0000
	24	#define DMFC_WR_CHAN 0x0004
	25	#define DMFC_WR_CHAN_DEF 0x0008
	26	#define DMFC_DP_CHAN 0x000c
	27	#define DMFC_DP_CHAN_DEF 0x0010
	28	#define DMFC_GENERAL1 0x0014
	29	#define DMFC_GENERAL2 0x0018
	30	#define DMFC_IC_CTRL 0x001c
47348661 PZ	31	#define DMFC_WR_CHAN_ALT 0x0020
	32	#define DMFC_WR_CHAN_DEF_ALT 0x0024
	33	#define DMFC_DP_CHAN_ALT 0x0028
	34	#define DMFC_DP_CHAN_DEF_ALT 0x002c
	35	#define DMFC_GENERAL1_ALT 0x0030
	36	#define DMFC_STAT 0x0034
aecfbdb1 SH	37
	38	#define DMFC_WR_CHAN_1_28 0
	39	#define DMFC_WR_CHAN_2_41 8
	40	#define DMFC_WR_CHAN_1C_42 16
	41	#define DMFC_WR_CHAN_2C_43 24
	42
	43	#define DMFC_DP_CHAN_5B_23 0
	44	#define DMFC_DP_CHAN_5F_27 8
	45	#define DMFC_DP_CHAN_6B_24 16
	46	#define DMFC_DP_CHAN_6F_29 24
	47
aecfbdb1 SH	48	struct dmfc_channel_data {
	49	int ipu_channel;
	50	unsigned long channel_reg;
	51	unsigned long shift;
	52	unsigned eot_shift;
	53	unsigned max_fifo_lines;
	54	};
	55
	56	static const struct dmfc_channel_data dmfcdata[] = {
	57	{
134b87b0	58	.ipu_channel = IPUV3_CHANNEL_MEM_BG_SYNC,
aecfbdb1 SH	59	.channel_reg = DMFC_DP_CHAN,
	60	.shift = DMFC_DP_CHAN_5B_23,
	61	.eot_shift = 20,
	62	.max_fifo_lines = 3,
	63	}, {
	64	.ipu_channel = 24,
	65	.channel_reg = DMFC_DP_CHAN,
	66	.shift = DMFC_DP_CHAN_6B_24,
	67	.eot_shift = 22,
	68	.max_fifo_lines = 1,
	69	}, {
134b87b0	70	.ipu_channel = IPUV3_CHANNEL_MEM_FG_SYNC,
aecfbdb1 SH	71	.channel_reg = DMFC_DP_CHAN,
	72	.shift = DMFC_DP_CHAN_5F_27,
	73	.eot_shift = 21,
	74	.max_fifo_lines = 2,
	75	}, {
134b87b0	76	.ipu_channel = IPUV3_CHANNEL_MEM_DC_SYNC,
aecfbdb1 SH	77	.channel_reg = DMFC_WR_CHAN,
	78	.shift = DMFC_WR_CHAN_1_28,
	79	.eot_shift = 16,
	80	.max_fifo_lines = 2,
	81	}, {
	82	.ipu_channel = 29,
	83	.channel_reg = DMFC_DP_CHAN,
	84	.shift = DMFC_DP_CHAN_6F_29,
	85	.eot_shift = 23,
	86	.max_fifo_lines = 1,
	87	},
	88	};
	89
	90	#define DMFC_NUM_CHANNELS ARRAY_SIZE(dmfcdata)
	91
	92	struct ipu_dmfc_priv;
	93
	94	struct dmfc_channel {
	95	unsigned slots;
aecfbdb1 SH	96	struct ipu_soc *ipu;
	97	struct ipu_dmfc_priv *priv;
	98	const struct dmfc_channel_data *data;
	99	};
	100
	101	struct ipu_dmfc_priv {
	102	struct ipu_soc *ipu;
	103	struct device *dev;
	104	struct dmfc_channel channels[DMFC_NUM_CHANNELS];
	105	struct mutex mutex;
aecfbdb1 SH	106	void __iomem *base;
	107	int use_count;
	108	};
	109
	110	int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc)
	111	{
	112	struct ipu_dmfc_priv *priv = dmfc->priv;
	113	mutex_lock(&priv->mutex);
	114
	115	if (!priv->use_count)
	116	ipu_module_enable(priv->ipu, IPU_CONF_DMFC_EN);
	117
	118	priv->use_count++;
	119
	120	mutex_unlock(&priv->mutex);
	121
	122	return 0;
	123	}
	124	EXPORT_SYMBOL_GPL(ipu_dmfc_enable_channel);
	125
47348661 PZ	126	static void ipu_dmfc_wait_fifos(struct ipu_dmfc_priv *priv)
	127	{
	128	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
	129
	130	while ((readl(priv->base + DMFC_STAT) & 0x02fff000) != 0x02fff000) {
	131	if (time_after(jiffies, timeout)) {
	132	dev_warn(priv->dev,
	133	"Timeout waiting for DMFC FIFOs to clear\n");
	134	break;
	135	}
	136	cpu_relax();
	137	}
	138	}
	139
aecfbdb1 SH	140	void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc)
	141	{
	142	struct ipu_dmfc_priv *priv = dmfc->priv;
	143
	144	mutex_lock(&priv->mutex);
	145
	146	priv->use_count--;
	147
47348661 PZ	148	if (!priv->use_count) {
47348661 PZ	149	ipu_dmfc_wait_fifos(priv);
aecfbdb1	150	ipu_module_disable(priv->ipu, IPU_CONF_DMFC_EN);
47348661	151	}
aecfbdb1 SH	152
	153	if (priv->use_count < 0)
	154	priv->use_count = 0;
	155
	156	mutex_unlock(&priv->mutex);
	157	}
	158	EXPORT_SYMBOL_GPL(ipu_dmfc_disable_channel);
	159
27630c20	160	void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width)
aecfbdb1 SH	161	{
	162	struct ipu_dmfc_priv *priv = dmfc->priv;
	163	u32 dmfc_gen1;
	164
32c26a56 LY	165	mutex_lock(&priv->mutex);
32c26a56 LY	166
aecfbdb1 SH	167	dmfc_gen1 = readl(priv->base + DMFC_GENERAL1);
	168
	169	if ((dmfc->slots * 64 * 4) / width > dmfc->data->max_fifo_lines)
	170	dmfc_gen1 \|= 1 << dmfc->data->eot_shift;
	171	else
	172	dmfc_gen1 &= ~(1 << dmfc->data->eot_shift);
	173
	174	writel(dmfc_gen1, priv->base + DMFC_GENERAL1);
	175
32c26a56	176	mutex_unlock(&priv->mutex);
aecfbdb1	177	}
27630c20	178	EXPORT_SYMBOL_GPL(ipu_dmfc_config_wait4eot);
aecfbdb1 SH	179
	180	struct dmfc_channel ipu_dmfc_get(struct ipu_soc ipu, int ipu_channel)
	181	{
	182	struct ipu_dmfc_priv *priv = ipu->dmfc_priv;
	183	int i;
	184
	185	for (i = 0; i < DMFC_NUM_CHANNELS; i++)
	186	if (dmfcdata[i].ipu_channel == ipu_channel)
	187	return &priv->channels[i];
	188	return ERR_PTR(-ENODEV);
	189	}
	190	EXPORT_SYMBOL_GPL(ipu_dmfc_get);
	191
	192	void ipu_dmfc_put(struct dmfc_channel *dmfc)
	193	{
aecfbdb1 SH	194	}
	195	EXPORT_SYMBOL_GPL(ipu_dmfc_put);
	196
	197	int ipu_dmfc_init(struct ipu_soc ipu, struct device dev, unsigned long base,
	198	struct clk *ipu_clk)
	199	{
	200	struct ipu_dmfc_priv *priv;
	201	int i;
	202
	203	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	204	if (!priv)
	205	return -ENOMEM;
	206
	207	priv->base = devm_ioremap(dev, base, PAGE_SIZE);
	208	if (!priv->base)
	209	return -ENOMEM;
	210
	211	priv->dev = dev;
	212	priv->ipu = ipu;
	213	mutex_init(&priv->mutex);
	214
	215	ipu->dmfc_priv = priv;
	216
	217	for (i = 0; i < DMFC_NUM_CHANNELS; i++) {
	218	priv->channels[i].priv = priv;
	219	priv->channels[i].ipu = ipu;
	220	priv->channels[i].data = &dmfcdata[i];
aecfbdb1	221
d7868cb7 LY	222	if (dmfcdata[i].ipu_channel == IPUV3_CHANNEL_MEM_BG_SYNC \|\|
	223	dmfcdata[i].ipu_channel == IPUV3_CHANNEL_MEM_FG_SYNC \|\|
	224	dmfcdata[i].ipu_channel == IPUV3_CHANNEL_MEM_DC_SYNC)
	225	priv->channels[i].slots = 2;
	226	}
aecfbdb1	227
d7868cb7 LY	228	writel(0x00000050, priv->base + DMFC_WR_CHAN);
d7868cb7 LY	229	writel(0x00005654, priv->base + DMFC_DP_CHAN);
aecfbdb1 SH	230	writel(0x202020f6, priv->base + DMFC_WR_CHAN_DEF);
	231	writel(0x2020f6f6, priv->base + DMFC_DP_CHAN_DEF);
	232	writel(0x00000003, priv->base + DMFC_GENERAL1);
	233
	234	return 0;
	235	}
	236
	237	void ipu_dmfc_exit(struct ipu_soc *ipu)
	238	{
	239	}