[deliverable/linux.git] / drivers / gpu / ipu-v3 / ipu-prv.h

/*
 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 */
#ifndef __IPU_PRV_H__
#define __IPU_PRV_H__

struct ipu_soc;

#include <linux/types.h>
#include <linux/device.h>
#include <linux/clk.h>
#include <linux/platform_device.h>

#include <video/imx-ipu-v3.h>

#define IPUV3_CHANNEL_CSI0			 0
#define IPUV3_CHANNEL_CSI1			 1
#define IPUV3_CHANNEL_CSI2			 2
#define IPUV3_CHANNEL_CSI3			 3
#define IPUV3_CHANNEL_VDI_MEM_IC_VF              5
#define IPUV3_CHANNEL_MEM_IC_PP                 11
#define IPUV3_CHANNEL_MEM_IC_PRP_VF             12
#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF           14
#define IPUV3_CHANNEL_G_MEM_IC_PP               15
#define IPUV3_CHANNEL_IC_PRP_ENC_MEM            20
#define IPUV3_CHANNEL_IC_PRP_VF_MEM             21
#define IPUV3_CHANNEL_IC_PP_MEM                 22
#define IPUV3_CHANNEL_MEM_BG_SYNC		23
#define IPUV3_CHANNEL_MEM_FG_SYNC		27
#define IPUV3_CHANNEL_MEM_DC_SYNC		28
#define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA		31
#define IPUV3_CHANNEL_MEM_DC_ASYNC		41
#define IPUV3_CHANNEL_MEM_ROT_ENC		45
#define IPUV3_CHANNEL_MEM_ROT_VF		46
#define IPUV3_CHANNEL_MEM_ROT_PP		47
#define IPUV3_CHANNEL_ROT_ENC_MEM		48
#define IPUV3_CHANNEL_ROT_VF_MEM		49
#define IPUV3_CHANNEL_ROT_PP_MEM		50
#define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA		51

#define IPU_MCU_T_DEFAULT	8
#define IPU_CM_IDMAC_REG_OFS	0x00008000
#define IPU_CM_IC_REG_OFS	0x00020000
#define IPU_CM_IRT_REG_OFS	0x00028000
#define IPU_CM_CSI0_REG_OFS	0x00030000
#define IPU_CM_CSI1_REG_OFS	0x00038000
#define IPU_CM_SMFC_REG_OFS	0x00050000
#define IPU_CM_DC_REG_OFS	0x00058000
#define IPU_CM_DMFC_REG_OFS	0x00060000

/* Register addresses */
/* IPU Common registers */
#define IPU_CM_REG(offset)	(offset)

#define IPU_CONF			IPU_CM_REG(0)

#define IPU_SRM_PRI1			IPU_CM_REG(0x00a0)
#define IPU_SRM_PRI2			IPU_CM_REG(0x00a4)
#define IPU_FS_PROC_FLOW1		IPU_CM_REG(0x00a8)
#define IPU_FS_PROC_FLOW2		IPU_CM_REG(0x00ac)
#define IPU_FS_PROC_FLOW3		IPU_CM_REG(0x00b0)
#define IPU_FS_DISP_FLOW1		IPU_CM_REG(0x00b4)
#define IPU_FS_DISP_FLOW2		IPU_CM_REG(0x00b8)
#define IPU_SKIP			IPU_CM_REG(0x00bc)
#define IPU_DISP_ALT_CONF		IPU_CM_REG(0x00c0)
#define IPU_DISP_GEN			IPU_CM_REG(0x00c4)
#define IPU_DISP_ALT1			IPU_CM_REG(0x00c8)
#define IPU_DISP_ALT2			IPU_CM_REG(0x00cc)
#define IPU_DISP_ALT3			IPU_CM_REG(0x00d0)
#define IPU_DISP_ALT4			IPU_CM_REG(0x00d4)
#define IPU_SNOOP			IPU_CM_REG(0x00d8)
#define IPU_MEM_RST			IPU_CM_REG(0x00dc)
#define IPU_PM				IPU_CM_REG(0x00e0)
#define IPU_GPR				IPU_CM_REG(0x00e4)
#define IPU_CHA_DB_MODE_SEL(ch)		IPU_CM_REG(0x0150 + 4 * ((ch) / 32))
#define IPU_ALT_CHA_DB_MODE_SEL(ch)	IPU_CM_REG(0x0168 + 4 * ((ch) / 32))
#define IPU_CHA_CUR_BUF(ch)		IPU_CM_REG(0x023C + 4 * ((ch) / 32))
#define IPU_ALT_CUR_BUF0		IPU_CM_REG(0x0244)
#define IPU_ALT_CUR_BUF1		IPU_CM_REG(0x0248)
#define IPU_SRM_STAT			IPU_CM_REG(0x024C)
#define IPU_PROC_TASK_STAT		IPU_CM_REG(0x0250)
#define IPU_DISP_TASK_STAT		IPU_CM_REG(0x0254)
#define IPU_CHA_BUF0_RDY(ch)		IPU_CM_REG(0x0268 + 4 * ((ch) / 32))
#define IPU_CHA_BUF1_RDY(ch)		IPU_CM_REG(0x0270 + 4 * ((ch) / 32))
#define IPU_ALT_CHA_BUF0_RDY(ch)	IPU_CM_REG(0x0278 + 4 * ((ch) / 32))
#define IPU_ALT_CHA_BUF1_RDY(ch)	IPU_CM_REG(0x0280 + 4 * ((ch) / 32))

#define IPU_INT_CTRL(n)		IPU_CM_REG(0x003C + 4 * (n))
#define IPU_INT_STAT(n)		IPU_CM_REG(0x0200 + 4 * (n))

#define IPU_DI0_COUNTER_RELEASE			(1 << 24)
#define IPU_DI1_COUNTER_RELEASE			(1 << 25)

#define IPU_IDMAC_REG(offset)	(offset)

#define IDMAC_CONF			IPU_IDMAC_REG(0x0000)
#define IDMAC_CHA_EN(ch)		IPU_IDMAC_REG(0x0004 + 4 * ((ch) / 32))
#define IDMAC_SEP_ALPHA			IPU_IDMAC_REG(0x000c)
#define IDMAC_ALT_SEP_ALPHA		IPU_IDMAC_REG(0x0010)
#define IDMAC_CHA_PRI(ch)		IPU_IDMAC_REG(0x0014 + 4 * ((ch) / 32))
#define IDMAC_WM_EN(ch)			IPU_IDMAC_REG(0x001c + 4 * ((ch) / 32))
#define IDMAC_CH_LOCK_EN_1		IPU_IDMAC_REG(0x0024)
#define IDMAC_CH_LOCK_EN_2		IPU_IDMAC_REG(0x0028)
#define IDMAC_SUB_ADDR_0		IPU_IDMAC_REG(0x002c)
#define IDMAC_SUB_ADDR_1		IPU_IDMAC_REG(0x0030)
#define IDMAC_SUB_ADDR_2		IPU_IDMAC_REG(0x0034)
#define IDMAC_BAND_EN(ch)		IPU_IDMAC_REG(0x0040 + 4 * ((ch) / 32))
#define IDMAC_CHA_BUSY(ch)		IPU_IDMAC_REG(0x0100 + 4 * ((ch) / 32))

#define IPU_NUM_IRQS	(32 * 15)

enum ipu_modules {
	IPU_CONF_CSI0_EN		= (1 << 0),
	IPU_CONF_CSI1_EN		= (1 << 1),
	IPU_CONF_IC_EN			= (1 << 2),
	IPU_CONF_ROT_EN			= (1 << 3),
	IPU_CONF_ISP_EN			= (1 << 4),
	IPU_CONF_DP_EN			= (1 << 5),
	IPU_CONF_DI0_EN			= (1 << 6),
	IPU_CONF_DI1_EN			= (1 << 7),
	IPU_CONF_SMFC_EN		= (1 << 8),
	IPU_CONF_DC_EN			= (1 << 9),
	IPU_CONF_DMFC_EN		= (1 << 10),

	IPU_CONF_VDI_EN			= (1 << 12),

	IPU_CONF_IDMAC_DIS		= (1 << 22),

	IPU_CONF_IC_DMFC_SEL		= (1 << 25),
	IPU_CONF_IC_DMFC_SYNC		= (1 << 26),
	IPU_CONF_VDI_DMFC_SYNC		= (1 << 27),

	IPU_CONF_CSI0_DATA_SOURCE	= (1 << 28),
	IPU_CONF_CSI1_DATA_SOURCE	= (1 << 29),
	IPU_CONF_IC_INPUT		= (1 << 30),
	IPU_CONF_CSI_SEL		= (1 << 31),
};

struct ipuv3_channel {
	unsigned int num;

	bool enabled;
	bool busy;

	struct ipu_soc *ipu;
};

struct ipu_cpmem;
struct ipu_dc_priv;
struct ipu_dmfc_priv;
struct ipu_di;
struct ipu_smfc_priv;

struct ipu_devtype;

struct ipu_soc {
	struct device		*dev;
	const struct ipu_devtype	*devtype;
	enum ipuv3_type		ipu_type;
	spinlock_t		lock;
	struct mutex		channel_lock;

	void __iomem		*cm_reg;
	void __iomem		*idmac_reg;

	int			usecount;

	struct clk		*clk;

	struct ipuv3_channel	channel[64];

	int			irq_sync;
	int			irq_err;
	struct irq_domain	*domain;

	struct ipu_cpmem	*cpmem_priv;
	struct ipu_dc_priv	*dc_priv;
	struct ipu_dp_priv	*dp_priv;
	struct ipu_dmfc_priv	*dmfc_priv;
	struct ipu_di		*di_priv[2];
	struct ipu_smfc_priv	*smfc_priv;
};

static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset)
{
	return readl(ipu->idmac_reg + offset);
}

static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value,
				   unsigned offset)
{
	writel(value, ipu->idmac_reg + offset);
}

void ipu_srm_dp_sync_update(struct ipu_soc *ipu);

int ipu_module_enable(struct ipu_soc *ipu, u32 mask);
int ipu_module_disable(struct ipu_soc *ipu, u32 mask);

bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno);
int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms);

int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
		unsigned long base, u32 module, struct clk *ipu_clk);
void ipu_di_exit(struct ipu_soc *ipu, int id);

int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
		struct clk *ipu_clk);
void ipu_dmfc_exit(struct ipu_soc *ipu);

int ipu_dp_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
void ipu_dp_exit(struct ipu_soc *ipu);

int ipu_dc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
		unsigned long template_base);
void ipu_dc_exit(struct ipu_soc *ipu);

int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
void ipu_cpmem_exit(struct ipu_soc *ipu);

int ipu_smfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
void ipu_smfc_exit(struct ipu_soc *ipu);

#endif				/* __IPU_PRV_H__ */
Commit	Line	Data
aecfbdb1 SH	1	/*
	2	* Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
	3	* Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful, but
	11	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	12	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	13	* for more details.
	14	*/
	15	#ifndef __IPU_PRV_H__
	16	#define __IPU_PRV_H__
	17
	18	struct ipu_soc;
	19
	20	#include <linux/types.h>
	21	#include <linux/device.h>
	22	#include <linux/clk.h>
	23	#include <linux/platform_device.h>
	24
39b9004d	25	#include <video/imx-ipu-v3.h>
aecfbdb1 SH	26
	27	#define IPUV3_CHANNEL_CSI0 0
	28	#define IPUV3_CHANNEL_CSI1 1
	29	#define IPUV3_CHANNEL_CSI2 2
	30	#define IPUV3_CHANNEL_CSI3 3
c2d670fd SL	31	#define IPUV3_CHANNEL_VDI_MEM_IC_VF 5
	32	#define IPUV3_CHANNEL_MEM_IC_PP 11
	33	#define IPUV3_CHANNEL_MEM_IC_PRP_VF 12
	34	#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14
	35	#define IPUV3_CHANNEL_G_MEM_IC_PP 15
	36	#define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20
	37	#define IPUV3_CHANNEL_IC_PRP_VF_MEM 21
	38	#define IPUV3_CHANNEL_IC_PP_MEM 22
aecfbdb1 SH	39	#define IPUV3_CHANNEL_MEM_BG_SYNC 23
	40	#define IPUV3_CHANNEL_MEM_FG_SYNC 27
	41	#define IPUV3_CHANNEL_MEM_DC_SYNC 28
	42	#define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31
	43	#define IPUV3_CHANNEL_MEM_DC_ASYNC 41
c2d670fd SL	44	#define IPUV3_CHANNEL_MEM_ROT_ENC 45
	45	#define IPUV3_CHANNEL_MEM_ROT_VF 46
	46	#define IPUV3_CHANNEL_MEM_ROT_PP 47
	47	#define IPUV3_CHANNEL_ROT_ENC_MEM 48
	48	#define IPUV3_CHANNEL_ROT_VF_MEM 49
	49	#define IPUV3_CHANNEL_ROT_PP_MEM 50
aecfbdb1 SH	50	#define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51
	51
	52	#define IPU_MCU_T_DEFAULT 8
	53	#define IPU_CM_IDMAC_REG_OFS 0x00008000
	54	#define IPU_CM_IC_REG_OFS 0x00020000
	55	#define IPU_CM_IRT_REG_OFS 0x00028000
	56	#define IPU_CM_CSI0_REG_OFS 0x00030000
	57	#define IPU_CM_CSI1_REG_OFS 0x00038000
	58	#define IPU_CM_SMFC_REG_OFS 0x00050000
	59	#define IPU_CM_DC_REG_OFS 0x00058000
	60	#define IPU_CM_DMFC_REG_OFS 0x00060000
	61
	62	/* Register addresses */
	63	/* IPU Common registers */
	64	#define IPU_CM_REG(offset) (offset)
	65
	66	#define IPU_CONF IPU_CM_REG(0)
	67
	68	#define IPU_SRM_PRI1 IPU_CM_REG(0x00a0)
	69	#define IPU_SRM_PRI2 IPU_CM_REG(0x00a4)
	70	#define IPU_FS_PROC_FLOW1 IPU_CM_REG(0x00a8)
	71	#define IPU_FS_PROC_FLOW2 IPU_CM_REG(0x00ac)
	72	#define IPU_FS_PROC_FLOW3 IPU_CM_REG(0x00b0)
	73	#define IPU_FS_DISP_FLOW1 IPU_CM_REG(0x00b4)
	74	#define IPU_FS_DISP_FLOW2 IPU_CM_REG(0x00b8)
	75	#define IPU_SKIP IPU_CM_REG(0x00bc)
	76	#define IPU_DISP_ALT_CONF IPU_CM_REG(0x00c0)
	77	#define IPU_DISP_GEN IPU_CM_REG(0x00c4)
	78	#define IPU_DISP_ALT1 IPU_CM_REG(0x00c8)
	79	#define IPU_DISP_ALT2 IPU_CM_REG(0x00cc)
	80	#define IPU_DISP_ALT3 IPU_CM_REG(0x00d0)
	81	#define IPU_DISP_ALT4 IPU_CM_REG(0x00d4)
	82	#define IPU_SNOOP IPU_CM_REG(0x00d8)
	83	#define IPU_MEM_RST IPU_CM_REG(0x00dc)
	84	#define IPU_PM IPU_CM_REG(0x00e0)
	85	#define IPU_GPR IPU_CM_REG(0x00e4)
	86	#define IPU_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0150 + 4 * ((ch) / 32))
	87	#define IPU_ALT_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0168 + 4 * ((ch) / 32))
	88	#define IPU_CHA_CUR_BUF(ch) IPU_CM_REG(0x023C + 4 * ((ch) / 32))
	89	#define IPU_ALT_CUR_BUF0 IPU_CM_REG(0x0244)
	90	#define IPU_ALT_CUR_BUF1 IPU_CM_REG(0x0248)
	91	#define IPU_SRM_STAT IPU_CM_REG(0x024C)
	92	#define IPU_PROC_TASK_STAT IPU_CM_REG(0x0250)
	93	#define IPU_DISP_TASK_STAT IPU_CM_REG(0x0254)
	94	#define IPU_CHA_BUF0_RDY(ch) IPU_CM_REG(0x0268 + 4 * ((ch) / 32))
	95	#define IPU_CHA_BUF1_RDY(ch) IPU_CM_REG(0x0270 + 4 * ((ch) / 32))
	96	#define IPU_ALT_CHA_BUF0_RDY(ch) IPU_CM_REG(0x0278 + 4 * ((ch) / 32))
	97	#define IPU_ALT_CHA_BUF1_RDY(ch) IPU_CM_REG(0x0280 + 4 * ((ch) / 32))
	98
	99	#define IPU_INT_CTRL(n) IPU_CM_REG(0x003C + 4 * (n))
	100	#define IPU_INT_STAT(n) IPU_CM_REG(0x0200 + 4 * (n))
	101
	102	#define IPU_DI0_COUNTER_RELEASE (1 << 24)
	103	#define IPU_DI1_COUNTER_RELEASE (1 << 25)
	104
	105	#define IPU_IDMAC_REG(offset) (offset)
	106
	107	#define IDMAC_CONF IPU_IDMAC_REG(0x0000)
	108	#define IDMAC_CHA_EN(ch) IPU_IDMAC_REG(0x0004 + 4 * ((ch) / 32))
	109	#define IDMAC_SEP_ALPHA IPU_IDMAC_REG(0x000c)
	110	#define IDMAC_ALT_SEP_ALPHA IPU_IDMAC_REG(0x0010)
	111	#define IDMAC_CHA_PRI(ch) IPU_IDMAC_REG(0x0014 + 4 * ((ch) / 32))
	112	#define IDMAC_WM_EN(ch) IPU_IDMAC_REG(0x001c + 4 * ((ch) / 32))
	113	#define IDMAC_CH_LOCK_EN_1 IPU_IDMAC_REG(0x0024)
114	#define IDMAC_CH_LOCK_EN_2 IPU_IDMAC_REG(0x0028)
115	#define IDMAC_SUB_ADDR_0 IPU_IDMAC_REG(0x002c)
116	#define IDMAC_SUB_ADDR_1 IPU_IDMAC_REG(0x0030)
117	#define IDMAC_SUB_ADDR_2 IPU_IDMAC_REG(0x0034)
118	#define IDMAC_BAND_EN(ch) IPU_IDMAC_REG(0x0040 + 4 * ((ch) / 32))
119	#define IDMAC_CHA_BUSY(ch) IPU_IDMAC_REG(0x0100 + 4 * ((ch) / 32))
120
e4f2a54e	121	#define IPU_NUM_IRQS (32 * 15)
aecfbdb1 SH	122
	123	enum ipu_modules {
	124	IPU_CONF_CSI0_EN = (1 << 0),
	125	IPU_CONF_CSI1_EN = (1 << 1),
	126	IPU_CONF_IC_EN = (1 << 2),
	127	IPU_CONF_ROT_EN = (1 << 3),
	128	IPU_CONF_ISP_EN = (1 << 4),
	129	IPU_CONF_DP_EN = (1 << 5),
	130	IPU_CONF_DI0_EN = (1 << 6),
	131	IPU_CONF_DI1_EN = (1 << 7),
	132	IPU_CONF_SMFC_EN = (1 << 8),
	133	IPU_CONF_DC_EN = (1 << 9),
	134	IPU_CONF_DMFC_EN = (1 << 10),
	135
	136	IPU_CONF_VDI_EN = (1 << 12),
	137
	138	IPU_CONF_IDMAC_DIS = (1 << 22),
	139
	140	IPU_CONF_IC_DMFC_SEL = (1 << 25),
	141	IPU_CONF_IC_DMFC_SYNC = (1 << 26),
	142	IPU_CONF_VDI_DMFC_SYNC = (1 << 27),
	143
	144	IPU_CONF_CSI0_DATA_SOURCE = (1 << 28),
	145	IPU_CONF_CSI1_DATA_SOURCE = (1 << 29),
	146	IPU_CONF_IC_INPUT = (1 << 30),
	147	IPU_CONF_CSI_SEL = (1 << 31),
	148	};
	149
	150	struct ipuv3_channel {
	151	unsigned int num;
	152
	153	bool enabled;
	154	bool busy;
	155
	156	struct ipu_soc *ipu;
	157	};
	158
7d2691da	159	struct ipu_cpmem;
aecfbdb1 SH	160	struct ipu_dc_priv;
	161	struct ipu_dmfc_priv;
	162	struct ipu_di;
35de925f PZ	163	struct ipu_smfc_priv;
35de925f PZ	164
aecfbdb1 SH	165	struct ipu_devtype;
	166
	167	struct ipu_soc {
	168	struct device *dev;
	169	const struct ipu_devtype *devtype;
	170	enum ipuv3_type ipu_type;
	171	spinlock_t lock;
	172	struct mutex channel_lock;
	173
	174	void __iomem *cm_reg;
	175	void __iomem *idmac_reg;
aecfbdb1 SH	176
	177	int usecount;
	178
	179	struct clk *clk;
	180
	181	struct ipuv3_channel channel[64];
	182
aecfbdb1 SH	183	int irq_sync;
aecfbdb1 SH	184	int irq_err;
b728766c	185	struct irq_domain *domain;
aecfbdb1	186
7d2691da	187	struct ipu_cpmem *cpmem_priv;
aecfbdb1 SH	188	struct ipu_dc_priv *dc_priv;
	189	struct ipu_dp_priv *dp_priv;
	190	struct ipu_dmfc_priv *dmfc_priv;
	191	struct ipu_di *di_priv[2];
35de925f	192	struct ipu_smfc_priv *smfc_priv;
aecfbdb1 SH	193	};
aecfbdb1 SH	194
7d2691da SL	195	static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset)
	196	{
	197	return readl(ipu->idmac_reg + offset);
	198	}
	199
	200	static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value,
	201	unsigned offset)
	202	{
	203	writel(value, ipu->idmac_reg + offset);
	204	}
	205
aecfbdb1 SH	206	void ipu_srm_dp_sync_update(struct ipu_soc *ipu);
	207
	208	int ipu_module_enable(struct ipu_soc *ipu, u32 mask);
	209	int ipu_module_disable(struct ipu_soc *ipu, u32 mask);
	210
17075504 PZ	211	bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno);
	212	int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms);
	213
aecfbdb1 SH	214	int ipu_di_init(struct ipu_soc ipu, struct device dev, int id,
	215	unsigned long base, u32 module, struct clk *ipu_clk);
	216	void ipu_di_exit(struct ipu_soc *ipu, int id);
	217
	218	int ipu_dmfc_init(struct ipu_soc ipu, struct device dev, unsigned long base,
	219	struct clk *ipu_clk);
	220	void ipu_dmfc_exit(struct ipu_soc *ipu);
	221
	222	int ipu_dp_init(struct ipu_soc ipu, struct device dev, unsigned long base);
	223	void ipu_dp_exit(struct ipu_soc *ipu);
	224
	225	int ipu_dc_init(struct ipu_soc ipu, struct device dev, unsigned long base,
	226	unsigned long template_base);
	227	void ipu_dc_exit(struct ipu_soc *ipu);
	228
	229	int ipu_cpmem_init(struct ipu_soc ipu, struct device dev, unsigned long base);
	230	void ipu_cpmem_exit(struct ipu_soc *ipu);
	231
35de925f PZ	232	int ipu_smfc_init(struct ipu_soc ipu, struct device dev, unsigned long base);
	233	void ipu_smfc_exit(struct ipu_soc *ipu);
	234
aecfbdb1	235	#endif /* __IPU_PRV_H__ */