Commit | Line | Data |
---|---|---|
bebe4678 RM |
1 | /* |
2 | * coretemp.c - Linux kernel module for hardware monitoring | |
3 | * | |
4 | * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> | |
5 | * | |
6 | * Inspired from many hwmon drivers | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA. | |
21 | */ | |
22 | ||
f8bb8925 JP |
23 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
24 | ||
bebe4678 | 25 | #include <linux/module.h> |
bebe4678 RM |
26 | #include <linux/init.h> |
27 | #include <linux/slab.h> | |
28 | #include <linux/jiffies.h> | |
29 | #include <linux/hwmon.h> | |
30 | #include <linux/sysfs.h> | |
31 | #include <linux/hwmon-sysfs.h> | |
32 | #include <linux/err.h> | |
33 | #include <linux/mutex.h> | |
34 | #include <linux/list.h> | |
35 | #include <linux/platform_device.h> | |
36 | #include <linux/cpu.h> | |
1fe63ab4 | 37 | #include <linux/pci.h> |
bebe4678 RM |
38 | #include <asm/msr.h> |
39 | #include <asm/processor.h> | |
fff20173 | 40 | #include <asm/smp.h> |
bebe4678 RM |
41 | |
42 | #define DRVNAME "coretemp" | |
43 | ||
6369a288 RM |
44 | typedef enum { SHOW_TEMP, SHOW_TJMAX, SHOW_TTARGET, SHOW_LABEL, |
45 | SHOW_NAME } SHOW; | |
bebe4678 RM |
46 | |
47 | /* | |
48 | * Functions declaration | |
49 | */ | |
50 | ||
51 | static struct coretemp_data *coretemp_update_device(struct device *dev); | |
52 | ||
53 | struct coretemp_data { | |
1beeffe4 | 54 | struct device *hwmon_dev; |
bebe4678 RM |
55 | struct mutex update_lock; |
56 | const char *name; | |
57 | u32 id; | |
3f4f09b4 | 58 | u16 core_id; |
bebe4678 RM |
59 | char valid; /* zero until following fields are valid */ |
60 | unsigned long last_updated; /* in jiffies */ | |
61 | int temp; | |
62 | int tjmax; | |
6369a288 | 63 | int ttarget; |
bebe4678 RM |
64 | u8 alarm; |
65 | }; | |
66 | ||
bebe4678 RM |
67 | /* |
68 | * Sysfs stuff | |
69 | */ | |
70 | ||
71 | static ssize_t show_name(struct device *dev, struct device_attribute | |
72 | *devattr, char *buf) | |
73 | { | |
74 | int ret; | |
75 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
76 | struct coretemp_data *data = dev_get_drvdata(dev); | |
77 | ||
78 | if (attr->index == SHOW_NAME) | |
79 | ret = sprintf(buf, "%s\n", data->name); | |
80 | else /* show label */ | |
3f4f09b4 | 81 | ret = sprintf(buf, "Core %d\n", data->core_id); |
bebe4678 RM |
82 | return ret; |
83 | } | |
84 | ||
85 | static ssize_t show_alarm(struct device *dev, struct device_attribute | |
86 | *devattr, char *buf) | |
87 | { | |
88 | struct coretemp_data *data = coretemp_update_device(dev); | |
89 | /* read the Out-of-spec log, never clear */ | |
90 | return sprintf(buf, "%d\n", data->alarm); | |
91 | } | |
92 | ||
93 | static ssize_t show_temp(struct device *dev, | |
94 | struct device_attribute *devattr, char *buf) | |
95 | { | |
96 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
97 | struct coretemp_data *data = coretemp_update_device(dev); | |
98 | int err; | |
99 | ||
100 | if (attr->index == SHOW_TEMP) | |
101 | err = data->valid ? sprintf(buf, "%d\n", data->temp) : -EAGAIN; | |
6369a288 | 102 | else if (attr->index == SHOW_TJMAX) |
bebe4678 | 103 | err = sprintf(buf, "%d\n", data->tjmax); |
6369a288 RM |
104 | else |
105 | err = sprintf(buf, "%d\n", data->ttarget); | |
bebe4678 RM |
106 | return err; |
107 | } | |
108 | ||
109 | static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL, | |
110 | SHOW_TEMP); | |
111 | static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp, NULL, | |
112 | SHOW_TJMAX); | |
6369a288 RM |
113 | static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, show_temp, NULL, |
114 | SHOW_TTARGET); | |
bebe4678 RM |
115 | static DEVICE_ATTR(temp1_crit_alarm, S_IRUGO, show_alarm, NULL); |
116 | static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, show_name, NULL, SHOW_LABEL); | |
117 | static SENSOR_DEVICE_ATTR(name, S_IRUGO, show_name, NULL, SHOW_NAME); | |
118 | ||
119 | static struct attribute *coretemp_attributes[] = { | |
120 | &sensor_dev_attr_name.dev_attr.attr, | |
121 | &sensor_dev_attr_temp1_label.dev_attr.attr, | |
122 | &dev_attr_temp1_crit_alarm.attr, | |
123 | &sensor_dev_attr_temp1_input.dev_attr.attr, | |
124 | &sensor_dev_attr_temp1_crit.dev_attr.attr, | |
125 | NULL | |
126 | }; | |
127 | ||
128 | static const struct attribute_group coretemp_group = { | |
129 | .attrs = coretemp_attributes, | |
130 | }; | |
131 | ||
132 | static struct coretemp_data *coretemp_update_device(struct device *dev) | |
133 | { | |
134 | struct coretemp_data *data = dev_get_drvdata(dev); | |
135 | ||
136 | mutex_lock(&data->update_lock); | |
137 | ||
138 | if (!data->valid || time_after(jiffies, data->last_updated + HZ)) { | |
139 | u32 eax, edx; | |
140 | ||
141 | data->valid = 0; | |
142 | rdmsr_on_cpu(data->id, MSR_IA32_THERM_STATUS, &eax, &edx); | |
143 | data->alarm = (eax >> 5) & 1; | |
144 | /* update only if data has been valid */ | |
145 | if (eax & 0x80000000) { | |
146 | data->temp = data->tjmax - (((eax >> 16) | |
147 | & 0x7f) * 1000); | |
148 | data->valid = 1; | |
149 | } else { | |
150 | dev_dbg(dev, "Temperature data invalid (0x%x)\n", eax); | |
151 | } | |
152 | data->last_updated = jiffies; | |
153 | } | |
154 | ||
155 | mutex_unlock(&data->update_lock); | |
156 | return data; | |
157 | } | |
158 | ||
118a8871 RM |
159 | static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) |
160 | { | |
161 | /* The 100C is default for both mobile and non mobile CPUs */ | |
162 | ||
163 | int tjmax = 100000; | |
eccfed42 | 164 | int tjmax_ee = 85000; |
708a62bc | 165 | int usemsr_ee = 1; |
118a8871 RM |
166 | int err; |
167 | u32 eax, edx; | |
1fe63ab4 | 168 | struct pci_dev *host_bridge; |
118a8871 RM |
169 | |
170 | /* Early chips have no MSR for TjMax */ | |
171 | ||
172 | if ((c->x86_model == 0xf) && (c->x86_mask < 4)) { | |
708a62bc | 173 | usemsr_ee = 0; |
118a8871 RM |
174 | } |
175 | ||
1fe63ab4 | 176 | /* Atom CPUs */ |
708a62bc RM |
177 | |
178 | if (c->x86_model == 0x1c) { | |
179 | usemsr_ee = 0; | |
1fe63ab4 YW |
180 | |
181 | host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); | |
182 | ||
183 | if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL | |
184 | && (host_bridge->device == 0xa000 /* NM10 based nettop */ | |
185 | || host_bridge->device == 0xa010)) /* NM10 based netbook */ | |
186 | tjmax = 100000; | |
187 | else | |
188 | tjmax = 90000; | |
189 | ||
190 | pci_dev_put(host_bridge); | |
708a62bc RM |
191 | } |
192 | ||
193 | if ((c->x86_model > 0xe) && (usemsr_ee)) { | |
eccfed42 | 194 | u8 platform_id; |
118a8871 RM |
195 | |
196 | /* Now we can detect the mobile CPU using Intel provided table | |
197 | http://softwarecommunity.intel.com/Wiki/Mobility/720.htm | |
198 | For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU | |
199 | */ | |
200 | ||
201 | err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx); | |
202 | if (err) { | |
203 | dev_warn(dev, | |
204 | "Unable to access MSR 0x17, assuming desktop" | |
205 | " CPU\n"); | |
708a62bc | 206 | usemsr_ee = 0; |
eccfed42 RM |
207 | } else if (c->x86_model < 0x17 && !(eax & 0x10000000)) { |
208 | /* Trust bit 28 up to Penryn, I could not find any | |
209 | documentation on that; if you happen to know | |
210 | someone at Intel please ask */ | |
708a62bc | 211 | usemsr_ee = 0; |
eccfed42 RM |
212 | } else { |
213 | /* Platform ID bits 52:50 (EDX starts at bit 32) */ | |
214 | platform_id = (edx >> 18) & 0x7; | |
215 | ||
216 | /* Mobile Penryn CPU seems to be platform ID 7 or 5 | |
217 | (guesswork) */ | |
218 | if ((c->x86_model == 0x17) && | |
219 | ((platform_id == 5) || (platform_id == 7))) { | |
220 | /* If MSR EE bit is set, set it to 90 degrees C, | |
221 | otherwise 105 degrees C */ | |
222 | tjmax_ee = 90000; | |
223 | tjmax = 105000; | |
224 | } | |
118a8871 RM |
225 | } |
226 | } | |
227 | ||
708a62bc | 228 | if (usemsr_ee) { |
118a8871 RM |
229 | |
230 | err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx); | |
231 | if (err) { | |
232 | dev_warn(dev, | |
233 | "Unable to access MSR 0xEE, for Tjmax, left" | |
4d7a5644 | 234 | " at default\n"); |
118a8871 | 235 | } else if (eax & 0x40000000) { |
eccfed42 | 236 | tjmax = tjmax_ee; |
118a8871 | 237 | } |
708a62bc RM |
238 | /* if we dont use msr EE it means we are desktop CPU (with exeception |
239 | of Atom) */ | |
240 | } else if (tjmax == 100000) { | |
118a8871 RM |
241 | dev_warn(dev, "Using relative temperature scale!\n"); |
242 | } | |
243 | ||
244 | return tjmax; | |
245 | } | |
246 | ||
a321cedb CE |
247 | static int __devinit get_tjmax(struct cpuinfo_x86 *c, u32 id, |
248 | struct device *dev) | |
249 | { | |
250 | /* The 100C is default for both mobile and non mobile CPUs */ | |
251 | int err; | |
252 | u32 eax, edx; | |
253 | u32 val; | |
254 | ||
255 | /* A new feature of current Intel(R) processors, the | |
256 | IA32_TEMPERATURE_TARGET contains the TjMax value */ | |
257 | err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); | |
258 | if (err) { | |
259 | dev_warn(dev, "Unable to read TjMax from CPU.\n"); | |
260 | } else { | |
261 | val = (eax >> 16) & 0xff; | |
262 | /* | |
263 | * If the TjMax is not plausible, an assumption | |
264 | * will be used | |
265 | */ | |
266 | if ((val > 80) && (val < 120)) { | |
267 | dev_info(dev, "TjMax is %d C.\n", val); | |
268 | return val * 1000; | |
269 | } | |
270 | } | |
271 | ||
272 | /* | |
273 | * An assumption is made for early CPUs and unreadable MSR. | |
274 | * NOTE: the given value may not be correct. | |
275 | */ | |
276 | ||
277 | switch (c->x86_model) { | |
278 | case 0xe: | |
279 | case 0xf: | |
280 | case 0x16: | |
281 | case 0x1a: | |
282 | dev_warn(dev, "TjMax is assumed as 100 C!\n"); | |
283 | return 100000; | |
a321cedb CE |
284 | case 0x17: |
285 | case 0x1c: /* Atom CPUs */ | |
286 | return adjust_tjmax(c, id, dev); | |
a321cedb CE |
287 | default: |
288 | dev_warn(dev, "CPU (model=0x%x) is not supported yet," | |
289 | " using default TjMax of 100C.\n", c->x86_model); | |
290 | return 100000; | |
291 | } | |
292 | } | |
293 | ||
32478006 JB |
294 | static void __devinit get_ucode_rev_on_cpu(void *edx) |
295 | { | |
296 | u32 eax; | |
297 | ||
298 | wrmsr(MSR_IA32_UCODE_REV, 0, 0); | |
299 | sync_core(); | |
300 | rdmsr(MSR_IA32_UCODE_REV, eax, *(u32 *)edx); | |
301 | } | |
302 | ||
bebe4678 RM |
303 | static int __devinit coretemp_probe(struct platform_device *pdev) |
304 | { | |
305 | struct coretemp_data *data; | |
92cb7612 | 306 | struct cpuinfo_x86 *c = &cpu_data(pdev->id); |
bebe4678 RM |
307 | int err; |
308 | u32 eax, edx; | |
309 | ||
310 | if (!(data = kzalloc(sizeof(struct coretemp_data), GFP_KERNEL))) { | |
311 | err = -ENOMEM; | |
312 | dev_err(&pdev->dev, "Out of memory\n"); | |
313 | goto exit; | |
314 | } | |
315 | ||
316 | data->id = pdev->id; | |
3f4f09b4 JD |
317 | #ifdef CONFIG_SMP |
318 | data->core_id = c->cpu_core_id; | |
319 | #endif | |
bebe4678 RM |
320 | data->name = "coretemp"; |
321 | mutex_init(&data->update_lock); | |
bebe4678 RM |
322 | |
323 | /* test if we can access the THERM_STATUS MSR */ | |
324 | err = rdmsr_safe_on_cpu(data->id, MSR_IA32_THERM_STATUS, &eax, &edx); | |
325 | if (err) { | |
326 | dev_err(&pdev->dev, | |
327 | "Unable to access THERM_STATUS MSR, giving up\n"); | |
328 | goto exit_free; | |
329 | } | |
330 | ||
67f363b1 RM |
331 | /* Check if we have problem with errata AE18 of Core processors: |
332 | Readings might stop update when processor visited too deep sleep, | |
333 | fixed for stepping D0 (6EC). | |
334 | */ | |
335 | ||
336 | if ((c->x86_model == 0xe) && (c->x86_mask < 0xc)) { | |
337 | /* check for microcode update */ | |
32478006 JB |
338 | err = smp_call_function_single(data->id, get_ucode_rev_on_cpu, |
339 | &edx, 1); | |
340 | if (err) { | |
341 | dev_err(&pdev->dev, | |
342 | "Cannot determine microcode revision of " | |
343 | "CPU#%u (%d)!\n", data->id, err); | |
344 | err = -ENODEV; | |
345 | goto exit_free; | |
346 | } else if (edx < 0x39) { | |
6d79af70 | 347 | err = -ENODEV; |
67f363b1 RM |
348 | dev_err(&pdev->dev, |
349 | "Errata AE18 not fixed, update BIOS or " | |
350 | "microcode of the CPU!\n"); | |
351 | goto exit_free; | |
352 | } | |
353 | } | |
354 | ||
a321cedb | 355 | data->tjmax = get_tjmax(c, data->id, &pdev->dev); |
bebe4678 RM |
356 | platform_set_drvdata(pdev, data); |
357 | ||
a321cedb CE |
358 | /* |
359 | * read the still undocumented IA32_TEMPERATURE_TARGET. It exists | |
360 | * on older CPUs but not in this register, | |
361 | * Atoms don't have it either. | |
362 | */ | |
6369a288 | 363 | |
708a62bc | 364 | if ((c->x86_model > 0xe) && (c->x86_model != 0x1c)) { |
a321cedb CE |
365 | err = rdmsr_safe_on_cpu(data->id, MSR_IA32_TEMPERATURE_TARGET, |
366 | &eax, &edx); | |
6369a288 RM |
367 | if (err) { |
368 | dev_warn(&pdev->dev, "Unable to read" | |
369 | " IA32_TEMPERATURE_TARGET MSR\n"); | |
370 | } else { | |
371 | data->ttarget = data->tjmax - | |
372 | (((eax >> 8) & 0xff) * 1000); | |
373 | err = device_create_file(&pdev->dev, | |
374 | &sensor_dev_attr_temp1_max.dev_attr); | |
375 | if (err) | |
376 | goto exit_free; | |
377 | } | |
378 | } | |
379 | ||
bebe4678 | 380 | if ((err = sysfs_create_group(&pdev->dev.kobj, &coretemp_group))) |
6369a288 | 381 | goto exit_dev; |
bebe4678 | 382 | |
1beeffe4 TJ |
383 | data->hwmon_dev = hwmon_device_register(&pdev->dev); |
384 | if (IS_ERR(data->hwmon_dev)) { | |
385 | err = PTR_ERR(data->hwmon_dev); | |
bebe4678 RM |
386 | dev_err(&pdev->dev, "Class registration failed (%d)\n", |
387 | err); | |
388 | goto exit_class; | |
389 | } | |
390 | ||
391 | return 0; | |
392 | ||
393 | exit_class: | |
394 | sysfs_remove_group(&pdev->dev.kobj, &coretemp_group); | |
6369a288 RM |
395 | exit_dev: |
396 | device_remove_file(&pdev->dev, &sensor_dev_attr_temp1_max.dev_attr); | |
bebe4678 RM |
397 | exit_free: |
398 | kfree(data); | |
399 | exit: | |
400 | return err; | |
401 | } | |
402 | ||
403 | static int __devexit coretemp_remove(struct platform_device *pdev) | |
404 | { | |
405 | struct coretemp_data *data = platform_get_drvdata(pdev); | |
406 | ||
1beeffe4 | 407 | hwmon_device_unregister(data->hwmon_dev); |
bebe4678 | 408 | sysfs_remove_group(&pdev->dev.kobj, &coretemp_group); |
6369a288 | 409 | device_remove_file(&pdev->dev, &sensor_dev_attr_temp1_max.dev_attr); |
bebe4678 RM |
410 | platform_set_drvdata(pdev, NULL); |
411 | kfree(data); | |
412 | return 0; | |
413 | } | |
414 | ||
415 | static struct platform_driver coretemp_driver = { | |
416 | .driver = { | |
417 | .owner = THIS_MODULE, | |
418 | .name = DRVNAME, | |
419 | }, | |
420 | .probe = coretemp_probe, | |
421 | .remove = __devexit_p(coretemp_remove), | |
422 | }; | |
423 | ||
424 | struct pdev_entry { | |
425 | struct list_head list; | |
426 | struct platform_device *pdev; | |
427 | unsigned int cpu; | |
d883b9f0 JD |
428 | #ifdef CONFIG_SMP |
429 | u16 phys_proc_id; | |
430 | u16 cpu_core_id; | |
431 | #endif | |
bebe4678 RM |
432 | }; |
433 | ||
434 | static LIST_HEAD(pdev_list); | |
435 | static DEFINE_MUTEX(pdev_list_mutex); | |
436 | ||
437 | static int __cpuinit coretemp_device_add(unsigned int cpu) | |
438 | { | |
439 | int err; | |
440 | struct platform_device *pdev; | |
441 | struct pdev_entry *pdev_entry; | |
d883b9f0 | 442 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
a4659053 JB |
443 | |
444 | /* | |
445 | * CPUID.06H.EAX[0] indicates whether the CPU has thermal | |
446 | * sensors. We check this bit only, all the early CPUs | |
447 | * without thermal sensors will be filtered out. | |
448 | */ | |
449 | if (!cpu_has(c, X86_FEATURE_DTS)) { | |
f8bb8925 JP |
450 | pr_info("CPU (model=0x%x) has no thermal sensor\n", |
451 | c->x86_model); | |
a4659053 JB |
452 | return 0; |
453 | } | |
d883b9f0 JD |
454 | |
455 | mutex_lock(&pdev_list_mutex); | |
456 | ||
457 | #ifdef CONFIG_SMP | |
458 | /* Skip second HT entry of each core */ | |
459 | list_for_each_entry(pdev_entry, &pdev_list, list) { | |
460 | if (c->phys_proc_id == pdev_entry->phys_proc_id && | |
461 | c->cpu_core_id == pdev_entry->cpu_core_id) { | |
462 | err = 0; /* Not an error */ | |
463 | goto exit; | |
464 | } | |
465 | } | |
466 | #endif | |
bebe4678 RM |
467 | |
468 | pdev = platform_device_alloc(DRVNAME, cpu); | |
469 | if (!pdev) { | |
470 | err = -ENOMEM; | |
f8bb8925 | 471 | pr_err("Device allocation failed\n"); |
bebe4678 RM |
472 | goto exit; |
473 | } | |
474 | ||
475 | pdev_entry = kzalloc(sizeof(struct pdev_entry), GFP_KERNEL); | |
476 | if (!pdev_entry) { | |
477 | err = -ENOMEM; | |
478 | goto exit_device_put; | |
479 | } | |
480 | ||
481 | err = platform_device_add(pdev); | |
482 | if (err) { | |
f8bb8925 | 483 | pr_err("Device addition failed (%d)\n", err); |
bebe4678 RM |
484 | goto exit_device_free; |
485 | } | |
486 | ||
487 | pdev_entry->pdev = pdev; | |
488 | pdev_entry->cpu = cpu; | |
d883b9f0 JD |
489 | #ifdef CONFIG_SMP |
490 | pdev_entry->phys_proc_id = c->phys_proc_id; | |
491 | pdev_entry->cpu_core_id = c->cpu_core_id; | |
492 | #endif | |
bebe4678 RM |
493 | list_add_tail(&pdev_entry->list, &pdev_list); |
494 | mutex_unlock(&pdev_list_mutex); | |
495 | ||
496 | return 0; | |
497 | ||
498 | exit_device_free: | |
499 | kfree(pdev_entry); | |
500 | exit_device_put: | |
501 | platform_device_put(pdev); | |
502 | exit: | |
d883b9f0 | 503 | mutex_unlock(&pdev_list_mutex); |
bebe4678 RM |
504 | return err; |
505 | } | |
506 | ||
a5f42a6b | 507 | static void __cpuinit coretemp_device_remove(unsigned int cpu) |
bebe4678 | 508 | { |
e40cc4bd JB |
509 | struct pdev_entry *p; |
510 | unsigned int i; | |
511 | ||
bebe4678 | 512 | mutex_lock(&pdev_list_mutex); |
e40cc4bd JB |
513 | list_for_each_entry(p, &pdev_list, list) { |
514 | if (p->cpu != cpu) | |
515 | continue; | |
516 | ||
517 | platform_device_unregister(p->pdev); | |
518 | list_del(&p->list); | |
519 | mutex_unlock(&pdev_list_mutex); | |
520 | kfree(p); | |
521 | for_each_cpu(i, cpu_sibling_mask(cpu)) | |
522 | if (i != cpu && !coretemp_device_add(i)) | |
523 | break; | |
524 | return; | |
bebe4678 RM |
525 | } |
526 | mutex_unlock(&pdev_list_mutex); | |
527 | } | |
528 | ||
ba7c1927 | 529 | static int __cpuinit coretemp_cpu_callback(struct notifier_block *nfb, |
bebe4678 RM |
530 | unsigned long action, void *hcpu) |
531 | { | |
532 | unsigned int cpu = (unsigned long) hcpu; | |
533 | ||
534 | switch (action) { | |
535 | case CPU_ONLINE: | |
561d9a96 | 536 | case CPU_DOWN_FAILED: |
bebe4678 RM |
537 | coretemp_device_add(cpu); |
538 | break; | |
561d9a96 | 539 | case CPU_DOWN_PREPARE: |
bebe4678 RM |
540 | coretemp_device_remove(cpu); |
541 | break; | |
542 | } | |
543 | return NOTIFY_OK; | |
544 | } | |
545 | ||
ba7c1927 | 546 | static struct notifier_block coretemp_cpu_notifier __refdata = { |
bebe4678 RM |
547 | .notifier_call = coretemp_cpu_callback, |
548 | }; | |
bebe4678 RM |
549 | |
550 | static int __init coretemp_init(void) | |
551 | { | |
552 | int i, err = -ENODEV; | |
bebe4678 | 553 | |
bebe4678 | 554 | /* quick check if we run Intel */ |
92cb7612 | 555 | if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL) |
bebe4678 RM |
556 | goto exit; |
557 | ||
558 | err = platform_driver_register(&coretemp_driver); | |
559 | if (err) | |
560 | goto exit; | |
561 | ||
a4659053 JB |
562 | for_each_online_cpu(i) |
563 | coretemp_device_add(i); | |
89a3fd35 JB |
564 | |
565 | #ifndef CONFIG_HOTPLUG_CPU | |
bebe4678 RM |
566 | if (list_empty(&pdev_list)) { |
567 | err = -ENODEV; | |
568 | goto exit_driver_unreg; | |
569 | } | |
89a3fd35 | 570 | #endif |
bebe4678 | 571 | |
bebe4678 | 572 | register_hotcpu_notifier(&coretemp_cpu_notifier); |
bebe4678 RM |
573 | return 0; |
574 | ||
0dca94ba | 575 | #ifndef CONFIG_HOTPLUG_CPU |
89a3fd35 | 576 | exit_driver_unreg: |
bebe4678 | 577 | platform_driver_unregister(&coretemp_driver); |
0dca94ba | 578 | #endif |
bebe4678 RM |
579 | exit: |
580 | return err; | |
581 | } | |
582 | ||
583 | static void __exit coretemp_exit(void) | |
584 | { | |
585 | struct pdev_entry *p, *n; | |
17c10d61 | 586 | |
bebe4678 | 587 | unregister_hotcpu_notifier(&coretemp_cpu_notifier); |
bebe4678 RM |
588 | mutex_lock(&pdev_list_mutex); |
589 | list_for_each_entry_safe(p, n, &pdev_list, list) { | |
590 | platform_device_unregister(p->pdev); | |
591 | list_del(&p->list); | |
592 | kfree(p); | |
593 | } | |
594 | mutex_unlock(&pdev_list_mutex); | |
595 | platform_driver_unregister(&coretemp_driver); | |
596 | } | |
597 | ||
598 | MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>"); | |
599 | MODULE_DESCRIPTION("Intel Core temperature monitor"); | |
600 | MODULE_LICENSE("GPL"); | |
601 | ||
602 | module_init(coretemp_init) | |
603 | module_exit(coretemp_exit) |