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hwmon: (ibmpex) Allow format string checking
[deliverable/linux.git] / drivers / hwmon / it87.c
CommitLineData
1da177e4 1/*
5f2dc798
JD		 2 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
3 * monitoring.
4 *
5 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
6 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
7 * addition to an Environment Controller (Enhanced Hardware Monitor and
8 * Fan Controller)
9 *
10 * This driver supports only the Environment Controller in the IT8705F and
11 * similar parts. The other devices are supported by different drivers.
12 *
c145d5c6 13 * Supports: IT8603E Super I/O chip w/LPC interface
574e9bd8 14 * IT8623E Super I/O chip w/LPC interface
c145d5c6 15 * IT8705F Super I/O chip w/LPC interface
5f2dc798
JD		 16 * IT8712F Super I/O chip w/LPC interface
17 * IT8716F Super I/O chip w/LPC interface
18 * IT8718F Super I/O chip w/LPC interface
19 * IT8720F Super I/O chip w/LPC interface
44c1bcd4 20 * IT8721F Super I/O chip w/LPC interface
5f2dc798 21 * IT8726F Super I/O chip w/LPC interface
16b5dda2 22 * IT8728F Super I/O chip w/LPC interface
44c1bcd4 23 * IT8758E Super I/O chip w/LPC interface
b0636707
GR		 24 * IT8771E Super I/O chip w/LPC interface
25 * IT8772E Super I/O chip w/LPC interface
0531d98b
GR		 26 * IT8782F Super I/O chip w/LPC interface
27 * IT8783E/F Super I/O chip w/LPC interface
5f2dc798
JD		 28 * Sis950 A clone of the IT8705F
29 *
30 * Copyright (C) 2001 Chris Gauthron
7c81c60f 31 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
5f2dc798
JD		 32 *
33 * This program is free software; you can redistribute it and/or modify
34 * it under the terms of the GNU General Public License as published by
35 * the Free Software Foundation; either version 2 of the License, or
36 * (at your option) any later version.
37 *
38 * This program is distributed in the hope that it will be useful,
39 * but WITHOUT ANY WARRANTY; without even the implied warranty of
40 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
41 * GNU General Public License for more details.
42 *
43 * You should have received a copy of the GNU General Public License
44 * along with this program; if not, write to the Free Software
45 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
46 */
1da177e4 47
a8ca1037
JP		 48#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
1da177e4
LT		 50#include <linux/module.h>
51#include <linux/init.h>
52#include <linux/slab.h>
53#include <linux/jiffies.h>
b74f3fdd 54#include <linux/platform_device.h>
943b0830 55#include <linux/hwmon.h>
303760b4
JD		 56#include <linux/hwmon-sysfs.h>
57#include <linux/hwmon-vid.h>
943b0830 58#include <linux/err.h>
9a61bf63 59#include <linux/mutex.h>
87808be4 60#include <linux/sysfs.h>
98dd22c3
JD		 61#include <linux/string.h>
62#include <linux/dmi.h>
b9acb64a 63#include <linux/acpi.h>
6055fae8 64#include <linux/io.h>
1da177e4 65
b74f3fdd 66#define DRVNAME "it87"
1da177e4 67
b0636707 68enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8771,
c145d5c6 69 it8772, it8782, it8783, it8603 };
1da177e4 70
67b671bc
JD		 71static unsigned short force_id;
72module_param(force_id, ushort, 0);
73MODULE_PARM_DESC(force_id, "Override the detected device ID");
74
b74f3fdd 75static struct platform_device *pdev;
76
1da177e4
LT		 77#define REG 0x2e /* The register to read/write */
78#define DEV 0x07 /* Register: Logical device select */
79#define VAL 0x2f /* The value to read/write */
80#define PME 0x04 /* The device with the fan registers in it */
b4da93e4
JMS		 81
82/* The device with the IT8718F/IT8720F VID value in it */
83#define GPIO 0x07
84
1da177e4
LT		 85#define DEVID 0x20 /* Register: Device ID */
86#define DEVREV 0x22 /* Register: Device Revision */
87
5b0380c9 88static inline int superio_inb(int reg)
1da177e4
LT		 89{
90 outb(reg, REG);
91 return inb(VAL);
92}
93
5b0380c9 94static inline void superio_outb(int reg, int val)
436cad2a
JD		 95{
96 outb(reg, REG);
97 outb(val, VAL);
98}
99
1da177e4
LT		 100static int superio_inw(int reg)
101{
102 int val;
103 outb(reg++, REG);
104 val = inb(VAL) << 8;
105 outb(reg, REG);
106 val |= inb(VAL);
107 return val;
108}
109
5b0380c9 110static inline void superio_select(int ldn)
1da177e4
LT		 111{
112 outb(DEV, REG);
87673dd7 113 outb(ldn, VAL);
1da177e4
LT		 114}
115
5b0380c9 116static inline int superio_enter(void)
1da177e4 117{
5b0380c9
NG		 118 /*
119 * Try to reserve REG and REG + 1 for exclusive access.
120 */
121 if (!request_muxed_region(REG, 2, DRVNAME))
122 return -EBUSY;
123
1da177e4
LT		 124 outb(0x87, REG);
125 outb(0x01, REG);
126 outb(0x55, REG);
127 outb(0x55, REG);
5b0380c9 128 return 0;
1da177e4
LT		 129}
130
5b0380c9 131static inline void superio_exit(void)
1da177e4
LT		 132{
133 outb(0x02, REG);
134 outb(0x02, VAL);
5b0380c9 135 release_region(REG, 2);
1da177e4
LT		 136}
137
87673dd7 138/* Logical device 4 registers */
1da177e4
LT		 139#define IT8712F_DEVID 0x8712
140#define IT8705F_DEVID 0x8705
17d648bf 141#define IT8716F_DEVID 0x8716
87673dd7 142#define IT8718F_DEVID 0x8718
b4da93e4 143#define IT8720F_DEVID 0x8720
44c1bcd4 144#define IT8721F_DEVID 0x8721
08a8f6e9 145#define IT8726F_DEVID 0x8726
16b5dda2 146#define IT8728F_DEVID 0x8728
b0636707
GR		 147#define IT8771E_DEVID 0x8771
148#define IT8772E_DEVID 0x8772
0531d98b
GR		 149#define IT8782F_DEVID 0x8782
150#define IT8783E_DEVID 0x8783
7183ae8c 151#define IT8603E_DEVID 0x8603
574e9bd8 152#define IT8623E_DEVID 0x8623
1da177e4
LT		 153#define IT87_ACT_REG 0x30
154#define IT87_BASE_REG 0x60
155
87673dd7 156/* Logical device 7 registers (IT8712F and later) */
0531d98b 157#define IT87_SIO_GPIO1_REG 0x25
895ff267 158#define IT87_SIO_GPIO3_REG 0x27
591ec650 159#define IT87_SIO_GPIO5_REG 0x29
0531d98b 160#define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
87673dd7 161#define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
0531d98b 162#define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
87673dd7 163#define IT87_SIO_VID_REG 0xfc /* VID value */
d9b327c3 164#define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
87673dd7 165
1da177e4 166/* Update battery voltage after every reading if true */
90ab5ee9 167static bool update_vbat;
1da177e4
LT		 168
169/* Not all BIOSes properly configure the PWM registers */
90ab5ee9 170static bool fix_pwm_polarity;
1da177e4 171
1da177e4
LT		 172/* Many IT87 constants specified below */
173
174/* Length of ISA address segment */
175#define IT87_EXTENT 8
176
87b4b663
BH		 177/* Length of ISA address segment for Environmental Controller */
178#define IT87_EC_EXTENT 2
179
180/* Offset of EC registers from ISA base address */
181#define IT87_EC_OFFSET 5
182
183/* Where are the ISA address/data registers relative to the EC base address */
184#define IT87_ADDR_REG_OFFSET 0
185#define IT87_DATA_REG_OFFSET 1
1da177e4
LT		 186
187/*----- The IT87 registers -----*/
188
189#define IT87_REG_CONFIG 0x00
190
191#define IT87_REG_ALARM1 0x01
192#define IT87_REG_ALARM2 0x02
193#define IT87_REG_ALARM3 0x03
194
4a0d71cf
GR		 195/*
196 * The IT8718F and IT8720F have the VID value in a different register, in
197 * Super-I/O configuration space.
198 */
1da177e4 199#define IT87_REG_VID 0x0a
4a0d71cf
GR		 200/*
201 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
202 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
203 * mode.
204 */
1da177e4 205#define IT87_REG_FAN_DIV 0x0b
17d648bf 206#define IT87_REG_FAN_16BIT 0x0c
1da177e4
LT		 207
208/* Monitors: 9 voltage (0 to 7, battery), 3 temp (1 to 3), 3 fan (1 to 3) */
209
c7f1f716
JD		 210static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82 };
211static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86 };
212static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83 };
213static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87 };
161d898a
GR		 214static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 };
215
1da177e4
LT		 216#define IT87_REG_FAN_MAIN_CTRL 0x13
217#define IT87_REG_FAN_CTL 0x14
218#define IT87_REG_PWM(nr) (0x15 + (nr))
6229cdb2 219#define IT87_REG_PWM_DUTY(nr) (0x63 + (nr) * 8)
1da177e4
LT		 220
221#define IT87_REG_VIN(nr) (0x20 + (nr))
222#define IT87_REG_TEMP(nr) (0x29 + (nr))
223
224#define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
225#define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
226#define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2)
227#define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2)
228
1da177e4
LT		 229#define IT87_REG_VIN_ENABLE 0x50
230#define IT87_REG_TEMP_ENABLE 0x51
4573acbc 231#define IT87_REG_TEMP_EXTRA 0x55
d9b327c3 232#define IT87_REG_BEEP_ENABLE 0x5c
1da177e4
LT		 233
234#define IT87_REG_CHIPID 0x58
235
4f3f51bc
JD		 236#define IT87_REG_AUTO_TEMP(nr, i) (0x60 + (nr) * 8 + (i))
237#define IT87_REG_AUTO_PWM(nr, i) (0x65 + (nr) * 8 + (i))
238
483db43e
GR		 239struct it87_devices {
240 const char *name;
241 u16 features;
19529784
GR		 242 u8 peci_mask;
243 u8 old_peci_mask;
483db43e
GR		 244};
245
246#define FEAT_12MV_ADC (1 << 0)
247#define FEAT_NEWER_AUTOPWM (1 << 1)
248#define FEAT_OLD_AUTOPWM (1 << 2)
249#define FEAT_16BIT_FANS (1 << 3)
250#define FEAT_TEMP_OFFSET (1 << 4)
5d8d2f2b 251#define FEAT_TEMP_PECI (1 << 5)
19529784 252#define FEAT_TEMP_OLD_PECI (1 << 6)
483db43e
GR		 253
254static const struct it87_devices it87_devices[] = {
255 [it87] = {
256 .name = "it87",
257 .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
258 },
259 [it8712] = {
260 .name = "it8712",
261 .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
262 },
263 [it8716] = {
264 .name = "it8716",
265 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET,
266 },
267 [it8718] = {
268 .name = "it8718",
19529784
GR		 269 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
270 | FEAT_TEMP_OLD_PECI,
271 .old_peci_mask = 0x4,
483db43e
GR		 272 },
273 [it8720] = {
274 .name = "it8720",
19529784
GR		 275 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
276 | FEAT_TEMP_OLD_PECI,
277 .old_peci_mask = 0x4,
483db43e
GR		 278 },
279 [it8721] = {
280 .name = "it8721",
281 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
19529784 282 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI,
5d8d2f2b 283 .peci_mask = 0x05,
19529784 284 .old_peci_mask = 0x02, /* Actually reports PCH */
483db43e
GR		 285 },
286 [it8728] = {
287 .name = "it8728",
288 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
5d8d2f2b
GR		 289 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI,
290 .peci_mask = 0x07,
483db43e 291 },
b0636707
GR		 292 [it8771] = {
293 .name = "it8771",
294 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
295 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI,
296 /* PECI: guesswork */
297 /* 12mV ADC (OHM) */
298 /* 16 bit fans (OHM) */
299 .peci_mask = 0x07,
300 },
301 [it8772] = {
302 .name = "it8772",
303 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
304 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI,
305 /* PECI (coreboot) */
306 /* 12mV ADC (HWSensors4, OHM) */
307 /* 16 bit fans (HWSensors4, OHM) */
308 .peci_mask = 0x07,
309 },
483db43e
GR		 310 [it8782] = {
311 .name = "it8782",
19529784
GR		 312 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
313 | FEAT_TEMP_OLD_PECI,
314 .old_peci_mask = 0x4,
483db43e
GR		 315 },
316 [it8783] = {
317 .name = "it8783",
19529784
GR		 318 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
319 | FEAT_TEMP_OLD_PECI,
320 .old_peci_mask = 0x4,
483db43e 321 },
c145d5c6
RM		 322 [it8603] = {
323 .name = "it8603",
324 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
325 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI,
326 .peci_mask = 0x07,
327 },
483db43e
GR		 328};
329
330#define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
331#define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
332#define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
333#define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
334#define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET)
5d8d2f2b
GR		 335#define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
336 ((data)->peci_mask & (1 << nr)))
19529784
GR		 337#define has_temp_old_peci(data, nr) \
338 (((data)->features & FEAT_TEMP_OLD_PECI) && \
339 ((data)->old_peci_mask & (1 << nr)))
1da177e4 340
b74f3fdd 341struct it87_sio_data {
342 enum chips type;
343 /* Values read from Super-I/O config space */
0475169c 344 u8 revision;
b74f3fdd 345 u8 vid_value;
d9b327c3 346 u8 beep_pin;
738e5e05 347 u8 internal; /* Internal sensors can be labeled */
591ec650 348 /* Features skipped based on config or DMI */
9172b5d1 349 u16 skip_in;
895ff267 350 u8 skip_vid;
591ec650 351 u8 skip_fan;
98dd22c3 352 u8 skip_pwm;
4573acbc 353 u8 skip_temp;
b74f3fdd 354};
355
4a0d71cf
GR		 356/*
357 * For each registered chip, we need to keep some data in memory.
358 * The structure is dynamically allocated.
359 */
1da177e4 360struct it87_data {
1beeffe4 361 struct device *hwmon_dev;
1da177e4 362 enum chips type;
483db43e 363 u16 features;
19529784
GR		 364 u8 peci_mask;
365 u8 old_peci_mask;
1da177e4 366
b74f3fdd 367 unsigned short addr;
368 const char *name;
9a61bf63 369 struct mutex update_lock;
1da177e4
LT		 370 char valid; /* !=0 if following fields are valid */
371 unsigned long last_updated; /* In jiffies */
372
44c1bcd4 373 u16 in_scaled; /* Internal voltage sensors are scaled */
c145d5c6 374 u8 in[10][3]; /* [nr][0]=in, [1]=min, [2]=max */
9060f8bd 375 u8 has_fan; /* Bitfield, fans enabled */
e1169ba0 376 u16 fan[5][2]; /* Register values, [nr][0]=fan, [1]=min */
4573acbc 377 u8 has_temp; /* Bitfield, temp sensors enabled */
161d898a 378 s8 temp[3][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
19529784
GR		 379 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
380 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
1da177e4
LT		 381 u8 fan_div[3]; /* Register encoding, shifted right */
382 u8 vid; /* Register encoding, combined */
a7be58a1 383 u8 vrm;
1da177e4 384 u32 alarms; /* Register encoding, combined */
d9b327c3 385 u8 beeps; /* Register encoding */
1da177e4 386 u8 fan_main_ctrl; /* Register value */
f8d0c19a 387 u8 fan_ctl; /* Register value */
b99883dc 388
4a0d71cf
GR		 389 /*
390 * The following 3 arrays correspond to the same registers up to
6229cdb2
JD		 391 * the IT8720F. The meaning of bits 6-0 depends on the value of bit
392 * 7, and we want to preserve settings on mode changes, so we have
393 * to track all values separately.
394 * Starting with the IT8721F, the manual PWM duty cycles are stored
395 * in separate registers (8-bit values), so the separate tracking
396 * is no longer needed, but it is still done to keep the driver
4a0d71cf
GR		 397 * simple.
398 */
b99883dc 399 u8 pwm_ctrl[3]; /* Register value */
6229cdb2 400 u8 pwm_duty[3]; /* Manual PWM value set by user */
b99883dc 401 u8 pwm_temp_map[3]; /* PWM to temp. chan. mapping (bits 1-0) */
4f3f51bc
JD		 402
403 /* Automatic fan speed control registers */
404 u8 auto_pwm[3][4]; /* [nr][3] is hard-coded */
405 s8 auto_temp[3][5]; /* [nr][0] is point1_temp_hyst */
1da177e4 406};
0df6454d 407
0531d98b 408static int adc_lsb(const struct it87_data *data, int nr)
44c1bcd4 409{
0531d98b
GR		 410 int lsb = has_12mv_adc(data) ? 12 : 16;
411 if (data->in_scaled & (1 << nr))
412 lsb <<= 1;
413 return lsb;
414}
44c1bcd4 415
0531d98b
GR		 416static u8 in_to_reg(const struct it87_data *data, int nr, long val)
417{
418 val = DIV_ROUND_CLOSEST(val, adc_lsb(data, nr));
2a844c14 419 return clamp_val(val, 0, 255);
44c1bcd4
JD		 420}
421
422static int in_from_reg(const struct it87_data *data, int nr, int val)
423{
0531d98b 424 return val * adc_lsb(data, nr);
44c1bcd4 425}
0df6454d
JD		 426
427static inline u8 FAN_TO_REG(long rpm, int div)
428{
429 if (rpm == 0)
430 return 255;
2a844c14
GR		 431 rpm = clamp_val(rpm, 1, 1000000);
432 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
0df6454d
JD		 433}
434
435static inline u16 FAN16_TO_REG(long rpm)
436{
437 if (rpm == 0)
438 return 0xffff;
2a844c14 439 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
0df6454d
JD		 440}
441
442#define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
443 1350000 / ((val) * (div)))
444/* The divider is fixed to 2 in 16-bit mode */
445#define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
446 1350000 / ((val) * 2))
447
2a844c14
GR		 448#define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
449 ((val) + 500) / 1000), -128, 127))
0df6454d
JD		 450#define TEMP_FROM_REG(val) ((val) * 1000)
451
44c1bcd4
JD		 452static u8 pwm_to_reg(const struct it87_data *data, long val)
453{
16b5dda2 454 if (has_newer_autopwm(data))
44c1bcd4
JD		 455 return val;
456 else
457 return val >> 1;
458}
459
460static int pwm_from_reg(const struct it87_data *data, u8 reg)
461{
16b5dda2 462 if (has_newer_autopwm(data))
44c1bcd4
JD		 463 return reg;
464 else
465 return (reg & 0x7f) << 1;
466}
467
0df6454d
JD		 468
469static int DIV_TO_REG(int val)
470{
471 int answer = 0;
472 while (answer < 7 && (val >>= 1))
473 answer++;
474 return answer;
475}
476#define DIV_FROM_REG(val) (1 << (val))
477
478static const unsigned int pwm_freq[8] = {
479 48000000 / 128,
480 24000000 / 128,
481 12000000 / 128,
482 8000000 / 128,
483 6000000 / 128,
484 3000000 / 128,
485 1500000 / 128,
486 750000 / 128,
487};
1da177e4 488
b74f3fdd 489static int it87_probe(struct platform_device *pdev);
281dfd0b 490static int it87_remove(struct platform_device *pdev);
1da177e4 491
b74f3fdd 492static int it87_read_value(struct it87_data *data, u8 reg);
493static void it87_write_value(struct it87_data *data, u8 reg, u8 value);
1da177e4 494static struct it87_data *it87_update_device(struct device *dev);
b74f3fdd 495static int it87_check_pwm(struct device *dev);
496static void it87_init_device(struct platform_device *pdev);
1da177e4
LT		 497
498
b74f3fdd 499static struct platform_driver it87_driver = {
cdaf7934 500 .driver = {
b74f3fdd 501 .name = DRVNAME,
cdaf7934 502 },
b74f3fdd 503 .probe = it87_probe,
9e5e9b7a 504 .remove = it87_remove,
fde09509
JD		 505};
506
20ad93d4 507static ssize_t show_in(struct device *dev, struct device_attribute *attr,
929c6a56 508 char *buf)
1da177e4 509{
929c6a56
GR		 510 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
511 int nr = sattr->nr;
512 int index = sattr->index;
20ad93d4 513
1da177e4 514 struct it87_data *data = it87_update_device(dev);
929c6a56 515 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1da177e4
LT		 516}
517
929c6a56
GR		 518static ssize_t set_in(struct device *dev, struct device_attribute *attr,
519 const char *buf, size_t count)
1da177e4 520{
929c6a56
GR		 521 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
522 int nr = sattr->nr;
523 int index = sattr->index;
20ad93d4 524
b74f3fdd 525 struct it87_data *data = dev_get_drvdata(dev);
f5f64501
JD		 526 unsigned long val;
527
179c4fdb 528 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 529 return -EINVAL;
1da177e4 530
9a61bf63 531 mutex_lock(&data->update_lock);
929c6a56
GR		 532 data->in[nr][index] = in_to_reg(data, nr, val);
533 it87_write_value(data,
534 index == 1 ? IT87_REG_VIN_MIN(nr)
535 : IT87_REG_VIN_MAX(nr),
536 data->in[nr][index]);
9a61bf63 537 mutex_unlock(&data->update_lock);
1da177e4
LT		 538 return count;
539}
20ad93d4 540
929c6a56
GR		 541static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
542static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
543 0, 1);
544static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
545 0, 2);
f5f64501 546
929c6a56
GR		 547static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
548static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
549 1, 1);
550static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
551 1, 2);
1da177e4 552
929c6a56
GR		 553static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
554static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
555 2, 1);
556static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
557 2, 2);
1da177e4 558
929c6a56
GR		 559static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
560static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
561 3, 1);
562static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
563 3, 2);
564
565static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
566static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
567 4, 1);
568static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
569 4, 2);
570
571static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
572static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
573 5, 1);
574static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
575 5, 2);
576
577static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
578static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
579 6, 1);
580static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
581 6, 2);
582
583static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
584static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
585 7, 1);
586static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
587 7, 2);
588
589static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
c145d5c6 590static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1da177e4
LT		 591
592/* 3 temperatures */
20ad93d4 593static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
60ca385a 594 char *buf)
1da177e4 595{
60ca385a
GR		 596 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
597 int nr = sattr->nr;
598 int index = sattr->index;
1da177e4 599 struct it87_data *data = it87_update_device(dev);
20ad93d4 600
60ca385a 601 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1da177e4 602}
20ad93d4 603
60ca385a
GR		 604static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
605 const char *buf, size_t count)
1da177e4 606{
60ca385a
GR		 607 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
608 int nr = sattr->nr;
609 int index = sattr->index;
b74f3fdd 610 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 611 long val;
161d898a 612 u8 reg, regval;
f5f64501 613
179c4fdb 614 if (kstrtol(buf, 10, &val) < 0)
f5f64501 615 return -EINVAL;
1da177e4 616
9a61bf63 617 mutex_lock(&data->update_lock);
161d898a
GR		 618
619 switch (index) {
620 default:
621 case 1:
622 reg = IT87_REG_TEMP_LOW(nr);
623 break;
624 case 2:
625 reg = IT87_REG_TEMP_HIGH(nr);
626 break;
627 case 3:
628 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
629 if (!(regval & 0x80)) {
630 regval |= 0x80;
631 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
632 }
633 data->valid = 0;
634 reg = IT87_REG_TEMP_OFFSET[nr];
635 break;
636 }
637
60ca385a 638 data->temp[nr][index] = TEMP_TO_REG(val);
161d898a 639 it87_write_value(data, reg, data->temp[nr][index]);
9a61bf63 640 mutex_unlock(&data->update_lock);
1da177e4
LT		 641 return count;
642}
1da177e4 643
60ca385a
GR		 644static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
645static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
646 0, 1);
647static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
648 0, 2);
161d898a
GR		 649static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
650 set_temp, 0, 3);
60ca385a
GR		 651static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
652static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
653 1, 1);
654static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
655 1, 2);
161d898a
GR		 656static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
657 set_temp, 1, 3);
60ca385a
GR		 658static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
659static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
660 2, 1);
661static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
662 2, 2);
161d898a
GR		 663static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
664 set_temp, 2, 3);
1da177e4 665
2cece01f
GR		 666static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
667 char *buf)
1da177e4 668{
20ad93d4
JD		 669 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
670 int nr = sensor_attr->index;
1da177e4 671 struct it87_data *data = it87_update_device(dev);
4a0d71cf 672 u8 reg = data->sensor; /* In case value is updated while used */
19529784 673 u8 extra = data->extra;
5f2dc798 674
19529784
GR		 675 if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1))
676 || (has_temp_old_peci(data, nr) && (extra & 0x80)))
5d8d2f2b 677 return sprintf(buf, "6\n"); /* Intel PECI */
1da177e4
LT		 678 if (reg & (1 << nr))
679 return sprintf(buf, "3\n"); /* thermal diode */
680 if (reg & (8 << nr))
4ed10779 681 return sprintf(buf, "4\n"); /* thermistor */
1da177e4
LT		 682 return sprintf(buf, "0\n"); /* disabled */
683}
2cece01f
GR		 684
685static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
686 const char *buf, size_t count)
1da177e4 687{
20ad93d4
JD		 688 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
689 int nr = sensor_attr->index;
690
b74f3fdd 691 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 692 long val;
19529784 693 u8 reg, extra;
f5f64501 694
179c4fdb 695 if (kstrtol(buf, 10, &val) < 0)
f5f64501 696 return -EINVAL;
1da177e4 697
8acf07c5
JD		 698 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
699 reg &= ~(1 << nr);
700 reg &= ~(8 << nr);
5d8d2f2b
GR		 701 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
702 reg &= 0x3f;
19529784
GR		 703 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
704 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
705 extra &= 0x7f;
4ed10779 706 if (val == 2) { /* backwards compatibility */
1d9bcf6a
GR		 707 dev_warn(dev,
708 "Sensor type 2 is deprecated, please use 4 instead\n");
4ed10779
JD		 709 val = 4;
710 }
5d8d2f2b 711 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1da177e4 712 if (val == 3)
8acf07c5 713 reg |= 1 << nr;
4ed10779 714 else if (val == 4)
8acf07c5 715 reg |= 8 << nr;
5d8d2f2b
GR		 716 else if (has_temp_peci(data, nr) && val == 6)
717 reg |= (nr + 1) << 6;
19529784
GR		 718 else if (has_temp_old_peci(data, nr) && val == 6)
719 extra |= 0x80;
8acf07c5 720 else if (val != 0)
1da177e4 721 return -EINVAL;
8acf07c5
JD		 722
723 mutex_lock(&data->update_lock);
724 data->sensor = reg;
19529784 725 data->extra = extra;
b74f3fdd 726 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
19529784
GR		 727 if (has_temp_old_peci(data, nr))
728 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
2b3d1d87 729 data->valid = 0; /* Force cache refresh */
9a61bf63 730 mutex_unlock(&data->update_lock);
1da177e4
LT		 731 return count;
732}
1da177e4 733
2cece01f
GR		 734static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
735 set_temp_type, 0);
736static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
737 set_temp_type, 1);
738static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
739 set_temp_type, 2);
1da177e4
LT		 740
741/* 3 Fans */
b99883dc
JD		 742
743static int pwm_mode(const struct it87_data *data, int nr)
744{
745 int ctrl = data->fan_main_ctrl & (1 << nr);
746
c145d5c6 747 if (ctrl == 0 && data->type != it8603) /* Full speed */
b99883dc
JD		 748 return 0;
749 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
750 return 2;
751 else /* Manual mode */
752 return 1;
753}
754
20ad93d4 755static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
e1169ba0 756 char *buf)
1da177e4 757{
e1169ba0
GR		 758 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
759 int nr = sattr->nr;
760 int index = sattr->index;
761 int speed;
1da177e4 762 struct it87_data *data = it87_update_device(dev);
20ad93d4 763
e1169ba0
GR		 764 speed = has_16bit_fans(data) ?
765 FAN16_FROM_REG(data->fan[nr][index]) :
766 FAN_FROM_REG(data->fan[nr][index],
767 DIV_FROM_REG(data->fan_div[nr]));
768 return sprintf(buf, "%d\n", speed);
1da177e4 769}
e1169ba0 770
20ad93d4
JD		 771static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
772 char *buf)
1da177e4 773{
20ad93d4
JD		 774 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
775 int nr = sensor_attr->index;
776
1da177e4
LT		 777 struct it87_data *data = it87_update_device(dev);
778 return sprintf(buf, "%d\n", DIV_FROM_REG(data->fan_div[nr]));
779}
5f2dc798
JD		 780static ssize_t show_pwm_enable(struct device *dev,
781 struct device_attribute *attr, char *buf)
1da177e4 782{
20ad93d4
JD		 783 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
784 int nr = sensor_attr->index;
785
1da177e4 786 struct it87_data *data = it87_update_device(dev);
b99883dc 787 return sprintf(buf, "%d\n", pwm_mode(data, nr));
1da177e4 788}
20ad93d4
JD		 789static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
790 char *buf)
1da177e4 791{
20ad93d4
JD		 792 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
793 int nr = sensor_attr->index;
794
1da177e4 795 struct it87_data *data = it87_update_device(dev);
44c1bcd4
JD		 796 return sprintf(buf, "%d\n",
797 pwm_from_reg(data, data->pwm_duty[nr]));
1da177e4 798}
f8d0c19a
JD		 799static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
800 char *buf)
801{
802 struct it87_data *data = it87_update_device(dev);
803 int index = (data->fan_ctl >> 4) & 0x07;
804
805 return sprintf(buf, "%u\n", pwm_freq[index]);
806}
e1169ba0
GR		 807
808static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
809 const char *buf, size_t count)
1da177e4 810{
e1169ba0
GR		 811 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
812 int nr = sattr->nr;
813 int index = sattr->index;
20ad93d4 814
b74f3fdd 815 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 816 long val;
7f999aa7 817 u8 reg;
1da177e4 818
179c4fdb 819 if (kstrtol(buf, 10, &val) < 0)
f5f64501
JD		 820 return -EINVAL;
821
9a61bf63 822 mutex_lock(&data->update_lock);
e1169ba0
GR		 823
824 if (has_16bit_fans(data)) {
825 data->fan[nr][index] = FAN16_TO_REG(val);
826 it87_write_value(data, IT87_REG_FAN_MIN[nr],
827 data->fan[nr][index] & 0xff);
828 it87_write_value(data, IT87_REG_FANX_MIN[nr],
829 data->fan[nr][index] >> 8);
830 } else {
831 reg = it87_read_value(data, IT87_REG_FAN_DIV);
832 switch (nr) {
833 case 0:
834 data->fan_div[nr] = reg & 0x07;
835 break;
836 case 1:
837 data->fan_div[nr] = (reg >> 3) & 0x07;
838 break;
839 case 2:
840 data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
841 break;
842 }
843 data->fan[nr][index] =
844 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
845 it87_write_value(data, IT87_REG_FAN_MIN[nr],
846 data->fan[nr][index]);
07eab46d
JD		 847 }
848
9a61bf63 849 mutex_unlock(&data->update_lock);
1da177e4
LT		 850 return count;
851}
e1169ba0 852
20ad93d4
JD		 853static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
854 const char *buf, size_t count)
1da177e4 855{
20ad93d4
JD		 856 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
857 int nr = sensor_attr->index;
858
b74f3fdd 859 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 860 unsigned long val;
8ab4ec3e 861 int min;
1da177e4
LT		 862 u8 old;
863
179c4fdb 864 if (kstrtoul(buf, 10, &val) < 0)
f5f64501
JD		 865 return -EINVAL;
866
9a61bf63 867 mutex_lock(&data->update_lock);
b74f3fdd 868 old = it87_read_value(data, IT87_REG_FAN_DIV);
1da177e4 869
8ab4ec3e 870 /* Save fan min limit */
e1169ba0 871 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1da177e4
LT		 872
873 switch (nr) {
874 case 0:
875 case 1:
876 data->fan_div[nr] = DIV_TO_REG(val);
877 break;
878 case 2:
879 if (val < 8)
880 data->fan_div[nr] = 1;
881 else
882 data->fan_div[nr] = 3;
883 }
884 val = old & 0x80;
885 val |= (data->fan_div[0] & 0x07);
886 val |= (data->fan_div[1] & 0x07) << 3;
887 if (data->fan_div[2] == 3)
888 val |= 0x1 << 6;
b74f3fdd 889 it87_write_value(data, IT87_REG_FAN_DIV, val);
1da177e4 890
8ab4ec3e 891 /* Restore fan min limit */
e1169ba0
GR		 892 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
893 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]);
8ab4ec3e 894
9a61bf63 895 mutex_unlock(&data->update_lock);
1da177e4
LT		 896 return count;
897}
cccfc9c4
JD		 898
899/* Returns 0 if OK, -EINVAL otherwise */
900static int check_trip_points(struct device *dev, int nr)
901{
902 const struct it87_data *data = dev_get_drvdata(dev);
903 int i, err = 0;
904
905 if (has_old_autopwm(data)) {
906 for (i = 0; i < 3; i++) {
907 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
908 err = -EINVAL;
909 }
910 for (i = 0; i < 2; i++) {
911 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
912 err = -EINVAL;
913 }
914 }
915
916 if (err) {
1d9bcf6a
GR		 917 dev_err(dev,
918 "Inconsistent trip points, not switching to automatic mode\n");
cccfc9c4
JD		 919 dev_err(dev, "Adjust the trip points and try again\n");
920 }
921 return err;
922}
923
20ad93d4
JD		 924static ssize_t set_pwm_enable(struct device *dev,
925 struct device_attribute *attr, const char *buf, size_t count)
1da177e4 926{
20ad93d4
JD		 927 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
928 int nr = sensor_attr->index;
929
b74f3fdd 930 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 931 long val;
1da177e4 932
179c4fdb 933 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
b99883dc
JD		 934 return -EINVAL;
935
cccfc9c4
JD		 936 /* Check trip points before switching to automatic mode */
937 if (val == 2) {
938 if (check_trip_points(dev, nr) < 0)
939 return -EINVAL;
940 }
941
c145d5c6
RM		 942 /* IT8603E does not have on/off mode */
943 if (val == 0 && data->type == it8603)
944 return -EINVAL;
945
9a61bf63 946 mutex_lock(&data->update_lock);
1da177e4
LT		 947
948 if (val == 0) {
949 int tmp;
950 /* make sure the fan is on when in on/off mode */
b74f3fdd 951 tmp = it87_read_value(data, IT87_REG_FAN_CTL);
952 it87_write_value(data, IT87_REG_FAN_CTL, tmp | (1 << nr));
1da177e4
LT		 953 /* set on/off mode */
954 data->fan_main_ctrl &= ~(1 << nr);
5f2dc798
JD		 955 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
956 data->fan_main_ctrl);
b99883dc
JD		 957 } else {
958 if (val == 1) /* Manual mode */
16b5dda2 959 data->pwm_ctrl[nr] = has_newer_autopwm(data) ?
6229cdb2
JD		 960 data->pwm_temp_map[nr] :
961 data->pwm_duty[nr];
b99883dc
JD		 962 else /* Automatic mode */
963 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
964 it87_write_value(data, IT87_REG_PWM(nr), data->pwm_ctrl[nr]);
c145d5c6
RM		 965
966 if (data->type != it8603) {
967 /* set SmartGuardian mode */
968 data->fan_main_ctrl |= (1 << nr);
969 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
970 data->fan_main_ctrl);
971 }
1da177e4
LT		 972 }
973
9a61bf63 974 mutex_unlock(&data->update_lock);
1da177e4
LT		 975 return count;
976}
20ad93d4
JD		 977static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
978 const char *buf, size_t count)
1da177e4 979{
20ad93d4
JD		 980 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
981 int nr = sensor_attr->index;
982
b74f3fdd 983 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 984 long val;
1da177e4 985
179c4fdb 986 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1da177e4
LT		 987 return -EINVAL;
988
9a61bf63 989 mutex_lock(&data->update_lock);
16b5dda2 990 if (has_newer_autopwm(data)) {
4a0d71cf
GR		 991 /*
992 * If we are in automatic mode, the PWM duty cycle register
993 * is read-only so we can't write the value.
994 */
6229cdb2
JD		 995 if (data->pwm_ctrl[nr] & 0x80) {
996 mutex_unlock(&data->update_lock);
997 return -EBUSY;
998 }
999 data->pwm_duty[nr] = pwm_to_reg(data, val);
1000 it87_write_value(data, IT87_REG_PWM_DUTY(nr),
1001 data->pwm_duty[nr]);
1002 } else {
1003 data->pwm_duty[nr] = pwm_to_reg(data, val);
4a0d71cf
GR		 1004 /*
1005 * If we are in manual mode, write the duty cycle immediately;
1006 * otherwise, just store it for later use.
1007 */
6229cdb2
JD		 1008 if (!(data->pwm_ctrl[nr] & 0x80)) {
1009 data->pwm_ctrl[nr] = data->pwm_duty[nr];
1010 it87_write_value(data, IT87_REG_PWM(nr),
1011 data->pwm_ctrl[nr]);
1012 }
b99883dc 1013 }
9a61bf63 1014 mutex_unlock(&data->update_lock);
1da177e4
LT		 1015 return count;
1016}
f8d0c19a
JD		 1017static ssize_t set_pwm_freq(struct device *dev,
1018 struct device_attribute *attr, const char *buf, size_t count)
1019{
b74f3fdd 1020 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 1021 unsigned long val;
f8d0c19a
JD		 1022 int i;
1023
179c4fdb 1024 if (kstrtoul(buf, 10, &val) < 0)
f5f64501
JD		 1025 return -EINVAL;
1026
f8d0c19a
JD		 1027 /* Search for the nearest available frequency */
1028 for (i = 0; i < 7; i++) {
1029 if (val > (pwm_freq[i] + pwm_freq[i+1]) / 2)
1030 break;
1031 }
1032
1033 mutex_lock(&data->update_lock);
b74f3fdd 1034 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
f8d0c19a 1035 data->fan_ctl |= i << 4;
b74f3fdd 1036 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
f8d0c19a
JD		 1037 mutex_unlock(&data->update_lock);
1038
1039 return count;
1040}
94ac7ee6
JD		 1041static ssize_t show_pwm_temp_map(struct device *dev,
1042 struct device_attribute *attr, char *buf)
1043{
1044 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1045 int nr = sensor_attr->index;
1046
1047 struct it87_data *data = it87_update_device(dev);
1048 int map;
1049
1050 if (data->pwm_temp_map[nr] < 3)
1051 map = 1 << data->pwm_temp_map[nr];
1052 else
1053 map = 0; /* Should never happen */
1054 return sprintf(buf, "%d\n", map);
1055}
1056static ssize_t set_pwm_temp_map(struct device *dev,
1057 struct device_attribute *attr, const char *buf, size_t count)
1058{
1059 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1060 int nr = sensor_attr->index;
1061
1062 struct it87_data *data = dev_get_drvdata(dev);
1063 long val;
1064 u8 reg;
1065
4a0d71cf
GR		 1066 /*
1067 * This check can go away if we ever support automatic fan speed
1068 * control on newer chips.
1069 */
4f3f51bc
JD		 1070 if (!has_old_autopwm(data)) {
1071 dev_notice(dev, "Mapping change disabled for safety reasons\n");
1072 return -EINVAL;
1073 }
1074
179c4fdb 1075 if (kstrtol(buf, 10, &val) < 0)
94ac7ee6
JD		 1076 return -EINVAL;
1077
1078 switch (val) {
1079 case (1 << 0):
1080 reg = 0x00;
1081 break;
1082 case (1 << 1):
1083 reg = 0x01;
1084 break;
1085 case (1 << 2):
1086 reg = 0x02;
1087 break;
1088 default:
1089 return -EINVAL;
1090 }
1091
1092 mutex_lock(&data->update_lock);
1093 data->pwm_temp_map[nr] = reg;
4a0d71cf
GR		 1094 /*
1095 * If we are in automatic mode, write the temp mapping immediately;
1096 * otherwise, just store it for later use.
1097 */
94ac7ee6
JD		 1098 if (data->pwm_ctrl[nr] & 0x80) {
1099 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
1100 it87_write_value(data, IT87_REG_PWM(nr), data->pwm_ctrl[nr]);
1101 }
1102 mutex_unlock(&data->update_lock);
1103 return count;
1104}
1da177e4 1105
4f3f51bc
JD		 1106static ssize_t show_auto_pwm(struct device *dev,
1107 struct device_attribute *attr, char *buf)
1108{
1109 struct it87_data *data = it87_update_device(dev);
1110 struct sensor_device_attribute_2 *sensor_attr =
1111 to_sensor_dev_attr_2(attr);
1112 int nr = sensor_attr->nr;
1113 int point = sensor_attr->index;
1114
44c1bcd4
JD		 1115 return sprintf(buf, "%d\n",
1116 pwm_from_reg(data, data->auto_pwm[nr][point]));
4f3f51bc
JD		 1117}
1118
1119static ssize_t set_auto_pwm(struct device *dev,
1120 struct device_attribute *attr, const char *buf, size_t count)
1121{
1122 struct it87_data *data = dev_get_drvdata(dev);
1123 struct sensor_device_attribute_2 *sensor_attr =
1124 to_sensor_dev_attr_2(attr);
1125 int nr = sensor_attr->nr;
1126 int point = sensor_attr->index;
1127 long val;
1128
179c4fdb 1129 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
4f3f51bc
JD		 1130 return -EINVAL;
1131
1132 mutex_lock(&data->update_lock);
44c1bcd4 1133 data->auto_pwm[nr][point] = pwm_to_reg(data, val);
4f3f51bc
JD		 1134 it87_write_value(data, IT87_REG_AUTO_PWM(nr, point),
1135 data->auto_pwm[nr][point]);
1136 mutex_unlock(&data->update_lock);
1137 return count;
1138}
1139
1140static ssize_t show_auto_temp(struct device *dev,
1141 struct device_attribute *attr, char *buf)
1142{
1143 struct it87_data *data = it87_update_device(dev);
1144 struct sensor_device_attribute_2 *sensor_attr =
1145 to_sensor_dev_attr_2(attr);
1146 int nr = sensor_attr->nr;
1147 int point = sensor_attr->index;
1148
1149 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->auto_temp[nr][point]));
1150}
1151
1152static ssize_t set_auto_temp(struct device *dev,
1153 struct device_attribute *attr, const char *buf, size_t count)
1154{
1155 struct it87_data *data = dev_get_drvdata(dev);
1156 struct sensor_device_attribute_2 *sensor_attr =
1157 to_sensor_dev_attr_2(attr);
1158 int nr = sensor_attr->nr;
1159 int point = sensor_attr->index;
1160 long val;
1161
179c4fdb 1162 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
4f3f51bc
JD		 1163 return -EINVAL;
1164
1165 mutex_lock(&data->update_lock);
1166 data->auto_temp[nr][point] = TEMP_TO_REG(val);
1167 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point),
1168 data->auto_temp[nr][point]);
1169 mutex_unlock(&data->update_lock);
1170 return count;
1171}
1172
e1169ba0
GR		 1173static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1174static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1175 0, 1);
1176static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1177 set_fan_div, 0);
1178
1179static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1180static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1181 1, 1);
1182static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1183 set_fan_div, 1);
1184
1185static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1186static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1187 2, 1);
1188static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1189 set_fan_div, 2);
1190
1191static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1192static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1193 3, 1);
1da177e4 1194
e1169ba0
GR		 1195static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1196static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1197 4, 1);
1da177e4 1198
c4458db3
GR		 1199static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
1200 show_pwm_enable, set_pwm_enable, 0);
1201static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
1202static DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq, set_pwm_freq);
1203static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO | S_IWUSR,
1204 show_pwm_temp_map, set_pwm_temp_map, 0);
1205static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
1206 show_auto_pwm, set_auto_pwm, 0, 0);
1207static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
1208 show_auto_pwm, set_auto_pwm, 0, 1);
1209static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
1210 show_auto_pwm, set_auto_pwm, 0, 2);
1211static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
1212 show_auto_pwm, NULL, 0, 3);
1213static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
1214 show_auto_temp, set_auto_temp, 0, 1);
1215static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1216 show_auto_temp, set_auto_temp, 0, 0);
1217static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
1218 show_auto_temp, set_auto_temp, 0, 2);
1219static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
1220 show_auto_temp, set_auto_temp, 0, 3);
1221static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
1222 show_auto_temp, set_auto_temp, 0, 4);
1223
1224static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
1225 show_pwm_enable, set_pwm_enable, 1);
1226static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
1227static DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, NULL);
1228static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO | S_IWUSR,
1229 show_pwm_temp_map, set_pwm_temp_map, 1);
1230static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
1231 show_auto_pwm, set_auto_pwm, 1, 0);
1232static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
1233 show_auto_pwm, set_auto_pwm, 1, 1);
1234static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
1235 show_auto_pwm, set_auto_pwm, 1, 2);
1236static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
1237 show_auto_pwm, NULL, 1, 3);
1238static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
1239 show_auto_temp, set_auto_temp, 1, 1);
1240static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1241 show_auto_temp, set_auto_temp, 1, 0);
1242static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
1243 show_auto_temp, set_auto_temp, 1, 2);
1244static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
1245 show_auto_temp, set_auto_temp, 1, 3);
1246static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
1247 show_auto_temp, set_auto_temp, 1, 4);
1248
1249static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
1250 show_pwm_enable, set_pwm_enable, 2);
1251static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
1252static DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL);
1253static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO | S_IWUSR,
1254 show_pwm_temp_map, set_pwm_temp_map, 2);
1255static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
1256 show_auto_pwm, set_auto_pwm, 2, 0);
1257static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
1258 show_auto_pwm, set_auto_pwm, 2, 1);
1259static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
1260 show_auto_pwm, set_auto_pwm, 2, 2);
1261static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
1262 show_auto_pwm, NULL, 2, 3);
1263static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
1264 show_auto_temp, set_auto_temp, 2, 1);
1265static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1266 show_auto_temp, set_auto_temp, 2, 0);
1267static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
1268 show_auto_temp, set_auto_temp, 2, 2);
1269static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
1270 show_auto_temp, set_auto_temp, 2, 3);
1271static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
1272 show_auto_temp, set_auto_temp, 2, 4);
1da177e4
LT		 1273
1274/* Alarms */
5f2dc798
JD		 1275static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
1276 char *buf)
1da177e4
LT		 1277{
1278 struct it87_data *data = it87_update_device(dev);
68188ba7 1279 return sprintf(buf, "%u\n", data->alarms);
1da177e4 1280}
1d66c64c 1281static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
1da177e4 1282
0124dd78
JD		 1283static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
1284 char *buf)
1285{
1286 int bitnr = to_sensor_dev_attr(attr)->index;
1287 struct it87_data *data = it87_update_device(dev);
1288 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
1289}
3d30f9e6
JD		 1290
1291static ssize_t clear_intrusion(struct device *dev, struct device_attribute
1292 *attr, const char *buf, size_t count)
1293{
1294 struct it87_data *data = dev_get_drvdata(dev);
1295 long val;
1296 int config;
1297
179c4fdb 1298 if (kstrtol(buf, 10, &val) < 0 || val != 0)
3d30f9e6
JD		 1299 return -EINVAL;
1300
1301 mutex_lock(&data->update_lock);
1302 config = it87_read_value(data, IT87_REG_CONFIG);
1303 if (config < 0) {
1304 count = config;
1305 } else {
1306 config |= 1 << 5;
1307 it87_write_value(data, IT87_REG_CONFIG, config);
1308 /* Invalidate cache to force re-read */
1309 data->valid = 0;
1310 }
1311 mutex_unlock(&data->update_lock);
1312
1313 return count;
1314}
1315
0124dd78
JD		 1316static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
1317static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
1318static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
1319static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
1320static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
1321static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
1322static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
1323static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
1324static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
1325static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
1326static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
1327static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
1328static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
1329static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
1330static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
1331static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
3d30f9e6
JD		 1332static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
1333 show_alarm, clear_intrusion, 4);
0124dd78 1334
d9b327c3
JD		 1335static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
1336 char *buf)
1337{
1338 int bitnr = to_sensor_dev_attr(attr)->index;
1339 struct it87_data *data = it87_update_device(dev);
1340 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
1341}
1342static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
1343 const char *buf, size_t count)
1344{
1345 int bitnr = to_sensor_dev_attr(attr)->index;
1346 struct it87_data *data = dev_get_drvdata(dev);
1347 long val;
1348
179c4fdb 1349 if (kstrtol(buf, 10, &val) < 0
d9b327c3
JD		 1350 || (val != 0 && val != 1))
1351 return -EINVAL;
1352
1353 mutex_lock(&data->update_lock);
1354 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1355 if (val)
1356 data->beeps |= (1 << bitnr);
1357 else
1358 data->beeps &= ~(1 << bitnr);
1359 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
1360 mutex_unlock(&data->update_lock);
1361 return count;
1362}
1363
1364static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
1365 show_beep, set_beep, 1);
1366static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
1367static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
1368static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
1369static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
1370static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
1371static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
1372static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
1373/* fanX_beep writability is set later */
1374static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
1375static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
1376static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
1377static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
1378static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
1379static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
1380 show_beep, set_beep, 2);
1381static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
1382static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
1383
5f2dc798
JD		 1384static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
1385 char *buf)
1da177e4 1386{
90d6619a 1387 struct it87_data *data = dev_get_drvdata(dev);
a7be58a1 1388 return sprintf(buf, "%u\n", data->vrm);
1da177e4 1389}
5f2dc798
JD		 1390static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
1391 const char *buf, size_t count)
1da177e4 1392{
b74f3fdd 1393 struct it87_data *data = dev_get_drvdata(dev);
f5f64501
JD		 1394 unsigned long val;
1395
179c4fdb 1396 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 1397 return -EINVAL;
1da177e4 1398
1da177e4
LT		 1399 data->vrm = val;
1400
1401 return count;
1402}
1403static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
1da177e4 1404
5f2dc798
JD		 1405static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
1406 char *buf)
1da177e4
LT		 1407{
1408 struct it87_data *data = it87_update_device(dev);
1409 return sprintf(buf, "%ld\n", (long) vid_from_reg(data->vid, data->vrm));
1410}
1411static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
87808be4 1412
738e5e05
JD		 1413static ssize_t show_label(struct device *dev, struct device_attribute *attr,
1414 char *buf)
1415{
3c4c4971 1416 static const char * const labels[] = {
738e5e05
JD		 1417 "+5V",
1418 "5VSB",
1419 "Vbat",
1420 };
3c4c4971 1421 static const char * const labels_it8721[] = {
44c1bcd4
JD		 1422 "+3.3V",
1423 "3VSB",
1424 "Vbat",
1425 };
1426 struct it87_data *data = dev_get_drvdata(dev);
738e5e05
JD		 1427 int nr = to_sensor_dev_attr(attr)->index;
1428
16b5dda2
JD		 1429 return sprintf(buf, "%s\n", has_12mv_adc(data) ? labels_it8721[nr]
1430 : labels[nr]);
738e5e05
JD		 1431}
1432static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
1433static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
1434static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
7183ae8c 1435/* special AVCC3 IT8603E in9 */
c145d5c6 1436static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 0);
738e5e05 1437
b74f3fdd 1438static ssize_t show_name(struct device *dev, struct device_attribute
1439 *devattr, char *buf)
1440{
1441 struct it87_data *data = dev_get_drvdata(dev);
1442 return sprintf(buf, "%s\n", data->name);
1443}
1444static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
1445
c145d5c6 1446static struct attribute *it87_attributes_in[10][5] = {
9172b5d1 1447{
87808be4 1448 &sensor_dev_attr_in0_input.dev_attr.attr,
87808be4 1449 &sensor_dev_attr_in0_min.dev_attr.attr,
87808be4 1450 &sensor_dev_attr_in0_max.dev_attr.attr,
0124dd78 1451 &sensor_dev_attr_in0_alarm.dev_attr.attr,
9172b5d1
GR		 1452 NULL
1453}, {
1454 &sensor_dev_attr_in1_input.dev_attr.attr,
1455 &sensor_dev_attr_in1_min.dev_attr.attr,
1456 &sensor_dev_attr_in1_max.dev_attr.attr,
0124dd78 1457 &sensor_dev_attr_in1_alarm.dev_attr.attr,
9172b5d1
GR		 1458 NULL
1459}, {
1460 &sensor_dev_attr_in2_input.dev_attr.attr,
1461 &sensor_dev_attr_in2_min.dev_attr.attr,
1462 &sensor_dev_attr_in2_max.dev_attr.attr,
0124dd78 1463 &sensor_dev_attr_in2_alarm.dev_attr.attr,
9172b5d1
GR		 1464 NULL
1465}, {
1466 &sensor_dev_attr_in3_input.dev_attr.attr,
1467 &sensor_dev_attr_in3_min.dev_attr.attr,
1468 &sensor_dev_attr_in3_max.dev_attr.attr,
0124dd78 1469 &sensor_dev_attr_in3_alarm.dev_attr.attr,
9172b5d1
GR		 1470 NULL
1471}, {
1472 &sensor_dev_attr_in4_input.dev_attr.attr,
1473 &sensor_dev_attr_in4_min.dev_attr.attr,
1474 &sensor_dev_attr_in4_max.dev_attr.attr,
0124dd78 1475 &sensor_dev_attr_in4_alarm.dev_attr.attr,
9172b5d1
GR		 1476 NULL
1477}, {
1478 &sensor_dev_attr_in5_input.dev_attr.attr,
1479 &sensor_dev_attr_in5_min.dev_attr.attr,
1480 &sensor_dev_attr_in5_max.dev_attr.attr,
0124dd78 1481 &sensor_dev_attr_in5_alarm.dev_attr.attr,
9172b5d1
GR		 1482 NULL
1483}, {
1484 &sensor_dev_attr_in6_input.dev_attr.attr,
1485 &sensor_dev_attr_in6_min.dev_attr.attr,
1486 &sensor_dev_attr_in6_max.dev_attr.attr,
0124dd78 1487 &sensor_dev_attr_in6_alarm.dev_attr.attr,
9172b5d1
GR		 1488 NULL
1489}, {
1490 &sensor_dev_attr_in7_input.dev_attr.attr,
1491 &sensor_dev_attr_in7_min.dev_attr.attr,
1492 &sensor_dev_attr_in7_max.dev_attr.attr,
0124dd78 1493 &sensor_dev_attr_in7_alarm.dev_attr.attr,
9172b5d1
GR		 1494 NULL
1495}, {
1496 &sensor_dev_attr_in8_input.dev_attr.attr,
1497 NULL
c145d5c6
RM		 1498}, {
1499 &sensor_dev_attr_in9_input.dev_attr.attr,
1500 NULL
9172b5d1 1501} };
87808be4 1502
c145d5c6 1503static const struct attribute_group it87_group_in[10] = {
9172b5d1
GR		 1504 { .attrs = it87_attributes_in[0] },
1505 { .attrs = it87_attributes_in[1] },
1506 { .attrs = it87_attributes_in[2] },
1507 { .attrs = it87_attributes_in[3] },
1508 { .attrs = it87_attributes_in[4] },
1509 { .attrs = it87_attributes_in[5] },
1510 { .attrs = it87_attributes_in[6] },
1511 { .attrs = it87_attributes_in[7] },
1512 { .attrs = it87_attributes_in[8] },
c145d5c6 1513 { .attrs = it87_attributes_in[9] },
9172b5d1
GR		 1514};
1515
4573acbc
GR		 1516static struct attribute *it87_attributes_temp[3][6] = {
1517{
87808be4 1518 &sensor_dev_attr_temp1_input.dev_attr.attr,
87808be4 1519 &sensor_dev_attr_temp1_max.dev_attr.attr,
87808be4 1520 &sensor_dev_attr_temp1_min.dev_attr.attr,
87808be4 1521 &sensor_dev_attr_temp1_type.dev_attr.attr,
0124dd78 1522 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
4573acbc
GR		 1523 NULL
1524} , {
1525 &sensor_dev_attr_temp2_input.dev_attr.attr,
1526 &sensor_dev_attr_temp2_max.dev_attr.attr,
1527 &sensor_dev_attr_temp2_min.dev_attr.attr,
1528 &sensor_dev_attr_temp2_type.dev_attr.attr,
0124dd78 1529 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
4573acbc
GR		 1530 NULL
1531} , {
1532 &sensor_dev_attr_temp3_input.dev_attr.attr,
1533 &sensor_dev_attr_temp3_max.dev_attr.attr,
1534 &sensor_dev_attr_temp3_min.dev_attr.attr,
1535 &sensor_dev_attr_temp3_type.dev_attr.attr,
0124dd78 1536 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
4573acbc
GR		 1537 NULL
1538} };
1539
1540static const struct attribute_group it87_group_temp[3] = {
1541 { .attrs = it87_attributes_temp[0] },
1542 { .attrs = it87_attributes_temp[1] },
1543 { .attrs = it87_attributes_temp[2] },
1544};
87808be4 1545
161d898a
GR		 1546static struct attribute *it87_attributes_temp_offset[] = {
1547 &sensor_dev_attr_temp1_offset.dev_attr.attr,
1548 &sensor_dev_attr_temp2_offset.dev_attr.attr,
1549 &sensor_dev_attr_temp3_offset.dev_attr.attr,
1550};
1551
4573acbc 1552static struct attribute *it87_attributes[] = {
87808be4 1553 &dev_attr_alarms.attr,
3d30f9e6 1554 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
b74f3fdd 1555 &dev_attr_name.attr,
87808be4
JD		 1556 NULL
1557};
1558
1559static const struct attribute_group it87_group = {
1560 .attrs = it87_attributes,
1561};
1562
9172b5d1 1563static struct attribute *it87_attributes_in_beep[] = {
d9b327c3
JD		 1564 &sensor_dev_attr_in0_beep.dev_attr.attr,
1565 &sensor_dev_attr_in1_beep.dev_attr.attr,
1566 &sensor_dev_attr_in2_beep.dev_attr.attr,
1567 &sensor_dev_attr_in3_beep.dev_attr.attr,
1568 &sensor_dev_attr_in4_beep.dev_attr.attr,
1569 &sensor_dev_attr_in5_beep.dev_attr.attr,
1570 &sensor_dev_attr_in6_beep.dev_attr.attr,
1571 &sensor_dev_attr_in7_beep.dev_attr.attr,
c145d5c6
RM		 1572 NULL,
1573 NULL,
9172b5d1 1574};
d9b327c3 1575
4573acbc 1576static struct attribute *it87_attributes_temp_beep[] = {
d9b327c3
JD		 1577 &sensor_dev_attr_temp1_beep.dev_attr.attr,
1578 &sensor_dev_attr_temp2_beep.dev_attr.attr,
1579 &sensor_dev_attr_temp3_beep.dev_attr.attr,
d9b327c3
JD		 1580};
1581
e1169ba0
GR		 1582static struct attribute *it87_attributes_fan[5][3+1] = { {
1583 &sensor_dev_attr_fan1_input.dev_attr.attr,
1584 &sensor_dev_attr_fan1_min.dev_attr.attr,
723a0aa0
JD		 1585 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
1586 NULL
1587}, {
e1169ba0
GR		 1588 &sensor_dev_attr_fan2_input.dev_attr.attr,
1589 &sensor_dev_attr_fan2_min.dev_attr.attr,
723a0aa0
JD		 1590 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
1591 NULL
1592}, {
e1169ba0
GR		 1593 &sensor_dev_attr_fan3_input.dev_attr.attr,
1594 &sensor_dev_attr_fan3_min.dev_attr.attr,
723a0aa0
JD		 1595 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
1596 NULL
1597}, {
e1169ba0
GR		 1598 &sensor_dev_attr_fan4_input.dev_attr.attr,
1599 &sensor_dev_attr_fan4_min.dev_attr.attr,
723a0aa0
JD		 1600 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
1601 NULL
1602}, {
e1169ba0
GR		 1603 &sensor_dev_attr_fan5_input.dev_attr.attr,
1604 &sensor_dev_attr_fan5_min.dev_attr.attr,
723a0aa0
JD		 1605 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
1606 NULL
1607} };
1608
e1169ba0
GR		 1609static const struct attribute_group it87_group_fan[5] = {
1610 { .attrs = it87_attributes_fan[0] },
1611 { .attrs = it87_attributes_fan[1] },
1612 { .attrs = it87_attributes_fan[2] },
1613 { .attrs = it87_attributes_fan[3] },
1614 { .attrs = it87_attributes_fan[4] },
723a0aa0 1615};
87808be4 1616
e1169ba0 1617static const struct attribute *it87_attributes_fan_div[] = {
87808be4 1618 &sensor_dev_attr_fan1_div.dev_attr.attr,
87808be4 1619 &sensor_dev_attr_fan2_div.dev_attr.attr,
87808be4 1620 &sensor_dev_attr_fan3_div.dev_attr.attr,
723a0aa0
JD		 1621};
1622
723a0aa0 1623static struct attribute *it87_attributes_pwm[3][4+1] = { {
87808be4 1624 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
87808be4 1625 &sensor_dev_attr_pwm1.dev_attr.attr,
d5b0b5d6 1626 &dev_attr_pwm1_freq.attr,
94ac7ee6 1627 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
723a0aa0
JD		 1628 NULL
1629}, {
1630 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
1631 &sensor_dev_attr_pwm2.dev_attr.attr,
1632 &dev_attr_pwm2_freq.attr,
94ac7ee6 1633 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
723a0aa0
JD		 1634 NULL
1635}, {
1636 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
1637 &sensor_dev_attr_pwm3.dev_attr.attr,
1638 &dev_attr_pwm3_freq.attr,
94ac7ee6 1639 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
723a0aa0
JD		 1640 NULL
1641} };
87808be4 1642
723a0aa0
JD		 1643static const struct attribute_group it87_group_pwm[3] = {
1644 { .attrs = it87_attributes_pwm[0] },
1645 { .attrs = it87_attributes_pwm[1] },
1646 { .attrs = it87_attributes_pwm[2] },
1647};
1648
4f3f51bc
JD		 1649static struct attribute *it87_attributes_autopwm[3][9+1] = { {
1650 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
1651 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
1652 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
1653 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
1654 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
1655 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
1656 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
1657 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
1658 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
1659 NULL
1660}, {
1661 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
1662 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
1663 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
1664 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
1665 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
1666 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
1667 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
1668 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
1669 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
1670 NULL
1671}, {
1672 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
1673 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
1674 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
1675 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
1676 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
1677 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
1678 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
1679 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
1680 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
1681 NULL
1682} };
1683
1684static const struct attribute_group it87_group_autopwm[3] = {
1685 { .attrs = it87_attributes_autopwm[0] },
1686 { .attrs = it87_attributes_autopwm[1] },
1687 { .attrs = it87_attributes_autopwm[2] },
1688};
1689
d9b327c3
JD		 1690static struct attribute *it87_attributes_fan_beep[] = {
1691 &sensor_dev_attr_fan1_beep.dev_attr.attr,
1692 &sensor_dev_attr_fan2_beep.dev_attr.attr,
1693 &sensor_dev_attr_fan3_beep.dev_attr.attr,
1694 &sensor_dev_attr_fan4_beep.dev_attr.attr,
1695 &sensor_dev_attr_fan5_beep.dev_attr.attr,
1696};
1697
6a8d7acf 1698static struct attribute *it87_attributes_vid[] = {
87808be4
JD		 1699 &dev_attr_vrm.attr,
1700 &dev_attr_cpu0_vid.attr,
1701 NULL
1702};
1703
6a8d7acf
JD		 1704static const struct attribute_group it87_group_vid = {
1705 .attrs = it87_attributes_vid,
87808be4 1706};
1da177e4 1707
738e5e05
JD		 1708static struct attribute *it87_attributes_label[] = {
1709 &sensor_dev_attr_in3_label.dev_attr.attr,
1710 &sensor_dev_attr_in7_label.dev_attr.attr,
1711 &sensor_dev_attr_in8_label.dev_attr.attr,
c145d5c6 1712 &sensor_dev_attr_in9_label.dev_attr.attr,
738e5e05
JD		 1713 NULL
1714};
1715
1716static const struct attribute_group it87_group_label = {
fa8b6975 1717 .attrs = it87_attributes_label,
738e5e05
JD		 1718};
1719
2d8672c5 1720/* SuperIO detection - will change isa_address if a chip is found */
b74f3fdd 1721static int __init it87_find(unsigned short *address,
1722 struct it87_sio_data *sio_data)
1da177e4 1723{
5b0380c9 1724 int err;
b74f3fdd 1725 u16 chip_type;
98dd22c3 1726 const char *board_vendor, *board_name;
1da177e4 1727
5b0380c9
NG		 1728 err = superio_enter();
1729 if (err)
1730 return err;
1731
1732 err = -ENODEV;
67b671bc 1733 chip_type = force_id ? force_id : superio_inw(DEVID);
b74f3fdd 1734
1735 switch (chip_type) {
1736 case IT8705F_DEVID:
1737 sio_data->type = it87;
1738 break;
1739 case IT8712F_DEVID:
1740 sio_data->type = it8712;
1741 break;
1742 case IT8716F_DEVID:
1743 case IT8726F_DEVID:
1744 sio_data->type = it8716;
1745 break;
1746 case IT8718F_DEVID:
1747 sio_data->type = it8718;
1748 break;
b4da93e4
JMS		 1749 case IT8720F_DEVID:
1750 sio_data->type = it8720;
1751 break;
44c1bcd4
JD		 1752 case IT8721F_DEVID:
1753 sio_data->type = it8721;
1754 break;
16b5dda2
JD		 1755 case IT8728F_DEVID:
1756 sio_data->type = it8728;
1757 break;
b0636707
GR		 1758 case IT8771E_DEVID:
1759 sio_data->type = it8771;
1760 break;
1761 case IT8772E_DEVID:
1762 sio_data->type = it8772;
1763 break;
0531d98b
GR		 1764 case IT8782F_DEVID:
1765 sio_data->type = it8782;
1766 break;
1767 case IT8783E_DEVID:
1768 sio_data->type = it8783;
1769 break;
7183ae8c 1770 case IT8603E_DEVID:
574e9bd8 1771 case IT8623E_DEVID:
c145d5c6
RM		 1772 sio_data->type = it8603;
1773 break;
b74f3fdd 1774 case 0xffff: /* No device at all */
1775 goto exit;
1776 default:
a8ca1037 1777 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
b74f3fdd 1778 goto exit;
1779 }
1da177e4 1780
87673dd7 1781 superio_select(PME);
1da177e4 1782 if (!(superio_inb(IT87_ACT_REG) & 0x01)) {
a8ca1037 1783 pr_info("Device not activated, skipping\n");
1da177e4
LT		 1784 goto exit;
1785 }
1786
1787 *address = superio_inw(IT87_BASE_REG) & ~(IT87_EXTENT - 1);
1788 if (*address == 0) {
a8ca1037 1789 pr_info("Base address not set, skipping\n");
1da177e4
LT		 1790 goto exit;
1791 }
1792
1793 err = 0;
0475169c 1794 sio_data->revision = superio_inb(DEVREV) & 0x0f;
c145d5c6 1795 pr_info("Found IT%04x%c chip at 0x%x, revision %d\n", chip_type,
b523bb75 1796 chip_type == 0x8771 || chip_type == 0x8772 ||
c145d5c6
RM		 1797 chip_type == 0x8603 ? 'E' : 'F', *address,
1798 sio_data->revision);
1da177e4 1799
738e5e05
JD		 1800 /* in8 (Vbat) is always internal */
1801 sio_data->internal = (1 << 2);
c145d5c6
RM		 1802 /* Only the IT8603E has in9 */
1803 if (sio_data->type != it8603)
1804 sio_data->skip_in |= (1 << 9);
738e5e05 1805
87673dd7 1806 /* Read GPIO config and VID value from LDN 7 (GPIO) */
895ff267
JD		 1807 if (sio_data->type == it87) {
1808 /* The IT8705F doesn't have VID pins at all */
1809 sio_data->skip_vid = 1;
d9b327c3
JD		 1810
1811 /* The IT8705F has a different LD number for GPIO */
1812 superio_select(5);
1813 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
0531d98b 1814 } else if (sio_data->type == it8783) {
088ce2ac 1815 int reg25, reg27, reg2a, reg2c, regef;
0531d98b
GR		 1816
1817 sio_data->skip_vid = 1; /* No VID */
1818
1819 superio_select(GPIO);
1820
1821 reg25 = superio_inb(IT87_SIO_GPIO1_REG);
1822 reg27 = superio_inb(IT87_SIO_GPIO3_REG);
088ce2ac
GR		 1823 reg2a = superio_inb(IT87_SIO_PINX1_REG);
1824 reg2c = superio_inb(IT87_SIO_PINX2_REG);
1825 regef = superio_inb(IT87_SIO_SPI_REG);
0531d98b 1826
0531d98b 1827 /* Check if fan3 is there or not */
088ce2ac 1828 if ((reg27 & (1 << 0)) || !(reg2c & (1 << 2)))
0531d98b
GR		 1829 sio_data->skip_fan |= (1 << 2);
1830 if ((reg25 & (1 << 4))
088ce2ac 1831 || (!(reg2a & (1 << 1)) && (regef & (1 << 0))))
0531d98b
GR		 1832 sio_data->skip_pwm |= (1 << 2);
1833
1834 /* Check if fan2 is there or not */
1835 if (reg27 & (1 << 7))
1836 sio_data->skip_fan |= (1 << 1);
1837 if (reg27 & (1 << 3))
1838 sio_data->skip_pwm |= (1 << 1);
1839
1840 /* VIN5 */
088ce2ac 1841 if ((reg27 & (1 << 0)) || (reg2c & (1 << 2)))
9172b5d1 1842 sio_data->skip_in |= (1 << 5); /* No VIN5 */
0531d98b
GR		 1843
1844 /* VIN6 */
9172b5d1
GR		 1845 if (reg27 & (1 << 1))
1846 sio_data->skip_in |= (1 << 6); /* No VIN6 */
0531d98b
GR		 1847
1848 /*
1849 * VIN7
1850 * Does not depend on bit 2 of Reg2C, contrary to datasheet.
1851 */
9172b5d1
GR		 1852 if (reg27 & (1 << 2)) {
1853 /*
1854 * The data sheet is a bit unclear regarding the
1855 * internal voltage divider for VCCH5V. It says
1856 * "This bit enables and switches VIN7 (pin 91) to the
1857 * internal voltage divider for VCCH5V".
1858 * This is different to other chips, where the internal
1859 * voltage divider would connect VIN7 to an internal
1860 * voltage source. Maybe that is the case here as well.
1861 *
1862 * Since we don't know for sure, re-route it if that is
1863 * not the case, and ask the user to report if the
1864 * resulting voltage is sane.
1865 */
088ce2ac
GR		 1866 if (!(reg2c & (1 << 1))) {
1867 reg2c |= (1 << 1);
1868 superio_outb(IT87_SIO_PINX2_REG, reg2c);
9172b5d1
GR		 1869 pr_notice("Routing internal VCCH5V to in7.\n");
1870 }
1871 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
1872 pr_notice("Please report if it displays a reasonable voltage.\n");
1873 }
0531d98b 1874
088ce2ac 1875 if (reg2c & (1 << 0))
0531d98b 1876 sio_data->internal |= (1 << 0);
088ce2ac 1877 if (reg2c & (1 << 1))
0531d98b
GR		 1878 sio_data->internal |= (1 << 1);
1879
1880 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
c145d5c6
RM		 1881 } else if (sio_data->type == it8603) {
1882 int reg27, reg29;
1883
1884 sio_data->skip_vid = 1; /* No VID */
1885 superio_select(GPIO);
0531d98b 1886
c145d5c6
RM		 1887 reg27 = superio_inb(IT87_SIO_GPIO3_REG);
1888
1889 /* Check if fan3 is there or not */
1890 if (reg27 & (1 << 6))
1891 sio_data->skip_pwm |= (1 << 2);
1892 if (reg27 & (1 << 7))
1893 sio_data->skip_fan |= (1 << 2);
1894
1895 /* Check if fan2 is there or not */
1896 reg29 = superio_inb(IT87_SIO_GPIO5_REG);
1897 if (reg29 & (1 << 1))
1898 sio_data->skip_pwm |= (1 << 1);
1899 if (reg29 & (1 << 2))
1900 sio_data->skip_fan |= (1 << 1);
1901
1902 sio_data->skip_in |= (1 << 5); /* No VIN5 */
1903 sio_data->skip_in |= (1 << 6); /* No VIN6 */
1904
1905 /* no fan4 */
1906 sio_data->skip_pwm |= (1 << 3);
1907 sio_data->skip_fan |= (1 << 3);
1908
1909 sio_data->internal |= (1 << 1); /* in7 is VSB */
1910 sio_data->internal |= (1 << 3); /* in9 is AVCC */
1911
1912 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
895ff267 1913 } else {
87673dd7 1914 int reg;
9172b5d1 1915 bool uart6;
87673dd7
JD		 1916
1917 superio_select(GPIO);
44c1bcd4 1918
895ff267 1919 reg = superio_inb(IT87_SIO_GPIO3_REG);
0531d98b 1920 if (sio_data->type == it8721 || sio_data->type == it8728 ||
b0636707 1921 sio_data->type == it8771 || sio_data->type == it8772 ||
0531d98b 1922 sio_data->type == it8782) {
16b5dda2 1923 /*
0531d98b 1924 * IT8721F/IT8758E, and IT8782F don't have VID pins
b0636707 1925 * at all, not sure about the IT8728F and compatibles.
16b5dda2 1926 */
895ff267 1927 sio_data->skip_vid = 1;
44c1bcd4
JD		 1928 } else {
1929 /* We need at least 4 VID pins */
1930 if (reg & 0x0f) {
a8ca1037 1931 pr_info("VID is disabled (pins used for GPIO)\n");
44c1bcd4
JD		 1932 sio_data->skip_vid = 1;
1933 }
895ff267
JD		 1934 }
1935
591ec650
JD		 1936 /* Check if fan3 is there or not */
1937 if (reg & (1 << 6))
1938 sio_data->skip_pwm |= (1 << 2);
1939 if (reg & (1 << 7))
1940 sio_data->skip_fan |= (1 << 2);
1941
1942 /* Check if fan2 is there or not */
1943 reg = superio_inb(IT87_SIO_GPIO5_REG);
1944 if (reg & (1 << 1))
1945 sio_data->skip_pwm |= (1 << 1);
1946 if (reg & (1 << 2))
1947 sio_data->skip_fan |= (1 << 1);
1948
895ff267
JD		 1949 if ((sio_data->type == it8718 || sio_data->type == it8720)
1950 && !(sio_data->skip_vid))
b74f3fdd 1951 sio_data->vid_value = superio_inb(IT87_SIO_VID_REG);
87673dd7
JD		 1952
1953 reg = superio_inb(IT87_SIO_PINX2_REG);
9172b5d1
GR		 1954
1955 uart6 = sio_data->type == it8782 && (reg & (1 << 2));
1956
436cad2a
JD		 1957 /*
1958 * The IT8720F has no VIN7 pin, so VCCH should always be
1959 * routed internally to VIN7 with an internal divider.
1960 * Curiously, there still is a configuration bit to control
1961 * this, which means it can be set incorrectly. And even
1962 * more curiously, many boards out there are improperly
1963 * configured, even though the IT8720F datasheet claims
1964 * that the internal routing of VCCH to VIN7 is the default
1965 * setting. So we force the internal routing in this case.
0531d98b
GR		 1966 *
1967 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
9172b5d1
GR		 1968 * If UART6 is enabled, re-route VIN7 to the internal divider
1969 * if that is not already the case.
436cad2a 1970 */
9172b5d1 1971 if ((sio_data->type == it8720 || uart6) && !(reg & (1 << 1))) {
436cad2a
JD		 1972 reg |= (1 << 1);
1973 superio_outb(IT87_SIO_PINX2_REG, reg);
a8ca1037 1974 pr_notice("Routing internal VCCH to in7\n");
436cad2a 1975 }
87673dd7 1976 if (reg & (1 << 0))
738e5e05 1977 sio_data->internal |= (1 << 0);
16b5dda2 1978 if ((reg & (1 << 1)) || sio_data->type == it8721 ||
b0636707
GR		 1979 sio_data->type == it8728 ||
1980 sio_data->type == it8771 ||
1981 sio_data->type == it8772)
738e5e05 1982 sio_data->internal |= (1 << 1);
d9b327c3 1983
9172b5d1
GR		 1984 /*
1985 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
1986 * While VIN7 can be routed to the internal voltage divider,
1987 * VIN5 and VIN6 are not available if UART6 is enabled.
4573acbc
GR		 1988 *
1989 * Also, temp3 is not available if UART6 is enabled and TEMPIN3
1990 * is the temperature source. Since we can not read the
1991 * temperature source here, skip_temp is preliminary.
9172b5d1 1992 */
4573acbc 1993 if (uart6) {
9172b5d1 1994 sio_data->skip_in |= (1 << 5) | (1 << 6);
4573acbc
GR		 1995 sio_data->skip_temp |= (1 << 2);
1996 }
9172b5d1 1997
d9b327c3 1998 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
87673dd7 1999 }
d9b327c3 2000 if (sio_data->beep_pin)
a8ca1037 2001 pr_info("Beeping is supported\n");
87673dd7 2002
98dd22c3
JD		 2003 /* Disable specific features based on DMI strings */
2004 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
2005 board_name = dmi_get_system_info(DMI_BOARD_NAME);
2006 if (board_vendor && board_name) {
2007 if (strcmp(board_vendor, "nVIDIA") == 0
2008 && strcmp(board_name, "FN68PT") == 0) {
4a0d71cf
GR		 2009 /*
2010 * On the Shuttle SN68PT, FAN_CTL2 is apparently not
2011 * connected to a fan, but to something else. One user
2012 * has reported instant system power-off when changing
2013 * the PWM2 duty cycle, so we disable it.
2014 * I use the board name string as the trigger in case
2015 * the same board is ever used in other systems.
2016 */
a8ca1037 2017 pr_info("Disabling pwm2 due to hardware constraints\n");
98dd22c3
JD		 2018 sio_data->skip_pwm = (1 << 1);
2019 }
2020 }
2021
1da177e4
LT		 2022exit:
2023 superio_exit();
2024 return err;
2025}
2026
723a0aa0
JD		 2027static void it87_remove_files(struct device *dev)
2028{
2029 struct it87_data *data = platform_get_drvdata(pdev);
a8b3a3a5 2030 struct it87_sio_data *sio_data = dev_get_platdata(dev);
723a0aa0
JD		 2031 int i;
2032
2033 sysfs_remove_group(&dev->kobj, &it87_group);
c145d5c6 2034 for (i = 0; i < 10; i++) {
9172b5d1
GR		 2035 if (sio_data->skip_in & (1 << i))
2036 continue;
2037 sysfs_remove_group(&dev->kobj, &it87_group_in[i]);
2038 if (it87_attributes_in_beep[i])
2039 sysfs_remove_file(&dev->kobj,
2040 it87_attributes_in_beep[i]);
2041 }
4573acbc
GR		 2042 for (i = 0; i < 3; i++) {
2043 if (!(data->has_temp & (1 << i)))
2044 continue;
2045 sysfs_remove_group(&dev->kobj, &it87_group_temp[i]);
161d898a
GR		 2046 if (has_temp_offset(data))
2047 sysfs_remove_file(&dev->kobj,
2048 it87_attributes_temp_offset[i]);
4573acbc
GR		 2049 if (sio_data->beep_pin)
2050 sysfs_remove_file(&dev->kobj,
2051 it87_attributes_temp_beep[i]);
2052 }
723a0aa0
JD		 2053 for (i = 0; i < 5; i++) {
2054 if (!(data->has_fan & (1 << i)))
2055 continue;
e1169ba0 2056 sysfs_remove_group(&dev->kobj, &it87_group_fan[i]);
d9b327c3
JD		 2057 if (sio_data->beep_pin)
2058 sysfs_remove_file(&dev->kobj,
2059 it87_attributes_fan_beep[i]);
e1169ba0
GR		 2060 if (i < 3 && !has_16bit_fans(data))
2061 sysfs_remove_file(&dev->kobj,
2062 it87_attributes_fan_div[i]);
723a0aa0
JD		 2063 }
2064 for (i = 0; i < 3; i++) {
2065 if (sio_data->skip_pwm & (1 << 0))
2066 continue;
2067 sysfs_remove_group(&dev->kobj, &it87_group_pwm[i]);
4f3f51bc
JD		 2068 if (has_old_autopwm(data))
2069 sysfs_remove_group(&dev->kobj,
2070 &it87_group_autopwm[i]);
723a0aa0 2071 }
6a8d7acf
JD		 2072 if (!sio_data->skip_vid)
2073 sysfs_remove_group(&dev->kobj, &it87_group_vid);
738e5e05 2074 sysfs_remove_group(&dev->kobj, &it87_group_label);
723a0aa0
JD		 2075}
2076
6c931ae1 2077static int it87_probe(struct platform_device *pdev)
1da177e4 2078{
1da177e4 2079 struct it87_data *data;
b74f3fdd 2080 struct resource *res;
2081 struct device *dev = &pdev->dev;
a8b3a3a5 2082 struct it87_sio_data *sio_data = dev_get_platdata(dev);
723a0aa0 2083 int err = 0, i;
1da177e4 2084 int enable_pwm_interface;
d9b327c3 2085 int fan_beep_need_rw;
b74f3fdd 2086
2087 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
62a1d05f
GR		 2088 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
2089 DRVNAME)) {
b74f3fdd 2090 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
2091 (unsigned long)res->start,
87b4b663 2092 (unsigned long)(res->start + IT87_EC_EXTENT - 1));
62a1d05f 2093 return -EBUSY;
8e9afcbb 2094 }
1da177e4 2095
62a1d05f
GR		 2096 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
2097 if (!data)
2098 return -ENOMEM;
1da177e4 2099
b74f3fdd 2100 data->addr = res->start;
2101 data->type = sio_data->type;
483db43e 2102 data->features = it87_devices[sio_data->type].features;
5d8d2f2b 2103 data->peci_mask = it87_devices[sio_data->type].peci_mask;
19529784 2104 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
483db43e
GR		 2105 data->name = it87_devices[sio_data->type].name;
2106 /*
2107 * IT8705F Datasheet 0.4.1, 3h == Version G.
2108 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
2109 * These are the first revisions with 16-bit tachometer support.
2110 */
2111 switch (data->type) {
2112 case it87:
2113 if (sio_data->revision >= 0x03) {
2114 data->features &= ~FEAT_OLD_AUTOPWM;
2115 data->features |= FEAT_16BIT_FANS;
2116 }
2117 break;
2118 case it8712:
2119 if (sio_data->revision >= 0x08) {
2120 data->features &= ~FEAT_OLD_AUTOPWM;
2121 data->features |= FEAT_16BIT_FANS;
2122 }
2123 break;
2124 default:
2125 break;
2126 }
1da177e4
LT		 2127
2128 /* Now, we do the remaining detection. */
b74f3fdd 2129 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80)
62a1d05f
GR		 2130 || it87_read_value(data, IT87_REG_CHIPID) != 0x90)
2131 return -ENODEV;
1da177e4 2132
b74f3fdd 2133 platform_set_drvdata(pdev, data);
1da177e4 2134
9a61bf63 2135 mutex_init(&data->update_lock);
1da177e4 2136
1da177e4 2137 /* Check PWM configuration */
b74f3fdd 2138 enable_pwm_interface = it87_check_pwm(dev);
1da177e4 2139
44c1bcd4 2140 /* Starting with IT8721F, we handle scaling of internal voltages */
16b5dda2 2141 if (has_12mv_adc(data)) {
44c1bcd4
JD		 2142 if (sio_data->internal & (1 << 0))
2143 data->in_scaled |= (1 << 3); /* in3 is AVCC */
2144 if (sio_data->internal & (1 << 1))
2145 data->in_scaled |= (1 << 7); /* in7 is VSB */
2146 if (sio_data->internal & (1 << 2))
2147 data->in_scaled |= (1 << 8); /* in8 is Vbat */
c145d5c6
RM		 2148 if (sio_data->internal & (1 << 3))
2149 data->in_scaled |= (1 << 9); /* in9 is AVCC */
0531d98b
GR		 2150 } else if (sio_data->type == it8782 || sio_data->type == it8783) {
2151 if (sio_data->internal & (1 << 0))
2152 data->in_scaled |= (1 << 3); /* in3 is VCC5V */
2153 if (sio_data->internal & (1 << 1))
2154 data->in_scaled |= (1 << 7); /* in7 is VCCH5V */
44c1bcd4
JD		 2155 }
2156
4573acbc
GR		 2157 data->has_temp = 0x07;
2158 if (sio_data->skip_temp & (1 << 2)) {
2159 if (sio_data->type == it8782
2160 && !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
2161 data->has_temp &= ~(1 << 2);
2162 }
2163
1da177e4 2164 /* Initialize the IT87 chip */
b74f3fdd 2165 it87_init_device(pdev);
1da177e4
LT		 2166
2167 /* Register sysfs hooks */
5f2dc798
JD		 2168 err = sysfs_create_group(&dev->kobj, &it87_group);
2169 if (err)
62a1d05f 2170 return err;
17d648bf 2171
c145d5c6 2172 for (i = 0; i < 10; i++) {
9172b5d1
GR		 2173 if (sio_data->skip_in & (1 << i))
2174 continue;
2175 err = sysfs_create_group(&dev->kobj, &it87_group_in[i]);
2176 if (err)
62a1d05f 2177 goto error;
9172b5d1
GR		 2178 if (sio_data->beep_pin && it87_attributes_in_beep[i]) {
2179 err = sysfs_create_file(&dev->kobj,
2180 it87_attributes_in_beep[i]);
2181 if (err)
62a1d05f 2182 goto error;
9172b5d1
GR		 2183 }
2184 }
2185
4573acbc
GR		 2186 for (i = 0; i < 3; i++) {
2187 if (!(data->has_temp & (1 << i)))
2188 continue;
2189 err = sysfs_create_group(&dev->kobj, &it87_group_temp[i]);
d9b327c3 2190 if (err)
62a1d05f 2191 goto error;
161d898a
GR		 2192 if (has_temp_offset(data)) {
2193 err = sysfs_create_file(&dev->kobj,
2194 it87_attributes_temp_offset[i]);
2195 if (err)
2196 goto error;
2197 }
4573acbc
GR		 2198 if (sio_data->beep_pin) {
2199 err = sysfs_create_file(&dev->kobj,
2200 it87_attributes_temp_beep[i]);
2201 if (err)
2202 goto error;
2203 }
d9b327c3
JD		 2204 }
2205
9060f8bd 2206 /* Do not create fan files for disabled fans */
d9b327c3 2207 fan_beep_need_rw = 1;
723a0aa0
JD		 2208 for (i = 0; i < 5; i++) {
2209 if (!(data->has_fan & (1 << i)))
2210 continue;
e1169ba0 2211 err = sysfs_create_group(&dev->kobj, &it87_group_fan[i]);
723a0aa0 2212 if (err)
62a1d05f 2213 goto error;
d9b327c3 2214
e1169ba0
GR		 2215 if (i < 3 && !has_16bit_fans(data)) {
2216 err = sysfs_create_file(&dev->kobj,
2217 it87_attributes_fan_div[i]);
2218 if (err)
2219 goto error;
2220 }
2221
d9b327c3
JD		 2222 if (sio_data->beep_pin) {
2223 err = sysfs_create_file(&dev->kobj,
2224 it87_attributes_fan_beep[i]);
2225 if (err)
62a1d05f 2226 goto error;
d9b327c3
JD		 2227 if (!fan_beep_need_rw)
2228 continue;
2229
4a0d71cf
GR		 2230 /*
2231 * As we have a single beep enable bit for all fans,
d9b327c3 2232 * only the first enabled fan has a writable attribute
4a0d71cf
GR		 2233 * for it.
2234 */
d9b327c3
JD		 2235 if (sysfs_chmod_file(&dev->kobj,
2236 it87_attributes_fan_beep[i],
2237 S_IRUGO | S_IWUSR))
2238 dev_dbg(dev, "chmod +w fan%d_beep failed\n",
2239 i + 1);
2240 fan_beep_need_rw = 0;
2241 }
17d648bf
JD		 2242 }
2243
1da177e4 2244 if (enable_pwm_interface) {
723a0aa0
JD		 2245 for (i = 0; i < 3; i++) {
2246 if (sio_data->skip_pwm & (1 << i))
2247 continue;
2248 err = sysfs_create_group(&dev->kobj,
2249 &it87_group_pwm[i]);
2250 if (err)
62a1d05f 2251 goto error;
4f3f51bc
JD		 2252
2253 if (!has_old_autopwm(data))
2254 continue;
2255 err = sysfs_create_group(&dev->kobj,
2256 &it87_group_autopwm[i]);
2257 if (err)
62a1d05f 2258 goto error;
98dd22c3 2259 }
1da177e4
LT		 2260 }
2261
895ff267 2262 if (!sio_data->skip_vid) {
303760b4 2263 data->vrm = vid_which_vrm();
87673dd7 2264 /* VID reading from Super-I/O config space if available */
b74f3fdd 2265 data->vid = sio_data->vid_value;
6a8d7acf
JD		 2266 err = sysfs_create_group(&dev->kobj, &it87_group_vid);
2267 if (err)
62a1d05f 2268 goto error;
87808be4
JD		 2269 }
2270
738e5e05 2271 /* Export labels for internal sensors */
c145d5c6 2272 for (i = 0; i < 4; i++) {
738e5e05
JD		 2273 if (!(sio_data->internal & (1 << i)))
2274 continue;
2275 err = sysfs_create_file(&dev->kobj,
2276 it87_attributes_label[i]);
2277 if (err)
62a1d05f 2278 goto error;
738e5e05
JD		 2279 }
2280
1beeffe4
TJ		 2281 data->hwmon_dev = hwmon_device_register(dev);
2282 if (IS_ERR(data->hwmon_dev)) {
2283 err = PTR_ERR(data->hwmon_dev);
62a1d05f 2284 goto error;
1da177e4
LT		 2285 }
2286
2287 return 0;
2288
62a1d05f 2289error:
723a0aa0 2290 it87_remove_files(dev);
1da177e4
LT		 2291 return err;
2292}
2293
281dfd0b 2294static int it87_remove(struct platform_device *pdev)
1da177e4 2295{
b74f3fdd 2296 struct it87_data *data = platform_get_drvdata(pdev);
1da177e4 2297
1beeffe4 2298 hwmon_device_unregister(data->hwmon_dev);
723a0aa0 2299 it87_remove_files(&pdev->dev);
943b0830 2300
1da177e4
LT		 2301 return 0;
2302}
2303
4a0d71cf
GR		 2304/*
2305 * Must be called with data->update_lock held, except during initialization.
2306 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
2307 * would slow down the IT87 access and should not be necessary.
2308 */
b74f3fdd 2309static int it87_read_value(struct it87_data *data, u8 reg)
1da177e4 2310{
b74f3fdd 2311 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
2312 return inb_p(data->addr + IT87_DATA_REG_OFFSET);
1da177e4
LT		 2313}
2314
4a0d71cf
GR		 2315/*
2316 * Must be called with data->update_lock held, except during initialization.
2317 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
2318 * would slow down the IT87 access and should not be necessary.
2319 */
b74f3fdd 2320static void it87_write_value(struct it87_data *data, u8 reg, u8 value)
1da177e4 2321{
b74f3fdd 2322 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
2323 outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
1da177e4
LT		 2324}
2325
2326/* Return 1 if and only if the PWM interface is safe to use */
6c931ae1 2327static int it87_check_pwm(struct device *dev)
1da177e4 2328{
b74f3fdd 2329 struct it87_data *data = dev_get_drvdata(dev);
4a0d71cf
GR		 2330 /*
2331 * Some BIOSes fail to correctly configure the IT87 fans. All fans off
1da177e4 2332 * and polarity set to active low is sign that this is the case so we
4a0d71cf
GR		 2333 * disable pwm control to protect the user.
2334 */
b74f3fdd 2335 int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1da177e4
LT		 2336 if ((tmp & 0x87) == 0) {
2337 if (fix_pwm_polarity) {
4a0d71cf
GR		 2338 /*
2339 * The user asks us to attempt a chip reconfiguration.
1da177e4 2340 * This means switching to active high polarity and
4a0d71cf
GR		 2341 * inverting all fan speed values.
2342 */
1da177e4
LT		 2343 int i;
2344 u8 pwm[3];
2345
2346 for (i = 0; i < 3; i++)
b74f3fdd 2347 pwm[i] = it87_read_value(data,
1da177e4
LT		 2348 IT87_REG_PWM(i));
2349
4a0d71cf
GR		 2350 /*
2351 * If any fan is in automatic pwm mode, the polarity
1da177e4
LT		 2352 * might be correct, as suspicious as it seems, so we
2353 * better don't change anything (but still disable the
4a0d71cf
GR		 2354 * PWM interface).
2355 */
1da177e4 2356 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
1d9bcf6a
GR		 2357 dev_info(dev,
2358 "Reconfiguring PWM to active high polarity\n");
b74f3fdd 2359 it87_write_value(data, IT87_REG_FAN_CTL,
1da177e4
LT		 2360 tmp | 0x87);
2361 for (i = 0; i < 3; i++)
b74f3fdd 2362 it87_write_value(data,
1da177e4
LT		 2363 IT87_REG_PWM(i),
2364 0x7f & ~pwm[i]);
2365 return 1;
2366 }
2367
1d9bcf6a
GR		 2368 dev_info(dev,
2369 "PWM configuration is too broken to be fixed\n");
1da177e4
LT		 2370 }
2371
1d9bcf6a
GR		 2372 dev_info(dev,
2373 "Detected broken BIOS defaults, disabling PWM interface\n");
1da177e4
LT		 2374 return 0;
2375 } else if (fix_pwm_polarity) {
1d9bcf6a
GR		 2376 dev_info(dev,
2377 "PWM configuration looks sane, won't touch\n");
1da177e4
LT		 2378 }
2379
2380 return 1;
2381}
2382
2383/* Called when we have found a new IT87. */
6c931ae1 2384static void it87_init_device(struct platform_device *pdev)
1da177e4 2385{
a8b3a3a5 2386 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
b74f3fdd 2387 struct it87_data *data = platform_get_drvdata(pdev);
1da177e4 2388 int tmp, i;
591ec650 2389 u8 mask;
1da177e4 2390
4a0d71cf
GR		 2391 /*
2392 * For each PWM channel:
b99883dc
JD		 2393 * - If it is in automatic mode, setting to manual mode should set
2394 * the fan to full speed by default.
2395 * - If it is in manual mode, we need a mapping to temperature
2396 * channels to use when later setting to automatic mode later.
2397 * Use a 1:1 mapping by default (we are clueless.)
2398 * In both cases, the value can (and should) be changed by the user
6229cdb2
JD		 2399 * prior to switching to a different mode.
2400 * Note that this is no longer needed for the IT8721F and later, as
2401 * these have separate registers for the temperature mapping and the
4a0d71cf
GR		 2402 * manual duty cycle.
2403 */
1da177e4 2404 for (i = 0; i < 3; i++) {
b99883dc
JD		 2405 data->pwm_temp_map[i] = i;
2406 data->pwm_duty[i] = 0x7f; /* Full speed */
4f3f51bc 2407 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
1da177e4
LT		 2408 }
2409
4a0d71cf
GR		 2410 /*
2411 * Some chips seem to have default value 0xff for all limit
c5df9b7a
JD		 2412 * registers. For low voltage limits it makes no sense and triggers
2413 * alarms, so change to 0 instead. For high temperature limits, it
2414 * means -1 degree C, which surprisingly doesn't trigger an alarm,
4a0d71cf
GR		 2415 * but is still confusing, so change to 127 degrees C.
2416 */
c5df9b7a 2417 for (i = 0; i < 8; i++) {
b74f3fdd 2418 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
c5df9b7a 2419 if (tmp == 0xff)
b74f3fdd 2420 it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
c5df9b7a
JD		 2421 }
2422 for (i = 0; i < 3; i++) {
b74f3fdd 2423 tmp = it87_read_value(data, IT87_REG_TEMP_HIGH(i));
c5df9b7a 2424 if (tmp == 0xff)
b74f3fdd 2425 it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127);
c5df9b7a
JD		 2426 }
2427
4a0d71cf
GR		 2428 /*
2429 * Temperature channels are not forcibly enabled, as they can be
a00afb97
JD		 2430 * set to two different sensor types and we can't guess which one
2431 * is correct for a given system. These channels can be enabled at
4a0d71cf
GR		 2432 * run-time through the temp{1-3}_type sysfs accessors if needed.
2433 */
1da177e4
LT		 2434
2435 /* Check if voltage monitors are reset manually or by some reason */
b74f3fdd 2436 tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
1da177e4
LT		 2437 if ((tmp & 0xff) == 0) {
2438 /* Enable all voltage monitors */
b74f3fdd 2439 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
1da177e4
LT		 2440 }
2441
2442 /* Check if tachometers are reset manually or by some reason */
591ec650 2443 mask = 0x70 & ~(sio_data->skip_fan << 4);
b74f3fdd 2444 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
591ec650 2445 if ((data->fan_main_ctrl & mask) == 0) {
1da177e4 2446 /* Enable all fan tachometers */
591ec650 2447 data->fan_main_ctrl |= mask;
5f2dc798
JD		 2448 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
2449 data->fan_main_ctrl);
1da177e4 2450 }
9060f8bd 2451 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
1da177e4 2452
c145d5c6
RM		 2453 /* Set tachometers to 16-bit mode if needed, IT8603E (and IT8728F?)
2454 * has it by default */
2455 if (has_16bit_fans(data) && data->type != it8603) {
b74f3fdd 2456 tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
9060f8bd 2457 if (~tmp & 0x07 & data->has_fan) {
b74f3fdd 2458 dev_dbg(&pdev->dev,
17d648bf 2459 "Setting fan1-3 to 16-bit mode\n");
b74f3fdd 2460 it87_write_value(data, IT87_REG_FAN_16BIT,
17d648bf
JD		 2461 tmp | 0x07);
2462 }
0531d98b
GR		 2463 /* IT8705F, IT8782F, and IT8783E/F only support three fans. */
2464 if (data->type != it87 && data->type != it8782 &&
2465 data->type != it8783) {
816d8c6a
AP		 2466 if (tmp & (1 << 4))
2467 data->has_fan |= (1 << 3); /* fan4 enabled */
2468 if (tmp & (1 << 5))
2469 data->has_fan |= (1 << 4); /* fan5 enabled */
2470 }
17d648bf
JD		 2471 }
2472
591ec650
JD		 2473 /* Fan input pins may be used for alternative functions */
2474 data->has_fan &= ~sio_data->skip_fan;
2475
1da177e4 2476 /* Start monitoring */
b74f3fdd 2477 it87_write_value(data, IT87_REG_CONFIG,
41002f8d 2478 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
1da177e4
LT		 2479 | (update_vbat ? 0x41 : 0x01));
2480}
2481
b99883dc
JD		 2482static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
2483{
2484 data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM(nr));
16b5dda2 2485 if (has_newer_autopwm(data)) {
b99883dc 2486 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
6229cdb2
JD		 2487 data->pwm_duty[nr] = it87_read_value(data,
2488 IT87_REG_PWM_DUTY(nr));
2489 } else {
2490 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
2491 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
2492 else /* Manual mode */
2493 data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
2494 }
4f3f51bc
JD		 2495
2496 if (has_old_autopwm(data)) {
2497 int i;
2498
2499 for (i = 0; i < 5 ; i++)
2500 data->auto_temp[nr][i] = it87_read_value(data,
2501 IT87_REG_AUTO_TEMP(nr, i));
2502 for (i = 0; i < 3 ; i++)
2503 data->auto_pwm[nr][i] = it87_read_value(data,
2504 IT87_REG_AUTO_PWM(nr, i));
2505 }
b99883dc
JD		 2506}
2507
1da177e4
LT		 2508static struct it87_data *it87_update_device(struct device *dev)
2509{
b74f3fdd 2510 struct it87_data *data = dev_get_drvdata(dev);
1da177e4
LT		 2511 int i;
2512
9a61bf63 2513 mutex_lock(&data->update_lock);
1da177e4
LT		 2514
2515 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
2516 || !data->valid) {
1da177e4 2517 if (update_vbat) {
4a0d71cf
GR		 2518 /*
2519 * Cleared after each update, so reenable. Value
2520 * returned by this read will be previous value
2521 */
b74f3fdd 2522 it87_write_value(data, IT87_REG_CONFIG,
5f2dc798 2523 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
1da177e4
LT		 2524 }
2525 for (i = 0; i <= 7; i++) {
929c6a56 2526 data->in[i][0] =
5f2dc798 2527 it87_read_value(data, IT87_REG_VIN(i));
929c6a56 2528 data->in[i][1] =
5f2dc798 2529 it87_read_value(data, IT87_REG_VIN_MIN(i));
929c6a56 2530 data->in[i][2] =
5f2dc798 2531 it87_read_value(data, IT87_REG_VIN_MAX(i));
1da177e4 2532 }
3543a53f 2533 /* in8 (battery) has no limit registers */
929c6a56 2534 data->in[8][0] = it87_read_value(data, IT87_REG_VIN(8));
c145d5c6
RM		 2535 if (data->type == it8603)
2536 data->in[9][0] = it87_read_value(data, 0x2f);
1da177e4 2537
c7f1f716 2538 for (i = 0; i < 5; i++) {
9060f8bd
JD		 2539 /* Skip disabled fans */
2540 if (!(data->has_fan & (1 << i)))
2541 continue;
2542
e1169ba0 2543 data->fan[i][1] =
5f2dc798 2544 it87_read_value(data, IT87_REG_FAN_MIN[i]);
e1169ba0 2545 data->fan[i][0] = it87_read_value(data,
c7f1f716 2546 IT87_REG_FAN[i]);
17d648bf 2547 /* Add high byte if in 16-bit mode */
0475169c 2548 if (has_16bit_fans(data)) {
e1169ba0 2549 data->fan[i][0] |= it87_read_value(data,
c7f1f716 2550 IT87_REG_FANX[i]) << 8;
e1169ba0 2551 data->fan[i][1] |= it87_read_value(data,
c7f1f716 2552 IT87_REG_FANX_MIN[i]) << 8;
17d648bf 2553 }
1da177e4
LT		 2554 }
2555 for (i = 0; i < 3; i++) {
4573acbc
GR		 2556 if (!(data->has_temp & (1 << i)))
2557 continue;
60ca385a 2558 data->temp[i][0] =
5f2dc798 2559 it87_read_value(data, IT87_REG_TEMP(i));
60ca385a 2560 data->temp[i][1] =
5f2dc798 2561 it87_read_value(data, IT87_REG_TEMP_LOW(i));
60ca385a
GR		 2562 data->temp[i][2] =
2563 it87_read_value(data, IT87_REG_TEMP_HIGH(i));
161d898a
GR		 2564 if (has_temp_offset(data))
2565 data->temp[i][3] =
2566 it87_read_value(data,
2567 IT87_REG_TEMP_OFFSET[i]);
1da177e4
LT		 2568 }
2569
17d648bf 2570 /* Newer chips don't have clock dividers */
0475169c 2571 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
b74f3fdd 2572 i = it87_read_value(data, IT87_REG_FAN_DIV);
17d648bf
JD		 2573 data->fan_div[0] = i & 0x07;
2574 data->fan_div[1] = (i >> 3) & 0x07;
2575 data->fan_div[2] = (i & 0x40) ? 3 : 1;
2576 }
1da177e4
LT		 2577
2578 data->alarms =
b74f3fdd 2579 it87_read_value(data, IT87_REG_ALARM1) |
2580 (it87_read_value(data, IT87_REG_ALARM2) << 8) |
2581 (it87_read_value(data, IT87_REG_ALARM3) << 16);
d9b327c3 2582 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
b99883dc 2583
b74f3fdd 2584 data->fan_main_ctrl = it87_read_value(data,
2585 IT87_REG_FAN_MAIN_CTRL);
2586 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
b99883dc
JD		 2587 for (i = 0; i < 3; i++)
2588 it87_update_pwm_ctrl(data, i);
b74f3fdd 2589
2590 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
19529784 2591 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
4a0d71cf
GR		 2592 /*
2593 * The IT8705F does not have VID capability.
2594 * The IT8718F and later don't use IT87_REG_VID for the
2595 * same purpose.
2596 */
17d648bf 2597 if (data->type == it8712 || data->type == it8716) {
b74f3fdd 2598 data->vid = it87_read_value(data, IT87_REG_VID);
4a0d71cf
GR		 2599 /*
2600 * The older IT8712F revisions had only 5 VID pins,
2601 * but we assume it is always safe to read 6 bits.
2602 */
17d648bf 2603 data->vid &= 0x3f;
1da177e4
LT		 2604 }
2605 data->last_updated = jiffies;
2606 data->valid = 1;
2607 }
2608
9a61bf63 2609 mutex_unlock(&data->update_lock);
1da177e4
LT		 2610
2611 return data;
2612}
2613
b74f3fdd 2614static int __init it87_device_add(unsigned short address,
2615 const struct it87_sio_data *sio_data)
2616{
2617 struct resource res = {
87b4b663
BH		 2618 .start = address + IT87_EC_OFFSET,
2619 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
b74f3fdd 2620 .name = DRVNAME,
2621 .flags = IORESOURCE_IO,
2622 };
2623 int err;
2624
b9acb64a
JD		 2625 err = acpi_check_resource_conflict(&res);
2626 if (err)
2627 goto exit;
2628
b74f3fdd 2629 pdev = platform_device_alloc(DRVNAME, address);
2630 if (!pdev) {
2631 err = -ENOMEM;
a8ca1037 2632 pr_err("Device allocation failed\n");
b74f3fdd 2633 goto exit;
2634 }
2635
2636 err = platform_device_add_resources(pdev, &res, 1);
2637 if (err) {
a8ca1037 2638 pr_err("Device resource addition failed (%d)\n", err);
b74f3fdd 2639 goto exit_device_put;
2640 }
2641
2642 err = platform_device_add_data(pdev, sio_data,
2643 sizeof(struct it87_sio_data));
2644 if (err) {
a8ca1037 2645 pr_err("Platform data allocation failed\n");
b74f3fdd 2646 goto exit_device_put;
2647 }
2648
2649 err = platform_device_add(pdev);
2650 if (err) {
a8ca1037 2651 pr_err("Device addition failed (%d)\n", err);
b74f3fdd 2652 goto exit_device_put;
2653 }
2654
2655 return 0;
2656
2657exit_device_put:
2658 platform_device_put(pdev);
2659exit:
2660 return err;
2661}
2662
1da177e4
LT		 2663static int __init sm_it87_init(void)
2664{
b74f3fdd 2665 int err;
5f2dc798 2666 unsigned short isa_address = 0;
b74f3fdd 2667 struct it87_sio_data sio_data;
2668
98dd22c3 2669 memset(&sio_data, 0, sizeof(struct it87_sio_data));
b74f3fdd 2670 err = it87_find(&isa_address, &sio_data);
2671 if (err)
2672 return err;
2673 err = platform_driver_register(&it87_driver);
2674 if (err)
2675 return err;
fde09509 2676
b74f3fdd 2677 err = it87_device_add(isa_address, &sio_data);
5f2dc798 2678 if (err) {
b74f3fdd 2679 platform_driver_unregister(&it87_driver);
2680 return err;
2681 }
2682
2683 return 0;
1da177e4
LT		 2684}
2685
2686static void __exit sm_it87_exit(void)
2687{
b74f3fdd 2688 platform_device_unregister(pdev);
2689 platform_driver_unregister(&it87_driver);
1da177e4
LT		 2690}
2691
2692
7c81c60f 2693MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
44c1bcd4 2694MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
1da177e4
LT		 2695module_param(update_vbat, bool, 0);
2696MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
2697module_param(fix_pwm_polarity, bool, 0);
5f2dc798
JD		 2698MODULE_PARM_DESC(fix_pwm_polarity,
2699 "Force PWM polarity to active high (DANGEROUS)");
1da177e4
LT		 2700MODULE_LICENSE("GPL");
2701
2702module_init(sm_it87_init);
2703module_exit(sm_it87_exit);
Linux kernel - Deliverables
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