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hwmon: (it87) Fix PWM frequency display for chips with newer PWM control
[deliverable/linux.git] / drivers / hwmon / it87.c
CommitLineData
1da177e4 1/*
5f2dc798
JD		 2 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
3 * monitoring.
4 *
5 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
6 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
7 * addition to an Environment Controller (Enhanced Hardware Monitor and
8 * Fan Controller)
9 *
10 * This driver supports only the Environment Controller in the IT8705F and
11 * similar parts. The other devices are supported by different drivers.
12 *
c145d5c6 13 * Supports: IT8603E Super I/O chip w/LPC interface
574e9bd8 14 * IT8623E Super I/O chip w/LPC interface
c145d5c6 15 * IT8705F Super I/O chip w/LPC interface
5f2dc798
JD		 16 * IT8712F Super I/O chip w/LPC interface
17 * IT8716F Super I/O chip w/LPC interface
18 * IT8718F Super I/O chip w/LPC interface
19 * IT8720F Super I/O chip w/LPC interface
44c1bcd4 20 * IT8721F Super I/O chip w/LPC interface
5f2dc798 21 * IT8726F Super I/O chip w/LPC interface
16b5dda2 22 * IT8728F Super I/O chip w/LPC interface
44c1bcd4 23 * IT8758E Super I/O chip w/LPC interface
b0636707
GR		 24 * IT8771E Super I/O chip w/LPC interface
25 * IT8772E Super I/O chip w/LPC interface
7bc32d29 26 * IT8781F Super I/O chip w/LPC interface
0531d98b
GR		 27 * IT8782F Super I/O chip w/LPC interface
28 * IT8783E/F Super I/O chip w/LPC interface
a0c1424a 29 * IT8786E Super I/O chip w/LPC interface
5f2dc798
JD		 30 * Sis950 A clone of the IT8705F
31 *
32 * Copyright (C) 2001 Chris Gauthron
7c81c60f 33 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
5f2dc798
JD		 34 *
35 * This program is free software; you can redistribute it and/or modify
36 * it under the terms of the GNU General Public License as published by
37 * the Free Software Foundation; either version 2 of the License, or
38 * (at your option) any later version.
39 *
40 * This program is distributed in the hope that it will be useful,
41 * but WITHOUT ANY WARRANTY; without even the implied warranty of
42 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
43 * GNU General Public License for more details.
44 *
45 * You should have received a copy of the GNU General Public License
46 * along with this program; if not, write to the Free Software
47 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
48 */
1da177e4 49
a8ca1037
JP		 50#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
51
1da177e4
LT		 52#include <linux/module.h>
53#include <linux/init.h>
54#include <linux/slab.h>
55#include <linux/jiffies.h>
b74f3fdd 56#include <linux/platform_device.h>
943b0830 57#include <linux/hwmon.h>
303760b4
JD		 58#include <linux/hwmon-sysfs.h>
59#include <linux/hwmon-vid.h>
943b0830 60#include <linux/err.h>
9a61bf63 61#include <linux/mutex.h>
87808be4 62#include <linux/sysfs.h>
98dd22c3
JD		 63#include <linux/string.h>
64#include <linux/dmi.h>
b9acb64a 65#include <linux/acpi.h>
6055fae8 66#include <linux/io.h>
1da177e4 67
b74f3fdd 68#define DRVNAME "it87"
1da177e4 69
b0636707 70enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8771,
a0c1424a 71 it8772, it8781, it8782, it8783, it8786, it8603 };
1da177e4 72
67b671bc
JD		 73static unsigned short force_id;
74module_param(force_id, ushort, 0);
75MODULE_PARM_DESC(force_id, "Override the detected device ID");
76
b74f3fdd 77static struct platform_device *pdev;
78
1da177e4
LT		 79#define REG 0x2e /* The register to read/write */
80#define DEV 0x07 /* Register: Logical device select */
81#define VAL 0x2f /* The value to read/write */
82#define PME 0x04 /* The device with the fan registers in it */
b4da93e4
JMS		 83
84/* The device with the IT8718F/IT8720F VID value in it */
85#define GPIO 0x07
86
1da177e4
LT		 87#define DEVID 0x20 /* Register: Device ID */
88#define DEVREV 0x22 /* Register: Device Revision */
89
5b0380c9 90static inline int superio_inb(int reg)
1da177e4
LT		 91{
92 outb(reg, REG);
93 return inb(VAL);
94}
95
5b0380c9 96static inline void superio_outb(int reg, int val)
436cad2a
JD		 97{
98 outb(reg, REG);
99 outb(val, VAL);
100}
101
1da177e4
LT		 102static int superio_inw(int reg)
103{
104 int val;
105 outb(reg++, REG);
106 val = inb(VAL) << 8;
107 outb(reg, REG);
108 val |= inb(VAL);
109 return val;
110}
111
5b0380c9 112static inline void superio_select(int ldn)
1da177e4
LT		 113{
114 outb(DEV, REG);
87673dd7 115 outb(ldn, VAL);
1da177e4
LT		 116}
117
5b0380c9 118static inline int superio_enter(void)
1da177e4 119{
5b0380c9
NG		 120 /*
121 * Try to reserve REG and REG + 1 for exclusive access.
122 */
123 if (!request_muxed_region(REG, 2, DRVNAME))
124 return -EBUSY;
125
1da177e4
LT		 126 outb(0x87, REG);
127 outb(0x01, REG);
128 outb(0x55, REG);
129 outb(0x55, REG);
5b0380c9 130 return 0;
1da177e4
LT		 131}
132
5b0380c9 133static inline void superio_exit(void)
1da177e4
LT		 134{
135 outb(0x02, REG);
136 outb(0x02, VAL);
5b0380c9 137 release_region(REG, 2);
1da177e4
LT		 138}
139
87673dd7 140/* Logical device 4 registers */
1da177e4
LT		 141#define IT8712F_DEVID 0x8712
142#define IT8705F_DEVID 0x8705
17d648bf 143#define IT8716F_DEVID 0x8716
87673dd7 144#define IT8718F_DEVID 0x8718
b4da93e4 145#define IT8720F_DEVID 0x8720
44c1bcd4 146#define IT8721F_DEVID 0x8721
08a8f6e9 147#define IT8726F_DEVID 0x8726
16b5dda2 148#define IT8728F_DEVID 0x8728
b0636707
GR		 149#define IT8771E_DEVID 0x8771
150#define IT8772E_DEVID 0x8772
7bc32d29 151#define IT8781F_DEVID 0x8781
0531d98b
GR		 152#define IT8782F_DEVID 0x8782
153#define IT8783E_DEVID 0x8783
a0c1424a 154#define IT8786E_DEVID 0x8786
7183ae8c 155#define IT8603E_DEVID 0x8603
574e9bd8 156#define IT8623E_DEVID 0x8623
1da177e4
LT		 157#define IT87_ACT_REG 0x30
158#define IT87_BASE_REG 0x60
159
87673dd7 160/* Logical device 7 registers (IT8712F and later) */
0531d98b 161#define IT87_SIO_GPIO1_REG 0x25
895ff267 162#define IT87_SIO_GPIO3_REG 0x27
591ec650 163#define IT87_SIO_GPIO5_REG 0x29
0531d98b 164#define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
87673dd7 165#define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
0531d98b 166#define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
87673dd7 167#define IT87_SIO_VID_REG 0xfc /* VID value */
d9b327c3 168#define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
87673dd7 169
1da177e4 170/* Update battery voltage after every reading if true */
90ab5ee9 171static bool update_vbat;
1da177e4
LT		 172
173/* Not all BIOSes properly configure the PWM registers */
90ab5ee9 174static bool fix_pwm_polarity;
1da177e4 175
1da177e4
LT		 176/* Many IT87 constants specified below */
177
178/* Length of ISA address segment */
179#define IT87_EXTENT 8
180
87b4b663
BH		 181/* Length of ISA address segment for Environmental Controller */
182#define IT87_EC_EXTENT 2
183
184/* Offset of EC registers from ISA base address */
185#define IT87_EC_OFFSET 5
186
187/* Where are the ISA address/data registers relative to the EC base address */
188#define IT87_ADDR_REG_OFFSET 0
189#define IT87_DATA_REG_OFFSET 1
1da177e4
LT		 190
191/*----- The IT87 registers -----*/
192
193#define IT87_REG_CONFIG 0x00
194
195#define IT87_REG_ALARM1 0x01
196#define IT87_REG_ALARM2 0x02
197#define IT87_REG_ALARM3 0x03
198
4a0d71cf
GR		 199/*
200 * The IT8718F and IT8720F have the VID value in a different register, in
201 * Super-I/O configuration space.
202 */
1da177e4 203#define IT87_REG_VID 0x0a
4a0d71cf
GR		 204/*
205 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
206 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
207 * mode.
208 */
1da177e4 209#define IT87_REG_FAN_DIV 0x0b
17d648bf 210#define IT87_REG_FAN_16BIT 0x0c
1da177e4
LT		 211
212/* Monitors: 9 voltage (0 to 7, battery), 3 temp (1 to 3), 3 fan (1 to 3) */
213
c7f1f716
JD		 214static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82 };
215static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86 };
216static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83 };
217static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87 };
161d898a
GR		 218static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 };
219
1da177e4
LT		 220#define IT87_REG_FAN_MAIN_CTRL 0x13
221#define IT87_REG_FAN_CTL 0x14
222#define IT87_REG_PWM(nr) (0x15 + (nr))
6229cdb2 223#define IT87_REG_PWM_DUTY(nr) (0x63 + (nr) * 8)
1da177e4
LT		 224
225#define IT87_REG_VIN(nr) (0x20 + (nr))
226#define IT87_REG_TEMP(nr) (0x29 + (nr))
227
228#define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
229#define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
230#define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2)
231#define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2)
232
1da177e4
LT		 233#define IT87_REG_VIN_ENABLE 0x50
234#define IT87_REG_TEMP_ENABLE 0x51
4573acbc 235#define IT87_REG_TEMP_EXTRA 0x55
d9b327c3 236#define IT87_REG_BEEP_ENABLE 0x5c
1da177e4
LT		 237
238#define IT87_REG_CHIPID 0x58
239
4f3f51bc
JD		 240#define IT87_REG_AUTO_TEMP(nr, i) (0x60 + (nr) * 8 + (i))
241#define IT87_REG_AUTO_PWM(nr, i) (0x65 + (nr) * 8 + (i))
242
483db43e
GR		 243struct it87_devices {
244 const char *name;
245 u16 features;
19529784
GR		 246 u8 peci_mask;
247 u8 old_peci_mask;
483db43e
GR		 248};
249
250#define FEAT_12MV_ADC (1 << 0)
251#define FEAT_NEWER_AUTOPWM (1 << 1)
252#define FEAT_OLD_AUTOPWM (1 << 2)
253#define FEAT_16BIT_FANS (1 << 3)
254#define FEAT_TEMP_OFFSET (1 << 4)
5d8d2f2b 255#define FEAT_TEMP_PECI (1 << 5)
19529784 256#define FEAT_TEMP_OLD_PECI (1 << 6)
9faf28ca
GR		 257#define FEAT_FAN16_CONFIG (1 << 7) /* Need to enable 16-bit fans */
258#define FEAT_FIVE_FANS (1 << 8) /* Supports five fans */
32dd7c40 259#define FEAT_VID (1 << 9) /* Set if chip supports VID */
483db43e
GR		 260
261static const struct it87_devices it87_devices[] = {
262 [it87] = {
263 .name = "it87",
264 .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
265 },
266 [it8712] = {
267 .name = "it8712",
32dd7c40
GR		 268 .features = FEAT_OLD_AUTOPWM | FEAT_VID,
269 /* may need to overwrite */
483db43e
GR		 270 },
271 [it8716] = {
272 .name = "it8716",
32dd7c40 273 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
9faf28ca 274 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS,
483db43e
GR		 275 },
276 [it8718] = {
277 .name = "it8718",
32dd7c40 278 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
9faf28ca 279 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS,
19529784 280 .old_peci_mask = 0x4,
483db43e
GR		 281 },
282 [it8720] = {
283 .name = "it8720",
32dd7c40 284 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
9faf28ca 285 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS,
19529784 286 .old_peci_mask = 0x4,
483db43e
GR		 287 },
288 [it8721] = {
289 .name = "it8721",
290 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
9faf28ca
GR		 291 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
292 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS,
5d8d2f2b 293 .peci_mask = 0x05,
19529784 294 .old_peci_mask = 0x02, /* Actually reports PCH */
483db43e
GR		 295 },
296 [it8728] = {
297 .name = "it8728",
298 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
9faf28ca 299 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS,
5d8d2f2b 300 .peci_mask = 0x07,
483db43e 301 },
b0636707
GR		 302 [it8771] = {
303 .name = "it8771",
304 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
305 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI,
9faf28ca
GR		 306 /* PECI: guesswork */
307 /* 12mV ADC (OHM) */
308 /* 16 bit fans (OHM) */
309 /* three fans, always 16 bit (guesswork) */
b0636707
GR		 310 .peci_mask = 0x07,
311 },
312 [it8772] = {
313 .name = "it8772",
314 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
315 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI,
9faf28ca
GR		 316 /* PECI (coreboot) */
317 /* 12mV ADC (HWSensors4, OHM) */
318 /* 16 bit fans (HWSensors4, OHM) */
319 /* three fans, always 16 bit (datasheet) */
b0636707
GR		 320 .peci_mask = 0x07,
321 },
7bc32d29
GR		 322 [it8781] = {
323 .name = "it8781",
324 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
9faf28ca 325 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG,
7bc32d29
GR		 326 .old_peci_mask = 0x4,
327 },
483db43e
GR		 328 [it8782] = {
329 .name = "it8782",
19529784 330 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
9faf28ca 331 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG,
19529784 332 .old_peci_mask = 0x4,
483db43e
GR		 333 },
334 [it8783] = {
335 .name = "it8783",
19529784 336 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
9faf28ca 337 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG,
19529784 338 .old_peci_mask = 0x4,
483db43e 339 },
a0c1424a
TL		 340 [it8786] = {
341 .name = "it8786",
342 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
343 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI,
344 .peci_mask = 0x07,
345 },
c145d5c6
RM		 346 [it8603] = {
347 .name = "it8603",
348 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
349 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI,
350 .peci_mask = 0x07,
351 },
483db43e
GR		 352};
353
354#define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
355#define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
356#define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
357#define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
358#define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET)
5d8d2f2b
GR		 359#define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
360 ((data)->peci_mask & (1 << nr)))
19529784
GR		 361#define has_temp_old_peci(data, nr) \
362 (((data)->features & FEAT_TEMP_OLD_PECI) && \
363 ((data)->old_peci_mask & (1 << nr)))
9faf28ca
GR		 364#define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG)
365#define has_five_fans(data) ((data)->features & FEAT_FIVE_FANS)
32dd7c40 366#define has_vid(data) ((data)->features & FEAT_VID)
1da177e4 367
b74f3fdd 368struct it87_sio_data {
369 enum chips type;
370 /* Values read from Super-I/O config space */
0475169c 371 u8 revision;
b74f3fdd 372 u8 vid_value;
d9b327c3 373 u8 beep_pin;
738e5e05 374 u8 internal; /* Internal sensors can be labeled */
591ec650 375 /* Features skipped based on config or DMI */
9172b5d1 376 u16 skip_in;
895ff267 377 u8 skip_vid;
591ec650 378 u8 skip_fan;
98dd22c3 379 u8 skip_pwm;
4573acbc 380 u8 skip_temp;
b74f3fdd 381};
382
4a0d71cf
GR		 383/*
384 * For each registered chip, we need to keep some data in memory.
385 * The structure is dynamically allocated.
386 */
1da177e4 387struct it87_data {
1beeffe4 388 struct device *hwmon_dev;
1da177e4 389 enum chips type;
483db43e 390 u16 features;
19529784
GR		 391 u8 peci_mask;
392 u8 old_peci_mask;
1da177e4 393
b74f3fdd 394 unsigned short addr;
395 const char *name;
9a61bf63 396 struct mutex update_lock;
1da177e4
LT		 397 char valid; /* !=0 if following fields are valid */
398 unsigned long last_updated; /* In jiffies */
399
44c1bcd4 400 u16 in_scaled; /* Internal voltage sensors are scaled */
c145d5c6 401 u8 in[10][3]; /* [nr][0]=in, [1]=min, [2]=max */
9060f8bd 402 u8 has_fan; /* Bitfield, fans enabled */
e1169ba0 403 u16 fan[5][2]; /* Register values, [nr][0]=fan, [1]=min */
4573acbc 404 u8 has_temp; /* Bitfield, temp sensors enabled */
161d898a 405 s8 temp[3][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
19529784
GR		 406 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
407 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
1da177e4
LT		 408 u8 fan_div[3]; /* Register encoding, shifted right */
409 u8 vid; /* Register encoding, combined */
a7be58a1 410 u8 vrm;
1da177e4 411 u32 alarms; /* Register encoding, combined */
d9b327c3 412 u8 beeps; /* Register encoding */
1da177e4 413 u8 fan_main_ctrl; /* Register value */
f8d0c19a 414 u8 fan_ctl; /* Register value */
b99883dc 415
4a0d71cf
GR		 416 /*
417 * The following 3 arrays correspond to the same registers up to
6229cdb2
JD		 418 * the IT8720F. The meaning of bits 6-0 depends on the value of bit
419 * 7, and we want to preserve settings on mode changes, so we have
420 * to track all values separately.
421 * Starting with the IT8721F, the manual PWM duty cycles are stored
422 * in separate registers (8-bit values), so the separate tracking
423 * is no longer needed, but it is still done to keep the driver
4a0d71cf
GR		 424 * simple.
425 */
b99883dc 426 u8 pwm_ctrl[3]; /* Register value */
6229cdb2 427 u8 pwm_duty[3]; /* Manual PWM value set by user */
b99883dc 428 u8 pwm_temp_map[3]; /* PWM to temp. chan. mapping (bits 1-0) */
4f3f51bc
JD		 429
430 /* Automatic fan speed control registers */
431 u8 auto_pwm[3][4]; /* [nr][3] is hard-coded */
432 s8 auto_temp[3][5]; /* [nr][0] is point1_temp_hyst */
1da177e4 433};
0df6454d 434
0531d98b 435static int adc_lsb(const struct it87_data *data, int nr)
44c1bcd4 436{
0531d98b
GR		 437 int lsb = has_12mv_adc(data) ? 12 : 16;
438 if (data->in_scaled & (1 << nr))
439 lsb <<= 1;
440 return lsb;
441}
44c1bcd4 442
0531d98b
GR		 443static u8 in_to_reg(const struct it87_data *data, int nr, long val)
444{
445 val = DIV_ROUND_CLOSEST(val, adc_lsb(data, nr));
2a844c14 446 return clamp_val(val, 0, 255);
44c1bcd4
JD		 447}
448
449static int in_from_reg(const struct it87_data *data, int nr, int val)
450{
0531d98b 451 return val * adc_lsb(data, nr);
44c1bcd4 452}
0df6454d
JD		 453
454static inline u8 FAN_TO_REG(long rpm, int div)
455{
456 if (rpm == 0)
457 return 255;
2a844c14
GR		 458 rpm = clamp_val(rpm, 1, 1000000);
459 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
0df6454d
JD		 460}
461
462static inline u16 FAN16_TO_REG(long rpm)
463{
464 if (rpm == 0)
465 return 0xffff;
2a844c14 466 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
0df6454d
JD		 467}
468
469#define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
470 1350000 / ((val) * (div)))
471/* The divider is fixed to 2 in 16-bit mode */
472#define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
473 1350000 / ((val) * 2))
474
2a844c14
GR		 475#define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
476 ((val) + 500) / 1000), -128, 127))
0df6454d
JD		 477#define TEMP_FROM_REG(val) ((val) * 1000)
478
44c1bcd4
JD		 479static u8 pwm_to_reg(const struct it87_data *data, long val)
480{
16b5dda2 481 if (has_newer_autopwm(data))
44c1bcd4
JD		 482 return val;
483 else
484 return val >> 1;
485}
486
487static int pwm_from_reg(const struct it87_data *data, u8 reg)
488{
16b5dda2 489 if (has_newer_autopwm(data))
44c1bcd4
JD		 490 return reg;
491 else
492 return (reg & 0x7f) << 1;
493}
494
0df6454d
JD		 495
496static int DIV_TO_REG(int val)
497{
498 int answer = 0;
499 while (answer < 7 && (val >>= 1))
500 answer++;
501 return answer;
502}
503#define DIV_FROM_REG(val) (1 << (val))
504
f56c9c0a
GR		 505/*
506 * PWM base frequencies. The frequency has to be divided by either 128 or 256,
507 * depending on the chip type, to calculate the actual PWM frequency.
508 *
509 * Some of the chip datasheets suggest a base frequency of 51 kHz instead
510 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
511 * of 200 Hz. Sometimes both PWM frequency select registers are affected,
512 * sometimes just one. It is unknown if this is a datasheet error or real,
513 * so this is ignored for now.
514 */
0df6454d 515static const unsigned int pwm_freq[8] = {
f56c9c0a
GR		 516 48000000,
517 24000000,
518 12000000,
519 8000000,
520 6000000,
521 3000000,
522 1500000,
523 750000,
0df6454d 524};
1da177e4 525
b74f3fdd 526static int it87_probe(struct platform_device *pdev);
281dfd0b 527static int it87_remove(struct platform_device *pdev);
1da177e4 528
b74f3fdd 529static int it87_read_value(struct it87_data *data, u8 reg);
530static void it87_write_value(struct it87_data *data, u8 reg, u8 value);
1da177e4 531static struct it87_data *it87_update_device(struct device *dev);
b74f3fdd 532static int it87_check_pwm(struct device *dev);
533static void it87_init_device(struct platform_device *pdev);
1da177e4
LT		 534
535
b74f3fdd 536static struct platform_driver it87_driver = {
cdaf7934 537 .driver = {
b74f3fdd 538 .name = DRVNAME,
cdaf7934 539 },
b74f3fdd 540 .probe = it87_probe,
9e5e9b7a 541 .remove = it87_remove,
fde09509
JD		 542};
543
20ad93d4 544static ssize_t show_in(struct device *dev, struct device_attribute *attr,
929c6a56 545 char *buf)
1da177e4 546{
929c6a56
GR		 547 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
548 int nr = sattr->nr;
549 int index = sattr->index;
20ad93d4 550
1da177e4 551 struct it87_data *data = it87_update_device(dev);
929c6a56 552 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1da177e4
LT		 553}
554
929c6a56
GR		 555static ssize_t set_in(struct device *dev, struct device_attribute *attr,
556 const char *buf, size_t count)
1da177e4 557{
929c6a56
GR		 558 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
559 int nr = sattr->nr;
560 int index = sattr->index;
20ad93d4 561
b74f3fdd 562 struct it87_data *data = dev_get_drvdata(dev);
f5f64501
JD		 563 unsigned long val;
564
179c4fdb 565 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 566 return -EINVAL;
1da177e4 567
9a61bf63 568 mutex_lock(&data->update_lock);
929c6a56
GR		 569 data->in[nr][index] = in_to_reg(data, nr, val);
570 it87_write_value(data,
571 index == 1 ? IT87_REG_VIN_MIN(nr)
572 : IT87_REG_VIN_MAX(nr),
573 data->in[nr][index]);
9a61bf63 574 mutex_unlock(&data->update_lock);
1da177e4
LT		 575 return count;
576}
20ad93d4 577
929c6a56
GR		 578static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
579static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
580 0, 1);
581static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
582 0, 2);
f5f64501 583
929c6a56
GR		 584static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
585static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
586 1, 1);
587static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
588 1, 2);
1da177e4 589
929c6a56
GR		 590static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
591static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
592 2, 1);
593static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
594 2, 2);
1da177e4 595
929c6a56
GR		 596static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
597static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
598 3, 1);
599static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
600 3, 2);
601
602static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
603static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
604 4, 1);
605static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
606 4, 2);
607
608static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
609static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
610 5, 1);
611static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
612 5, 2);
613
614static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
615static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
616 6, 1);
617static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
618 6, 2);
619
620static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
621static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
622 7, 1);
623static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
624 7, 2);
625
626static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
c145d5c6 627static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1da177e4
LT		 628
629/* 3 temperatures */
20ad93d4 630static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
60ca385a 631 char *buf)
1da177e4 632{
60ca385a
GR		 633 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
634 int nr = sattr->nr;
635 int index = sattr->index;
1da177e4 636 struct it87_data *data = it87_update_device(dev);
20ad93d4 637
60ca385a 638 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1da177e4 639}
20ad93d4 640
60ca385a
GR		 641static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
642 const char *buf, size_t count)
1da177e4 643{
60ca385a
GR		 644 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
645 int nr = sattr->nr;
646 int index = sattr->index;
b74f3fdd 647 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 648 long val;
161d898a 649 u8 reg, regval;
f5f64501 650
179c4fdb 651 if (kstrtol(buf, 10, &val) < 0)
f5f64501 652 return -EINVAL;
1da177e4 653
9a61bf63 654 mutex_lock(&data->update_lock);
161d898a
GR		 655
656 switch (index) {
657 default:
658 case 1:
659 reg = IT87_REG_TEMP_LOW(nr);
660 break;
661 case 2:
662 reg = IT87_REG_TEMP_HIGH(nr);
663 break;
664 case 3:
665 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
666 if (!(regval & 0x80)) {
667 regval |= 0x80;
668 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
669 }
670 data->valid = 0;
671 reg = IT87_REG_TEMP_OFFSET[nr];
672 break;
673 }
674
60ca385a 675 data->temp[nr][index] = TEMP_TO_REG(val);
161d898a 676 it87_write_value(data, reg, data->temp[nr][index]);
9a61bf63 677 mutex_unlock(&data->update_lock);
1da177e4
LT		 678 return count;
679}
1da177e4 680
60ca385a
GR		 681static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
682static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
683 0, 1);
684static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
685 0, 2);
161d898a
GR		 686static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
687 set_temp, 0, 3);
60ca385a
GR		 688static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
689static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
690 1, 1);
691static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
692 1, 2);
161d898a
GR		 693static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
694 set_temp, 1, 3);
60ca385a
GR		 695static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
696static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
697 2, 1);
698static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
699 2, 2);
161d898a
GR		 700static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
701 set_temp, 2, 3);
1da177e4 702
2cece01f
GR		 703static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
704 char *buf)
1da177e4 705{
20ad93d4
JD		 706 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
707 int nr = sensor_attr->index;
1da177e4 708 struct it87_data *data = it87_update_device(dev);
4a0d71cf 709 u8 reg = data->sensor; /* In case value is updated while used */
19529784 710 u8 extra = data->extra;
5f2dc798 711
19529784
GR		 712 if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1))
713 || (has_temp_old_peci(data, nr) && (extra & 0x80)))
5d8d2f2b 714 return sprintf(buf, "6\n"); /* Intel PECI */
1da177e4
LT		 715 if (reg & (1 << nr))
716 return sprintf(buf, "3\n"); /* thermal diode */
717 if (reg & (8 << nr))
4ed10779 718 return sprintf(buf, "4\n"); /* thermistor */
1da177e4
LT		 719 return sprintf(buf, "0\n"); /* disabled */
720}
2cece01f
GR		 721
722static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
723 const char *buf, size_t count)
1da177e4 724{
20ad93d4
JD		 725 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
726 int nr = sensor_attr->index;
727
b74f3fdd 728 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 729 long val;
19529784 730 u8 reg, extra;
f5f64501 731
179c4fdb 732 if (kstrtol(buf, 10, &val) < 0)
f5f64501 733 return -EINVAL;
1da177e4 734
8acf07c5
JD		 735 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
736 reg &= ~(1 << nr);
737 reg &= ~(8 << nr);
5d8d2f2b
GR		 738 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
739 reg &= 0x3f;
19529784
GR		 740 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
741 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
742 extra &= 0x7f;
4ed10779 743 if (val == 2) { /* backwards compatibility */
1d9bcf6a
GR		 744 dev_warn(dev,
745 "Sensor type 2 is deprecated, please use 4 instead\n");
4ed10779
JD		 746 val = 4;
747 }
5d8d2f2b 748 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1da177e4 749 if (val == 3)
8acf07c5 750 reg |= 1 << nr;
4ed10779 751 else if (val == 4)
8acf07c5 752 reg |= 8 << nr;
5d8d2f2b
GR		 753 else if (has_temp_peci(data, nr) && val == 6)
754 reg |= (nr + 1) << 6;
19529784
GR		 755 else if (has_temp_old_peci(data, nr) && val == 6)
756 extra |= 0x80;
8acf07c5 757 else if (val != 0)
1da177e4 758 return -EINVAL;
8acf07c5
JD		 759
760 mutex_lock(&data->update_lock);
761 data->sensor = reg;
19529784 762 data->extra = extra;
b74f3fdd 763 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
19529784
GR		 764 if (has_temp_old_peci(data, nr))
765 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
2b3d1d87 766 data->valid = 0; /* Force cache refresh */
9a61bf63 767 mutex_unlock(&data->update_lock);
1da177e4
LT		 768 return count;
769}
1da177e4 770
2cece01f
GR		 771static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
772 set_temp_type, 0);
773static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
774 set_temp_type, 1);
775static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
776 set_temp_type, 2);
1da177e4
LT		 777
778/* 3 Fans */
b99883dc
JD		 779
780static int pwm_mode(const struct it87_data *data, int nr)
781{
782 int ctrl = data->fan_main_ctrl & (1 << nr);
783
c145d5c6 784 if (ctrl == 0 && data->type != it8603) /* Full speed */
b99883dc
JD		 785 return 0;
786 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
787 return 2;
788 else /* Manual mode */
789 return 1;
790}
791
20ad93d4 792static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
e1169ba0 793 char *buf)
1da177e4 794{
e1169ba0
GR		 795 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
796 int nr = sattr->nr;
797 int index = sattr->index;
798 int speed;
1da177e4 799 struct it87_data *data = it87_update_device(dev);
20ad93d4 800
e1169ba0
GR		 801 speed = has_16bit_fans(data) ?
802 FAN16_FROM_REG(data->fan[nr][index]) :
803 FAN_FROM_REG(data->fan[nr][index],
804 DIV_FROM_REG(data->fan_div[nr]));
805 return sprintf(buf, "%d\n", speed);
1da177e4 806}
e1169ba0 807
20ad93d4
JD		 808static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
809 char *buf)
1da177e4 810{
20ad93d4
JD		 811 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
812 int nr = sensor_attr->index;
813
1da177e4
LT		 814 struct it87_data *data = it87_update_device(dev);
815 return sprintf(buf, "%d\n", DIV_FROM_REG(data->fan_div[nr]));
816}
5f2dc798
JD		 817static ssize_t show_pwm_enable(struct device *dev,
818 struct device_attribute *attr, char *buf)
1da177e4 819{
20ad93d4
JD		 820 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
821 int nr = sensor_attr->index;
822
1da177e4 823 struct it87_data *data = it87_update_device(dev);
b99883dc 824 return sprintf(buf, "%d\n", pwm_mode(data, nr));
1da177e4 825}
20ad93d4
JD		 826static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
827 char *buf)
1da177e4 828{
20ad93d4
JD		 829 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
830 int nr = sensor_attr->index;
831
1da177e4 832 struct it87_data *data = it87_update_device(dev);
44c1bcd4
JD		 833 return sprintf(buf, "%d\n",
834 pwm_from_reg(data, data->pwm_duty[nr]));
1da177e4 835}
f8d0c19a
JD		 836static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
837 char *buf)
838{
839 struct it87_data *data = it87_update_device(dev);
840 int index = (data->fan_ctl >> 4) & 0x07;
f56c9c0a 841 unsigned int freq;
f8d0c19a 842
f56c9c0a
GR		 843 freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
844
845 return sprintf(buf, "%u\n", freq);
f8d0c19a 846}
e1169ba0
GR		 847
848static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
849 const char *buf, size_t count)
1da177e4 850{
e1169ba0
GR		 851 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
852 int nr = sattr->nr;
853 int index = sattr->index;
20ad93d4 854
b74f3fdd 855 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 856 long val;
7f999aa7 857 u8 reg;
1da177e4 858
179c4fdb 859 if (kstrtol(buf, 10, &val) < 0)
f5f64501
JD		 860 return -EINVAL;
861
9a61bf63 862 mutex_lock(&data->update_lock);
e1169ba0
GR		 863
864 if (has_16bit_fans(data)) {
865 data->fan[nr][index] = FAN16_TO_REG(val);
866 it87_write_value(data, IT87_REG_FAN_MIN[nr],
867 data->fan[nr][index] & 0xff);
868 it87_write_value(data, IT87_REG_FANX_MIN[nr],
869 data->fan[nr][index] >> 8);
870 } else {
871 reg = it87_read_value(data, IT87_REG_FAN_DIV);
872 switch (nr) {
873 case 0:
874 data->fan_div[nr] = reg & 0x07;
875 break;
876 case 1:
877 data->fan_div[nr] = (reg >> 3) & 0x07;
878 break;
879 case 2:
880 data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
881 break;
882 }
883 data->fan[nr][index] =
884 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
885 it87_write_value(data, IT87_REG_FAN_MIN[nr],
886 data->fan[nr][index]);
07eab46d
JD		 887 }
888
9a61bf63 889 mutex_unlock(&data->update_lock);
1da177e4
LT		 890 return count;
891}
e1169ba0 892
20ad93d4
JD		 893static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
894 const char *buf, size_t count)
1da177e4 895{
20ad93d4
JD		 896 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
897 int nr = sensor_attr->index;
898
b74f3fdd 899 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 900 unsigned long val;
8ab4ec3e 901 int min;
1da177e4
LT		 902 u8 old;
903
179c4fdb 904 if (kstrtoul(buf, 10, &val) < 0)
f5f64501
JD		 905 return -EINVAL;
906
9a61bf63 907 mutex_lock(&data->update_lock);
b74f3fdd 908 old = it87_read_value(data, IT87_REG_FAN_DIV);
1da177e4 909
8ab4ec3e 910 /* Save fan min limit */
e1169ba0 911 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1da177e4
LT		 912
913 switch (nr) {
914 case 0:
915 case 1:
916 data->fan_div[nr] = DIV_TO_REG(val);
917 break;
918 case 2:
919 if (val < 8)
920 data->fan_div[nr] = 1;
921 else
922 data->fan_div[nr] = 3;
923 }
924 val = old & 0x80;
925 val |= (data->fan_div[0] & 0x07);
926 val |= (data->fan_div[1] & 0x07) << 3;
927 if (data->fan_div[2] == 3)
928 val |= 0x1 << 6;
b74f3fdd 929 it87_write_value(data, IT87_REG_FAN_DIV, val);
1da177e4 930
8ab4ec3e 931 /* Restore fan min limit */
e1169ba0
GR		 932 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
933 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]);
8ab4ec3e 934
9a61bf63 935 mutex_unlock(&data->update_lock);
1da177e4
LT		 936 return count;
937}
cccfc9c4
JD		 938
939/* Returns 0 if OK, -EINVAL otherwise */
940static int check_trip_points(struct device *dev, int nr)
941{
942 const struct it87_data *data = dev_get_drvdata(dev);
943 int i, err = 0;
944
945 if (has_old_autopwm(data)) {
946 for (i = 0; i < 3; i++) {
947 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
948 err = -EINVAL;
949 }
950 for (i = 0; i < 2; i++) {
951 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
952 err = -EINVAL;
953 }
954 }
955
956 if (err) {
1d9bcf6a
GR		 957 dev_err(dev,
958 "Inconsistent trip points, not switching to automatic mode\n");
cccfc9c4
JD		 959 dev_err(dev, "Adjust the trip points and try again\n");
960 }
961 return err;
962}
963
20ad93d4
JD		 964static ssize_t set_pwm_enable(struct device *dev,
965 struct device_attribute *attr, const char *buf, size_t count)
1da177e4 966{
20ad93d4
JD		 967 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
968 int nr = sensor_attr->index;
969
b74f3fdd 970 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 971 long val;
1da177e4 972
179c4fdb 973 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
b99883dc
JD		 974 return -EINVAL;
975
cccfc9c4
JD		 976 /* Check trip points before switching to automatic mode */
977 if (val == 2) {
978 if (check_trip_points(dev, nr) < 0)
979 return -EINVAL;
980 }
981
c145d5c6
RM		 982 /* IT8603E does not have on/off mode */
983 if (val == 0 && data->type == it8603)
984 return -EINVAL;
985
9a61bf63 986 mutex_lock(&data->update_lock);
1da177e4
LT		 987
988 if (val == 0) {
989 int tmp;
990 /* make sure the fan is on when in on/off mode */
b74f3fdd 991 tmp = it87_read_value(data, IT87_REG_FAN_CTL);
992 it87_write_value(data, IT87_REG_FAN_CTL, tmp | (1 << nr));
1da177e4
LT		 993 /* set on/off mode */
994 data->fan_main_ctrl &= ~(1 << nr);
5f2dc798
JD		 995 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
996 data->fan_main_ctrl);
b99883dc
JD		 997 } else {
998 if (val == 1) /* Manual mode */
16b5dda2 999 data->pwm_ctrl[nr] = has_newer_autopwm(data) ?
6229cdb2
JD		 1000 data->pwm_temp_map[nr] :
1001 data->pwm_duty[nr];
b99883dc
JD		 1002 else /* Automatic mode */
1003 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
1004 it87_write_value(data, IT87_REG_PWM(nr), data->pwm_ctrl[nr]);
c145d5c6
RM		 1005
1006 if (data->type != it8603) {
1007 /* set SmartGuardian mode */
1008 data->fan_main_ctrl |= (1 << nr);
1009 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1010 data->fan_main_ctrl);
1011 }
1da177e4
LT		 1012 }
1013
9a61bf63 1014 mutex_unlock(&data->update_lock);
1da177e4
LT		 1015 return count;
1016}
20ad93d4
JD		 1017static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1018 const char *buf, size_t count)
1da177e4 1019{
20ad93d4
JD		 1020 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1021 int nr = sensor_attr->index;
1022
b74f3fdd 1023 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 1024 long val;
1da177e4 1025
179c4fdb 1026 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1da177e4
LT		 1027 return -EINVAL;
1028
9a61bf63 1029 mutex_lock(&data->update_lock);
16b5dda2 1030 if (has_newer_autopwm(data)) {
4a0d71cf
GR		 1031 /*
1032 * If we are in automatic mode, the PWM duty cycle register
1033 * is read-only so we can't write the value.
1034 */
6229cdb2
JD		 1035 if (data->pwm_ctrl[nr] & 0x80) {
1036 mutex_unlock(&data->update_lock);
1037 return -EBUSY;
1038 }
1039 data->pwm_duty[nr] = pwm_to_reg(data, val);
1040 it87_write_value(data, IT87_REG_PWM_DUTY(nr),
1041 data->pwm_duty[nr]);
1042 } else {
1043 data->pwm_duty[nr] = pwm_to_reg(data, val);
4a0d71cf
GR		 1044 /*
1045 * If we are in manual mode, write the duty cycle immediately;
1046 * otherwise, just store it for later use.
1047 */
6229cdb2
JD		 1048 if (!(data->pwm_ctrl[nr] & 0x80)) {
1049 data->pwm_ctrl[nr] = data->pwm_duty[nr];
1050 it87_write_value(data, IT87_REG_PWM(nr),
1051 data->pwm_ctrl[nr]);
1052 }
b99883dc 1053 }
9a61bf63 1054 mutex_unlock(&data->update_lock);
1da177e4
LT		 1055 return count;
1056}
f8d0c19a
JD		 1057static ssize_t set_pwm_freq(struct device *dev,
1058 struct device_attribute *attr, const char *buf, size_t count)
1059{
b74f3fdd 1060 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 1061 unsigned long val;
f8d0c19a
JD		 1062 int i;
1063
179c4fdb 1064 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 1065 return -EINVAL;
f56c9c0a
GR		 1066
1067 val = clamp_val(val, 0, 1000000);
1068 val *= has_newer_autopwm(data) ? 256 : 128;
f5f64501 1069
f8d0c19a
JD		 1070 /* Search for the nearest available frequency */
1071 for (i = 0; i < 7; i++) {
1072 if (val > (pwm_freq[i] + pwm_freq[i+1]) / 2)
1073 break;
1074 }
1075
1076 mutex_lock(&data->update_lock);
b74f3fdd 1077 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
f8d0c19a 1078 data->fan_ctl |= i << 4;
b74f3fdd 1079 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
f8d0c19a
JD		 1080 mutex_unlock(&data->update_lock);
1081
1082 return count;
1083}
94ac7ee6
JD		 1084static ssize_t show_pwm_temp_map(struct device *dev,
1085 struct device_attribute *attr, char *buf)
1086{
1087 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1088 int nr = sensor_attr->index;
1089
1090 struct it87_data *data = it87_update_device(dev);
1091 int map;
1092
1093 if (data->pwm_temp_map[nr] < 3)
1094 map = 1 << data->pwm_temp_map[nr];
1095 else
1096 map = 0; /* Should never happen */
1097 return sprintf(buf, "%d\n", map);
1098}
1099static ssize_t set_pwm_temp_map(struct device *dev,
1100 struct device_attribute *attr, const char *buf, size_t count)
1101{
1102 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1103 int nr = sensor_attr->index;
1104
1105 struct it87_data *data = dev_get_drvdata(dev);
1106 long val;
1107 u8 reg;
1108
4a0d71cf
GR		 1109 /*
1110 * This check can go away if we ever support automatic fan speed
1111 * control on newer chips.
1112 */
4f3f51bc
JD		 1113 if (!has_old_autopwm(data)) {
1114 dev_notice(dev, "Mapping change disabled for safety reasons\n");
1115 return -EINVAL;
1116 }
1117
179c4fdb 1118 if (kstrtol(buf, 10, &val) < 0)
94ac7ee6
JD		 1119 return -EINVAL;
1120
1121 switch (val) {
1122 case (1 << 0):
1123 reg = 0x00;
1124 break;
1125 case (1 << 1):
1126 reg = 0x01;
1127 break;
1128 case (1 << 2):
1129 reg = 0x02;
1130 break;
1131 default:
1132 return -EINVAL;
1133 }
1134
1135 mutex_lock(&data->update_lock);
1136 data->pwm_temp_map[nr] = reg;
4a0d71cf
GR		 1137 /*
1138 * If we are in automatic mode, write the temp mapping immediately;
1139 * otherwise, just store it for later use.
1140 */
94ac7ee6
JD		 1141 if (data->pwm_ctrl[nr] & 0x80) {
1142 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
1143 it87_write_value(data, IT87_REG_PWM(nr), data->pwm_ctrl[nr]);
1144 }
1145 mutex_unlock(&data->update_lock);
1146 return count;
1147}
1da177e4 1148
4f3f51bc
JD		 1149static ssize_t show_auto_pwm(struct device *dev,
1150 struct device_attribute *attr, char *buf)
1151{
1152 struct it87_data *data = it87_update_device(dev);
1153 struct sensor_device_attribute_2 *sensor_attr =
1154 to_sensor_dev_attr_2(attr);
1155 int nr = sensor_attr->nr;
1156 int point = sensor_attr->index;
1157
44c1bcd4
JD		 1158 return sprintf(buf, "%d\n",
1159 pwm_from_reg(data, data->auto_pwm[nr][point]));
4f3f51bc
JD		 1160}
1161
1162static ssize_t set_auto_pwm(struct device *dev,
1163 struct device_attribute *attr, const char *buf, size_t count)
1164{
1165 struct it87_data *data = dev_get_drvdata(dev);
1166 struct sensor_device_attribute_2 *sensor_attr =
1167 to_sensor_dev_attr_2(attr);
1168 int nr = sensor_attr->nr;
1169 int point = sensor_attr->index;
1170 long val;
1171
179c4fdb 1172 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
4f3f51bc
JD		 1173 return -EINVAL;
1174
1175 mutex_lock(&data->update_lock);
44c1bcd4 1176 data->auto_pwm[nr][point] = pwm_to_reg(data, val);
4f3f51bc
JD		 1177 it87_write_value(data, IT87_REG_AUTO_PWM(nr, point),
1178 data->auto_pwm[nr][point]);
1179 mutex_unlock(&data->update_lock);
1180 return count;
1181}
1182
1183static ssize_t show_auto_temp(struct device *dev,
1184 struct device_attribute *attr, char *buf)
1185{
1186 struct it87_data *data = it87_update_device(dev);
1187 struct sensor_device_attribute_2 *sensor_attr =
1188 to_sensor_dev_attr_2(attr);
1189 int nr = sensor_attr->nr;
1190 int point = sensor_attr->index;
1191
1192 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->auto_temp[nr][point]));
1193}
1194
1195static ssize_t set_auto_temp(struct device *dev,
1196 struct device_attribute *attr, const char *buf, size_t count)
1197{
1198 struct it87_data *data = dev_get_drvdata(dev);
1199 struct sensor_device_attribute_2 *sensor_attr =
1200 to_sensor_dev_attr_2(attr);
1201 int nr = sensor_attr->nr;
1202 int point = sensor_attr->index;
1203 long val;
1204
179c4fdb 1205 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
4f3f51bc
JD		 1206 return -EINVAL;
1207
1208 mutex_lock(&data->update_lock);
1209 data->auto_temp[nr][point] = TEMP_TO_REG(val);
1210 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point),
1211 data->auto_temp[nr][point]);
1212 mutex_unlock(&data->update_lock);
1213 return count;
1214}
1215
e1169ba0
GR		 1216static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1217static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1218 0, 1);
1219static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1220 set_fan_div, 0);
1221
1222static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1223static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1224 1, 1);
1225static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1226 set_fan_div, 1);
1227
1228static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1229static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1230 2, 1);
1231static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1232 set_fan_div, 2);
1233
1234static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1235static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1236 3, 1);
1da177e4 1237
e1169ba0
GR		 1238static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1239static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1240 4, 1);
1da177e4 1241
c4458db3
GR		 1242static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
1243 show_pwm_enable, set_pwm_enable, 0);
1244static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
1245static DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq, set_pwm_freq);
1246static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO | S_IWUSR,
1247 show_pwm_temp_map, set_pwm_temp_map, 0);
1248static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
1249 show_auto_pwm, set_auto_pwm, 0, 0);
1250static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
1251 show_auto_pwm, set_auto_pwm, 0, 1);
1252static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
1253 show_auto_pwm, set_auto_pwm, 0, 2);
1254static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
1255 show_auto_pwm, NULL, 0, 3);
1256static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
1257 show_auto_temp, set_auto_temp, 0, 1);
1258static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1259 show_auto_temp, set_auto_temp, 0, 0);
1260static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
1261 show_auto_temp, set_auto_temp, 0, 2);
1262static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
1263 show_auto_temp, set_auto_temp, 0, 3);
1264static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
1265 show_auto_temp, set_auto_temp, 0, 4);
1266
1267static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
1268 show_pwm_enable, set_pwm_enable, 1);
1269static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
1270static DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, NULL);
1271static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO | S_IWUSR,
1272 show_pwm_temp_map, set_pwm_temp_map, 1);
1273static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
1274 show_auto_pwm, set_auto_pwm, 1, 0);
1275static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
1276 show_auto_pwm, set_auto_pwm, 1, 1);
1277static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
1278 show_auto_pwm, set_auto_pwm, 1, 2);
1279static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
1280 show_auto_pwm, NULL, 1, 3);
1281static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
1282 show_auto_temp, set_auto_temp, 1, 1);
1283static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1284 show_auto_temp, set_auto_temp, 1, 0);
1285static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
1286 show_auto_temp, set_auto_temp, 1, 2);
1287static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
1288 show_auto_temp, set_auto_temp, 1, 3);
1289static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
1290 show_auto_temp, set_auto_temp, 1, 4);
1291
1292static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
1293 show_pwm_enable, set_pwm_enable, 2);
1294static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
1295static DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL);
1296static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO | S_IWUSR,
1297 show_pwm_temp_map, set_pwm_temp_map, 2);
1298static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
1299 show_auto_pwm, set_auto_pwm, 2, 0);
1300static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
1301 show_auto_pwm, set_auto_pwm, 2, 1);
1302static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
1303 show_auto_pwm, set_auto_pwm, 2, 2);
1304static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
1305 show_auto_pwm, NULL, 2, 3);
1306static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
1307 show_auto_temp, set_auto_temp, 2, 1);
1308static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1309 show_auto_temp, set_auto_temp, 2, 0);
1310static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
1311 show_auto_temp, set_auto_temp, 2, 2);
1312static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
1313 show_auto_temp, set_auto_temp, 2, 3);
1314static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
1315 show_auto_temp, set_auto_temp, 2, 4);
1da177e4
LT		 1316
1317/* Alarms */
5f2dc798
JD		 1318static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
1319 char *buf)
1da177e4
LT		 1320{
1321 struct it87_data *data = it87_update_device(dev);
68188ba7 1322 return sprintf(buf, "%u\n", data->alarms);
1da177e4 1323}
1d66c64c 1324static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
1da177e4 1325
0124dd78
JD		 1326static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
1327 char *buf)
1328{
1329 int bitnr = to_sensor_dev_attr(attr)->index;
1330 struct it87_data *data = it87_update_device(dev);
1331 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
1332}
3d30f9e6
JD		 1333
1334static ssize_t clear_intrusion(struct device *dev, struct device_attribute
1335 *attr, const char *buf, size_t count)
1336{
1337 struct it87_data *data = dev_get_drvdata(dev);
1338 long val;
1339 int config;
1340
179c4fdb 1341 if (kstrtol(buf, 10, &val) < 0 || val != 0)
3d30f9e6
JD		 1342 return -EINVAL;
1343
1344 mutex_lock(&data->update_lock);
1345 config = it87_read_value(data, IT87_REG_CONFIG);
1346 if (config < 0) {
1347 count = config;
1348 } else {
1349 config |= 1 << 5;
1350 it87_write_value(data, IT87_REG_CONFIG, config);
1351 /* Invalidate cache to force re-read */
1352 data->valid = 0;
1353 }
1354 mutex_unlock(&data->update_lock);
1355
1356 return count;
1357}
1358
0124dd78
JD		 1359static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
1360static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
1361static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
1362static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
1363static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
1364static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
1365static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
1366static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
1367static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
1368static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
1369static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
1370static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
1371static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
1372static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
1373static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
1374static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
3d30f9e6
JD		 1375static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
1376 show_alarm, clear_intrusion, 4);
0124dd78 1377
d9b327c3
JD		 1378static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
1379 char *buf)
1380{
1381 int bitnr = to_sensor_dev_attr(attr)->index;
1382 struct it87_data *data = it87_update_device(dev);
1383 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
1384}
1385static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
1386 const char *buf, size_t count)
1387{
1388 int bitnr = to_sensor_dev_attr(attr)->index;
1389 struct it87_data *data = dev_get_drvdata(dev);
1390 long val;
1391
179c4fdb 1392 if (kstrtol(buf, 10, &val) < 0
d9b327c3
JD		 1393 || (val != 0 && val != 1))
1394 return -EINVAL;
1395
1396 mutex_lock(&data->update_lock);
1397 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1398 if (val)
1399 data->beeps |= (1 << bitnr);
1400 else
1401 data->beeps &= ~(1 << bitnr);
1402 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
1403 mutex_unlock(&data->update_lock);
1404 return count;
1405}
1406
1407static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
1408 show_beep, set_beep, 1);
1409static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
1410static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
1411static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
1412static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
1413static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
1414static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
1415static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
1416/* fanX_beep writability is set later */
1417static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
1418static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
1419static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
1420static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
1421static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
1422static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
1423 show_beep, set_beep, 2);
1424static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
1425static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
1426
5f2dc798
JD		 1427static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
1428 char *buf)
1da177e4 1429{
90d6619a 1430 struct it87_data *data = dev_get_drvdata(dev);
a7be58a1 1431 return sprintf(buf, "%u\n", data->vrm);
1da177e4 1432}
5f2dc798
JD		 1433static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
1434 const char *buf, size_t count)
1da177e4 1435{
b74f3fdd 1436 struct it87_data *data = dev_get_drvdata(dev);
f5f64501
JD		 1437 unsigned long val;
1438
179c4fdb 1439 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 1440 return -EINVAL;
1da177e4 1441
1da177e4
LT		 1442 data->vrm = val;
1443
1444 return count;
1445}
1446static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
1da177e4 1447
5f2dc798
JD		 1448static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
1449 char *buf)
1da177e4
LT		 1450{
1451 struct it87_data *data = it87_update_device(dev);
1452 return sprintf(buf, "%ld\n", (long) vid_from_reg(data->vid, data->vrm));
1453}
1454static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
87808be4 1455
738e5e05
JD		 1456static ssize_t show_label(struct device *dev, struct device_attribute *attr,
1457 char *buf)
1458{
3c4c4971 1459 static const char * const labels[] = {
738e5e05
JD		 1460 "+5V",
1461 "5VSB",
1462 "Vbat",
1463 };
3c4c4971 1464 static const char * const labels_it8721[] = {
44c1bcd4
JD		 1465 "+3.3V",
1466 "3VSB",
1467 "Vbat",
1468 };
1469 struct it87_data *data = dev_get_drvdata(dev);
738e5e05
JD		 1470 int nr = to_sensor_dev_attr(attr)->index;
1471
16b5dda2
JD		 1472 return sprintf(buf, "%s\n", has_12mv_adc(data) ? labels_it8721[nr]
1473 : labels[nr]);
738e5e05
JD		 1474}
1475static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
1476static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
1477static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
7183ae8c 1478/* special AVCC3 IT8603E in9 */
c145d5c6 1479static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 0);
738e5e05 1480
b74f3fdd 1481static ssize_t show_name(struct device *dev, struct device_attribute
1482 *devattr, char *buf)
1483{
1484 struct it87_data *data = dev_get_drvdata(dev);
1485 return sprintf(buf, "%s\n", data->name);
1486}
1487static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
1488
c145d5c6 1489static struct attribute *it87_attributes_in[10][5] = {
9172b5d1 1490{
87808be4 1491 &sensor_dev_attr_in0_input.dev_attr.attr,
87808be4 1492 &sensor_dev_attr_in0_min.dev_attr.attr,
87808be4 1493 &sensor_dev_attr_in0_max.dev_attr.attr,
0124dd78 1494 &sensor_dev_attr_in0_alarm.dev_attr.attr,
9172b5d1
GR		 1495 NULL
1496}, {
1497 &sensor_dev_attr_in1_input.dev_attr.attr,
1498 &sensor_dev_attr_in1_min.dev_attr.attr,
1499 &sensor_dev_attr_in1_max.dev_attr.attr,
0124dd78 1500 &sensor_dev_attr_in1_alarm.dev_attr.attr,
9172b5d1
GR		 1501 NULL
1502}, {
1503 &sensor_dev_attr_in2_input.dev_attr.attr,
1504 &sensor_dev_attr_in2_min.dev_attr.attr,
1505 &sensor_dev_attr_in2_max.dev_attr.attr,
0124dd78 1506 &sensor_dev_attr_in2_alarm.dev_attr.attr,
9172b5d1
GR		 1507 NULL
1508}, {
1509 &sensor_dev_attr_in3_input.dev_attr.attr,
1510 &sensor_dev_attr_in3_min.dev_attr.attr,
1511 &sensor_dev_attr_in3_max.dev_attr.attr,
0124dd78 1512 &sensor_dev_attr_in3_alarm.dev_attr.attr,
9172b5d1
GR		 1513 NULL
1514}, {
1515 &sensor_dev_attr_in4_input.dev_attr.attr,
1516 &sensor_dev_attr_in4_min.dev_attr.attr,
1517 &sensor_dev_attr_in4_max.dev_attr.attr,
0124dd78 1518 &sensor_dev_attr_in4_alarm.dev_attr.attr,
9172b5d1
GR		 1519 NULL
1520}, {
1521 &sensor_dev_attr_in5_input.dev_attr.attr,
1522 &sensor_dev_attr_in5_min.dev_attr.attr,
1523 &sensor_dev_attr_in5_max.dev_attr.attr,
0124dd78 1524 &sensor_dev_attr_in5_alarm.dev_attr.attr,
9172b5d1
GR		 1525 NULL
1526}, {
1527 &sensor_dev_attr_in6_input.dev_attr.attr,
1528 &sensor_dev_attr_in6_min.dev_attr.attr,
1529 &sensor_dev_attr_in6_max.dev_attr.attr,
0124dd78 1530 &sensor_dev_attr_in6_alarm.dev_attr.attr,
9172b5d1
GR		 1531 NULL
1532}, {
1533 &sensor_dev_attr_in7_input.dev_attr.attr,
1534 &sensor_dev_attr_in7_min.dev_attr.attr,
1535 &sensor_dev_attr_in7_max.dev_attr.attr,
0124dd78 1536 &sensor_dev_attr_in7_alarm.dev_attr.attr,
9172b5d1
GR		 1537 NULL
1538}, {
1539 &sensor_dev_attr_in8_input.dev_attr.attr,
1540 NULL
c145d5c6
RM		 1541}, {
1542 &sensor_dev_attr_in9_input.dev_attr.attr,
1543 NULL
9172b5d1 1544} };
87808be4 1545
c145d5c6 1546static const struct attribute_group it87_group_in[10] = {
9172b5d1
GR		 1547 { .attrs = it87_attributes_in[0] },
1548 { .attrs = it87_attributes_in[1] },
1549 { .attrs = it87_attributes_in[2] },
1550 { .attrs = it87_attributes_in[3] },
1551 { .attrs = it87_attributes_in[4] },
1552 { .attrs = it87_attributes_in[5] },
1553 { .attrs = it87_attributes_in[6] },
1554 { .attrs = it87_attributes_in[7] },
1555 { .attrs = it87_attributes_in[8] },
c145d5c6 1556 { .attrs = it87_attributes_in[9] },
9172b5d1
GR		 1557};
1558
4573acbc
GR		 1559static struct attribute *it87_attributes_temp[3][6] = {
1560{
87808be4 1561 &sensor_dev_attr_temp1_input.dev_attr.attr,
87808be4 1562 &sensor_dev_attr_temp1_max.dev_attr.attr,
87808be4 1563 &sensor_dev_attr_temp1_min.dev_attr.attr,
87808be4 1564 &sensor_dev_attr_temp1_type.dev_attr.attr,
0124dd78 1565 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
4573acbc
GR		 1566 NULL
1567} , {
1568 &sensor_dev_attr_temp2_input.dev_attr.attr,
1569 &sensor_dev_attr_temp2_max.dev_attr.attr,
1570 &sensor_dev_attr_temp2_min.dev_attr.attr,
1571 &sensor_dev_attr_temp2_type.dev_attr.attr,
0124dd78 1572 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
4573acbc
GR		 1573 NULL
1574} , {
1575 &sensor_dev_attr_temp3_input.dev_attr.attr,
1576 &sensor_dev_attr_temp3_max.dev_attr.attr,
1577 &sensor_dev_attr_temp3_min.dev_attr.attr,
1578 &sensor_dev_attr_temp3_type.dev_attr.attr,
0124dd78 1579 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
4573acbc
GR		 1580 NULL
1581} };
1582
1583static const struct attribute_group it87_group_temp[3] = {
1584 { .attrs = it87_attributes_temp[0] },
1585 { .attrs = it87_attributes_temp[1] },
1586 { .attrs = it87_attributes_temp[2] },
1587};
87808be4 1588
161d898a
GR		 1589static struct attribute *it87_attributes_temp_offset[] = {
1590 &sensor_dev_attr_temp1_offset.dev_attr.attr,
1591 &sensor_dev_attr_temp2_offset.dev_attr.attr,
1592 &sensor_dev_attr_temp3_offset.dev_attr.attr,
1593};
1594
4573acbc 1595static struct attribute *it87_attributes[] = {
87808be4 1596 &dev_attr_alarms.attr,
3d30f9e6 1597 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
b74f3fdd 1598 &dev_attr_name.attr,
87808be4
JD		 1599 NULL
1600};
1601
1602static const struct attribute_group it87_group = {
1603 .attrs = it87_attributes,
1604};
1605
9172b5d1 1606static struct attribute *it87_attributes_in_beep[] = {
d9b327c3
JD		 1607 &sensor_dev_attr_in0_beep.dev_attr.attr,
1608 &sensor_dev_attr_in1_beep.dev_attr.attr,
1609 &sensor_dev_attr_in2_beep.dev_attr.attr,
1610 &sensor_dev_attr_in3_beep.dev_attr.attr,
1611 &sensor_dev_attr_in4_beep.dev_attr.attr,
1612 &sensor_dev_attr_in5_beep.dev_attr.attr,
1613 &sensor_dev_attr_in6_beep.dev_attr.attr,
1614 &sensor_dev_attr_in7_beep.dev_attr.attr,
c145d5c6
RM		 1615 NULL,
1616 NULL,
9172b5d1 1617};
d9b327c3 1618
4573acbc 1619static struct attribute *it87_attributes_temp_beep[] = {
d9b327c3
JD		 1620 &sensor_dev_attr_temp1_beep.dev_attr.attr,
1621 &sensor_dev_attr_temp2_beep.dev_attr.attr,
1622 &sensor_dev_attr_temp3_beep.dev_attr.attr,
d9b327c3
JD		 1623};
1624
e1169ba0
GR		 1625static struct attribute *it87_attributes_fan[5][3+1] = { {
1626 &sensor_dev_attr_fan1_input.dev_attr.attr,
1627 &sensor_dev_attr_fan1_min.dev_attr.attr,
723a0aa0
JD		 1628 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
1629 NULL
1630}, {
e1169ba0
GR		 1631 &sensor_dev_attr_fan2_input.dev_attr.attr,
1632 &sensor_dev_attr_fan2_min.dev_attr.attr,
723a0aa0
JD		 1633 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
1634 NULL
1635}, {
e1169ba0
GR		 1636 &sensor_dev_attr_fan3_input.dev_attr.attr,
1637 &sensor_dev_attr_fan3_min.dev_attr.attr,
723a0aa0
JD		 1638 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
1639 NULL
1640}, {
e1169ba0
GR		 1641 &sensor_dev_attr_fan4_input.dev_attr.attr,
1642 &sensor_dev_attr_fan4_min.dev_attr.attr,
723a0aa0
JD		 1643 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
1644 NULL
1645}, {
e1169ba0
GR		 1646 &sensor_dev_attr_fan5_input.dev_attr.attr,
1647 &sensor_dev_attr_fan5_min.dev_attr.attr,
723a0aa0
JD		 1648 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
1649 NULL
1650} };
1651
e1169ba0
GR		 1652static const struct attribute_group it87_group_fan[5] = {
1653 { .attrs = it87_attributes_fan[0] },
1654 { .attrs = it87_attributes_fan[1] },
1655 { .attrs = it87_attributes_fan[2] },
1656 { .attrs = it87_attributes_fan[3] },
1657 { .attrs = it87_attributes_fan[4] },
723a0aa0 1658};
87808be4 1659
e1169ba0 1660static const struct attribute *it87_attributes_fan_div[] = {
87808be4 1661 &sensor_dev_attr_fan1_div.dev_attr.attr,
87808be4 1662 &sensor_dev_attr_fan2_div.dev_attr.attr,
87808be4 1663 &sensor_dev_attr_fan3_div.dev_attr.attr,
723a0aa0
JD		 1664};
1665
723a0aa0 1666static struct attribute *it87_attributes_pwm[3][4+1] = { {
87808be4 1667 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
87808be4 1668 &sensor_dev_attr_pwm1.dev_attr.attr,
d5b0b5d6 1669 &dev_attr_pwm1_freq.attr,
94ac7ee6 1670 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
723a0aa0
JD		 1671 NULL
1672}, {
1673 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
1674 &sensor_dev_attr_pwm2.dev_attr.attr,
1675 &dev_attr_pwm2_freq.attr,
94ac7ee6 1676 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
723a0aa0
JD		 1677 NULL
1678}, {
1679 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
1680 &sensor_dev_attr_pwm3.dev_attr.attr,
1681 &dev_attr_pwm3_freq.attr,
94ac7ee6 1682 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
723a0aa0
JD		 1683 NULL
1684} };
87808be4 1685
723a0aa0
JD		 1686static const struct attribute_group it87_group_pwm[3] = {
1687 { .attrs = it87_attributes_pwm[0] },
1688 { .attrs = it87_attributes_pwm[1] },
1689 { .attrs = it87_attributes_pwm[2] },
1690};
1691
4f3f51bc
JD		 1692static struct attribute *it87_attributes_autopwm[3][9+1] = { {
1693 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
1694 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
1695 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
1696 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
1697 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
1698 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
1699 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
1700 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
1701 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
1702 NULL
1703}, {
1704 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
1705 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
1706 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
1707 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
1708 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
1709 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
1710 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
1711 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
1712 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
1713 NULL
1714}, {
1715 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
1716 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
1717 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
1718 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
1719 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
1720 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
1721 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
1722 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
1723 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
1724 NULL
1725} };
1726
1727static const struct attribute_group it87_group_autopwm[3] = {
1728 { .attrs = it87_attributes_autopwm[0] },
1729 { .attrs = it87_attributes_autopwm[1] },
1730 { .attrs = it87_attributes_autopwm[2] },
1731};
1732
d9b327c3
JD		 1733static struct attribute *it87_attributes_fan_beep[] = {
1734 &sensor_dev_attr_fan1_beep.dev_attr.attr,
1735 &sensor_dev_attr_fan2_beep.dev_attr.attr,
1736 &sensor_dev_attr_fan3_beep.dev_attr.attr,
1737 &sensor_dev_attr_fan4_beep.dev_attr.attr,
1738 &sensor_dev_attr_fan5_beep.dev_attr.attr,
1739};
1740
6a8d7acf 1741static struct attribute *it87_attributes_vid[] = {
87808be4
JD		 1742 &dev_attr_vrm.attr,
1743 &dev_attr_cpu0_vid.attr,
1744 NULL
1745};
1746
6a8d7acf
JD		 1747static const struct attribute_group it87_group_vid = {
1748 .attrs = it87_attributes_vid,
87808be4 1749};
1da177e4 1750
738e5e05
JD		 1751static struct attribute *it87_attributes_label[] = {
1752 &sensor_dev_attr_in3_label.dev_attr.attr,
1753 &sensor_dev_attr_in7_label.dev_attr.attr,
1754 &sensor_dev_attr_in8_label.dev_attr.attr,
c145d5c6 1755 &sensor_dev_attr_in9_label.dev_attr.attr,
738e5e05
JD		 1756 NULL
1757};
1758
1759static const struct attribute_group it87_group_label = {
fa8b6975 1760 .attrs = it87_attributes_label,
738e5e05
JD		 1761};
1762
2d8672c5 1763/* SuperIO detection - will change isa_address if a chip is found */
b74f3fdd 1764static int __init it87_find(unsigned short *address,
1765 struct it87_sio_data *sio_data)
1da177e4 1766{
5b0380c9 1767 int err;
b74f3fdd 1768 u16 chip_type;
98dd22c3 1769 const char *board_vendor, *board_name;
1da177e4 1770
5b0380c9
NG		 1771 err = superio_enter();
1772 if (err)
1773 return err;
1774
1775 err = -ENODEV;
67b671bc 1776 chip_type = force_id ? force_id : superio_inw(DEVID);
b74f3fdd 1777
1778 switch (chip_type) {
1779 case IT8705F_DEVID:
1780 sio_data->type = it87;
1781 break;
1782 case IT8712F_DEVID:
1783 sio_data->type = it8712;
1784 break;
1785 case IT8716F_DEVID:
1786 case IT8726F_DEVID:
1787 sio_data->type = it8716;
1788 break;
1789 case IT8718F_DEVID:
1790 sio_data->type = it8718;
1791 break;
b4da93e4
JMS		 1792 case IT8720F_DEVID:
1793 sio_data->type = it8720;
1794 break;
44c1bcd4
JD		 1795 case IT8721F_DEVID:
1796 sio_data->type = it8721;
1797 break;
16b5dda2
JD		 1798 case IT8728F_DEVID:
1799 sio_data->type = it8728;
1800 break;
b0636707
GR		 1801 case IT8771E_DEVID:
1802 sio_data->type = it8771;
1803 break;
1804 case IT8772E_DEVID:
1805 sio_data->type = it8772;
1806 break;
7bc32d29
GR		 1807 case IT8781F_DEVID:
1808 sio_data->type = it8781;
1809 break;
0531d98b
GR		 1810 case IT8782F_DEVID:
1811 sio_data->type = it8782;
1812 break;
1813 case IT8783E_DEVID:
1814 sio_data->type = it8783;
1815 break;
a0c1424a
TL		 1816 case IT8786E_DEVID:
1817 sio_data->type = it8786;
1818 break;
7183ae8c 1819 case IT8603E_DEVID:
574e9bd8 1820 case IT8623E_DEVID:
c145d5c6
RM		 1821 sio_data->type = it8603;
1822 break;
b74f3fdd 1823 case 0xffff: /* No device at all */
1824 goto exit;
1825 default:
a8ca1037 1826 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
b74f3fdd 1827 goto exit;
1828 }
1da177e4 1829
87673dd7 1830 superio_select(PME);
1da177e4 1831 if (!(superio_inb(IT87_ACT_REG) & 0x01)) {
a8ca1037 1832 pr_info("Device not activated, skipping\n");
1da177e4
LT		 1833 goto exit;
1834 }
1835
1836 *address = superio_inw(IT87_BASE_REG) & ~(IT87_EXTENT - 1);
1837 if (*address == 0) {
a8ca1037 1838 pr_info("Base address not set, skipping\n");
1da177e4
LT		 1839 goto exit;
1840 }
1841
1842 err = 0;
0475169c 1843 sio_data->revision = superio_inb(DEVREV) & 0x0f;
c145d5c6 1844 pr_info("Found IT%04x%c chip at 0x%x, revision %d\n", chip_type,
b523bb75 1845 chip_type == 0x8771 || chip_type == 0x8772 ||
a0c1424a
TL		 1846 chip_type == 0x8786 || chip_type == 0x8603 ? 'E' : 'F',
1847 *address, sio_data->revision);
1da177e4 1848
738e5e05
JD		 1849 /* in8 (Vbat) is always internal */
1850 sio_data->internal = (1 << 2);
c145d5c6
RM		 1851 /* Only the IT8603E has in9 */
1852 if (sio_data->type != it8603)
1853 sio_data->skip_in |= (1 << 9);
738e5e05 1854
32dd7c40 1855 if (!(it87_devices[sio_data->type].features & FEAT_VID))
895ff267 1856 sio_data->skip_vid = 1;
d9b327c3 1857
32dd7c40
GR		 1858 /* Read GPIO config and VID value from LDN 7 (GPIO) */
1859 if (sio_data->type == it87) {
d9b327c3
JD		 1860 /* The IT8705F has a different LD number for GPIO */
1861 superio_select(5);
1862 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
0531d98b 1863 } else if (sio_data->type == it8783) {
088ce2ac 1864 int reg25, reg27, reg2a, reg2c, regef;
0531d98b 1865
0531d98b
GR		 1866 superio_select(GPIO);
1867
1868 reg25 = superio_inb(IT87_SIO_GPIO1_REG);
1869 reg27 = superio_inb(IT87_SIO_GPIO3_REG);
088ce2ac
GR		 1870 reg2a = superio_inb(IT87_SIO_PINX1_REG);
1871 reg2c = superio_inb(IT87_SIO_PINX2_REG);
1872 regef = superio_inb(IT87_SIO_SPI_REG);
0531d98b 1873
0531d98b 1874 /* Check if fan3 is there or not */
088ce2ac 1875 if ((reg27 & (1 << 0)) || !(reg2c & (1 << 2)))
0531d98b
GR		 1876 sio_data->skip_fan |= (1 << 2);
1877 if ((reg25 & (1 << 4))
088ce2ac 1878 || (!(reg2a & (1 << 1)) && (regef & (1 << 0))))
0531d98b
GR		 1879 sio_data->skip_pwm |= (1 << 2);
1880
1881 /* Check if fan2 is there or not */
1882 if (reg27 & (1 << 7))
1883 sio_data->skip_fan |= (1 << 1);
1884 if (reg27 & (1 << 3))
1885 sio_data->skip_pwm |= (1 << 1);
1886
1887 /* VIN5 */
088ce2ac 1888 if ((reg27 & (1 << 0)) || (reg2c & (1 << 2)))
9172b5d1 1889 sio_data->skip_in |= (1 << 5); /* No VIN5 */
0531d98b
GR		 1890
1891 /* VIN6 */
9172b5d1
GR		 1892 if (reg27 & (1 << 1))
1893 sio_data->skip_in |= (1 << 6); /* No VIN6 */
0531d98b
GR		 1894
1895 /*
1896 * VIN7
1897 * Does not depend on bit 2 of Reg2C, contrary to datasheet.
1898 */
9172b5d1
GR		 1899 if (reg27 & (1 << 2)) {
1900 /*
1901 * The data sheet is a bit unclear regarding the
1902 * internal voltage divider for VCCH5V. It says
1903 * "This bit enables and switches VIN7 (pin 91) to the
1904 * internal voltage divider for VCCH5V".
1905 * This is different to other chips, where the internal
1906 * voltage divider would connect VIN7 to an internal
1907 * voltage source. Maybe that is the case here as well.
1908 *
1909 * Since we don't know for sure, re-route it if that is
1910 * not the case, and ask the user to report if the
1911 * resulting voltage is sane.
1912 */
088ce2ac
GR		 1913 if (!(reg2c & (1 << 1))) {
1914 reg2c |= (1 << 1);
1915 superio_outb(IT87_SIO_PINX2_REG, reg2c);
9172b5d1
GR		 1916 pr_notice("Routing internal VCCH5V to in7.\n");
1917 }
1918 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
1919 pr_notice("Please report if it displays a reasonable voltage.\n");
1920 }
0531d98b 1921
088ce2ac 1922 if (reg2c & (1 << 0))
0531d98b 1923 sio_data->internal |= (1 << 0);
088ce2ac 1924 if (reg2c & (1 << 1))
0531d98b
GR		 1925 sio_data->internal |= (1 << 1);
1926
1927 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
c145d5c6
RM		 1928 } else if (sio_data->type == it8603) {
1929 int reg27, reg29;
1930
c145d5c6 1931 superio_select(GPIO);
0531d98b 1932
c145d5c6
RM		 1933 reg27 = superio_inb(IT87_SIO_GPIO3_REG);
1934
1935 /* Check if fan3 is there or not */
1936 if (reg27 & (1 << 6))
1937 sio_data->skip_pwm |= (1 << 2);
1938 if (reg27 & (1 << 7))
1939 sio_data->skip_fan |= (1 << 2);
1940
1941 /* Check if fan2 is there or not */
1942 reg29 = superio_inb(IT87_SIO_GPIO5_REG);
1943 if (reg29 & (1 << 1))
1944 sio_data->skip_pwm |= (1 << 1);
1945 if (reg29 & (1 << 2))
1946 sio_data->skip_fan |= (1 << 1);
1947
1948 sio_data->skip_in |= (1 << 5); /* No VIN5 */
1949 sio_data->skip_in |= (1 << 6); /* No VIN6 */
1950
c145d5c6
RM		 1951 sio_data->internal |= (1 << 1); /* in7 is VSB */
1952 sio_data->internal |= (1 << 3); /* in9 is AVCC */
1953
1954 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
895ff267 1955 } else {
87673dd7 1956 int reg;
9172b5d1 1957 bool uart6;
87673dd7
JD		 1958
1959 superio_select(GPIO);
44c1bcd4 1960
895ff267 1961 reg = superio_inb(IT87_SIO_GPIO3_REG);
32dd7c40 1962 if (!sio_data->skip_vid) {
44c1bcd4
JD		 1963 /* We need at least 4 VID pins */
1964 if (reg & 0x0f) {
a8ca1037 1965 pr_info("VID is disabled (pins used for GPIO)\n");
44c1bcd4
JD		 1966 sio_data->skip_vid = 1;
1967 }
895ff267
JD		 1968 }
1969
591ec650
JD		 1970 /* Check if fan3 is there or not */
1971 if (reg & (1 << 6))
1972 sio_data->skip_pwm |= (1 << 2);
1973 if (reg & (1 << 7))
1974 sio_data->skip_fan |= (1 << 2);
1975
1976 /* Check if fan2 is there or not */
1977 reg = superio_inb(IT87_SIO_GPIO5_REG);
1978 if (reg & (1 << 1))
1979 sio_data->skip_pwm |= (1 << 1);
1980 if (reg & (1 << 2))
1981 sio_data->skip_fan |= (1 << 1);
1982
895ff267
JD		 1983 if ((sio_data->type == it8718 || sio_data->type == it8720)
1984 && !(sio_data->skip_vid))
b74f3fdd 1985 sio_data->vid_value = superio_inb(IT87_SIO_VID_REG);
87673dd7
JD		 1986
1987 reg = superio_inb(IT87_SIO_PINX2_REG);
9172b5d1
GR		 1988
1989 uart6 = sio_data->type == it8782 && (reg & (1 << 2));
1990
436cad2a
JD		 1991 /*
1992 * The IT8720F has no VIN7 pin, so VCCH should always be
1993 * routed internally to VIN7 with an internal divider.
1994 * Curiously, there still is a configuration bit to control
1995 * this, which means it can be set incorrectly. And even
1996 * more curiously, many boards out there are improperly
1997 * configured, even though the IT8720F datasheet claims
1998 * that the internal routing of VCCH to VIN7 is the default
1999 * setting. So we force the internal routing in this case.
0531d98b
GR		 2000 *
2001 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
9172b5d1
GR		 2002 * If UART6 is enabled, re-route VIN7 to the internal divider
2003 * if that is not already the case.
436cad2a 2004 */
9172b5d1 2005 if ((sio_data->type == it8720 || uart6) && !(reg & (1 << 1))) {
436cad2a
JD		 2006 reg |= (1 << 1);
2007 superio_outb(IT87_SIO_PINX2_REG, reg);
a8ca1037 2008 pr_notice("Routing internal VCCH to in7\n");
436cad2a 2009 }
87673dd7 2010 if (reg & (1 << 0))
738e5e05 2011 sio_data->internal |= (1 << 0);
16b5dda2 2012 if ((reg & (1 << 1)) || sio_data->type == it8721 ||
a0c1424a
TL		 2013 sio_data->type == it8728 || sio_data->type == it8771 ||
2014 sio_data->type == it8772 || sio_data->type == it8786)
738e5e05 2015 sio_data->internal |= (1 << 1);
d9b327c3 2016
9172b5d1
GR		 2017 /*
2018 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
2019 * While VIN7 can be routed to the internal voltage divider,
2020 * VIN5 and VIN6 are not available if UART6 is enabled.
4573acbc
GR		 2021 *
2022 * Also, temp3 is not available if UART6 is enabled and TEMPIN3
2023 * is the temperature source. Since we can not read the
2024 * temperature source here, skip_temp is preliminary.
9172b5d1 2025 */
4573acbc 2026 if (uart6) {
9172b5d1 2027 sio_data->skip_in |= (1 << 5) | (1 << 6);
4573acbc
GR		 2028 sio_data->skip_temp |= (1 << 2);
2029 }
9172b5d1 2030
d9b327c3 2031 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
87673dd7 2032 }
d9b327c3 2033 if (sio_data->beep_pin)
a8ca1037 2034 pr_info("Beeping is supported\n");
87673dd7 2035
98dd22c3
JD		 2036 /* Disable specific features based on DMI strings */
2037 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
2038 board_name = dmi_get_system_info(DMI_BOARD_NAME);
2039 if (board_vendor && board_name) {
2040 if (strcmp(board_vendor, "nVIDIA") == 0
2041 && strcmp(board_name, "FN68PT") == 0) {
4a0d71cf
GR		 2042 /*
2043 * On the Shuttle SN68PT, FAN_CTL2 is apparently not
2044 * connected to a fan, but to something else. One user
2045 * has reported instant system power-off when changing
2046 * the PWM2 duty cycle, so we disable it.
2047 * I use the board name string as the trigger in case
2048 * the same board is ever used in other systems.
2049 */
a8ca1037 2050 pr_info("Disabling pwm2 due to hardware constraints\n");
98dd22c3
JD		 2051 sio_data->skip_pwm = (1 << 1);
2052 }
2053 }
2054
1da177e4
LT		 2055exit:
2056 superio_exit();
2057 return err;
2058}
2059
723a0aa0
JD		 2060static void it87_remove_files(struct device *dev)
2061{
2062 struct it87_data *data = platform_get_drvdata(pdev);
a8b3a3a5 2063 struct it87_sio_data *sio_data = dev_get_platdata(dev);
723a0aa0
JD		 2064 int i;
2065
2066 sysfs_remove_group(&dev->kobj, &it87_group);
c145d5c6 2067 for (i = 0; i < 10; i++) {
9172b5d1
GR		 2068 if (sio_data->skip_in & (1 << i))
2069 continue;
2070 sysfs_remove_group(&dev->kobj, &it87_group_in[i]);
2071 if (it87_attributes_in_beep[i])
2072 sysfs_remove_file(&dev->kobj,
2073 it87_attributes_in_beep[i]);
2074 }
4573acbc
GR		 2075 for (i = 0; i < 3; i++) {
2076 if (!(data->has_temp & (1 << i)))
2077 continue;
2078 sysfs_remove_group(&dev->kobj, &it87_group_temp[i]);
161d898a
GR		 2079 if (has_temp_offset(data))
2080 sysfs_remove_file(&dev->kobj,
2081 it87_attributes_temp_offset[i]);
4573acbc
GR		 2082 if (sio_data->beep_pin)
2083 sysfs_remove_file(&dev->kobj,
2084 it87_attributes_temp_beep[i]);
2085 }
723a0aa0
JD		 2086 for (i = 0; i < 5; i++) {
2087 if (!(data->has_fan & (1 << i)))
2088 continue;
e1169ba0 2089 sysfs_remove_group(&dev->kobj, &it87_group_fan[i]);
d9b327c3
JD		 2090 if (sio_data->beep_pin)
2091 sysfs_remove_file(&dev->kobj,
2092 it87_attributes_fan_beep[i]);
e1169ba0
GR		 2093 if (i < 3 && !has_16bit_fans(data))
2094 sysfs_remove_file(&dev->kobj,
2095 it87_attributes_fan_div[i]);
723a0aa0
JD		 2096 }
2097 for (i = 0; i < 3; i++) {
1696d1de 2098 if (sio_data->skip_pwm & (1 << i))
723a0aa0
JD		 2099 continue;
2100 sysfs_remove_group(&dev->kobj, &it87_group_pwm[i]);
4f3f51bc
JD		 2101 if (has_old_autopwm(data))
2102 sysfs_remove_group(&dev->kobj,
2103 &it87_group_autopwm[i]);
723a0aa0 2104 }
6a8d7acf
JD		 2105 if (!sio_data->skip_vid)
2106 sysfs_remove_group(&dev->kobj, &it87_group_vid);
738e5e05 2107 sysfs_remove_group(&dev->kobj, &it87_group_label);
723a0aa0
JD		 2108}
2109
6c931ae1 2110static int it87_probe(struct platform_device *pdev)
1da177e4 2111{
1da177e4 2112 struct it87_data *data;
b74f3fdd 2113 struct resource *res;
2114 struct device *dev = &pdev->dev;
a8b3a3a5 2115 struct it87_sio_data *sio_data = dev_get_platdata(dev);
723a0aa0 2116 int err = 0, i;
1da177e4 2117 int enable_pwm_interface;
d9b327c3 2118 int fan_beep_need_rw;
b74f3fdd 2119
2120 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
62a1d05f
GR		 2121 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
2122 DRVNAME)) {
b74f3fdd 2123 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
2124 (unsigned long)res->start,
87b4b663 2125 (unsigned long)(res->start + IT87_EC_EXTENT - 1));
62a1d05f 2126 return -EBUSY;
8e9afcbb 2127 }
1da177e4 2128
62a1d05f
GR		 2129 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
2130 if (!data)
2131 return -ENOMEM;
1da177e4 2132
b74f3fdd 2133 data->addr = res->start;
2134 data->type = sio_data->type;
483db43e 2135 data->features = it87_devices[sio_data->type].features;
5d8d2f2b 2136 data->peci_mask = it87_devices[sio_data->type].peci_mask;
19529784 2137 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
483db43e
GR		 2138 data->name = it87_devices[sio_data->type].name;
2139 /*
2140 * IT8705F Datasheet 0.4.1, 3h == Version G.
2141 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
2142 * These are the first revisions with 16-bit tachometer support.
2143 */
2144 switch (data->type) {
2145 case it87:
2146 if (sio_data->revision >= 0x03) {
2147 data->features &= ~FEAT_OLD_AUTOPWM;
9faf28ca 2148 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
483db43e
GR		 2149 }
2150 break;
2151 case it8712:
2152 if (sio_data->revision >= 0x08) {
2153 data->features &= ~FEAT_OLD_AUTOPWM;
9faf28ca
GR		 2154 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
2155 FEAT_FIVE_FANS;
483db43e
GR		 2156 }
2157 break;
2158 default:
2159 break;
2160 }
1da177e4
LT		 2161
2162 /* Now, we do the remaining detection. */
b74f3fdd 2163 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80)
62a1d05f
GR		 2164 || it87_read_value(data, IT87_REG_CHIPID) != 0x90)
2165 return -ENODEV;
1da177e4 2166
b74f3fdd 2167 platform_set_drvdata(pdev, data);
1da177e4 2168
9a61bf63 2169 mutex_init(&data->update_lock);
1da177e4 2170
1da177e4 2171 /* Check PWM configuration */
b74f3fdd 2172 enable_pwm_interface = it87_check_pwm(dev);
1da177e4 2173
44c1bcd4 2174 /* Starting with IT8721F, we handle scaling of internal voltages */
16b5dda2 2175 if (has_12mv_adc(data)) {
44c1bcd4
JD		 2176 if (sio_data->internal & (1 << 0))
2177 data->in_scaled |= (1 << 3); /* in3 is AVCC */
2178 if (sio_data->internal & (1 << 1))
2179 data->in_scaled |= (1 << 7); /* in7 is VSB */
2180 if (sio_data->internal & (1 << 2))
2181 data->in_scaled |= (1 << 8); /* in8 is Vbat */
c145d5c6
RM		 2182 if (sio_data->internal & (1 << 3))
2183 data->in_scaled |= (1 << 9); /* in9 is AVCC */
7bc32d29
GR		 2184 } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
2185 sio_data->type == it8783) {
0531d98b
GR		 2186 if (sio_data->internal & (1 << 0))
2187 data->in_scaled |= (1 << 3); /* in3 is VCC5V */
2188 if (sio_data->internal & (1 << 1))
2189 data->in_scaled |= (1 << 7); /* in7 is VCCH5V */
44c1bcd4
JD		 2190 }
2191
4573acbc
GR		 2192 data->has_temp = 0x07;
2193 if (sio_data->skip_temp & (1 << 2)) {
2194 if (sio_data->type == it8782
2195 && !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
2196 data->has_temp &= ~(1 << 2);
2197 }
2198
1da177e4 2199 /* Initialize the IT87 chip */
b74f3fdd 2200 it87_init_device(pdev);
1da177e4
LT		 2201
2202 /* Register sysfs hooks */
5f2dc798
JD		 2203 err = sysfs_create_group(&dev->kobj, &it87_group);
2204 if (err)
62a1d05f 2205 return err;
17d648bf 2206
c145d5c6 2207 for (i = 0; i < 10; i++) {
9172b5d1
GR		 2208 if (sio_data->skip_in & (1 << i))
2209 continue;
2210 err = sysfs_create_group(&dev->kobj, &it87_group_in[i]);
2211 if (err)
62a1d05f 2212 goto error;
9172b5d1
GR		 2213 if (sio_data->beep_pin && it87_attributes_in_beep[i]) {
2214 err = sysfs_create_file(&dev->kobj,
2215 it87_attributes_in_beep[i]);
2216 if (err)
62a1d05f 2217 goto error;
9172b5d1
GR		 2218 }
2219 }
2220
4573acbc
GR		 2221 for (i = 0; i < 3; i++) {
2222 if (!(data->has_temp & (1 << i)))
2223 continue;
2224 err = sysfs_create_group(&dev->kobj, &it87_group_temp[i]);
d9b327c3 2225 if (err)
62a1d05f 2226 goto error;
161d898a
GR		 2227 if (has_temp_offset(data)) {
2228 err = sysfs_create_file(&dev->kobj,
2229 it87_attributes_temp_offset[i]);
2230 if (err)
2231 goto error;
2232 }
4573acbc
GR		 2233 if (sio_data->beep_pin) {
2234 err = sysfs_create_file(&dev->kobj,
2235 it87_attributes_temp_beep[i]);
2236 if (err)
2237 goto error;
2238 }
d9b327c3
JD		 2239 }
2240
9060f8bd 2241 /* Do not create fan files for disabled fans */
d9b327c3 2242 fan_beep_need_rw = 1;
723a0aa0
JD		 2243 for (i = 0; i < 5; i++) {
2244 if (!(data->has_fan & (1 << i)))
2245 continue;
e1169ba0 2246 err = sysfs_create_group(&dev->kobj, &it87_group_fan[i]);
723a0aa0 2247 if (err)
62a1d05f 2248 goto error;
d9b327c3 2249
e1169ba0
GR		 2250 if (i < 3 && !has_16bit_fans(data)) {
2251 err = sysfs_create_file(&dev->kobj,
2252 it87_attributes_fan_div[i]);
2253 if (err)
2254 goto error;
2255 }
2256
d9b327c3
JD		 2257 if (sio_data->beep_pin) {
2258 err = sysfs_create_file(&dev->kobj,
2259 it87_attributes_fan_beep[i]);
2260 if (err)
62a1d05f 2261 goto error;
d9b327c3
JD		 2262 if (!fan_beep_need_rw)
2263 continue;
2264
4a0d71cf
GR		 2265 /*
2266 * As we have a single beep enable bit for all fans,
d9b327c3 2267 * only the first enabled fan has a writable attribute
4a0d71cf
GR		 2268 * for it.
2269 */
d9b327c3
JD		 2270 if (sysfs_chmod_file(&dev->kobj,
2271 it87_attributes_fan_beep[i],
2272 S_IRUGO | S_IWUSR))
2273 dev_dbg(dev, "chmod +w fan%d_beep failed\n",
2274 i + 1);
2275 fan_beep_need_rw = 0;
2276 }
17d648bf
JD		 2277 }
2278
1da177e4 2279 if (enable_pwm_interface) {
723a0aa0
JD		 2280 for (i = 0; i < 3; i++) {
2281 if (sio_data->skip_pwm & (1 << i))
2282 continue;
2283 err = sysfs_create_group(&dev->kobj,
2284 &it87_group_pwm[i]);
2285 if (err)
62a1d05f 2286 goto error;
4f3f51bc
JD		 2287
2288 if (!has_old_autopwm(data))
2289 continue;
2290 err = sysfs_create_group(&dev->kobj,
2291 &it87_group_autopwm[i]);
2292 if (err)
62a1d05f 2293 goto error;
98dd22c3 2294 }
1da177e4
LT		 2295 }
2296
895ff267 2297 if (!sio_data->skip_vid) {
303760b4 2298 data->vrm = vid_which_vrm();
87673dd7 2299 /* VID reading from Super-I/O config space if available */
b74f3fdd 2300 data->vid = sio_data->vid_value;
6a8d7acf
JD		 2301 err = sysfs_create_group(&dev->kobj, &it87_group_vid);
2302 if (err)
62a1d05f 2303 goto error;
87808be4
JD		 2304 }
2305
738e5e05 2306 /* Export labels for internal sensors */
c145d5c6 2307 for (i = 0; i < 4; i++) {
738e5e05
JD		 2308 if (!(sio_data->internal & (1 << i)))
2309 continue;
2310 err = sysfs_create_file(&dev->kobj,
2311 it87_attributes_label[i]);
2312 if (err)
62a1d05f 2313 goto error;
738e5e05
JD		 2314 }
2315
1beeffe4
TJ		 2316 data->hwmon_dev = hwmon_device_register(dev);
2317 if (IS_ERR(data->hwmon_dev)) {
2318 err = PTR_ERR(data->hwmon_dev);
62a1d05f 2319 goto error;
1da177e4
LT		 2320 }
2321
2322 return 0;
2323
62a1d05f 2324error:
723a0aa0 2325 it87_remove_files(dev);
1da177e4
LT		 2326 return err;
2327}
2328
281dfd0b 2329static int it87_remove(struct platform_device *pdev)
1da177e4 2330{
b74f3fdd 2331 struct it87_data *data = platform_get_drvdata(pdev);
1da177e4 2332
1beeffe4 2333 hwmon_device_unregister(data->hwmon_dev);
723a0aa0 2334 it87_remove_files(&pdev->dev);
943b0830 2335
1da177e4
LT		 2336 return 0;
2337}
2338
4a0d71cf
GR		 2339/*
2340 * Must be called with data->update_lock held, except during initialization.
2341 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
2342 * would slow down the IT87 access and should not be necessary.
2343 */
b74f3fdd 2344static int it87_read_value(struct it87_data *data, u8 reg)
1da177e4 2345{
b74f3fdd 2346 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
2347 return inb_p(data->addr + IT87_DATA_REG_OFFSET);
1da177e4
LT		 2348}
2349
4a0d71cf
GR		 2350/*
2351 * Must be called with data->update_lock held, except during initialization.
2352 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
2353 * would slow down the IT87 access and should not be necessary.
2354 */
b74f3fdd 2355static void it87_write_value(struct it87_data *data, u8 reg, u8 value)
1da177e4 2356{
b74f3fdd 2357 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
2358 outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
1da177e4
LT		 2359}
2360
2361/* Return 1 if and only if the PWM interface is safe to use */
6c931ae1 2362static int it87_check_pwm(struct device *dev)
1da177e4 2363{
b74f3fdd 2364 struct it87_data *data = dev_get_drvdata(dev);
4a0d71cf
GR		 2365 /*
2366 * Some BIOSes fail to correctly configure the IT87 fans. All fans off
1da177e4 2367 * and polarity set to active low is sign that this is the case so we
4a0d71cf
GR		 2368 * disable pwm control to protect the user.
2369 */
b74f3fdd 2370 int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1da177e4
LT		 2371 if ((tmp & 0x87) == 0) {
2372 if (fix_pwm_polarity) {
4a0d71cf
GR		 2373 /*
2374 * The user asks us to attempt a chip reconfiguration.
1da177e4 2375 * This means switching to active high polarity and
4a0d71cf
GR		 2376 * inverting all fan speed values.
2377 */
1da177e4
LT		 2378 int i;
2379 u8 pwm[3];
2380
2381 for (i = 0; i < 3; i++)
b74f3fdd 2382 pwm[i] = it87_read_value(data,
1da177e4
LT		 2383 IT87_REG_PWM(i));
2384
4a0d71cf
GR		 2385 /*
2386 * If any fan is in automatic pwm mode, the polarity
1da177e4
LT		 2387 * might be correct, as suspicious as it seems, so we
2388 * better don't change anything (but still disable the
4a0d71cf
GR		 2389 * PWM interface).
2390 */
1da177e4 2391 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
1d9bcf6a
GR		 2392 dev_info(dev,
2393 "Reconfiguring PWM to active high polarity\n");
b74f3fdd 2394 it87_write_value(data, IT87_REG_FAN_CTL,
1da177e4
LT		 2395 tmp | 0x87);
2396 for (i = 0; i < 3; i++)
b74f3fdd 2397 it87_write_value(data,
1da177e4
LT		 2398 IT87_REG_PWM(i),
2399 0x7f & ~pwm[i]);
2400 return 1;
2401 }
2402
1d9bcf6a
GR		 2403 dev_info(dev,
2404 "PWM configuration is too broken to be fixed\n");
1da177e4
LT		 2405 }
2406
1d9bcf6a
GR		 2407 dev_info(dev,
2408 "Detected broken BIOS defaults, disabling PWM interface\n");
1da177e4
LT		 2409 return 0;
2410 } else if (fix_pwm_polarity) {
1d9bcf6a
GR		 2411 dev_info(dev,
2412 "PWM configuration looks sane, won't touch\n");
1da177e4
LT		 2413 }
2414
2415 return 1;
2416}
2417
2418/* Called when we have found a new IT87. */
6c931ae1 2419static void it87_init_device(struct platform_device *pdev)
1da177e4 2420{
a8b3a3a5 2421 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
b74f3fdd 2422 struct it87_data *data = platform_get_drvdata(pdev);
1da177e4 2423 int tmp, i;
591ec650 2424 u8 mask;
1da177e4 2425
4a0d71cf
GR		 2426 /*
2427 * For each PWM channel:
b99883dc
JD		 2428 * - If it is in automatic mode, setting to manual mode should set
2429 * the fan to full speed by default.
2430 * - If it is in manual mode, we need a mapping to temperature
2431 * channels to use when later setting to automatic mode later.
2432 * Use a 1:1 mapping by default (we are clueless.)
2433 * In both cases, the value can (and should) be changed by the user
6229cdb2
JD		 2434 * prior to switching to a different mode.
2435 * Note that this is no longer needed for the IT8721F and later, as
2436 * these have separate registers for the temperature mapping and the
4a0d71cf
GR		 2437 * manual duty cycle.
2438 */
1da177e4 2439 for (i = 0; i < 3; i++) {
b99883dc
JD		 2440 data->pwm_temp_map[i] = i;
2441 data->pwm_duty[i] = 0x7f; /* Full speed */
4f3f51bc 2442 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
1da177e4
LT		 2443 }
2444
4a0d71cf
GR		 2445 /*
2446 * Some chips seem to have default value 0xff for all limit
c5df9b7a
JD		 2447 * registers. For low voltage limits it makes no sense and triggers
2448 * alarms, so change to 0 instead. For high temperature limits, it
2449 * means -1 degree C, which surprisingly doesn't trigger an alarm,
4a0d71cf
GR		 2450 * but is still confusing, so change to 127 degrees C.
2451 */
c5df9b7a 2452 for (i = 0; i < 8; i++) {
b74f3fdd 2453 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
c5df9b7a 2454 if (tmp == 0xff)
b74f3fdd 2455 it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
c5df9b7a
JD		 2456 }
2457 for (i = 0; i < 3; i++) {
b74f3fdd 2458 tmp = it87_read_value(data, IT87_REG_TEMP_HIGH(i));
c5df9b7a 2459 if (tmp == 0xff)
b74f3fdd 2460 it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127);
c5df9b7a
JD		 2461 }
2462
4a0d71cf
GR		 2463 /*
2464 * Temperature channels are not forcibly enabled, as they can be
a00afb97
JD		 2465 * set to two different sensor types and we can't guess which one
2466 * is correct for a given system. These channels can be enabled at
4a0d71cf
GR		 2467 * run-time through the temp{1-3}_type sysfs accessors if needed.
2468 */
1da177e4
LT		 2469
2470 /* Check if voltage monitors are reset manually or by some reason */
b74f3fdd 2471 tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
1da177e4
LT		 2472 if ((tmp & 0xff) == 0) {
2473 /* Enable all voltage monitors */
b74f3fdd 2474 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
1da177e4
LT		 2475 }
2476
2477 /* Check if tachometers are reset manually or by some reason */
591ec650 2478 mask = 0x70 & ~(sio_data->skip_fan << 4);
b74f3fdd 2479 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
591ec650 2480 if ((data->fan_main_ctrl & mask) == 0) {
1da177e4 2481 /* Enable all fan tachometers */
591ec650 2482 data->fan_main_ctrl |= mask;
5f2dc798
JD		 2483 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
2484 data->fan_main_ctrl);
1da177e4 2485 }
9060f8bd 2486 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
1da177e4 2487
9faf28ca
GR		 2488 /* Set tachometers to 16-bit mode if needed */
2489 if (has_fan16_config(data)) {
b74f3fdd 2490 tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
9060f8bd 2491 if (~tmp & 0x07 & data->has_fan) {
b74f3fdd 2492 dev_dbg(&pdev->dev,
17d648bf 2493 "Setting fan1-3 to 16-bit mode\n");
b74f3fdd 2494 it87_write_value(data, IT87_REG_FAN_16BIT,
17d648bf
JD		 2495 tmp | 0x07);
2496 }
9faf28ca
GR		 2497 }
2498
2499 /* Check for additional fans */
2500 if (has_five_fans(data)) {
2501 tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
2502 if (tmp & (1 << 4))
2503 data->has_fan |= (1 << 3); /* fan4 enabled */
2504 if (tmp & (1 << 5))
2505 data->has_fan |= (1 << 4); /* fan5 enabled */
17d648bf
JD		 2506 }
2507
591ec650
JD		 2508 /* Fan input pins may be used for alternative functions */
2509 data->has_fan &= ~sio_data->skip_fan;
2510
1da177e4 2511 /* Start monitoring */
b74f3fdd 2512 it87_write_value(data, IT87_REG_CONFIG,
41002f8d 2513 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
1da177e4
LT		 2514 | (update_vbat ? 0x41 : 0x01));
2515}
2516
b99883dc
JD		 2517static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
2518{
2519 data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM(nr));
16b5dda2 2520 if (has_newer_autopwm(data)) {
b99883dc 2521 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
6229cdb2
JD		 2522 data->pwm_duty[nr] = it87_read_value(data,
2523 IT87_REG_PWM_DUTY(nr));
2524 } else {
2525 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
2526 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
2527 else /* Manual mode */
2528 data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
2529 }
4f3f51bc
JD		 2530
2531 if (has_old_autopwm(data)) {
2532 int i;
2533
2534 for (i = 0; i < 5 ; i++)
2535 data->auto_temp[nr][i] = it87_read_value(data,
2536 IT87_REG_AUTO_TEMP(nr, i));
2537 for (i = 0; i < 3 ; i++)
2538 data->auto_pwm[nr][i] = it87_read_value(data,
2539 IT87_REG_AUTO_PWM(nr, i));
2540 }
b99883dc
JD		 2541}
2542
1da177e4
LT		 2543static struct it87_data *it87_update_device(struct device *dev)
2544{
b74f3fdd 2545 struct it87_data *data = dev_get_drvdata(dev);
1da177e4
LT		 2546 int i;
2547
9a61bf63 2548 mutex_lock(&data->update_lock);
1da177e4
LT		 2549
2550 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
2551 || !data->valid) {
1da177e4 2552 if (update_vbat) {
4a0d71cf
GR		 2553 /*
2554 * Cleared after each update, so reenable. Value
2555 * returned by this read will be previous value
2556 */
b74f3fdd 2557 it87_write_value(data, IT87_REG_CONFIG,
5f2dc798 2558 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
1da177e4
LT		 2559 }
2560 for (i = 0; i <= 7; i++) {
929c6a56 2561 data->in[i][0] =
5f2dc798 2562 it87_read_value(data, IT87_REG_VIN(i));
929c6a56 2563 data->in[i][1] =
5f2dc798 2564 it87_read_value(data, IT87_REG_VIN_MIN(i));
929c6a56 2565 data->in[i][2] =
5f2dc798 2566 it87_read_value(data, IT87_REG_VIN_MAX(i));
1da177e4 2567 }
3543a53f 2568 /* in8 (battery) has no limit registers */
929c6a56 2569 data->in[8][0] = it87_read_value(data, IT87_REG_VIN(8));
c145d5c6
RM		 2570 if (data->type == it8603)
2571 data->in[9][0] = it87_read_value(data, 0x2f);
1da177e4 2572
c7f1f716 2573 for (i = 0; i < 5; i++) {
9060f8bd
JD		 2574 /* Skip disabled fans */
2575 if (!(data->has_fan & (1 << i)))
2576 continue;
2577
e1169ba0 2578 data->fan[i][1] =
5f2dc798 2579 it87_read_value(data, IT87_REG_FAN_MIN[i]);
e1169ba0 2580 data->fan[i][0] = it87_read_value(data,
c7f1f716 2581 IT87_REG_FAN[i]);
17d648bf 2582 /* Add high byte if in 16-bit mode */
0475169c 2583 if (has_16bit_fans(data)) {
e1169ba0 2584 data->fan[i][0] |= it87_read_value(data,
c7f1f716 2585 IT87_REG_FANX[i]) << 8;
e1169ba0 2586 data->fan[i][1] |= it87_read_value(data,
c7f1f716 2587 IT87_REG_FANX_MIN[i]) << 8;
17d648bf 2588 }
1da177e4
LT		 2589 }
2590 for (i = 0; i < 3; i++) {
4573acbc
GR		 2591 if (!(data->has_temp & (1 << i)))
2592 continue;
60ca385a 2593 data->temp[i][0] =
5f2dc798 2594 it87_read_value(data, IT87_REG_TEMP(i));
60ca385a 2595 data->temp[i][1] =
5f2dc798 2596 it87_read_value(data, IT87_REG_TEMP_LOW(i));
60ca385a
GR		 2597 data->temp[i][2] =
2598 it87_read_value(data, IT87_REG_TEMP_HIGH(i));
161d898a
GR		 2599 if (has_temp_offset(data))
2600 data->temp[i][3] =
2601 it87_read_value(data,
2602 IT87_REG_TEMP_OFFSET[i]);
1da177e4
LT		 2603 }
2604
17d648bf 2605 /* Newer chips don't have clock dividers */
0475169c 2606 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
b74f3fdd 2607 i = it87_read_value(data, IT87_REG_FAN_DIV);
17d648bf
JD		 2608 data->fan_div[0] = i & 0x07;
2609 data->fan_div[1] = (i >> 3) & 0x07;
2610 data->fan_div[2] = (i & 0x40) ? 3 : 1;
2611 }
1da177e4
LT		 2612
2613 data->alarms =
b74f3fdd 2614 it87_read_value(data, IT87_REG_ALARM1) |
2615 (it87_read_value(data, IT87_REG_ALARM2) << 8) |
2616 (it87_read_value(data, IT87_REG_ALARM3) << 16);
d9b327c3 2617 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
b99883dc 2618
b74f3fdd 2619 data->fan_main_ctrl = it87_read_value(data,
2620 IT87_REG_FAN_MAIN_CTRL);
2621 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
b99883dc
JD		 2622 for (i = 0; i < 3; i++)
2623 it87_update_pwm_ctrl(data, i);
b74f3fdd 2624
2625 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
19529784 2626 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
4a0d71cf
GR		 2627 /*
2628 * The IT8705F does not have VID capability.
2629 * The IT8718F and later don't use IT87_REG_VID for the
2630 * same purpose.
2631 */
17d648bf 2632 if (data->type == it8712 || data->type == it8716) {
b74f3fdd 2633 data->vid = it87_read_value(data, IT87_REG_VID);
4a0d71cf
GR		 2634 /*
2635 * The older IT8712F revisions had only 5 VID pins,
2636 * but we assume it is always safe to read 6 bits.
2637 */
17d648bf 2638 data->vid &= 0x3f;
1da177e4
LT		 2639 }
2640 data->last_updated = jiffies;
2641 data->valid = 1;
2642 }
2643
9a61bf63 2644 mutex_unlock(&data->update_lock);
1da177e4
LT		 2645
2646 return data;
2647}
2648
b74f3fdd 2649static int __init it87_device_add(unsigned short address,
2650 const struct it87_sio_data *sio_data)
2651{
2652 struct resource res = {
87b4b663
BH		 2653 .start = address + IT87_EC_OFFSET,
2654 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
b74f3fdd 2655 .name = DRVNAME,
2656 .flags = IORESOURCE_IO,
2657 };
2658 int err;
2659
b9acb64a
JD		 2660 err = acpi_check_resource_conflict(&res);
2661 if (err)
2662 goto exit;
2663
b74f3fdd 2664 pdev = platform_device_alloc(DRVNAME, address);
2665 if (!pdev) {
2666 err = -ENOMEM;
a8ca1037 2667 pr_err("Device allocation failed\n");
b74f3fdd 2668 goto exit;
2669 }
2670
2671 err = platform_device_add_resources(pdev, &res, 1);
2672 if (err) {
a8ca1037 2673 pr_err("Device resource addition failed (%d)\n", err);
b74f3fdd 2674 goto exit_device_put;
2675 }
2676
2677 err = platform_device_add_data(pdev, sio_data,
2678 sizeof(struct it87_sio_data));
2679 if (err) {
a8ca1037 2680 pr_err("Platform data allocation failed\n");
b74f3fdd 2681 goto exit_device_put;
2682 }
2683
2684 err = platform_device_add(pdev);
2685 if (err) {
a8ca1037 2686 pr_err("Device addition failed (%d)\n", err);
b74f3fdd 2687 goto exit_device_put;
2688 }
2689
2690 return 0;
2691
2692exit_device_put:
2693 platform_device_put(pdev);
2694exit:
2695 return err;
2696}
2697
1da177e4
LT		 2698static int __init sm_it87_init(void)
2699{
b74f3fdd 2700 int err;
5f2dc798 2701 unsigned short isa_address = 0;
b74f3fdd 2702 struct it87_sio_data sio_data;
2703
98dd22c3 2704 memset(&sio_data, 0, sizeof(struct it87_sio_data));
b74f3fdd 2705 err = it87_find(&isa_address, &sio_data);
2706 if (err)
2707 return err;
2708 err = platform_driver_register(&it87_driver);
2709 if (err)
2710 return err;
fde09509 2711
b74f3fdd 2712 err = it87_device_add(isa_address, &sio_data);
5f2dc798 2713 if (err) {
b74f3fdd 2714 platform_driver_unregister(&it87_driver);
2715 return err;
2716 }
2717
2718 return 0;
1da177e4
LT		 2719}
2720
2721static void __exit sm_it87_exit(void)
2722{
b74f3fdd 2723 platform_device_unregister(pdev);
2724 platform_driver_unregister(&it87_driver);
1da177e4
LT		 2725}
2726
2727
7c81c60f 2728MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
44c1bcd4 2729MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
1da177e4
LT		 2730module_param(update_vbat, bool, 0);
2731MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
2732module_param(fix_pwm_polarity, bool, 0);
5f2dc798
JD		 2733MODULE_PARM_DESC(fix_pwm_polarity,
2734 "Force PWM polarity to active high (DANGEROUS)");
1da177e4
LT		 2735MODULE_LICENSE("GPL");
2736
2737module_init(sm_it87_init);
2738module_exit(sm_it87_exit);
Linux kernel - Deliverables
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