[deliverable/linux.git] / drivers / hwmon / jc42.c

/*
 * jc42.c - driver for Jedec JC42.4 compliant temperature sensors
 *
 * Copyright (c) 2010  Ericsson AB.
 *
 * Derived from lm77.c by Andras BALI <drewie@freemail.hu>.
 *
 * JC42.4 compliant temperature sensors are typically used on memory modules.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/of.h>

/* Addresses to scan */
static const unsigned short normal_i2c[] = {
	0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };

/* JC42 registers. All registers are 16 bit. */
#define JC42_REG_CAP		0x00
#define JC42_REG_CONFIG		0x01
#define JC42_REG_TEMP_UPPER	0x02
#define JC42_REG_TEMP_LOWER	0x03
#define JC42_REG_TEMP_CRITICAL	0x04
#define JC42_REG_TEMP		0x05
#define JC42_REG_MANID		0x06
#define JC42_REG_DEVICEID	0x07

/* Status bits in temperature register */
#define JC42_ALARM_CRIT_BIT	15
#define JC42_ALARM_MAX_BIT	14
#define JC42_ALARM_MIN_BIT	13

/* Configuration register defines */
#define JC42_CFG_CRIT_ONLY	(1 << 2)
#define JC42_CFG_TCRIT_LOCK	(1 << 6)
#define JC42_CFG_EVENT_LOCK	(1 << 7)
#define JC42_CFG_SHUTDOWN	(1 << 8)
#define JC42_CFG_HYST_SHIFT	9
#define JC42_CFG_HYST_MASK	(0x03 << 9)

/* Capabilities */
#define JC42_CAP_RANGE		(1 << 2)

/* Manufacturer IDs */
#define ADT_MANID		0x11d4  /* Analog Devices */
#define ATMEL_MANID		0x001f  /* Atmel */
#define ATMEL_MANID2		0x1114	/* Atmel */
#define MAX_MANID		0x004d  /* Maxim */
#define IDT_MANID		0x00b3  /* IDT */
#define MCP_MANID		0x0054  /* Microchip */
#define NXP_MANID		0x1131  /* NXP Semiconductors */
#define ONS_MANID		0x1b09  /* ON Semiconductor */
#define STM_MANID		0x104a  /* ST Microelectronics */

/* Supported chips */

/* Analog Devices */
#define ADT7408_DEVID		0x0801
#define ADT7408_DEVID_MASK	0xffff

/* Atmel */
#define AT30TS00_DEVID		0x8201
#define AT30TS00_DEVID_MASK	0xffff

#define AT30TSE004_DEVID	0x2200
#define AT30TSE004_DEVID_MASK	0xffff

/* IDT */
#define TSE2004_DEVID		0x2200
#define TSE2004_DEVID_MASK	0xff00

#define TS3000_DEVID		0x2900  /* Also matches TSE2002 */
#define TS3000_DEVID_MASK	0xff00

#define TS3001_DEVID		0x3000
#define TS3001_DEVID_MASK	0xff00

/* Maxim */
#define MAX6604_DEVID		0x3e00
#define MAX6604_DEVID_MASK	0xffff

/* Microchip */
#define MCP9804_DEVID		0x0200
#define MCP9804_DEVID_MASK	0xfffc

#define MCP9808_DEVID		0x0400
#define MCP9808_DEVID_MASK	0xfffc

#define MCP98242_DEVID		0x2000
#define MCP98242_DEVID_MASK	0xfffc

#define MCP98243_DEVID		0x2100
#define MCP98243_DEVID_MASK	0xfffc

#define MCP98244_DEVID		0x2200
#define MCP98244_DEVID_MASK	0xfffc

#define MCP9843_DEVID		0x0000	/* Also matches mcp9805 */
#define MCP9843_DEVID_MASK	0xfffe

/* NXP */
#define SE97_DEVID		0xa200
#define SE97_DEVID_MASK		0xfffc

#define SE98_DEVID		0xa100
#define SE98_DEVID_MASK		0xfffc

/* ON Semiconductor */
#define CAT6095_DEVID		0x0800	/* Also matches CAT34TS02 */
#define CAT6095_DEVID_MASK	0xffe0

/* ST Microelectronics */
#define STTS424_DEVID		0x0101
#define STTS424_DEVID_MASK	0xffff

#define STTS424E_DEVID		0x0000
#define STTS424E_DEVID_MASK	0xfffe

#define STTS2002_DEVID		0x0300
#define STTS2002_DEVID_MASK	0xffff

#define STTS2004_DEVID		0x2201
#define STTS2004_DEVID_MASK	0xffff

#define STTS3000_DEVID		0x0200
#define STTS3000_DEVID_MASK	0xffff

static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 };

struct jc42_chips {
	u16 manid;
	u16 devid;
	u16 devid_mask;
};

static struct jc42_chips jc42_chips[] = {
	{ ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK },
	{ ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK },
	{ ATMEL_MANID2, AT30TSE004_DEVID, AT30TSE004_DEVID_MASK },
	{ IDT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
	{ IDT_MANID, TS3000_DEVID, TS3000_DEVID_MASK },
	{ IDT_MANID, TS3001_DEVID, TS3001_DEVID_MASK },
	{ MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK },
	{ MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK },
	{ MCP_MANID, MCP9808_DEVID, MCP9808_DEVID_MASK },
	{ MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK },
	{ MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK },
	{ MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK },
	{ MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK },
	{ NXP_MANID, SE97_DEVID, SE97_DEVID_MASK },
	{ ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK },
	{ NXP_MANID, SE98_DEVID, SE98_DEVID_MASK },
	{ STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK },
	{ STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK },
	{ STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK },
	{ STM_MANID, STTS2004_DEVID, STTS2004_DEVID_MASK },
	{ STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK },
};

enum temp_index {
	t_input = 0,
	t_crit,
	t_min,
	t_max,
	t_num_temp
};

static const u8 temp_regs[t_num_temp] = {
	[t_input] = JC42_REG_TEMP,
	[t_crit] = JC42_REG_TEMP_CRITICAL,
	[t_min] = JC42_REG_TEMP_LOWER,
	[t_max] = JC42_REG_TEMP_UPPER,
};

/* Each client has this additional data */
struct jc42_data {
	struct i2c_client *client;
	struct mutex	update_lock;	/* protect register access */
	bool		extended;	/* true if extended range supported */
	bool		valid;
	unsigned long	last_updated;	/* In jiffies */
	u16		orig_config;	/* original configuration */
	u16		config;		/* current configuration */
	u16		temp[t_num_temp];/* Temperatures */
};

#define JC42_TEMP_MIN_EXTENDED	(-40000)
#define JC42_TEMP_MIN		0
#define JC42_TEMP_MAX		125000

static u16 jc42_temp_to_reg(long temp, bool extended)
{
	int ntemp = clamp_val(temp,
			      extended ? JC42_TEMP_MIN_EXTENDED :
			      JC42_TEMP_MIN, JC42_TEMP_MAX);

	/* convert from 0.001 to 0.0625 resolution */
	return (ntemp * 2 / 125) & 0x1fff;
}

static int jc42_temp_from_reg(s16 reg)
{
	reg = sign_extend32(reg, 12);

	/* convert from 0.0625 to 0.001 resolution */
	return reg * 125 / 2;
}

static struct jc42_data *jc42_update_device(struct device *dev)
{
	struct jc42_data *data = dev_get_drvdata(dev);
	struct i2c_client *client = data->client;
	struct jc42_data *ret = data;
	int i, val;

	mutex_lock(&data->update_lock);

	if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
		for (i = 0; i < t_num_temp; i++) {
			val = i2c_smbus_read_word_swapped(client, temp_regs[i]);
			if (val < 0) {
				ret = ERR_PTR(val);
				goto abort;
			}
			data->temp[i] = val;
		}
		data->last_updated = jiffies;
		data->valid = true;
	}
abort:
	mutex_unlock(&data->update_lock);
	return ret;
}

/* sysfs functions */

static ssize_t show_temp(struct device *dev, struct device_attribute *devattr,
			 char *buf)
{
	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
	struct jc42_data *data = jc42_update_device(dev);
	if (IS_ERR(data))
		return PTR_ERR(data);
	return sprintf(buf, "%d\n",
		       jc42_temp_from_reg(data->temp[attr->index]));
}

static ssize_t show_temp_hyst(struct device *dev,
			      struct device_attribute *devattr, char *buf)
{
	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
	struct jc42_data *data = jc42_update_device(dev);
	int temp, hyst;

	if (IS_ERR(data))
		return PTR_ERR(data);

	temp = jc42_temp_from_reg(data->temp[attr->index]);
	hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
			       >> JC42_CFG_HYST_SHIFT];
	return sprintf(buf, "%d\n", temp - hyst);
}

static ssize_t set_temp(struct device *dev, struct device_attribute *devattr,
			const char *buf, size_t count)
{
	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
	struct jc42_data *data = dev_get_drvdata(dev);
	int err, ret = count;
	int nr = attr->index;
	long val;

	if (kstrtol(buf, 10, &val) < 0)
		return -EINVAL;
	mutex_lock(&data->update_lock);
	data->temp[nr] = jc42_temp_to_reg(val, data->extended);
	err = i2c_smbus_write_word_swapped(data->client, temp_regs[nr],
					   data->temp[nr]);
	if (err < 0)
		ret = err;
	mutex_unlock(&data->update_lock);
	return ret;
}

/*
 * JC42.4 compliant chips only support four hysteresis values.
 * Pick best choice and go from there.
 */
static ssize_t set_temp_crit_hyst(struct device *dev,
				  struct device_attribute *attr,
				  const char *buf, size_t count)
{
	struct jc42_data *data = dev_get_drvdata(dev);
	long val;
	int diff, hyst;
	int err;
	int ret = count;

	if (kstrtol(buf, 10, &val) < 0)
		return -EINVAL;

	val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED :
			      JC42_TEMP_MIN) - 6000, JC42_TEMP_MAX);
	diff = jc42_temp_from_reg(data->temp[t_crit]) - val;

	hyst = 0;
	if (diff > 0) {
		if (diff < 2250)
			hyst = 1;	/* 1.5 degrees C */
		else if (diff < 4500)
			hyst = 2;	/* 3.0 degrees C */
		else
			hyst = 3;	/* 6.0 degrees C */
	}

	mutex_lock(&data->update_lock);
	data->config = (data->config & ~JC42_CFG_HYST_MASK)
	  | (hyst << JC42_CFG_HYST_SHIFT);
	err = i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
					   data->config);
	if (err < 0)
		ret = err;
	mutex_unlock(&data->update_lock);
	return ret;
}

static ssize_t show_alarm(struct device *dev,
			  struct device_attribute *attr, char *buf)
{
	u16 bit = to_sensor_dev_attr(attr)->index;
	struct jc42_data *data = jc42_update_device(dev);
	u16 val;

	if (IS_ERR(data))
		return PTR_ERR(data);

	val = data->temp[t_input];
	if (bit != JC42_ALARM_CRIT_BIT && (data->config & JC42_CFG_CRIT_ONLY))
		val = 0;
	return sprintf(buf, "%u\n", (val >> bit) & 1);
}

static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL, t_input);
static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp, set_temp, t_crit);
static SENSOR_DEVICE_ATTR(temp1_min, S_IRUGO, show_temp, set_temp, t_min);
static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, show_temp, set_temp, t_max);

static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_hyst,
			  set_temp_crit_hyst, t_crit);
static SENSOR_DEVICE_ATTR(temp1_max_hyst, S_IRUGO, show_temp_hyst, NULL, t_max);

static SENSOR_DEVICE_ATTR(temp1_crit_alarm, S_IRUGO, show_alarm, NULL,
			  JC42_ALARM_CRIT_BIT);
static SENSOR_DEVICE_ATTR(temp1_min_alarm, S_IRUGO, show_alarm, NULL,
			  JC42_ALARM_MIN_BIT);
static SENSOR_DEVICE_ATTR(temp1_max_alarm, S_IRUGO, show_alarm, NULL,
			  JC42_ALARM_MAX_BIT);

static struct attribute *jc42_attributes[] = {
	&sensor_dev_attr_temp1_input.dev_attr.attr,
	&sensor_dev_attr_temp1_crit.dev_attr.attr,
	&sensor_dev_attr_temp1_min.dev_attr.attr,
	&sensor_dev_attr_temp1_max.dev_attr.attr,
	&sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
	&sensor_dev_attr_temp1_max_hyst.dev_attr.attr,
	&sensor_dev_attr_temp1_crit_alarm.dev_attr.attr,
	&sensor_dev_attr_temp1_min_alarm.dev_attr.attr,
	&sensor_dev_attr_temp1_max_alarm.dev_attr.attr,
	NULL
};

static umode_t jc42_attribute_mode(struct kobject *kobj,
				  struct attribute *attr, int index)
{
	struct device *dev = container_of(kobj, struct device, kobj);
	struct jc42_data *data = dev_get_drvdata(dev);
	unsigned int config = data->config;
	bool readonly;

	if (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr)
		readonly = config & JC42_CFG_TCRIT_LOCK;
	else if (attr == &sensor_dev_attr_temp1_min.dev_attr.attr ||
		 attr == &sensor_dev_attr_temp1_max.dev_attr.attr)
		readonly = config & JC42_CFG_EVENT_LOCK;
	else if (attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr)
		readonly = config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK);
	else
		readonly = true;

	return S_IRUGO | (readonly ? 0 : S_IWUSR);
}

static const struct attribute_group jc42_group = {
	.attrs = jc42_attributes,
	.is_visible = jc42_attribute_mode,
};
__ATTRIBUTE_GROUPS(jc42);

/* Return 0 if detection is successful, -ENODEV otherwise */
static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info)
{
	struct i2c_adapter *adapter = client->adapter;
	int i, config, cap, manid, devid;

	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
				     I2C_FUNC_SMBUS_WORD_DATA))
		return -ENODEV;

	cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
	config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
	manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID);
	devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID);

	if (cap < 0 || config < 0 || manid < 0 || devid < 0)
		return -ENODEV;

	if ((cap & 0xff00) || (config & 0xf800))
		return -ENODEV;

	for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) {
		struct jc42_chips *chip = &jc42_chips[i];
		if (manid == chip->manid &&
		    (devid & chip->devid_mask) == chip->devid) {
			strlcpy(info->type, "jc42", I2C_NAME_SIZE);
			return 0;
		}
	}
	return -ENODEV;
}

static int jc42_probe(struct i2c_client *client, const struct i2c_device_id *id)
{
	struct device *dev = &client->dev;
	struct device *hwmon_dev;
	struct jc42_data *data;
	int config, cap;

	data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->client = client;
	i2c_set_clientdata(client, data);
	mutex_init(&data->update_lock);

	cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
	if (cap < 0)
		return cap;

	data->extended = !!(cap & JC42_CAP_RANGE);

	config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
	if (config < 0)
		return config;

	data->orig_config = config;
	if (config & JC42_CFG_SHUTDOWN) {
		config &= ~JC42_CFG_SHUTDOWN;
		i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
	}
	data->config = config;

	hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
							   data,
							   jc42_groups);
	return PTR_ERR_OR_ZERO(hwmon_dev);
}

static int jc42_remove(struct i2c_client *client)
{
	struct jc42_data *data = i2c_get_clientdata(client);

	/* Restore original configuration except hysteresis */
	if ((data->config & ~JC42_CFG_HYST_MASK) !=
	    (data->orig_config & ~JC42_CFG_HYST_MASK)) {
		int config;

		config = (data->orig_config & ~JC42_CFG_HYST_MASK)
		  | (data->config & JC42_CFG_HYST_MASK);
		i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
	}
	return 0;
}

#ifdef CONFIG_PM

static int jc42_suspend(struct device *dev)
{
	struct jc42_data *data = dev_get_drvdata(dev);

	data->config |= JC42_CFG_SHUTDOWN;
	i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
				     data->config);
	return 0;
}

static int jc42_resume(struct device *dev)
{
	struct jc42_data *data = dev_get_drvdata(dev);

	data->config &= ~JC42_CFG_SHUTDOWN;
	i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
				     data->config);
	return 0;
}

static const struct dev_pm_ops jc42_dev_pm_ops = {
	.suspend = jc42_suspend,
	.resume = jc42_resume,
};

#define JC42_DEV_PM_OPS (&jc42_dev_pm_ops)
#else
#define JC42_DEV_PM_OPS NULL
#endif /* CONFIG_PM */

static const struct i2c_device_id jc42_id[] = {
	{ "jc42", 0 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, jc42_id);

#ifdef CONFIG_OF
static const struct of_device_id jc42_of_ids[] = {
	{ .compatible = "jedec,jc-42.4-temp", },
	{ }
};
MODULE_DEVICE_TABLE(of, jc42_of_ids);
#endif

static struct i2c_driver jc42_driver = {
	.class		= I2C_CLASS_SPD | I2C_CLASS_HWMON,
	.driver = {
		.name	= "jc42",
		.pm = JC42_DEV_PM_OPS,
		.of_match_table = of_match_ptr(jc42_of_ids),
	},
	.probe		= jc42_probe,
	.remove		= jc42_remove,
	.id_table	= jc42_id,
	.detect		= jc42_detect,
	.address_list	= normal_i2c,
};

module_i2c_driver(jc42_driver);

MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
MODULE_DESCRIPTION("JC42 driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
4453d736 GR	1	/*
	2	* jc42.c - driver for Jedec JC42.4 compliant temperature sensors
	3	*
	4	* Copyright (c) 2010 Ericsson AB.
	5	*
	6	* Derived from lm77.c by Andras BALI <drewie@freemail.hu>.
	7	*
	8	* JC42.4 compliant temperature sensors are typically used on memory modules.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	23	*/
	24
	25	#include <linux/module.h>
	26	#include <linux/init.h>
	27	#include <linux/slab.h>
	28	#include <linux/jiffies.h>
	29	#include <linux/i2c.h>
	30	#include <linux/hwmon.h>
	31	#include <linux/hwmon-sysfs.h>
	32	#include <linux/err.h>
	33	#include <linux/mutex.h>
803decce	34	#include <linux/of.h>
4453d736 GR	35
	36	/* Addresses to scan */
	37	static const unsigned short normal_i2c[] = {
	38	0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
	39
	40	/* JC42 registers. All registers are 16 bit. */
	41	#define JC42_REG_CAP 0x00
	42	#define JC42_REG_CONFIG 0x01
	43	#define JC42_REG_TEMP_UPPER 0x02
	44	#define JC42_REG_TEMP_LOWER 0x03
	45	#define JC42_REG_TEMP_CRITICAL 0x04
	46	#define JC42_REG_TEMP 0x05
	47	#define JC42_REG_MANID 0x06
	48	#define JC42_REG_DEVICEID 0x07
	49
	50	/* Status bits in temperature register */
	51	#define JC42_ALARM_CRIT_BIT 15
	52	#define JC42_ALARM_MAX_BIT 14
	53	#define JC42_ALARM_MIN_BIT 13
	54
	55	/* Configuration register defines */
	56	#define JC42_CFG_CRIT_ONLY (1 << 2)
2c6315da CL	57	#define JC42_CFG_TCRIT_LOCK (1 << 6)
2c6315da CL	58	#define JC42_CFG_EVENT_LOCK (1 << 7)
4453d736 GR	59	#define JC42_CFG_SHUTDOWN (1 << 8)
4453d736 GR	60	#define JC42_CFG_HYST_SHIFT 9
2ccc8731	61	#define JC42_CFG_HYST_MASK (0x03 << 9)
4453d736 GR	62
	63	/* Capabilities */
	64	#define JC42_CAP_RANGE (1 << 2)
	65
	66	/* Manufacturer IDs */
	67	#define ADT_MANID 0x11d4 /* Analog Devices */
1bd612a2	68	#define ATMEL_MANID 0x001f /* Atmel */
175c490c	69	#define ATMEL_MANID2 0x1114 /* Atmel */
4453d736 GR	70	#define MAX_MANID 0x004d /* Maxim */
	71	#define IDT_MANID 0x00b3 /* IDT */
	72	#define MCP_MANID 0x0054 /* Microchip */
	73	#define NXP_MANID 0x1131 /* NXP Semiconductors */
	74	#define ONS_MANID 0x1b09 /* ON Semiconductor */
	75	#define STM_MANID 0x104a /* ST Microelectronics */
	76
	77	/* Supported chips */
	78
	79	/* Analog Devices */
	80	#define ADT7408_DEVID 0x0801
	81	#define ADT7408_DEVID_MASK 0xffff
	82
1bd612a2 GR	83	/* Atmel */
	84	#define AT30TS00_DEVID 0x8201
	85	#define AT30TS00_DEVID_MASK 0xffff
	86
175c490c GR	87	#define AT30TSE004_DEVID 0x2200
	88	#define AT30TSE004_DEVID_MASK 0xffff
	89
4453d736	90	/* IDT */
0ea2f1db GR	91	#define TSE2004_DEVID 0x2200
0ea2f1db GR	92	#define TSE2004_DEVID_MASK 0xff00
4453d736	93
0ea2f1db GR	94	#define TS3000_DEVID 0x2900 /* Also matches TSE2002 */
	95	#define TS3000_DEVID_MASK 0xff00
	96
	97	#define TS3001_DEVID 0x3000
	98	#define TS3001_DEVID_MASK 0xff00
1bd612a2	99
4453d736 GR	100	/* Maxim */
	101	#define MAX6604_DEVID 0x3e00
	102	#define MAX6604_DEVID_MASK 0xffff
	103
	104	/* Microchip */
1bd612a2 GR	105	#define MCP9804_DEVID 0x0200
	106	#define MCP9804_DEVID_MASK 0xfffc
	107
a31887dc AS	108	#define MCP9808_DEVID 0x0400
	109	#define MCP9808_DEVID_MASK 0xfffc
	110
4453d736 GR	111	#define MCP98242_DEVID 0x2000
	112	#define MCP98242_DEVID_MASK 0xfffc
	113
	114	#define MCP98243_DEVID 0x2100
	115	#define MCP98243_DEVID_MASK 0xfffc
	116
d4768280 GR	117	#define MCP98244_DEVID 0x2200
	118	#define MCP98244_DEVID_MASK 0xfffc
	119
4453d736 GR	120	#define MCP9843_DEVID 0x0000 /* Also matches mcp9805 */
	121	#define MCP9843_DEVID_MASK 0xfffe
	122
	123	/* NXP */
	124	#define SE97_DEVID 0xa200
	125	#define SE97_DEVID_MASK 0xfffc
	126
	127	#define SE98_DEVID 0xa100
	128	#define SE98_DEVID_MASK 0xfffc
	129
	130	/* ON Semiconductor */
	131	#define CAT6095_DEVID 0x0800 /* Also matches CAT34TS02 */
	132	#define CAT6095_DEVID_MASK 0xffe0
	133
	134	/* ST Microelectronics */
	135	#define STTS424_DEVID 0x0101
	136	#define STTS424_DEVID_MASK 0xffff
	137
	138	#define STTS424E_DEVID 0x0000
	139	#define STTS424E_DEVID_MASK 0xfffe
	140
4de86126 JD	141	#define STTS2002_DEVID 0x0300
	142	#define STTS2002_DEVID_MASK 0xffff
	143
175c490c GR	144	#define STTS2004_DEVID 0x2201
	145	#define STTS2004_DEVID_MASK 0xffff
	146
4de86126 JD	147	#define STTS3000_DEVID 0x0200
	148	#define STTS3000_DEVID_MASK 0xffff
	149
4453d736 GR	150	static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 };
	151
	152	struct jc42_chips {
	153	u16 manid;
	154	u16 devid;
	155	u16 devid_mask;
	156	};
	157
	158	static struct jc42_chips jc42_chips[] = {
	159	{ ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK },
1bd612a2	160	{ ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK },
175c490c	161	{ ATMEL_MANID2, AT30TSE004_DEVID, AT30TSE004_DEVID_MASK },
0ea2f1db GR	162	{ IDT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
	163	{ IDT_MANID, TS3000_DEVID, TS3000_DEVID_MASK },
	164	{ IDT_MANID, TS3001_DEVID, TS3001_DEVID_MASK },
4453d736	165	{ MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK },
1bd612a2	166	{ MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK },
a31887dc	167	{ MCP_MANID, MCP9808_DEVID, MCP9808_DEVID_MASK },
4453d736 GR	168	{ MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK },
4453d736 GR	169	{ MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK },
d4768280	170	{ MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK },
4453d736 GR	171	{ MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK },
	172	{ NXP_MANID, SE97_DEVID, SE97_DEVID_MASK },
	173	{ ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK },
	174	{ NXP_MANID, SE98_DEVID, SE98_DEVID_MASK },
	175	{ STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK },
	176	{ STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK },
4de86126	177	{ STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK },
175c490c	178	{ STM_MANID, STTS2004_DEVID, STTS2004_DEVID_MASK },
4de86126	179	{ STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK },
4453d736 GR	180	};
4453d736 GR	181
10192bc6 GR	182	enum temp_index {
	183	t_input = 0,
	184	t_crit,
	185	t_min,
	186	t_max,
	187	t_num_temp
	188	};
	189
	190	static const u8 temp_regs[t_num_temp] = {
	191	[t_input] = JC42_REG_TEMP,
	192	[t_crit] = JC42_REG_TEMP_CRITICAL,
	193	[t_min] = JC42_REG_TEMP_LOWER,
	194	[t_max] = JC42_REG_TEMP_UPPER,
	195	};
	196
4453d736 GR	197	/* Each client has this additional data */
4453d736 GR	198	struct jc42_data {
62f9a57c	199	struct i2c_client *client;
4453d736 GR	200	struct mutex update_lock; /* protect register access */
	201	bool extended; /* true if extended range supported */
	202	bool valid;
	203	unsigned long last_updated; /* In jiffies */
	204	u16 orig_config; /* original configuration */
	205	u16 config; /* current configuration */
10192bc6	206	u16 temp[t_num_temp];/* Temperatures */
4453d736 GR	207	};
4453d736 GR	208
4453d736 GR	209	#define JC42_TEMP_MIN_EXTENDED (-40000)
	210	#define JC42_TEMP_MIN 0
	211	#define JC42_TEMP_MAX 125000
	212
3a05633b	213	static u16 jc42_temp_to_reg(long temp, bool extended)
4453d736	214	{
2a844c14 GR	215	int ntemp = clamp_val(temp,
	216	extended ? JC42_TEMP_MIN_EXTENDED :
	217	JC42_TEMP_MIN, JC42_TEMP_MAX);
4453d736 GR	218
	219	/* convert from 0.001 to 0.0625 resolution */
	220	return (ntemp * 2 / 125) & 0x1fff;
	221	}
	222
	223	static int jc42_temp_from_reg(s16 reg)
	224	{
bca6a1ad	225	reg = sign_extend32(reg, 12);
4453d736 GR	226
	227	/* convert from 0.0625 to 0.001 resolution */
	228	return reg * 125 / 2;
	229	}
	230
d397276b GR	231	static struct jc42_data jc42_update_device(struct device dev)
	232	{
	233	struct jc42_data *data = dev_get_drvdata(dev);
	234	struct i2c_client *client = data->client;
	235	struct jc42_data *ret = data;
10192bc6	236	int i, val;
d397276b GR	237
	238	mutex_lock(&data->update_lock);
	239
	240	if (time_after(jiffies, data->last_updated + HZ) \|\| !data->valid) {
10192bc6 GR	241	for (i = 0; i < t_num_temp; i++) {
	242	val = i2c_smbus_read_word_swapped(client, temp_regs[i]);
	243	if (val < 0) {
	244	ret = ERR_PTR(val);
	245	goto abort;
	246	}
	247	data->temp[i] = val;
d397276b	248	}
d397276b GR	249	data->last_updated = jiffies;
	250	data->valid = true;
	251	}
	252	abort:
	253	mutex_unlock(&data->update_lock);
	254	return ret;
	255	}
	256
10192bc6	257	/* sysfs functions */
4453d736	258
10192bc6 GR	259	static ssize_t show_temp(struct device dev, struct device_attribute devattr,
10192bc6 GR	260	char *buf)
4453d736	261	{
10192bc6	262	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
4453d736	263	struct jc42_data *data = jc42_update_device(dev);
4453d736 GR	264	if (IS_ERR(data))
4453d736 GR	265	return PTR_ERR(data);
10192bc6 GR	266	return sprintf(buf, "%d\n",
10192bc6 GR	267	jc42_temp_from_reg(data->temp[attr->index]));
4453d736 GR	268	}
4453d736 GR	269
10192bc6 GR	270	static ssize_t show_temp_hyst(struct device *dev,
10192bc6 GR	271	struct device_attribute devattr, char buf)
4453d736	272	{
10192bc6	273	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
4453d736 GR	274	struct jc42_data *data = jc42_update_device(dev);
	275	int temp, hyst;
	276
	277	if (IS_ERR(data))
	278	return PTR_ERR(data);
	279
10192bc6	280	temp = jc42_temp_from_reg(data->temp[attr->index]);
2ccc8731 JD	281	hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
2ccc8731 JD	282	>> JC42_CFG_HYST_SHIFT];
4453d736 GR	283	return sprintf(buf, "%d\n", temp - hyst);
	284	}
	285
10192bc6 GR	286	static ssize_t set_temp(struct device dev, struct device_attribute devattr,
	287	const char *buf, size_t count)
	288	{
	289	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
	290	struct jc42_data *data = dev_get_drvdata(dev);
	291	int err, ret = count;
	292	int nr = attr->index;
	293	long val;
4453d736	294
10192bc6 GR	295	if (kstrtol(buf, 10, &val) < 0)
	296	return -EINVAL;
	297	mutex_lock(&data->update_lock);
	298	data->temp[nr] = jc42_temp_to_reg(val, data->extended);
	299	err = i2c_smbus_write_word_swapped(data->client, temp_regs[nr],
	300	data->temp[nr]);
	301	if (err < 0)
	302	ret = err;
	303	mutex_unlock(&data->update_lock);
	304	return ret;
	305	}
4453d736	306
5d577dba GR	307	/*
	308	* JC42.4 compliant chips only support four hysteresis values.
	309	* Pick best choice and go from there.
	310	*/
4453d736 GR	311	static ssize_t set_temp_crit_hyst(struct device *dev,
	312	struct device_attribute *attr,
	313	const char *buf, size_t count)
	314	{
62f9a57c	315	struct jc42_data *data = dev_get_drvdata(dev);
9130880a	316	long val;
4453d736 GR	317	int diff, hyst;
	318	int err;
	319	int ret = count;
	320
9130880a	321	if (kstrtol(buf, 10, &val) < 0)
4453d736 GR	322	return -EINVAL;
4453d736 GR	323
9130880a JD	324	val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED :
9130880a JD	325	JC42_TEMP_MIN) - 6000, JC42_TEMP_MAX);
10192bc6	326	diff = jc42_temp_from_reg(data->temp[t_crit]) - val;
e2c26f05	327
4453d736 GR	328	hyst = 0;
	329	if (diff > 0) {
	330	if (diff < 2250)
	331	hyst = 1; /* 1.5 degrees C */
	332	else if (diff < 4500)
	333	hyst = 2; /* 3.0 degrees C */
	334	else
	335	hyst = 3; /* 6.0 degrees C */
	336	}
	337
	338	mutex_lock(&data->update_lock);
2ccc8731	339	data->config = (data->config & ~JC42_CFG_HYST_MASK)
4453d736	340	\| (hyst << JC42_CFG_HYST_SHIFT);
62f9a57c	341	err = i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
90f4102c	342	data->config);
4453d736 GR	343	if (err < 0)
	344	ret = err;
	345	mutex_unlock(&data->update_lock);
	346	return ret;
	347	}
	348
	349	static ssize_t show_alarm(struct device *dev,
	350	struct device_attribute attr, char buf)
	351	{
	352	u16 bit = to_sensor_dev_attr(attr)->index;
	353	struct jc42_data *data = jc42_update_device(dev);
	354	u16 val;
	355
	356	if (IS_ERR(data))
	357	return PTR_ERR(data);
	358
10192bc6	359	val = data->temp[t_input];
4453d736 GR	360	if (bit != JC42_ALARM_CRIT_BIT && (data->config & JC42_CFG_CRIT_ONLY))
	361	val = 0;
	362	return sprintf(buf, "%u\n", (val >> bit) & 1);
	363	}
	364
10192bc6 GR	365	static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL, t_input);
	366	static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp, set_temp, t_crit);
	367	static SENSOR_DEVICE_ATTR(temp1_min, S_IRUGO, show_temp, set_temp, t_min);
	368	static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, show_temp, set_temp, t_max);
4453d736	369
10192bc6 GR	370	static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_hyst,
	371	set_temp_crit_hyst, t_crit);
	372	static SENSOR_DEVICE_ATTR(temp1_max_hyst, S_IRUGO, show_temp_hyst, NULL, t_max);
4453d736 GR	373
	374	static SENSOR_DEVICE_ATTR(temp1_crit_alarm, S_IRUGO, show_alarm, NULL,
	375	JC42_ALARM_CRIT_BIT);
	376	static SENSOR_DEVICE_ATTR(temp1_min_alarm, S_IRUGO, show_alarm, NULL,
	377	JC42_ALARM_MIN_BIT);
	378	static SENSOR_DEVICE_ATTR(temp1_max_alarm, S_IRUGO, show_alarm, NULL,
	379	JC42_ALARM_MAX_BIT);
	380
	381	static struct attribute *jc42_attributes[] = {
10192bc6 GR	382	&sensor_dev_attr_temp1_input.dev_attr.attr,
	383	&sensor_dev_attr_temp1_crit.dev_attr.attr,
	384	&sensor_dev_attr_temp1_min.dev_attr.attr,
	385	&sensor_dev_attr_temp1_max.dev_attr.attr,
	386	&sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
	387	&sensor_dev_attr_temp1_max_hyst.dev_attr.attr,
4453d736 GR	388	&sensor_dev_attr_temp1_crit_alarm.dev_attr.attr,
	389	&sensor_dev_attr_temp1_min_alarm.dev_attr.attr,
	390	&sensor_dev_attr_temp1_max_alarm.dev_attr.attr,
	391	NULL
	392	};
	393
587a1f16	394	static umode_t jc42_attribute_mode(struct kobject *kobj,
2c6315da CL	395	struct attribute *attr, int index)
	396	{
	397	struct device *dev = container_of(kobj, struct device, kobj);
62f9a57c	398	struct jc42_data *data = dev_get_drvdata(dev);
2c6315da CL	399	unsigned int config = data->config;
	400	bool readonly;
	401
10192bc6	402	if (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr)
2c6315da	403	readonly = config & JC42_CFG_TCRIT_LOCK;
10192bc6 GR	404	else if (attr == &sensor_dev_attr_temp1_min.dev_attr.attr \|\|
10192bc6 GR	405	attr == &sensor_dev_attr_temp1_max.dev_attr.attr)
2c6315da	406	readonly = config & JC42_CFG_EVENT_LOCK;
10192bc6	407	else if (attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr)
2c6315da CL	408	readonly = config & (JC42_CFG_EVENT_LOCK \| JC42_CFG_TCRIT_LOCK);
	409	else
	410	readonly = true;
	411
	412	return S_IRUGO \| (readonly ? 0 : S_IWUSR);
	413	}
	414
4453d736 GR	415	static const struct attribute_group jc42_group = {
4453d736 GR	416	.attrs = jc42_attributes,
2c6315da	417	.is_visible = jc42_attribute_mode,
4453d736	418	};
62f9a57c	419	__ATTRIBUTE_GROUPS(jc42);
4453d736 GR	420
4453d736 GR	421	/* Return 0 if detection is successful, -ENODEV otherwise */
f15df57d	422	static int jc42_detect(struct i2c_client client, struct i2c_board_info info)
4453d736	423	{
f15df57d	424	struct i2c_adapter *adapter = client->adapter;
4453d736 GR	425	int i, config, cap, manid, devid;
	426
	427	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA \|
	428	I2C_FUNC_SMBUS_WORD_DATA))
	429	return -ENODEV;
	430
f15df57d GR	431	cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
	432	config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
	433	manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID);
	434	devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID);
4453d736 GR	435
	436	if (cap < 0 \|\| config < 0 \|\| manid < 0 \|\| devid < 0)
	437	return -ENODEV;
	438
	439	if ((cap & 0xff00) \|\| (config & 0xf800))
	440	return -ENODEV;
	441
	442	for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) {
	443	struct jc42_chips *chip = &jc42_chips[i];
	444	if (manid == chip->manid &&
	445	(devid & chip->devid_mask) == chip->devid) {
	446	strlcpy(info->type, "jc42", I2C_NAME_SIZE);
	447	return 0;
	448	}
	449	}
	450	return -ENODEV;
	451	}
	452
f15df57d	453	static int jc42_probe(struct i2c_client client, const struct i2c_device_id id)
4453d736	454	{
f15df57d	455	struct device *dev = &client->dev;
62f9a57c GR	456	struct device *hwmon_dev;
	457	struct jc42_data *data;
	458	int config, cap;
4453d736	459
f15df57d GR	460	data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL);
	461	if (!data)
	462	return -ENOMEM;
4453d736	463
62f9a57c	464	data->client = client;
f15df57d	465	i2c_set_clientdata(client, data);
4453d736 GR	466	mutex_init(&data->update_lock);
4453d736 GR	467
f15df57d GR	468	cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
	469	if (cap < 0)
	470	return cap;
	471
4453d736 GR	472	data->extended = !!(cap & JC42_CAP_RANGE);
4453d736 GR	473
f15df57d GR	474	config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
	475	if (config < 0)
	476	return config;
	477
4453d736 GR	478	data->orig_config = config;
	479	if (config & JC42_CFG_SHUTDOWN) {
	480	config &= ~JC42_CFG_SHUTDOWN;
f15df57d	481	i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
4453d736 GR	482	}
	483	data->config = config;
	484
62f9a57c GR	485	hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
	486	data,
	487	jc42_groups);
650a2c02	488	return PTR_ERR_OR_ZERO(hwmon_dev);
4453d736 GR	489	}
	490
	491	static int jc42_remove(struct i2c_client *client)
	492	{
	493	struct jc42_data *data = i2c_get_clientdata(client);
5953e276 JD	494
	495	/* Restore original configuration except hysteresis */
	496	if ((data->config & ~JC42_CFG_HYST_MASK) !=
	497	(data->orig_config & ~JC42_CFG_HYST_MASK)) {
	498	int config;
	499
	500	config = (data->orig_config & ~JC42_CFG_HYST_MASK)
	501	\| (data->config & JC42_CFG_HYST_MASK);
	502	i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
	503	}
4453d736 GR	504	return 0;
	505	}
	506
d397276b GR	507	#ifdef CONFIG_PM
	508
	509	static int jc42_suspend(struct device *dev)
4453d736	510	{
62f9a57c	511	struct jc42_data *data = dev_get_drvdata(dev);
4453d736	512
d397276b GR	513	data->config \|= JC42_CFG_SHUTDOWN;
	514	i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
	515	data->config);
	516	return 0;
	517	}
4453d736	518
d397276b GR	519	static int jc42_resume(struct device *dev)
	520	{
	521	struct jc42_data *data = dev_get_drvdata(dev);
4453d736	522
d397276b GR	523	data->config &= ~JC42_CFG_SHUTDOWN;
	524	i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
	525	data->config);
	526	return 0;
	527	}
4453d736	528
d397276b GR	529	static const struct dev_pm_ops jc42_dev_pm_ops = {
	530	.suspend = jc42_suspend,
	531	.resume = jc42_resume,
	532	};
4453d736	533
d397276b GR	534	#define JC42_DEV_PM_OPS (&jc42_dev_pm_ops)
	535	#else
	536	#define JC42_DEV_PM_OPS NULL
	537	#endif /* CONFIG_PM */
4453d736	538
d397276b GR	539	static const struct i2c_device_id jc42_id[] = {
	540	{ "jc42", 0 },
	541	{ }
	542	};
	543	MODULE_DEVICE_TABLE(i2c, jc42_id);
	544
803decce GR	545	#ifdef CONFIG_OF
	546	static const struct of_device_id jc42_of_ids[] = {
	547	{ .compatible = "jedec,jc-42.4-temp", },
	548	{ }
	549	};
	550	MODULE_DEVICE_TABLE(of, jc42_of_ids);
	551	#endif
	552
d397276b	553	static struct i2c_driver jc42_driver = {
eacc48ce	554	.class = I2C_CLASS_SPD \| I2C_CLASS_HWMON,
d397276b GR	555	.driver = {
	556	.name = "jc42",
	557	.pm = JC42_DEV_PM_OPS,
803decce	558	.of_match_table = of_match_ptr(jc42_of_ids),
d397276b GR	559	},
	560	.probe = jc42_probe,
	561	.remove = jc42_remove,
	562	.id_table = jc42_id,
	563	.detect = jc42_detect,
	564	.address_list = normal_i2c,
	565	};
4453d736	566
f0967eea	567	module_i2c_driver(jc42_driver);
4453d736	568
bb9a80e5	569	MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
4453d736 GR	570	MODULE_DESCRIPTION("JC42 driver");
4453d736 GR	571	MODULE_LICENSE("GPL");