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455fbdd3 PM |
1 | /* |
2 | * lis3lv02d.h - ST LIS3LV02DL accelerometer driver | |
3 | * | |
4 | * Copyright (C) 2007-2008 Yan Burman | |
5 | * Copyright (C) 2008 Eric Piel | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
dc6ea97b EP |
21 | #include <linux/platform_device.h> |
22 | #include <linux/input-polldev.h> | |
455fbdd3 PM |
23 | |
24 | /* | |
25 | * The actual chip is STMicroelectronics LIS3LV02DL or LIS3LV02DQ that seems to | |
26 | * be connected via SPI. There exists also several similar chips (such as LIS302DL or | |
137bad32 GB |
27 | * LIS3L02DQ) and they have slightly different registers, but we can provide a |
28 | * common interface for all of them. | |
cfce41a6 | 29 | * They can also be connected via I²C. |
455fbdd3 PM |
30 | */ |
31 | ||
8f3128e7 DM |
32 | #include <linux/lis3lv02d.h> |
33 | ||
137bad32 GB |
34 | /* 2-byte registers */ |
35 | #define LIS_DOUBLE_ID 0x3A /* LIS3LV02D[LQ] */ | |
36 | /* 1-byte registers */ | |
37 | #define LIS_SINGLE_ID 0x3B /* LIS[32]02DL and others */ | |
455fbdd3 | 38 | |
8f3128e7 | 39 | enum lis3_reg { |
455fbdd3 PM |
40 | WHO_AM_I = 0x0F, |
41 | OFFSET_X = 0x16, | |
42 | OFFSET_Y = 0x17, | |
43 | OFFSET_Z = 0x18, | |
44 | GAIN_X = 0x19, | |
45 | GAIN_Y = 0x1A, | |
46 | GAIN_Z = 0x1B, | |
47 | CTRL_REG1 = 0x20, | |
48 | CTRL_REG2 = 0x21, | |
49 | CTRL_REG3 = 0x22, | |
50 | HP_FILTER_RESET = 0x23, | |
51 | STATUS_REG = 0x27, | |
52 | OUTX_L = 0x28, | |
53 | OUTX_H = 0x29, | |
137bad32 | 54 | OUTX = 0x29, |
455fbdd3 PM |
55 | OUTY_L = 0x2A, |
56 | OUTY_H = 0x2B, | |
137bad32 | 57 | OUTY = 0x2B, |
455fbdd3 PM |
58 | OUTZ_L = 0x2C, |
59 | OUTZ_H = 0x2D, | |
137bad32 | 60 | OUTZ = 0x2D, |
8f3128e7 DM |
61 | }; |
62 | ||
63 | enum lis302d_reg { | |
8873c334 DM |
64 | FF_WU_CFG_1 = 0x30, |
65 | FF_WU_SRC_1 = 0x31, | |
66 | FF_WU_THS_1 = 0x32, | |
67 | FF_WU_DURATION_1 = 0x33, | |
68 | FF_WU_CFG_2 = 0x34, | |
69 | FF_WU_SRC_2 = 0x35, | |
70 | FF_WU_THS_2 = 0x36, | |
71 | FF_WU_DURATION_2 = 0x37, | |
8f3128e7 DM |
72 | CLICK_CFG = 0x38, |
73 | CLICK_SRC = 0x39, | |
74 | CLICK_THSY_X = 0x3B, | |
75 | CLICK_THSZ = 0x3C, | |
76 | CLICK_TIMELIMIT = 0x3D, | |
77 | CLICK_LATENCY = 0x3E, | |
78 | CLICK_WINDOW = 0x3F, | |
79 | }; | |
80 | ||
81 | enum lis3lv02d_reg { | |
8873c334 DM |
82 | FF_WU_CFG = 0x30, |
83 | FF_WU_SRC = 0x31, | |
84 | FF_WU_ACK = 0x32, | |
85 | FF_WU_THS_L = 0x34, | |
86 | FF_WU_THS_H = 0x35, | |
87 | FF_WU_DURATION = 0x36, | |
455fbdd3 PM |
88 | DD_CFG = 0x38, |
89 | DD_SRC = 0x39, | |
90 | DD_ACK = 0x3A, | |
91 | DD_THSI_L = 0x3C, | |
92 | DD_THSI_H = 0x3D, | |
93 | DD_THSE_L = 0x3E, | |
94 | DD_THSE_H = 0x3F, | |
95 | }; | |
96 | ||
97 | enum lis3lv02d_ctrl1 { | |
98 | CTRL1_Xen = 0x01, | |
99 | CTRL1_Yen = 0x02, | |
100 | CTRL1_Zen = 0x04, | |
101 | CTRL1_ST = 0x08, | |
102 | CTRL1_DF0 = 0x10, | |
103 | CTRL1_DF1 = 0x20, | |
104 | CTRL1_PD0 = 0x40, | |
105 | CTRL1_PD1 = 0x80, | |
106 | }; | |
107 | enum lis3lv02d_ctrl2 { | |
108 | CTRL2_DAS = 0x01, | |
109 | CTRL2_SIM = 0x02, | |
110 | CTRL2_DRDY = 0x04, | |
111 | CTRL2_IEN = 0x08, | |
112 | CTRL2_BOOT = 0x10, | |
113 | CTRL2_BLE = 0x20, | |
114 | CTRL2_BDU = 0x40, /* Block Data Update */ | |
115 | CTRL2_FS = 0x80, /* Full Scale selection */ | |
116 | }; | |
117 | ||
8873c334 DM |
118 | enum lis302d_ctrl2 { |
119 | HP_FF_WU2 = 0x08, | |
120 | HP_FF_WU1 = 0x04, | |
121 | }; | |
455fbdd3 PM |
122 | |
123 | enum lis3lv02d_ctrl3 { | |
124 | CTRL3_CFS0 = 0x01, | |
125 | CTRL3_CFS1 = 0x02, | |
126 | CTRL3_FDS = 0x10, | |
127 | CTRL3_HPFF = 0x20, | |
128 | CTRL3_HPDD = 0x40, | |
129 | CTRL3_ECK = 0x80, | |
130 | }; | |
131 | ||
132 | enum lis3lv02d_status_reg { | |
133 | STATUS_XDA = 0x01, | |
134 | STATUS_YDA = 0x02, | |
135 | STATUS_ZDA = 0x04, | |
136 | STATUS_XYZDA = 0x08, | |
137 | STATUS_XOR = 0x10, | |
138 | STATUS_YOR = 0x20, | |
139 | STATUS_ZOR = 0x40, | |
140 | STATUS_XYZOR = 0x80, | |
141 | }; | |
142 | ||
143 | enum lis3lv02d_ff_wu_cfg { | |
144 | FF_WU_CFG_XLIE = 0x01, | |
145 | FF_WU_CFG_XHIE = 0x02, | |
146 | FF_WU_CFG_YLIE = 0x04, | |
147 | FF_WU_CFG_YHIE = 0x08, | |
148 | FF_WU_CFG_ZLIE = 0x10, | |
149 | FF_WU_CFG_ZHIE = 0x20, | |
150 | FF_WU_CFG_LIR = 0x40, | |
151 | FF_WU_CFG_AOI = 0x80, | |
152 | }; | |
153 | ||
154 | enum lis3lv02d_ff_wu_src { | |
155 | FF_WU_SRC_XL = 0x01, | |
156 | FF_WU_SRC_XH = 0x02, | |
157 | FF_WU_SRC_YL = 0x04, | |
158 | FF_WU_SRC_YH = 0x08, | |
159 | FF_WU_SRC_ZL = 0x10, | |
160 | FF_WU_SRC_ZH = 0x20, | |
161 | FF_WU_SRC_IA = 0x40, | |
162 | }; | |
163 | ||
164 | enum lis3lv02d_dd_cfg { | |
165 | DD_CFG_XLIE = 0x01, | |
166 | DD_CFG_XHIE = 0x02, | |
167 | DD_CFG_YLIE = 0x04, | |
168 | DD_CFG_YHIE = 0x08, | |
169 | DD_CFG_ZLIE = 0x10, | |
170 | DD_CFG_ZHIE = 0x20, | |
171 | DD_CFG_LIR = 0x40, | |
172 | DD_CFG_IEND = 0x80, | |
173 | }; | |
174 | ||
175 | enum lis3lv02d_dd_src { | |
176 | DD_SRC_XL = 0x01, | |
177 | DD_SRC_XH = 0x02, | |
178 | DD_SRC_YL = 0x04, | |
179 | DD_SRC_YH = 0x08, | |
180 | DD_SRC_ZL = 0x10, | |
181 | DD_SRC_ZH = 0x20, | |
182 | DD_SRC_IA = 0x40, | |
183 | }; | |
184 | ||
cfce41a6 EP |
185 | struct axis_conversion { |
186 | s8 x; | |
187 | s8 y; | |
188 | s8 z; | |
189 | }; | |
190 | ||
a38da2ed DM |
191 | struct lis3lv02d { |
192 | void *bus_priv; /* used by the bus layer only */ | |
193 | int (*init) (struct lis3lv02d *lis3); | |
194 | int (*write) (struct lis3lv02d *lis3, int reg, u8 val); | |
195 | int (*read) (struct lis3lv02d *lis3, int reg, u8 *ret); | |
cfce41a6 | 196 | |
137bad32 | 197 | u8 whoami; /* 3Ah: 2-byte registries, 3Bh: 1-byte registries */ |
a38da2ed | 198 | s16 (*read_data) (struct lis3lv02d *lis3, int reg); |
137bad32 GB |
199 | int mdps_max_val; |
200 | ||
dc6ea97b | 201 | struct input_polled_dev *idev; /* input device */ |
cfce41a6 EP |
202 | struct platform_device *pdev; /* platform device */ |
203 | atomic_t count; /* interrupt count after last read */ | |
204 | int xcalib; /* calibrated null value for x */ | |
205 | int ycalib; /* calibrated null value for y */ | |
206 | int zcalib; /* calibrated null value for z */ | |
cfce41a6 | 207 | struct axis_conversion ac; /* hw -> logical axis */ |
ef2cfc79 PM |
208 | |
209 | u32 irq; /* IRQ number */ | |
210 | struct fasync_struct *async_queue; /* queue for the misc device */ | |
211 | wait_queue_head_t misc_wait; /* Wait queue for the misc device */ | |
212 | unsigned long misc_opened; /* bit0: whether the device is open */ | |
8f3128e7 DM |
213 | |
214 | struct lis3lv02d_platform_data *pdata; /* for passing board config */ | |
cfce41a6 EP |
215 | }; |
216 | ||
a38da2ed | 217 | int lis3lv02d_init_device(struct lis3lv02d *lis3); |
cfce41a6 EP |
218 | int lis3lv02d_joystick_enable(void); |
219 | void lis3lv02d_joystick_disable(void); | |
a38da2ed DM |
220 | void lis3lv02d_poweroff(struct lis3lv02d *lis3); |
221 | void lis3lv02d_poweron(struct lis3lv02d *lis3); | |
a002ee89 | 222 | int lis3lv02d_remove_fs(struct lis3lv02d *lis3); |
cfce41a6 | 223 | |
a38da2ed | 224 | extern struct lis3lv02d lis3_dev; |