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x86: make 32bit use irq_cfg_alloc, etc
[deliverable/linux.git] / drivers / hwmon / w83627ehf.c
CommitLineData
08e7e278
JD		 1/*
2 w83627ehf - Driver for the hardware monitoring functionality of
3 the Winbond W83627EHF Super-I/O chip
4 Copyright (C) 2005 Jean Delvare <khali@linux-fr.org>
3379ceee 5 Copyright (C) 2006 Yuan Mu (Winbond),
7188cc66 6 Rudolf Marek <r.marek@assembler.cz>
c18beb5b 7 David Hubbard <david.c.hubbard@gmail.com>
08e7e278
JD		 8
9 Shamelessly ripped from the w83627hf driver
10 Copyright (C) 2003 Mark Studebaker
11
12 Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
13 in testing and debugging this driver.
14
8dd2d2ca
JD		 15 This driver also supports the W83627EHG, which is the lead-free
16 version of the W83627EHF.
17
08e7e278
JD		 18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
22
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
27
28 You should have received a copy of the GNU General Public License
29 along with this program; if not, write to the Free Software
30 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31
32
33 Supports the following chips:
34
657c93b1
DH		 35 Chip #vin #fan #pwm #temp chip IDs man ID
36 w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
37 0x8860 0xa1
38 w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
08e7e278
JD		 39*/
40
41#include <linux/module.h>
42#include <linux/init.h>
43#include <linux/slab.h>
1ea6dd38
DH		 44#include <linux/jiffies.h>
45#include <linux/platform_device.h>
943b0830 46#include <linux/hwmon.h>
412fec82 47#include <linux/hwmon-sysfs.h>
fc18d6c0 48#include <linux/hwmon-vid.h>
943b0830 49#include <linux/err.h>
9a61bf63 50#include <linux/mutex.h>
08e7e278
JD		 51#include <asm/io.h>
52#include "lm75.h"
53
1ea6dd38 54enum kinds { w83627ehf, w83627dhg };
08e7e278 55
1ea6dd38
DH		 56/* used to set data->name = w83627ehf_device_names[data->sio_kind] */
57static const char * w83627ehf_device_names[] = {
58 "w83627ehf",
59 "w83627dhg",
60};
61
67b671bc
JD		 62static unsigned short force_id;
63module_param(force_id, ushort, 0);
64MODULE_PARM_DESC(force_id, "Override the detected device ID");
65
1ea6dd38 66#define DRVNAME "w83627ehf"
08e7e278 67
657c93b1 68/*
1ea6dd38 69 * Super-I/O constants and functions
657c93b1 70 */
08e7e278
JD		 71
72#define W83627EHF_LD_HWM 0x0b
73
74#define SIO_REG_LDSEL 0x07 /* Logical device select */
75#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
fc18d6c0 76#define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
08e7e278
JD		 77#define SIO_REG_ENABLE 0x30 /* Logical device enable */
78#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
fc18d6c0
JD		 79#define SIO_REG_VID_CTRL 0xF0 /* VID control */
80#define SIO_REG_VID_DATA 0xF1 /* VID data */
08e7e278 81
657c93b1
DH		 82#define SIO_W83627EHF_ID 0x8850
83#define SIO_W83627EHG_ID 0x8860
84#define SIO_W83627DHG_ID 0xa020
85#define SIO_ID_MASK 0xFFF0
08e7e278
JD		 86
87static inline void
1ea6dd38 88superio_outb(int ioreg, int reg, int val)
08e7e278 89{
1ea6dd38
DH		 90 outb(reg, ioreg);
91 outb(val, ioreg + 1);
08e7e278
JD		 92}
93
94static inline int
1ea6dd38 95superio_inb(int ioreg, int reg)
08e7e278 96{
1ea6dd38
DH		 97 outb(reg, ioreg);
98 return inb(ioreg + 1);
08e7e278
JD		 99}
100
101static inline void
1ea6dd38 102superio_select(int ioreg, int ld)
08e7e278 103{
1ea6dd38
DH		 104 outb(SIO_REG_LDSEL, ioreg);
105 outb(ld, ioreg + 1);
08e7e278
JD		 106}
107
108static inline void
1ea6dd38 109superio_enter(int ioreg)
08e7e278 110{
1ea6dd38
DH		 111 outb(0x87, ioreg);
112 outb(0x87, ioreg);
08e7e278
JD		 113}
114
115static inline void
1ea6dd38 116superio_exit(int ioreg)
08e7e278 117{
1ea6dd38
DH		 118 outb(0x02, ioreg);
119 outb(0x02, ioreg + 1);
08e7e278
JD		 120}
121
122/*
123 * ISA constants
124 */
125
1a641fce
JD		 126#define IOREGION_ALIGNMENT ~7
127#define IOREGION_OFFSET 5
128#define IOREGION_LENGTH 2
1ea6dd38
DH		 129#define ADDR_REG_OFFSET 0
130#define DATA_REG_OFFSET 1
08e7e278
JD		 131
132#define W83627EHF_REG_BANK 0x4E
133#define W83627EHF_REG_CONFIG 0x40
657c93b1
DH		 134
135/* Not currently used:
136 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
137 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
138 * REG_MAN_ID is at port 0x4f
139 * REG_CHIP_ID is at port 0x58 */
08e7e278
JD		 140
141static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
142static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
143
cf0676fe
RM		 144/* The W83627EHF registers for nr=7,8,9 are in bank 5 */
145#define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
146 (0x554 + (((nr) - 7) * 2)))
147#define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
148 (0x555 + (((nr) - 7) * 2)))
149#define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
150 (0x550 + (nr) - 7))
151
08e7e278
JD		 152#define W83627EHF_REG_TEMP1 0x27
153#define W83627EHF_REG_TEMP1_HYST 0x3a
154#define W83627EHF_REG_TEMP1_OVER 0x39
155static const u16 W83627EHF_REG_TEMP[] = { 0x150, 0x250 };
156static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x153, 0x253 };
157static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x155, 0x255 };
158static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0x152, 0x252 };
159
160/* Fan clock dividers are spread over the following five registers */
161#define W83627EHF_REG_FANDIV1 0x47
162#define W83627EHF_REG_FANDIV2 0x4B
163#define W83627EHF_REG_VBAT 0x5D
164#define W83627EHF_REG_DIODE 0x59
165#define W83627EHF_REG_SMI_OVT 0x4C
166
a4589dbb
JD		 167#define W83627EHF_REG_ALARM1 0x459
168#define W83627EHF_REG_ALARM2 0x45A
169#define W83627EHF_REG_ALARM3 0x45B
170
08c79950
RM		 171/* SmartFan registers */
172/* DC or PWM output fan configuration */
173static const u8 W83627EHF_REG_PWM_ENABLE[] = {
174 0x04, /* SYS FAN0 output mode and PWM mode */
175 0x04, /* CPU FAN0 output mode and PWM mode */
176 0x12, /* AUX FAN mode */
177 0x62, /* CPU fan1 mode */
178};
179
180static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
181static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
182
183/* FAN Duty Cycle, be used to control */
184static const u8 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
185static const u8 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
186static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
187
188
189/* Advanced Fan control, some values are common for all fans */
190static const u8 W83627EHF_REG_FAN_MIN_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
191static const u8 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0C, 0x0D, 0x17, 0x66 };
192
08e7e278
JD		 193/*
194 * Conversions
195 */
196
08c79950
RM		 197/* 1 is PWM mode, output in ms */
198static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
199{
200 return mode ? 100 * reg : 400 * reg;
201}
202
203static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
204{
205 return SENSORS_LIMIT((mode ? (msec + 50) / 100 :
206 (msec + 200) / 400), 1, 255);
207}
208
08e7e278
JD		 209static inline unsigned int
210fan_from_reg(u8 reg, unsigned int div)
211{
212 if (reg == 0 || reg == 255)
213 return 0;
214 return 1350000U / (reg * div);
215}
216
217static inline unsigned int
218div_from_reg(u8 reg)
219{
220 return 1 << reg;
221}
222
223static inline int
224temp1_from_reg(s8 reg)
225{
226 return reg * 1000;
227}
228
229static inline s8
5bfedac0 230temp1_to_reg(long temp, int min, int max)
08e7e278 231{
08c79950
RM		 232 if (temp <= min)
233 return min / 1000;
234 if (temp >= max)
235 return max / 1000;
08e7e278
JD		 236 if (temp < 0)
237 return (temp - 500) / 1000;
238 return (temp + 500) / 1000;
239}
240
cf0676fe
RM		 241/* Some of analog inputs have internal scaling (2x), 8mV is ADC LSB */
242
243static u8 scale_in[10] = { 8, 8, 16, 16, 8, 8, 8, 16, 16, 8 };
244
245static inline long in_from_reg(u8 reg, u8 nr)
246{
247 return reg * scale_in[nr];
248}
249
250static inline u8 in_to_reg(u32 val, u8 nr)
251{
252 return SENSORS_LIMIT(((val + (scale_in[nr] / 2)) / scale_in[nr]), 0, 255);
253}
254
08e7e278
JD		 255/*
256 * Data structures and manipulation thereof
257 */
258
259struct w83627ehf_data {
1ea6dd38
DH		 260 int addr; /* IO base of hw monitor block */
261 const char *name;
262
1beeffe4 263 struct device *hwmon_dev;
9a61bf63 264 struct mutex lock;
08e7e278 265
9a61bf63 266 struct mutex update_lock;
08e7e278
JD		 267 char valid; /* !=0 if following fields are valid */
268 unsigned long last_updated; /* In jiffies */
269
270 /* Register values */
1ea6dd38 271 u8 in_num; /* number of in inputs we have */
cf0676fe
RM		 272 u8 in[10]; /* Register value */
273 u8 in_max[10]; /* Register value */
274 u8 in_min[10]; /* Register value */
08e7e278
JD		 275 u8 fan[5];
276 u8 fan_min[5];
277 u8 fan_div[5];
278 u8 has_fan; /* some fan inputs can be disabled */
da667365 279 u8 temp_type[3];
08e7e278
JD		 280 s8 temp1;
281 s8 temp1_max;
282 s8 temp1_max_hyst;
283 s16 temp[2];
284 s16 temp_max[2];
285 s16 temp_max_hyst[2];
a4589dbb 286 u32 alarms;
08c79950
RM		 287
288 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
289 u8 pwm_enable[4]; /* 1->manual
290 2->thermal cruise (also called SmartFan I) */
291 u8 pwm[4];
292 u8 target_temp[4];
293 u8 tolerance[4];
294
295 u8 fan_min_output[4]; /* minimum fan speed */
296 u8 fan_stop_time[4];
fc18d6c0
JD		 297
298 u8 vid;
299 u8 vrm;
08e7e278
JD		 300};
301
1ea6dd38
DH		 302struct w83627ehf_sio_data {
303 int sioreg;
304 enum kinds kind;
305};
306
08e7e278
JD		 307static inline int is_word_sized(u16 reg)
308{
309 return (((reg & 0xff00) == 0x100
310 || (reg & 0xff00) == 0x200)
311 && ((reg & 0x00ff) == 0x50
312 || (reg & 0x00ff) == 0x53
313 || (reg & 0x00ff) == 0x55));
314}
315
0956895a 316/* Registers 0x50-0x5f are banked */
1ea6dd38 317static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
08e7e278 318{
0956895a 319 if ((reg & 0x00f0) == 0x50) {
1ea6dd38
DH		 320 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
321 outb_p(reg >> 8, data->addr + DATA_REG_OFFSET);
08e7e278
JD		 322 }
323}
324
0956895a 325/* Not strictly necessary, but play it safe for now */
1ea6dd38 326static inline void w83627ehf_reset_bank(struct w83627ehf_data *data, u16 reg)
08e7e278
JD		 327{
328 if (reg & 0xff00) {
1ea6dd38
DH		 329 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
330 outb_p(0, data->addr + DATA_REG_OFFSET);
08e7e278
JD		 331 }
332}
333
1ea6dd38 334static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
08e7e278 335{
08e7e278
JD		 336 int res, word_sized = is_word_sized(reg);
337
9a61bf63 338 mutex_lock(&data->lock);
08e7e278 339
1ea6dd38
DH		 340 w83627ehf_set_bank(data, reg);
341 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
342 res = inb_p(data->addr + DATA_REG_OFFSET);
08e7e278
JD		 343 if (word_sized) {
344 outb_p((reg & 0xff) + 1,
1ea6dd38
DH		 345 data->addr + ADDR_REG_OFFSET);
346 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
08e7e278 347 }
1ea6dd38 348 w83627ehf_reset_bank(data, reg);
08e7e278 349
9a61bf63 350 mutex_unlock(&data->lock);
08e7e278
JD		 351
352 return res;
353}
354
1ea6dd38 355static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg, u16 value)
08e7e278 356{
08e7e278
JD		 357 int word_sized = is_word_sized(reg);
358
9a61bf63 359 mutex_lock(&data->lock);
08e7e278 360
1ea6dd38
DH		 361 w83627ehf_set_bank(data, reg);
362 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
08e7e278 363 if (word_sized) {
1ea6dd38 364 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
08e7e278 365 outb_p((reg & 0xff) + 1,
1ea6dd38 366 data->addr + ADDR_REG_OFFSET);
08e7e278 367 }
1ea6dd38
DH		 368 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
369 w83627ehf_reset_bank(data, reg);
08e7e278 370
9a61bf63 371 mutex_unlock(&data->lock);
08e7e278
JD		 372 return 0;
373}
374
375/* This function assumes that the caller holds data->update_lock */
1ea6dd38 376static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
08e7e278 377{
08e7e278
JD		 378 u8 reg;
379
380 switch (nr) {
381 case 0:
1ea6dd38 382 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
08e7e278 383 | ((data->fan_div[0] & 0x03) << 4);
14992c7e
RM		 384 /* fan5 input control bit is write only, compute the value */
385 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 386 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
387 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
08e7e278 388 | ((data->fan_div[0] & 0x04) << 3);
1ea6dd38 389 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 390 break;
391 case 1:
1ea6dd38 392 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
08e7e278 393 | ((data->fan_div[1] & 0x03) << 6);
14992c7e
RM		 394 /* fan5 input control bit is write only, compute the value */
395 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 396 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
397 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
08e7e278 398 | ((data->fan_div[1] & 0x04) << 4);
1ea6dd38 399 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 400 break;
401 case 2:
1ea6dd38 402 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
08e7e278 403 | ((data->fan_div[2] & 0x03) << 6);
1ea6dd38
DH		 404 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
405 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
08e7e278 406 | ((data->fan_div[2] & 0x04) << 5);
1ea6dd38 407 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 408 break;
409 case 3:
1ea6dd38 410 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
08e7e278 411 | (data->fan_div[3] & 0x03);
1ea6dd38
DH		 412 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
413 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
08e7e278 414 | ((data->fan_div[3] & 0x04) << 5);
1ea6dd38 415 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
08e7e278
JD		 416 break;
417 case 4:
1ea6dd38 418 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
33725ad3 419 | ((data->fan_div[4] & 0x03) << 2)
08e7e278 420 | ((data->fan_div[4] & 0x04) << 5);
1ea6dd38 421 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
08e7e278
JD		 422 break;
423 }
424}
425
ea7be66c
MH		 426static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
427{
428 int i;
429
430 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
431 data->fan_div[0] = (i >> 4) & 0x03;
432 data->fan_div[1] = (i >> 6) & 0x03;
433 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
434 data->fan_div[2] = (i >> 6) & 0x03;
435 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
436 data->fan_div[0] |= (i >> 3) & 0x04;
437 data->fan_div[1] |= (i >> 4) & 0x04;
438 data->fan_div[2] |= (i >> 5) & 0x04;
439 if (data->has_fan & ((1 << 3) | (1 << 4))) {
440 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
441 data->fan_div[3] = i & 0x03;
442 data->fan_div[4] = ((i >> 2) & 0x03)
443 | ((i >> 5) & 0x04);
444 }
445 if (data->has_fan & (1 << 3)) {
446 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
447 data->fan_div[3] |= (i >> 5) & 0x04;
448 }
449}
450
08e7e278
JD		 451static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
452{
1ea6dd38 453 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950 454 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
08e7e278
JD		 455 int i;
456
9a61bf63 457 mutex_lock(&data->update_lock);
08e7e278 458
6b3e4645 459 if (time_after(jiffies, data->last_updated + HZ + HZ/2)
08e7e278
JD		 460 || !data->valid) {
461 /* Fan clock dividers */
ea7be66c 462 w83627ehf_update_fan_div(data);
08e7e278 463
cf0676fe 464 /* Measured voltages and limits */
1ea6dd38
DH		 465 for (i = 0; i < data->in_num; i++) {
466 data->in[i] = w83627ehf_read_value(data,
cf0676fe 467 W83627EHF_REG_IN(i));
1ea6dd38 468 data->in_min[i] = w83627ehf_read_value(data,
cf0676fe 469 W83627EHF_REG_IN_MIN(i));
1ea6dd38 470 data->in_max[i] = w83627ehf_read_value(data,
cf0676fe
RM		 471 W83627EHF_REG_IN_MAX(i));
472 }
473
08e7e278
JD		 474 /* Measured fan speeds and limits */
475 for (i = 0; i < 5; i++) {
476 if (!(data->has_fan & (1 << i)))
477 continue;
478
1ea6dd38 479 data->fan[i] = w83627ehf_read_value(data,
08e7e278 480 W83627EHF_REG_FAN[i]);
1ea6dd38 481 data->fan_min[i] = w83627ehf_read_value(data,
08e7e278
JD		 482 W83627EHF_REG_FAN_MIN[i]);
483
484 /* If we failed to measure the fan speed and clock
485 divider can be increased, let's try that for next
486 time */
487 if (data->fan[i] == 0xff
488 && data->fan_div[i] < 0x07) {
1ea6dd38 489 dev_dbg(dev, "Increasing fan%d "
08e7e278 490 "clock divider from %u to %u\n",
33725ad3 491 i + 1, div_from_reg(data->fan_div[i]),
08e7e278
JD		 492 div_from_reg(data->fan_div[i] + 1));
493 data->fan_div[i]++;
1ea6dd38 494 w83627ehf_write_fan_div(data, i);
08e7e278
JD		 495 /* Preserve min limit if possible */
496 if (data->fan_min[i] >= 2
497 && data->fan_min[i] != 255)
1ea6dd38 498 w83627ehf_write_value(data,
08e7e278
JD		 499 W83627EHF_REG_FAN_MIN[i],
500 (data->fan_min[i] /= 2));
501 }
502 }
503
08c79950
RM		 504 for (i = 0; i < 4; i++) {
505 /* pwmcfg, tolarance mapped for i=0, i=1 to same reg */
506 if (i != 1) {
1ea6dd38 507 pwmcfg = w83627ehf_read_value(data,
08c79950 508 W83627EHF_REG_PWM_ENABLE[i]);
1ea6dd38 509 tolerance = w83627ehf_read_value(data,
08c79950
RM		 510 W83627EHF_REG_TOLERANCE[i]);
511 }
512 data->pwm_mode[i] =
513 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1)
514 ? 0 : 1;
515 data->pwm_enable[i] =
516 ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
517 & 3) + 1;
1ea6dd38 518 data->pwm[i] = w83627ehf_read_value(data,
08c79950 519 W83627EHF_REG_PWM[i]);
1ea6dd38 520 data->fan_min_output[i] = w83627ehf_read_value(data,
08c79950 521 W83627EHF_REG_FAN_MIN_OUTPUT[i]);
1ea6dd38 522 data->fan_stop_time[i] = w83627ehf_read_value(data,
08c79950
RM		 523 W83627EHF_REG_FAN_STOP_TIME[i]);
524 data->target_temp[i] =
1ea6dd38 525 w83627ehf_read_value(data,
08c79950
RM		 526 W83627EHF_REG_TARGET[i]) &
527 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
528 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0))
529 & 0x0f;
530 }
531
08e7e278 532 /* Measured temperatures and limits */
1ea6dd38 533 data->temp1 = w83627ehf_read_value(data,
08e7e278 534 W83627EHF_REG_TEMP1);
1ea6dd38 535 data->temp1_max = w83627ehf_read_value(data,
08e7e278 536 W83627EHF_REG_TEMP1_OVER);
1ea6dd38 537 data->temp1_max_hyst = w83627ehf_read_value(data,
08e7e278
JD		 538 W83627EHF_REG_TEMP1_HYST);
539 for (i = 0; i < 2; i++) {
1ea6dd38 540 data->temp[i] = w83627ehf_read_value(data,
08e7e278 541 W83627EHF_REG_TEMP[i]);
1ea6dd38 542 data->temp_max[i] = w83627ehf_read_value(data,
08e7e278 543 W83627EHF_REG_TEMP_OVER[i]);
1ea6dd38 544 data->temp_max_hyst[i] = w83627ehf_read_value(data,
08e7e278
JD		 545 W83627EHF_REG_TEMP_HYST[i]);
546 }
547
1ea6dd38 548 data->alarms = w83627ehf_read_value(data,
a4589dbb 549 W83627EHF_REG_ALARM1) |
1ea6dd38 550 (w83627ehf_read_value(data,
a4589dbb 551 W83627EHF_REG_ALARM2) << 8) |
1ea6dd38 552 (w83627ehf_read_value(data,
a4589dbb
JD		 553 W83627EHF_REG_ALARM3) << 16);
554
08e7e278
JD		 555 data->last_updated = jiffies;
556 data->valid = 1;
557 }
558
9a61bf63 559 mutex_unlock(&data->update_lock);
08e7e278
JD		 560 return data;
561}
562
563/*
564 * Sysfs callback functions
565 */
cf0676fe
RM		 566#define show_in_reg(reg) \
567static ssize_t \
568show_##reg(struct device *dev, struct device_attribute *attr, \
569 char *buf) \
570{ \
571 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
572 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
573 int nr = sensor_attr->index; \
574 return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr)); \
575}
576show_in_reg(in)
577show_in_reg(in_min)
578show_in_reg(in_max)
579
580#define store_in_reg(REG, reg) \
581static ssize_t \
582store_in_##reg (struct device *dev, struct device_attribute *attr, \
583 const char *buf, size_t count) \
584{ \
1ea6dd38 585 struct w83627ehf_data *data = dev_get_drvdata(dev); \
cf0676fe
RM		 586 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
587 int nr = sensor_attr->index; \
588 u32 val = simple_strtoul(buf, NULL, 10); \
589 \
590 mutex_lock(&data->update_lock); \
591 data->in_##reg[nr] = in_to_reg(val, nr); \
1ea6dd38 592 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \
cf0676fe
RM		 593 data->in_##reg[nr]); \
594 mutex_unlock(&data->update_lock); \
595 return count; \
596}
597
598store_in_reg(MIN, min)
599store_in_reg(MAX, max)
600
a4589dbb
JD		 601static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, char *buf)
602{
603 struct w83627ehf_data *data = w83627ehf_update_device(dev);
604 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
605 int nr = sensor_attr->index;
606 return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01);
607}
608
cf0676fe
RM		 609static struct sensor_device_attribute sda_in_input[] = {
610 SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
611 SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
612 SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
613 SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
614 SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
615 SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
616 SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
617 SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
618 SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
619 SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9),
620};
621
a4589dbb
JD		 622static struct sensor_device_attribute sda_in_alarm[] = {
623 SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0),
624 SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1),
625 SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2),
626 SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3),
627 SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8),
628 SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21),
629 SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20),
630 SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16),
631 SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17),
632 SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19),
633};
634
cf0676fe
RM		 635static struct sensor_device_attribute sda_in_min[] = {
636 SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0),
637 SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1),
638 SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2),
639 SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3),
640 SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4),
641 SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5),
642 SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6),
643 SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7),
644 SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8),
645 SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9),
646};
647
648static struct sensor_device_attribute sda_in_max[] = {
649 SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0),
650 SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1),
651 SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2),
652 SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3),
653 SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4),
654 SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5),
655 SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6),
656 SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7),
657 SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8),
658 SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9),
659};
660
08e7e278
JD		 661#define show_fan_reg(reg) \
662static ssize_t \
412fec82
YM		 663show_##reg(struct device *dev, struct device_attribute *attr, \
664 char *buf) \
08e7e278
JD		 665{ \
666 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
412fec82
YM		 667 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
668 int nr = sensor_attr->index; \
08e7e278
JD		 669 return sprintf(buf, "%d\n", \
670 fan_from_reg(data->reg[nr], \
671 div_from_reg(data->fan_div[nr]))); \
672}
673show_fan_reg(fan);
674show_fan_reg(fan_min);
675
676static ssize_t
412fec82
YM		 677show_fan_div(struct device *dev, struct device_attribute *attr,
678 char *buf)
08e7e278
JD		 679{
680 struct w83627ehf_data *data = w83627ehf_update_device(dev);
412fec82
YM		 681 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
682 int nr = sensor_attr->index;
683 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
08e7e278
JD		 684}
685
686static ssize_t
412fec82
YM		 687store_fan_min(struct device *dev, struct device_attribute *attr,
688 const char *buf, size_t count)
08e7e278 689{
1ea6dd38 690 struct w83627ehf_data *data = dev_get_drvdata(dev);
412fec82
YM		 691 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
692 int nr = sensor_attr->index;
08e7e278
JD		 693 unsigned int val = simple_strtoul(buf, NULL, 10);
694 unsigned int reg;
695 u8 new_div;
696
9a61bf63 697 mutex_lock(&data->update_lock);
08e7e278
JD		 698 if (!val) {
699 /* No min limit, alarm disabled */
700 data->fan_min[nr] = 255;
701 new_div = data->fan_div[nr]; /* No change */
702 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
703 } else if ((reg = 1350000U / val) >= 128 * 255) {
704 /* Speed below this value cannot possibly be represented,
705 even with the highest divider (128) */
706 data->fan_min[nr] = 254;
707 new_div = 7; /* 128 == (1 << 7) */
708 dev_warn(dev, "fan%u low limit %u below minimum %u, set to "
709 "minimum\n", nr + 1, val, fan_from_reg(254, 128));
710 } else if (!reg) {
711 /* Speed above this value cannot possibly be represented,
712 even with the lowest divider (1) */
713 data->fan_min[nr] = 1;
714 new_div = 0; /* 1 == (1 << 0) */
715 dev_warn(dev, "fan%u low limit %u above maximum %u, set to "
b9110b1c 716 "maximum\n", nr + 1, val, fan_from_reg(1, 1));
08e7e278
JD		 717 } else {
718 /* Automatically pick the best divider, i.e. the one such
719 that the min limit will correspond to a register value
720 in the 96..192 range */
721 new_div = 0;
722 while (reg > 192 && new_div < 7) {
723 reg >>= 1;
724 new_div++;
725 }
726 data->fan_min[nr] = reg;
727 }
728
729 /* Write both the fan clock divider (if it changed) and the new
730 fan min (unconditionally) */
731 if (new_div != data->fan_div[nr]) {
158ce075
JD		 732 /* Preserve the fan speed reading */
733 if (data->fan[nr] != 0xff) {
734 if (new_div > data->fan_div[nr])
735 data->fan[nr] >>= new_div - data->fan_div[nr];
736 else if (data->fan[nr] & 0x80)
737 data->fan[nr] = 0xff;
738 else
739 data->fan[nr] <<= data->fan_div[nr] - new_div;
740 }
08e7e278
JD		 741
742 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
743 nr + 1, div_from_reg(data->fan_div[nr]),
744 div_from_reg(new_div));
745 data->fan_div[nr] = new_div;
1ea6dd38 746 w83627ehf_write_fan_div(data, nr);
6b3e4645
JD		 747 /* Give the chip time to sample a new speed value */
748 data->last_updated = jiffies;
08e7e278 749 }
1ea6dd38 750 w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[nr],
08e7e278 751 data->fan_min[nr]);
9a61bf63 752 mutex_unlock(&data->update_lock);
08e7e278
JD		 753
754 return count;
755}
756
412fec82
YM		 757static struct sensor_device_attribute sda_fan_input[] = {
758 SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
759 SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
760 SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
761 SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
762 SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4),
763};
08e7e278 764
a4589dbb
JD		 765static struct sensor_device_attribute sda_fan_alarm[] = {
766 SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6),
767 SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7),
768 SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11),
769 SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10),
770 SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23),
771};
772
412fec82
YM		 773static struct sensor_device_attribute sda_fan_min[] = {
774 SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min,
775 store_fan_min, 0),
776 SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min,
777 store_fan_min, 1),
778 SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min,
779 store_fan_min, 2),
780 SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min,
781 store_fan_min, 3),
782 SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min,
783 store_fan_min, 4),
784};
08e7e278 785
412fec82
YM		 786static struct sensor_device_attribute sda_fan_div[] = {
787 SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0),
788 SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1),
789 SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2),
790 SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3),
791 SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4),
792};
793
08e7e278
JD		 794#define show_temp1_reg(reg) \
795static ssize_t \
6f637a64
GKH		 796show_##reg(struct device *dev, struct device_attribute *attr, \
797 char *buf) \
08e7e278
JD		 798{ \
799 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
800 return sprintf(buf, "%d\n", temp1_from_reg(data->reg)); \
801}
802show_temp1_reg(temp1);
803show_temp1_reg(temp1_max);
804show_temp1_reg(temp1_max_hyst);
805
806#define store_temp1_reg(REG, reg) \
807static ssize_t \
6f637a64
GKH		 808store_temp1_##reg(struct device *dev, struct device_attribute *attr, \
809 const char *buf, size_t count) \
08e7e278 810{ \
1ea6dd38 811 struct w83627ehf_data *data = dev_get_drvdata(dev); \
5bfedac0 812 long val = simple_strtol(buf, NULL, 10); \
08e7e278 813 \
9a61bf63 814 mutex_lock(&data->update_lock); \
08c79950 815 data->temp1_##reg = temp1_to_reg(val, -128000, 127000); \
1ea6dd38 816 w83627ehf_write_value(data, W83627EHF_REG_TEMP1_##REG, \
08e7e278 817 data->temp1_##reg); \
9a61bf63 818 mutex_unlock(&data->update_lock); \
08e7e278
JD		 819 return count; \
820}
821store_temp1_reg(OVER, max);
822store_temp1_reg(HYST, max_hyst);
823
08e7e278
JD		 824#define show_temp_reg(reg) \
825static ssize_t \
412fec82
YM		 826show_##reg(struct device *dev, struct device_attribute *attr, \
827 char *buf) \
08e7e278
JD		 828{ \
829 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
412fec82
YM		 830 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
831 int nr = sensor_attr->index; \
08e7e278
JD		 832 return sprintf(buf, "%d\n", \
833 LM75_TEMP_FROM_REG(data->reg[nr])); \
834}
835show_temp_reg(temp);
836show_temp_reg(temp_max);
837show_temp_reg(temp_max_hyst);
838
839#define store_temp_reg(REG, reg) \
840static ssize_t \
412fec82
YM		 841store_##reg(struct device *dev, struct device_attribute *attr, \
842 const char *buf, size_t count) \
08e7e278 843{ \
1ea6dd38 844 struct w83627ehf_data *data = dev_get_drvdata(dev); \
412fec82
YM		 845 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
846 int nr = sensor_attr->index; \
5bfedac0 847 long val = simple_strtol(buf, NULL, 10); \
08e7e278 848 \
9a61bf63 849 mutex_lock(&data->update_lock); \
08e7e278 850 data->reg[nr] = LM75_TEMP_TO_REG(val); \
1ea6dd38 851 w83627ehf_write_value(data, W83627EHF_REG_TEMP_##REG[nr], \
08e7e278 852 data->reg[nr]); \
9a61bf63 853 mutex_unlock(&data->update_lock); \
08e7e278
JD		 854 return count; \
855}
856store_temp_reg(OVER, temp_max);
857store_temp_reg(HYST, temp_max_hyst);
858
da667365
JD		 859static ssize_t
860show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
861{
862 struct w83627ehf_data *data = w83627ehf_update_device(dev);
863 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
864 int nr = sensor_attr->index;
865 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
866}
867
412fec82
YM		 868static struct sensor_device_attribute sda_temp[] = {
869 SENSOR_ATTR(temp1_input, S_IRUGO, show_temp1, NULL, 0),
870 SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 0),
871 SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 1),
872 SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp1_max,
873 store_temp1_max, 0),
874 SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max,
875 store_temp_max, 0),
876 SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max,
877 store_temp_max, 1),
878 SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp1_max_hyst,
879 store_temp1_max_hyst, 0),
880 SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
881 store_temp_max_hyst, 0),
882 SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
883 store_temp_max_hyst, 1),
a4589dbb
JD		 884 SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
885 SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
886 SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
da667365
JD		 887 SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0),
888 SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1),
889 SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2),
412fec82 890};
08e7e278 891
08c79950
RM		 892#define show_pwm_reg(reg) \
893static ssize_t show_##reg (struct device *dev, struct device_attribute *attr, \
894 char *buf) \
895{ \
896 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
897 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
898 int nr = sensor_attr->index; \
899 return sprintf(buf, "%d\n", data->reg[nr]); \
900}
901
902show_pwm_reg(pwm_mode)
903show_pwm_reg(pwm_enable)
904show_pwm_reg(pwm)
905
906static ssize_t
907store_pwm_mode(struct device *dev, struct device_attribute *attr,
908 const char *buf, size_t count)
909{
1ea6dd38 910 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 911 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
912 int nr = sensor_attr->index;
913 u32 val = simple_strtoul(buf, NULL, 10);
914 u16 reg;
915
916 if (val > 1)
917 return -EINVAL;
918 mutex_lock(&data->update_lock);
1ea6dd38 919 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 920 data->pwm_mode[nr] = val;
921 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]);
922 if (!val)
923 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr];
1ea6dd38 924 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 925 mutex_unlock(&data->update_lock);
926 return count;
927}
928
929static ssize_t
930store_pwm(struct device *dev, struct device_attribute *attr,
931 const char *buf, size_t count)
932{
1ea6dd38 933 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 934 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
935 int nr = sensor_attr->index;
936 u32 val = SENSORS_LIMIT(simple_strtoul(buf, NULL, 10), 0, 255);
937
938 mutex_lock(&data->update_lock);
939 data->pwm[nr] = val;
1ea6dd38 940 w83627ehf_write_value(data, W83627EHF_REG_PWM[nr], val);
08c79950
RM		 941 mutex_unlock(&data->update_lock);
942 return count;
943}
944
945static ssize_t
946store_pwm_enable(struct device *dev, struct device_attribute *attr,
947 const char *buf, size_t count)
948{
1ea6dd38 949 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 950 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
951 int nr = sensor_attr->index;
952 u32 val = simple_strtoul(buf, NULL, 10);
953 u16 reg;
954
955 if (!val || (val > 2)) /* only modes 1 and 2 are supported */
956 return -EINVAL;
957 mutex_lock(&data->update_lock);
1ea6dd38 958 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 959 data->pwm_enable[nr] = val;
960 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]);
961 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr];
1ea6dd38 962 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 963 mutex_unlock(&data->update_lock);
964 return count;
965}
966
967
968#define show_tol_temp(reg) \
969static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
970 char *buf) \
971{ \
972 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
973 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
974 int nr = sensor_attr->index; \
975 return sprintf(buf, "%d\n", temp1_from_reg(data->reg[nr])); \
976}
977
978show_tol_temp(tolerance)
979show_tol_temp(target_temp)
980
981static ssize_t
982store_target_temp(struct device *dev, struct device_attribute *attr,
983 const char *buf, size_t count)
984{
1ea6dd38 985 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 986 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
987 int nr = sensor_attr->index;
988 u8 val = temp1_to_reg(simple_strtoul(buf, NULL, 10), 0, 127000);
989
990 mutex_lock(&data->update_lock);
991 data->target_temp[nr] = val;
1ea6dd38 992 w83627ehf_write_value(data, W83627EHF_REG_TARGET[nr], val);
08c79950
RM		 993 mutex_unlock(&data->update_lock);
994 return count;
995}
996
997static ssize_t
998store_tolerance(struct device *dev, struct device_attribute *attr,
999 const char *buf, size_t count)
1000{
1ea6dd38 1001 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1002 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1003 int nr = sensor_attr->index;
1004 u16 reg;
1005 /* Limit the temp to 0C - 15C */
1006 u8 val = temp1_to_reg(simple_strtoul(buf, NULL, 10), 0, 15000);
1007
1008 mutex_lock(&data->update_lock);
1ea6dd38 1009 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
08c79950
RM		 1010 data->tolerance[nr] = val;
1011 if (nr == 1)
1012 reg = (reg & 0x0f) | (val << 4);
1013 else
1014 reg = (reg & 0xf0) | val;
1ea6dd38 1015 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
08c79950
RM		 1016 mutex_unlock(&data->update_lock);
1017 return count;
1018}
1019
1020static struct sensor_device_attribute sda_pwm[] = {
1021 SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0),
1022 SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1),
1023 SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2),
1024 SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3),
1025};
1026
1027static struct sensor_device_attribute sda_pwm_mode[] = {
1028 SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1029 store_pwm_mode, 0),
1030 SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1031 store_pwm_mode, 1),
1032 SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1033 store_pwm_mode, 2),
1034 SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1035 store_pwm_mode, 3),
1036};
1037
1038static struct sensor_device_attribute sda_pwm_enable[] = {
1039 SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1040 store_pwm_enable, 0),
1041 SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1042 store_pwm_enable, 1),
1043 SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1044 store_pwm_enable, 2),
1045 SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1046 store_pwm_enable, 3),
1047};
1048
1049static struct sensor_device_attribute sda_target_temp[] = {
1050 SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp,
1051 store_target_temp, 0),
1052 SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp,
1053 store_target_temp, 1),
1054 SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp,
1055 store_target_temp, 2),
1056 SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp,
1057 store_target_temp, 3),
1058};
1059
1060static struct sensor_device_attribute sda_tolerance[] = {
1061 SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1062 store_tolerance, 0),
1063 SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1064 store_tolerance, 1),
1065 SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1066 store_tolerance, 2),
1067 SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1068 store_tolerance, 3),
1069};
1070
08c79950
RM		 1071/* Smart Fan registers */
1072
1073#define fan_functions(reg, REG) \
1074static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1075 char *buf) \
1076{ \
1077 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1078 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1079 int nr = sensor_attr->index; \
1080 return sprintf(buf, "%d\n", data->reg[nr]); \
1081}\
1082static ssize_t \
1083store_##reg(struct device *dev, struct device_attribute *attr, \
1084 const char *buf, size_t count) \
1085{\
1ea6dd38 1086 struct w83627ehf_data *data = dev_get_drvdata(dev); \
08c79950
RM		 1087 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1088 int nr = sensor_attr->index; \
1089 u32 val = SENSORS_LIMIT(simple_strtoul(buf, NULL, 10), 1, 255); \
1090 mutex_lock(&data->update_lock); \
1091 data->reg[nr] = val; \
1ea6dd38 1092 w83627ehf_write_value(data, W83627EHF_REG_##REG[nr], val); \
08c79950
RM		 1093 mutex_unlock(&data->update_lock); \
1094 return count; \
1095}
1096
1097fan_functions(fan_min_output, FAN_MIN_OUTPUT)
1098
1099#define fan_time_functions(reg, REG) \
1100static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1101 char *buf) \
1102{ \
1103 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1104 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1105 int nr = sensor_attr->index; \
1106 return sprintf(buf, "%d\n", \
1107 step_time_from_reg(data->reg[nr], data->pwm_mode[nr])); \
1108} \
1109\
1110static ssize_t \
1111store_##reg(struct device *dev, struct device_attribute *attr, \
1112 const char *buf, size_t count) \
1113{ \
1ea6dd38 1114 struct w83627ehf_data *data = dev_get_drvdata(dev); \
08c79950
RM		 1115 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1116 int nr = sensor_attr->index; \
1117 u8 val = step_time_to_reg(simple_strtoul(buf, NULL, 10), \
1118 data->pwm_mode[nr]); \
1119 mutex_lock(&data->update_lock); \
1120 data->reg[nr] = val; \
1ea6dd38 1121 w83627ehf_write_value(data, W83627EHF_REG_##REG[nr], val); \
08c79950
RM		 1122 mutex_unlock(&data->update_lock); \
1123 return count; \
1124} \
1125
1126fan_time_functions(fan_stop_time, FAN_STOP_TIME)
1127
1ea6dd38
DH		 1128static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1129 char *buf)
1130{
1131 struct w83627ehf_data *data = dev_get_drvdata(dev);
1132
1133 return sprintf(buf, "%s\n", data->name);
1134}
1135static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
08c79950
RM		 1136
1137static struct sensor_device_attribute sda_sf3_arrays_fan4[] = {
1138 SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1139 store_fan_stop_time, 3),
1140 SENSOR_ATTR(pwm4_min_output, S_IWUSR | S_IRUGO, show_fan_min_output,
1141 store_fan_min_output, 3),
1142};
1143
1144static struct sensor_device_attribute sda_sf3_arrays[] = {
1145 SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1146 store_fan_stop_time, 0),
1147 SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1148 store_fan_stop_time, 1),
1149 SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1150 store_fan_stop_time, 2),
1151 SENSOR_ATTR(pwm1_min_output, S_IWUSR | S_IRUGO, show_fan_min_output,
1152 store_fan_min_output, 0),
1153 SENSOR_ATTR(pwm2_min_output, S_IWUSR | S_IRUGO, show_fan_min_output,
1154 store_fan_min_output, 1),
1155 SENSOR_ATTR(pwm3_min_output, S_IWUSR | S_IRUGO, show_fan_min_output,
1156 store_fan_min_output, 2),
1157};
1158
fc18d6c0
JD		 1159static ssize_t
1160show_vid(struct device *dev, struct device_attribute *attr, char *buf)
1161{
1162 struct w83627ehf_data *data = dev_get_drvdata(dev);
1163 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1164}
1165static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1166
08e7e278 1167/*
1ea6dd38 1168 * Driver and device management
08e7e278
JD		 1169 */
1170
c18beb5b
DH		 1171static void w83627ehf_device_remove_files(struct device *dev)
1172{
1173 /* some entries in the following arrays may not have been used in
1174 * device_create_file(), but device_remove_file() will ignore them */
1175 int i;
1ea6dd38 1176 struct w83627ehf_data *data = dev_get_drvdata(dev);
c18beb5b
DH		 1177
1178 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
1179 device_remove_file(dev, &sda_sf3_arrays[i].dev_attr);
1180 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++)
1181 device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr);
1ea6dd38 1182 for (i = 0; i < data->in_num; i++) {
c18beb5b
DH		 1183 device_remove_file(dev, &sda_in_input[i].dev_attr);
1184 device_remove_file(dev, &sda_in_alarm[i].dev_attr);
1185 device_remove_file(dev, &sda_in_min[i].dev_attr);
1186 device_remove_file(dev, &sda_in_max[i].dev_attr);
1187 }
1188 for (i = 0; i < 5; i++) {
1189 device_remove_file(dev, &sda_fan_input[i].dev_attr);
1190 device_remove_file(dev, &sda_fan_alarm[i].dev_attr);
1191 device_remove_file(dev, &sda_fan_div[i].dev_attr);
1192 device_remove_file(dev, &sda_fan_min[i].dev_attr);
1193 }
1194 for (i = 0; i < 4; i++) {
1195 device_remove_file(dev, &sda_pwm[i].dev_attr);
1196 device_remove_file(dev, &sda_pwm_mode[i].dev_attr);
1197 device_remove_file(dev, &sda_pwm_enable[i].dev_attr);
1198 device_remove_file(dev, &sda_target_temp[i].dev_attr);
1199 device_remove_file(dev, &sda_tolerance[i].dev_attr);
1200 }
1201 for (i = 0; i < ARRAY_SIZE(sda_temp); i++)
1202 device_remove_file(dev, &sda_temp[i].dev_attr);
c18beb5b 1203
1ea6dd38 1204 device_remove_file(dev, &dev_attr_name);
cbe311f2 1205 device_remove_file(dev, &dev_attr_cpu0_vid);
1ea6dd38 1206}
08e7e278 1207
1ea6dd38
DH		 1208/* Get the monitoring functions started */
1209static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data)
08e7e278
JD		 1210{
1211 int i;
da667365 1212 u8 tmp, diode;
08e7e278
JD		 1213
1214 /* Start monitoring is needed */
1ea6dd38 1215 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
08e7e278 1216 if (!(tmp & 0x01))
1ea6dd38 1217 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
08e7e278
JD		 1218 tmp | 0x01);
1219
1220 /* Enable temp2 and temp3 if needed */
1221 for (i = 0; i < 2; i++) {
1ea6dd38 1222 tmp = w83627ehf_read_value(data,
08e7e278
JD		 1223 W83627EHF_REG_TEMP_CONFIG[i]);
1224 if (tmp & 0x01)
1ea6dd38 1225 w83627ehf_write_value(data,
08e7e278
JD		 1226 W83627EHF_REG_TEMP_CONFIG[i],
1227 tmp & 0xfe);
1228 }
d3130f0e
JD		 1229
1230 /* Enable VBAT monitoring if needed */
1231 tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1232 if (!(tmp & 0x01))
1233 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
da667365
JD		 1234
1235 /* Get thermal sensor types */
1236 diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
1237 for (i = 0; i < 3; i++) {
1238 if ((tmp & (0x02 << i)))
1239 data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 2;
1240 else
1241 data->temp_type[i] = 4; /* thermistor */
1242 }
08e7e278
JD		 1243}
1244
1ea6dd38 1245static int __devinit w83627ehf_probe(struct platform_device *pdev)
08e7e278 1246{
1ea6dd38
DH		 1247 struct device *dev = &pdev->dev;
1248 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08e7e278 1249 struct w83627ehf_data *data;
1ea6dd38 1250 struct resource *res;
fc18d6c0 1251 u8 fan4pin, fan5pin, en_vrm10;
08e7e278
JD		 1252 int i, err = 0;
1253
1ea6dd38
DH		 1254 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1255 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
08e7e278 1256 err = -EBUSY;
1ea6dd38
DH		 1257 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
1258 (unsigned long)res->start,
1259 (unsigned long)res->start + IOREGION_LENGTH - 1);
08e7e278
JD		 1260 goto exit;
1261 }
1262
ba9c2e8d 1263 if (!(data = kzalloc(sizeof(struct w83627ehf_data), GFP_KERNEL))) {
08e7e278
JD		 1264 err = -ENOMEM;
1265 goto exit_release;
1266 }
08e7e278 1267
1ea6dd38 1268 data->addr = res->start;
9a61bf63 1269 mutex_init(&data->lock);
9a61bf63 1270 mutex_init(&data->update_lock);
1ea6dd38
DH		 1271 data->name = w83627ehf_device_names[sio_data->kind];
1272 platform_set_drvdata(pdev, data);
08e7e278 1273
1ea6dd38
DH		 1274 /* 627EHG and 627EHF have 10 voltage inputs; DHG has 9 */
1275 data->in_num = (sio_data->kind == w83627dhg) ? 9 : 10;
08e7e278
JD		 1276
1277 /* Initialize the chip */
1ea6dd38 1278 w83627ehf_init_device(data);
08e7e278 1279
fc18d6c0
JD		 1280 data->vrm = vid_which_vrm();
1281 superio_enter(sio_data->sioreg);
fc18d6c0
JD		 1282 /* Read VID value */
1283 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
58e6e781
JD		 1284 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
1285 /* Set VID input sensibility if needed. In theory the BIOS
1286 should have set it, but in practice it's not always the
1287 case. We only do it for the W83627EHF/EHG because the
1288 W83627DHG is more complex in this respect. */
1289 if (sio_data->kind == w83627ehf) {
1290 en_vrm10 = superio_inb(sio_data->sioreg,
1291 SIO_REG_EN_VRM10);
1292 if ((en_vrm10 & 0x08) && data->vrm == 90) {
1293 dev_warn(dev, "Setting VID input voltage to "
1294 "TTL\n");
1295 superio_outb(sio_data->sioreg, SIO_REG_EN_VRM10,
1296 en_vrm10 & ~0x08);
1297 } else if (!(en_vrm10 & 0x08) && data->vrm == 100) {
1298 dev_warn(dev, "Setting VID input voltage to "
1299 "VRM10\n");
1300 superio_outb(sio_data->sioreg, SIO_REG_EN_VRM10,
1301 en_vrm10 | 0x08);
1302 }
1303 }
1304
cbe311f2
JD		 1305 data->vid = superio_inb(sio_data->sioreg, SIO_REG_VID_DATA);
1306 if (sio_data->kind == w83627ehf) /* 6 VID pins only */
1307 data->vid &= 0x3f;
1308
1309 err = device_create_file(dev, &dev_attr_cpu0_vid);
1310 if (err)
1311 goto exit_release;
58e6e781 1312 } else {
fc18d6c0
JD		 1313 dev_info(dev, "VID pins in output mode, CPU VID not "
1314 "available\n");
fc18d6c0
JD		 1315 }
1316
08c79950
RM		 1317 /* fan4 and fan5 share some pins with the GPIO and serial flash */
1318
1ea6dd38
DH		 1319 fan5pin = superio_inb(sio_data->sioreg, 0x24) & 0x2;
1320 fan4pin = superio_inb(sio_data->sioreg, 0x29) & 0x6;
1321 superio_exit(sio_data->sioreg);
08c79950 1322
08e7e278 1323 /* It looks like fan4 and fan5 pins can be alternatively used
14992c7e
RM		 1324 as fan on/off switches, but fan5 control is write only :/
1325 We assume that if the serial interface is disabled, designers
1326 connected fan5 as input unless they are emitting log 1, which
1327 is not the default. */
08c79950 1328
08e7e278 1329 data->has_fan = 0x07; /* fan1, fan2 and fan3 */
1ea6dd38 1330 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
08c79950 1331 if ((i & (1 << 2)) && (!fan4pin))
08e7e278 1332 data->has_fan |= (1 << 3);
14992c7e 1333 if (!(i & (1 << 1)) && (!fan5pin))
08e7e278
JD		 1334 data->has_fan |= (1 << 4);
1335
ea7be66c
MH		 1336 /* Read fan clock dividers immediately */
1337 w83627ehf_update_fan_div(data);
1338
08e7e278 1339 /* Register sysfs hooks */
08c79950 1340 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
c18beb5b
DH		 1341 if ((err = device_create_file(dev,
1342 &sda_sf3_arrays[i].dev_attr)))
1343 goto exit_remove;
08c79950
RM		 1344
1345 /* if fan4 is enabled create the sf3 files for it */
1346 if (data->has_fan & (1 << 3))
c18beb5b
DH		 1347 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) {
1348 if ((err = device_create_file(dev,
1349 &sda_sf3_arrays_fan4[i].dev_attr)))
1350 goto exit_remove;
1351 }
08c79950 1352
1ea6dd38 1353 for (i = 0; i < data->in_num; i++)
c18beb5b
DH		 1354 if ((err = device_create_file(dev, &sda_in_input[i].dev_attr))
1355 || (err = device_create_file(dev,
1356 &sda_in_alarm[i].dev_attr))
1357 || (err = device_create_file(dev,
1358 &sda_in_min[i].dev_attr))
1359 || (err = device_create_file(dev,
1360 &sda_in_max[i].dev_attr)))
1361 goto exit_remove;
cf0676fe 1362
412fec82 1363 for (i = 0; i < 5; i++) {
08c79950 1364 if (data->has_fan & (1 << i)) {
c18beb5b
DH		 1365 if ((err = device_create_file(dev,
1366 &sda_fan_input[i].dev_attr))
1367 || (err = device_create_file(dev,
1368 &sda_fan_alarm[i].dev_attr))
1369 || (err = device_create_file(dev,
1370 &sda_fan_div[i].dev_attr))
1371 || (err = device_create_file(dev,
1372 &sda_fan_min[i].dev_attr)))
1373 goto exit_remove;
1374 if (i < 4 && /* w83627ehf only has 4 pwm */
1375 ((err = device_create_file(dev,
1376 &sda_pwm[i].dev_attr))
1377 || (err = device_create_file(dev,
1378 &sda_pwm_mode[i].dev_attr))
1379 || (err = device_create_file(dev,
1380 &sda_pwm_enable[i].dev_attr))
1381 || (err = device_create_file(dev,
1382 &sda_target_temp[i].dev_attr))
1383 || (err = device_create_file(dev,
1384 &sda_tolerance[i].dev_attr))))
1385 goto exit_remove;
08c79950 1386 }
08e7e278 1387 }
08c79950 1388
412fec82 1389 for (i = 0; i < ARRAY_SIZE(sda_temp); i++)
c18beb5b
DH		 1390 if ((err = device_create_file(dev, &sda_temp[i].dev_attr)))
1391 goto exit_remove;
1392
1ea6dd38
DH		 1393 err = device_create_file(dev, &dev_attr_name);
1394 if (err)
1395 goto exit_remove;
1396
1beeffe4
TJ		 1397 data->hwmon_dev = hwmon_device_register(dev);
1398 if (IS_ERR(data->hwmon_dev)) {
1399 err = PTR_ERR(data->hwmon_dev);
c18beb5b
DH		 1400 goto exit_remove;
1401 }
08e7e278
JD		 1402
1403 return 0;
1404
c18beb5b
DH		 1405exit_remove:
1406 w83627ehf_device_remove_files(dev);
08e7e278 1407 kfree(data);
1ea6dd38 1408 platform_set_drvdata(pdev, NULL);
08e7e278 1409exit_release:
1ea6dd38 1410 release_region(res->start, IOREGION_LENGTH);
08e7e278
JD		 1411exit:
1412 return err;
1413}
1414
1ea6dd38 1415static int __devexit w83627ehf_remove(struct platform_device *pdev)
08e7e278 1416{
1ea6dd38 1417 struct w83627ehf_data *data = platform_get_drvdata(pdev);
08e7e278 1418
1beeffe4 1419 hwmon_device_unregister(data->hwmon_dev);
1ea6dd38
DH		 1420 w83627ehf_device_remove_files(&pdev->dev);
1421 release_region(data->addr, IOREGION_LENGTH);
1422 platform_set_drvdata(pdev, NULL);
943b0830 1423 kfree(data);
08e7e278
JD		 1424
1425 return 0;
1426}
1427
1ea6dd38 1428static struct platform_driver w83627ehf_driver = {
cdaf7934 1429 .driver = {
87218842 1430 .owner = THIS_MODULE,
1ea6dd38 1431 .name = DRVNAME,
cdaf7934 1432 },
1ea6dd38
DH		 1433 .probe = w83627ehf_probe,
1434 .remove = __devexit_p(w83627ehf_remove),
08e7e278
JD		 1435};
1436
1ea6dd38
DH		 1437/* w83627ehf_find() looks for a '627 in the Super-I/O config space */
1438static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
1439 struct w83627ehf_sio_data *sio_data)
08e7e278 1440{
1ea6dd38
DH		 1441 static const char __initdata sio_name_W83627EHF[] = "W83627EHF";
1442 static const char __initdata sio_name_W83627EHG[] = "W83627EHG";
1443 static const char __initdata sio_name_W83627DHG[] = "W83627DHG";
1444
08e7e278 1445 u16 val;
1ea6dd38 1446 const char *sio_name;
08e7e278 1447
1ea6dd38 1448 superio_enter(sioaddr);
08e7e278 1449
67b671bc
JD		 1450 if (force_id)
1451 val = force_id;
1452 else
1453 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
1454 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
657c93b1 1455 switch (val & SIO_ID_MASK) {
657c93b1 1456 case SIO_W83627EHF_ID:
1ea6dd38
DH		 1457 sio_data->kind = w83627ehf;
1458 sio_name = sio_name_W83627EHF;
1459 break;
657c93b1 1460 case SIO_W83627EHG_ID:
1ea6dd38
DH		 1461 sio_data->kind = w83627ehf;
1462 sio_name = sio_name_W83627EHG;
1463 break;
1464 case SIO_W83627DHG_ID:
1465 sio_data->kind = w83627dhg;
1466 sio_name = sio_name_W83627DHG;
657c93b1
DH		 1467 break;
1468 default:
9f66036b
JD		 1469 if (val != 0xffff)
1470 pr_debug(DRVNAME ": unsupported chip ID: 0x%04x\n",
1471 val);
1ea6dd38 1472 superio_exit(sioaddr);
08e7e278
JD		 1473 return -ENODEV;
1474 }
1475
1ea6dd38
DH		 1476 /* We have a known chip, find the HWM I/O address */
1477 superio_select(sioaddr, W83627EHF_LD_HWM);
1478 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
1479 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
1a641fce 1480 *addr = val & IOREGION_ALIGNMENT;
2d8672c5 1481 if (*addr == 0) {
475ef855
DH		 1482 printk(KERN_ERR DRVNAME ": Refusing to enable a Super-I/O "
1483 "device with a base I/O port 0.\n");
1ea6dd38 1484 superio_exit(sioaddr);
08e7e278
JD		 1485 return -ENODEV;
1486 }
1487
1488 /* Activate logical device if needed */
1ea6dd38 1489 val = superio_inb(sioaddr, SIO_REG_ENABLE);
475ef855
DH		 1490 if (!(val & 0x01)) {
1491 printk(KERN_WARNING DRVNAME ": Forcibly enabling Super-I/O. "
1492 "Sensor is probably unusable.\n");
1ea6dd38 1493 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
475ef855 1494 }
1ea6dd38
DH		 1495
1496 superio_exit(sioaddr);
1497 pr_info(DRVNAME ": Found %s chip at %#x\n", sio_name, *addr);
1498 sio_data->sioreg = sioaddr;
08e7e278 1499
08e7e278
JD		 1500 return 0;
1501}
1502
1ea6dd38
DH		 1503/* when Super-I/O functions move to a separate file, the Super-I/O
1504 * bus will manage the lifetime of the device and this module will only keep
1505 * track of the w83627ehf driver. But since we platform_device_alloc(), we
1506 * must keep track of the device */
1507static struct platform_device *pdev;
1508
08e7e278
JD		 1509static int __init sensors_w83627ehf_init(void)
1510{
1ea6dd38
DH		 1511 int err;
1512 unsigned short address;
1513 struct resource res;
1514 struct w83627ehf_sio_data sio_data;
1515
1516 /* initialize sio_data->kind and sio_data->sioreg.
1517 *
1518 * when Super-I/O functions move to a separate file, the Super-I/O
1519 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
1520 * w83627ehf hardware monitor, and call probe() */
1521 if (w83627ehf_find(0x2e, &address, &sio_data) &&
1522 w83627ehf_find(0x4e, &address, &sio_data))
08e7e278
JD		 1523 return -ENODEV;
1524
1ea6dd38
DH		 1525 err = platform_driver_register(&w83627ehf_driver);
1526 if (err)
1527 goto exit;
1528
1529 if (!(pdev = platform_device_alloc(DRVNAME, address))) {
1530 err = -ENOMEM;
1531 printk(KERN_ERR DRVNAME ": Device allocation failed\n");
1532 goto exit_unregister;
1533 }
1534
1535 err = platform_device_add_data(pdev, &sio_data,
1536 sizeof(struct w83627ehf_sio_data));
1537 if (err) {
1538 printk(KERN_ERR DRVNAME ": Platform data allocation failed\n");
1539 goto exit_device_put;
1540 }
1541
1542 memset(&res, 0, sizeof(res));
1543 res.name = DRVNAME;
1544 res.start = address + IOREGION_OFFSET;
1545 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
1546 res.flags = IORESOURCE_IO;
1547 err = platform_device_add_resources(pdev, &res, 1);
1548 if (err) {
1549 printk(KERN_ERR DRVNAME ": Device resource addition failed "
1550 "(%d)\n", err);
1551 goto exit_device_put;
1552 }
1553
1554 /* platform_device_add calls probe() */
1555 err = platform_device_add(pdev);
1556 if (err) {
1557 printk(KERN_ERR DRVNAME ": Device addition failed (%d)\n",
1558 err);
1559 goto exit_device_put;
1560 }
1561
1562 return 0;
1563
1564exit_device_put:
1565 platform_device_put(pdev);
1566exit_unregister:
1567 platform_driver_unregister(&w83627ehf_driver);
1568exit:
1569 return err;
08e7e278
JD		 1570}
1571
1572static void __exit sensors_w83627ehf_exit(void)
1573{
1ea6dd38
DH		 1574 platform_device_unregister(pdev);
1575 platform_driver_unregister(&w83627ehf_driver);
08e7e278
JD		 1576}
1577
1578MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
1579MODULE_DESCRIPTION("W83627EHF driver");
1580MODULE_LICENSE("GPL");
1581
1582module_init(sensors_w83627ehf_init);
1583module_exit(sensors_w83627ehf_exit);
Linux kernel - Deliverables
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