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Merge branch 'nfs-for-3.2' of git://git.linux-nfs.org/projects/trondmy/linux-nfs
[deliverable/linux.git] / drivers / hwmon / w83627ehf.c
CommitLineData
08e7e278
JD		 1/*
2 w83627ehf - Driver for the hardware monitoring functionality of
e7e1ca6e 3 the Winbond W83627EHF Super-I/O chip
08e7e278 4 Copyright (C) 2005 Jean Delvare <khali@linux-fr.org>
3379ceee 5 Copyright (C) 2006 Yuan Mu (Winbond),
e7e1ca6e
GR		 6 Rudolf Marek <r.marek@assembler.cz>
7 David Hubbard <david.c.hubbard@gmail.com>
41e9a062 8 Daniel J Blueman <daniel.blueman@gmail.com>
ec3e5a16 9 Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
08e7e278
JD		 10
11 Shamelessly ripped from the w83627hf driver
12 Copyright (C) 2003 Mark Studebaker
13
14 Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
15 in testing and debugging this driver.
16
8dd2d2ca
JD		 17 This driver also supports the W83627EHG, which is the lead-free
18 version of the W83627EHF.
19
08e7e278
JD		 20 This program is free software; you can redistribute it and/or modify
21 it under the terms of the GNU General Public License as published by
22 the Free Software Foundation; either version 2 of the License, or
23 (at your option) any later version.
24
25 This program is distributed in the hope that it will be useful,
26 but WITHOUT ANY WARRANTY; without even the implied warranty of
27 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 GNU General Public License for more details.
29
30 You should have received a copy of the GNU General Public License
31 along with this program; if not, write to the Free Software
32 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
33
34
35 Supports the following chips:
36
657c93b1
DH		 37 Chip #vin #fan #pwm #temp chip IDs man ID
38 w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
e7e1ca6e 39 0x8860 0xa1
657c93b1 40 w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
c1e48dce 41 w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
237c8d2f 42 w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
d36cf32c 43 w83667hg-b 9 5 3 4 0xb350 0xc1 0x5ca3
ec3e5a16
GR		 44 nct6775f 9 4 3 9 0xb470 0xc1 0x5ca3
45 nct6776f 9 5 3 9 0xC330 0xc1 0x5ca3
08e7e278
JD		 46*/
47
abdc6fd1
JP		 48#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
08e7e278
JD		 50#include <linux/module.h>
51#include <linux/init.h>
52#include <linux/slab.h>
1ea6dd38
DH		 53#include <linux/jiffies.h>
54#include <linux/platform_device.h>
943b0830 55#include <linux/hwmon.h>
412fec82 56#include <linux/hwmon-sysfs.h>
fc18d6c0 57#include <linux/hwmon-vid.h>
943b0830 58#include <linux/err.h>
9a61bf63 59#include <linux/mutex.h>
b9acb64a 60#include <linux/acpi.h>
6055fae8 61#include <linux/io.h>
08e7e278
JD		 62#include "lm75.h"
63
ec3e5a16
GR		 64enum kinds { w83627ehf, w83627dhg, w83627dhg_p, w83667hg, w83667hg_b, nct6775,
65 nct6776 };
08e7e278 66
1ea6dd38 67/* used to set data->name = w83627ehf_device_names[data->sio_kind] */
e7e1ca6e 68static const char * const w83627ehf_device_names[] = {
1ea6dd38
DH		 69 "w83627ehf",
70 "w83627dhg",
c1e48dce 71 "w83627dhg",
237c8d2f 72 "w83667hg",
c39aedaf 73 "w83667hg",
ec3e5a16
GR		 74 "nct6775",
75 "nct6776",
1ea6dd38
DH		 76};
77
67b671bc
JD		 78static unsigned short force_id;
79module_param(force_id, ushort, 0);
80MODULE_PARM_DESC(force_id, "Override the detected device ID");
81
d42e869a
ID		 82static unsigned short fan_debounce;
83module_param(fan_debounce, ushort, 0);
84MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
85
1ea6dd38 86#define DRVNAME "w83627ehf"
08e7e278 87
657c93b1 88/*
1ea6dd38 89 * Super-I/O constants and functions
657c93b1 90 */
08e7e278
JD		 91
92#define W83627EHF_LD_HWM 0x0b
e7e1ca6e 93#define W83667HG_LD_VID 0x0d
08e7e278
JD		 94
95#define SIO_REG_LDSEL 0x07 /* Logical device select */
96#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
fc18d6c0 97#define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
08e7e278
JD		 98#define SIO_REG_ENABLE 0x30 /* Logical device enable */
99#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
fc18d6c0
JD		 100#define SIO_REG_VID_CTRL 0xF0 /* VID control */
101#define SIO_REG_VID_DATA 0xF1 /* VID data */
08e7e278 102
657c93b1
DH		 103#define SIO_W83627EHF_ID 0x8850
104#define SIO_W83627EHG_ID 0x8860
105#define SIO_W83627DHG_ID 0xa020
c1e48dce 106#define SIO_W83627DHG_P_ID 0xb070
e7e1ca6e 107#define SIO_W83667HG_ID 0xa510
c39aedaf 108#define SIO_W83667HG_B_ID 0xb350
ec3e5a16
GR		 109#define SIO_NCT6775_ID 0xb470
110#define SIO_NCT6776_ID 0xc330
657c93b1 111#define SIO_ID_MASK 0xFFF0
08e7e278
JD		 112
113static inline void
1ea6dd38 114superio_outb(int ioreg, int reg, int val)
08e7e278 115{
1ea6dd38
DH		 116 outb(reg, ioreg);
117 outb(val, ioreg + 1);
08e7e278
JD		 118}
119
120static inline int
1ea6dd38 121superio_inb(int ioreg, int reg)
08e7e278 122{
1ea6dd38
DH		 123 outb(reg, ioreg);
124 return inb(ioreg + 1);
08e7e278
JD		 125}
126
127static inline void
1ea6dd38 128superio_select(int ioreg, int ld)
08e7e278 129{
1ea6dd38
DH		 130 outb(SIO_REG_LDSEL, ioreg);
131 outb(ld, ioreg + 1);
08e7e278
JD		 132}
133
134static inline void
1ea6dd38 135superio_enter(int ioreg)
08e7e278 136{
1ea6dd38
DH		 137 outb(0x87, ioreg);
138 outb(0x87, ioreg);
08e7e278
JD		 139}
140
141static inline void
1ea6dd38 142superio_exit(int ioreg)
08e7e278 143{
022b75a3 144 outb(0xaa, ioreg);
1ea6dd38
DH		 145 outb(0x02, ioreg);
146 outb(0x02, ioreg + 1);
08e7e278
JD		 147}
148
149/*
150 * ISA constants
151 */
152
e7e1ca6e 153#define IOREGION_ALIGNMENT (~7)
1a641fce
JD		 154#define IOREGION_OFFSET 5
155#define IOREGION_LENGTH 2
1ea6dd38
DH		 156#define ADDR_REG_OFFSET 0
157#define DATA_REG_OFFSET 1
08e7e278
JD		 158
159#define W83627EHF_REG_BANK 0x4E
160#define W83627EHF_REG_CONFIG 0x40
657c93b1
DH		 161
162/* Not currently used:
163 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
164 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
165 * REG_MAN_ID is at port 0x4f
166 * REG_CHIP_ID is at port 0x58 */
08e7e278
JD		 167
168static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
169static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
170
cf0676fe
RM		 171/* The W83627EHF registers for nr=7,8,9 are in bank 5 */
172#define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
173 (0x554 + (((nr) - 7) * 2)))
174#define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
175 (0x555 + (((nr) - 7) * 2)))
176#define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
177 (0x550 + (nr) - 7))
178
d36cf32c
GR		 179static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250, 0x7e };
180static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253, 0 };
181static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255, 0 };
182static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252, 0 };
08e7e278
JD		 183
184/* Fan clock dividers are spread over the following five registers */
185#define W83627EHF_REG_FANDIV1 0x47
186#define W83627EHF_REG_FANDIV2 0x4B
187#define W83627EHF_REG_VBAT 0x5D
188#define W83627EHF_REG_DIODE 0x59
189#define W83627EHF_REG_SMI_OVT 0x4C
190
ec3e5a16
GR		 191/* NCT6775F has its own fan divider registers */
192#define NCT6775_REG_FANDIV1 0x506
193#define NCT6775_REG_FANDIV2 0x507
d42e869a 194#define NCT6775_REG_FAN_DEBOUNCE 0xf0
ec3e5a16 195
a4589dbb
JD		 196#define W83627EHF_REG_ALARM1 0x459
197#define W83627EHF_REG_ALARM2 0x45A
198#define W83627EHF_REG_ALARM3 0x45B
199
08c79950 200/* SmartFan registers */
41e9a062
DB		 201#define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
202#define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
203
08c79950
RM		 204/* DC or PWM output fan configuration */
205static const u8 W83627EHF_REG_PWM_ENABLE[] = {
206 0x04, /* SYS FAN0 output mode and PWM mode */
207 0x04, /* CPU FAN0 output mode and PWM mode */
208 0x12, /* AUX FAN mode */
41e9a062 209 0x62, /* CPU FAN1 mode */
08c79950
RM		 210};
211
212static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
213static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
214
215/* FAN Duty Cycle, be used to control */
279af1a9
GR		 216static const u16 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
217static const u16 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
08c79950
RM		 218static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
219
08c79950 220/* Advanced Fan control, some values are common for all fans */
279af1a9
GR		 221static const u16 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
222static const u16 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
223static const u16 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
c39aedaf 224
279af1a9 225static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[]
c39aedaf 226 = { 0xff, 0x67, 0xff, 0x69 };
279af1a9 227static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[]
c39aedaf
GR		 228 = { 0xff, 0x68, 0xff, 0x6a };
229
279af1a9
GR		 230static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b };
231static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[]
232 = { 0x68, 0x6a, 0x6c };
08c79950 233
ec3e5a16
GR		 234static const u16 NCT6775_REG_TARGET[] = { 0x101, 0x201, 0x301 };
235static const u16 NCT6775_REG_FAN_MODE[] = { 0x102, 0x202, 0x302 };
236static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = { 0x105, 0x205, 0x305 };
237static const u16 NCT6775_REG_FAN_START_OUTPUT[] = { 0x106, 0x206, 0x306 };
238static const u16 NCT6775_REG_FAN_STOP_TIME[] = { 0x107, 0x207, 0x307 };
239static const u16 NCT6775_REG_PWM[] = { 0x109, 0x209, 0x309 };
240static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
241static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
26bc440e 242static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
ec3e5a16
GR		 243static const u16 NCT6776_REG_FAN_MIN[] = { 0x63a, 0x63c, 0x63e, 0x640, 0x642};
244
245static const u16 NCT6775_REG_TEMP[]
246 = { 0x27, 0x150, 0x250, 0x73, 0x75, 0x77, 0x62b, 0x62c, 0x62d };
247static const u16 NCT6775_REG_TEMP_CONFIG[]
248 = { 0, 0x152, 0x252, 0, 0, 0, 0x628, 0x629, 0x62A };
249static const u16 NCT6775_REG_TEMP_HYST[]
250 = { 0x3a, 0x153, 0x253, 0, 0, 0, 0x673, 0x678, 0x67D };
251static const u16 NCT6775_REG_TEMP_OVER[]
252 = { 0x39, 0x155, 0x255, 0, 0, 0, 0x672, 0x677, 0x67C };
253static const u16 NCT6775_REG_TEMP_SOURCE[]
254 = { 0x621, 0x622, 0x623, 0x100, 0x200, 0x300, 0x624, 0x625, 0x626 };
255
d36cf32c
GR		 256static const char *const w83667hg_b_temp_label[] = {
257 "SYSTIN",
258 "CPUTIN",
259 "AUXTIN",
260 "AMDTSI",
261 "PECI Agent 1",
262 "PECI Agent 2",
263 "PECI Agent 3",
264 "PECI Agent 4"
265};
266
ec3e5a16
GR		 267static const char *const nct6775_temp_label[] = {
268 "",
269 "SYSTIN",
270 "CPUTIN",
271 "AUXTIN",
272 "AMD SB-TSI",
273 "PECI Agent 0",
274 "PECI Agent 1",
275 "PECI Agent 2",
276 "PECI Agent 3",
277 "PECI Agent 4",
278 "PECI Agent 5",
279 "PECI Agent 6",
280 "PECI Agent 7",
281 "PCH_CHIP_CPU_MAX_TEMP",
282 "PCH_CHIP_TEMP",
283 "PCH_CPU_TEMP",
284 "PCH_MCH_TEMP",
285 "PCH_DIM0_TEMP",
286 "PCH_DIM1_TEMP",
287 "PCH_DIM2_TEMP",
288 "PCH_DIM3_TEMP"
289};
290
291static const char *const nct6776_temp_label[] = {
292 "",
293 "SYSTIN",
294 "CPUTIN",
295 "AUXTIN",
296 "SMBUSMASTER 0",
297 "SMBUSMASTER 1",
298 "SMBUSMASTER 2",
299 "SMBUSMASTER 3",
300 "SMBUSMASTER 4",
301 "SMBUSMASTER 5",
302 "SMBUSMASTER 6",
303 "SMBUSMASTER 7",
304 "PECI Agent 0",
305 "PECI Agent 1",
306 "PCH_CHIP_CPU_MAX_TEMP",
307 "PCH_CHIP_TEMP",
308 "PCH_CPU_TEMP",
309 "PCH_MCH_TEMP",
310 "PCH_DIM0_TEMP",
311 "PCH_DIM1_TEMP",
312 "PCH_DIM2_TEMP",
313 "PCH_DIM3_TEMP",
314 "BYTE_TEMP"
315};
316
317#define NUM_REG_TEMP ARRAY_SIZE(NCT6775_REG_TEMP)
d36cf32c 318
bce26c58
GR		 319static inline int is_word_sized(u16 reg)
320{
ec3e5a16 321 return ((((reg & 0xff00) == 0x100
bce26c58
GR		 322 || (reg & 0xff00) == 0x200)
323 && ((reg & 0x00ff) == 0x50
324 || (reg & 0x00ff) == 0x53
ec3e5a16
GR		 325 || (reg & 0x00ff) == 0x55))
326 || (reg & 0xfff0) == 0x630
327 || reg == 0x640 || reg == 0x642
328 || ((reg & 0xfff0) == 0x650
329 && (reg & 0x000f) >= 0x06)
330 || reg == 0x73 || reg == 0x75 || reg == 0x77
331 );
bce26c58
GR		 332}
333
08e7e278
JD		 334/*
335 * Conversions
336 */
337
08c79950
RM		 338/* 1 is PWM mode, output in ms */
339static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
340{
341 return mode ? 100 * reg : 400 * reg;
342}
343
344static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
345{
346 return SENSORS_LIMIT((mode ? (msec + 50) / 100 :
347 (msec + 200) / 400), 1, 255);
348}
349
26bc440e 350static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
08e7e278 351{
26bc440e 352 if (reg == 0 || reg == 255)
08e7e278 353 return 0;
26bc440e
GR		 354 return 1350000U / (reg << divreg);
355}
356
357static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
358{
359 if ((reg & 0xff1f) == 0xff1f)
360 return 0;
361
362 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
363
364 if (reg == 0)
365 return 0;
366
367 return 1350000U / reg;
368}
369
370static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
371{
372 if (reg == 0 || reg == 0xffff)
373 return 0;
374
375 /*
376 * Even though the registers are 16 bit wide, the fan divisor
377 * still applies.
378 */
379 return 1350000U / (reg << divreg);
08e7e278
JD		 380}
381
382static inline unsigned int
383div_from_reg(u8 reg)
384{
385 return 1 << reg;
386}
387
388static inline int
bce26c58 389temp_from_reg(u16 reg, s16 regval)
08e7e278 390{
bce26c58
GR		 391 if (is_word_sized(reg))
392 return LM75_TEMP_FROM_REG(regval);
133d324d 393 return ((s8)regval) * 1000;
08e7e278
JD		 394}
395
ec3e5a16 396static inline u16
bce26c58 397temp_to_reg(u16 reg, long temp)
08e7e278 398{
bce26c58
GR		 399 if (is_word_sized(reg))
400 return LM75_TEMP_TO_REG(temp);
133d324d
JD		 401 return (s8)DIV_ROUND_CLOSEST(SENSORS_LIMIT(temp, -127000, 128000),
402 1000);
08e7e278
JD		 403}
404
cf0676fe
RM		 405/* Some of analog inputs have internal scaling (2x), 8mV is ADC LSB */
406
407static u8 scale_in[10] = { 8, 8, 16, 16, 8, 8, 8, 16, 16, 8 };
408
409static inline long in_from_reg(u8 reg, u8 nr)
410{
411 return reg * scale_in[nr];
412}
413
414static inline u8 in_to_reg(u32 val, u8 nr)
415{
e7e1ca6e
GR		 416 return SENSORS_LIMIT(((val + (scale_in[nr] / 2)) / scale_in[nr]), 0,
417 255);
cf0676fe
RM		 418}
419
08e7e278
JD		 420/*
421 * Data structures and manipulation thereof
422 */
423
424struct w83627ehf_data {
1ea6dd38
DH		 425 int addr; /* IO base of hw monitor block */
426 const char *name;
427
1beeffe4 428 struct device *hwmon_dev;
9a61bf63 429 struct mutex lock;
08e7e278 430
ec3e5a16
GR		 431 u16 reg_temp[NUM_REG_TEMP];
432 u16 reg_temp_over[NUM_REG_TEMP];
433 u16 reg_temp_hyst[NUM_REG_TEMP];
434 u16 reg_temp_config[NUM_REG_TEMP];
d36cf32c
GR		 435 u8 temp_src[NUM_REG_TEMP];
436 const char * const *temp_label;
437
279af1a9
GR		 438 const u16 *REG_PWM;
439 const u16 *REG_TARGET;
440 const u16 *REG_FAN;
441 const u16 *REG_FAN_MIN;
442 const u16 *REG_FAN_START_OUTPUT;
443 const u16 *REG_FAN_STOP_OUTPUT;
444 const u16 *REG_FAN_STOP_TIME;
445 const u16 *REG_FAN_MAX_OUTPUT;
446 const u16 *REG_FAN_STEP_OUTPUT;
da2e0255 447
26bc440e
GR		 448 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
449 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
450
9a61bf63 451 struct mutex update_lock;
08e7e278
JD		 452 char valid; /* !=0 if following fields are valid */
453 unsigned long last_updated; /* In jiffies */
454
455 /* Register values */
83cc8985 456 u8 bank; /* current register bank */
1ea6dd38 457 u8 in_num; /* number of in inputs we have */
cf0676fe
RM		 458 u8 in[10]; /* Register value */
459 u8 in_max[10]; /* Register value */
460 u8 in_min[10]; /* Register value */
3382a918 461 unsigned int rpm[5];
ec3e5a16 462 u16 fan_min[5];
08e7e278
JD		 463 u8 fan_div[5];
464 u8 has_fan; /* some fan inputs can be disabled */
ec3e5a16 465 u8 has_fan_min; /* some fans don't have min register */
26bc440e 466 bool has_fan_div;
da667365 467 u8 temp_type[3];
ec3e5a16
GR		 468 s16 temp[9];
469 s16 temp_max[9];
470 s16 temp_max_hyst[9];
a4589dbb 471 u32 alarms;
08c79950
RM		 472
473 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
474 u8 pwm_enable[4]; /* 1->manual
41e9a062
DB		 475 2->thermal cruise mode (also called SmartFan I)
476 3->fan speed cruise mode
e7e1ca6e 477 4->variable thermal cruise (also called
b84bb518
GR		 478 SmartFan III)
479 5->enhanced variable thermal cruise (also called
480 SmartFan IV) */
481 u8 pwm_enable_orig[4]; /* original value of pwm_enable */
237c8d2f 482 u8 pwm_num; /* number of pwm */
08c79950
RM		 483 u8 pwm[4];
484 u8 target_temp[4];
485 u8 tolerance[4];
486
41e9a062
DB		 487 u8 fan_start_output[4]; /* minimum fan speed when spinning up */
488 u8 fan_stop_output[4]; /* minimum fan speed when spinning down */
489 u8 fan_stop_time[4]; /* time at minimum before disabling fan */
490 u8 fan_max_output[4]; /* maximum fan speed */
491 u8 fan_step_output[4]; /* rate of change output value */
fc18d6c0
JD		 492
493 u8 vid;
494 u8 vrm;
a157d06d 495
ec3e5a16 496 u16 have_temp;
a157d06d 497 u8 in6_skip;
08e7e278
JD		 498};
499
1ea6dd38
DH		 500struct w83627ehf_sio_data {
501 int sioreg;
502 enum kinds kind;
503};
504
83cc8985
GR		 505/*
506 * On older chips, only registers 0x50-0x5f are banked.
507 * On more recent chips, all registers are banked.
508 * Assume that is the case and set the bank number for each access.
509 * Cache the bank number so it only needs to be set if it changes.
510 */
1ea6dd38 511static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
08e7e278 512{
83cc8985
GR		 513 u8 bank = reg >> 8;
514 if (data->bank != bank) {
1ea6dd38 515 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
83cc8985
GR		 516 outb_p(bank, data->addr + DATA_REG_OFFSET);
517 data->bank = bank;
08e7e278
JD		 518 }
519}
520
1ea6dd38 521static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
08e7e278 522{
08e7e278
JD		 523 int res, word_sized = is_word_sized(reg);
524
9a61bf63 525 mutex_lock(&data->lock);
08e7e278 526
1ea6dd38
DH		 527 w83627ehf_set_bank(data, reg);
528 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
529 res = inb_p(data->addr + DATA_REG_OFFSET);
08e7e278
JD		 530 if (word_sized) {
531 outb_p((reg & 0xff) + 1,
1ea6dd38
DH		 532 data->addr + ADDR_REG_OFFSET);
533 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
08e7e278 534 }
08e7e278 535
9a61bf63 536 mutex_unlock(&data->lock);
08e7e278
JD		 537 return res;
538}
539
e7e1ca6e
GR		 540static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg,
541 u16 value)
08e7e278 542{
08e7e278
JD		 543 int word_sized = is_word_sized(reg);
544
9a61bf63 545 mutex_lock(&data->lock);
08e7e278 546
1ea6dd38
DH		 547 w83627ehf_set_bank(data, reg);
548 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
08e7e278 549 if (word_sized) {
1ea6dd38 550 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
08e7e278 551 outb_p((reg & 0xff) + 1,
1ea6dd38 552 data->addr + ADDR_REG_OFFSET);
08e7e278 553 }
1ea6dd38 554 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
08e7e278 555
9a61bf63 556 mutex_unlock(&data->lock);
08e7e278
JD		 557 return 0;
558}
559
ec3e5a16
GR		 560/* This function assumes that the caller holds data->update_lock */
561static void nct6775_write_fan_div(struct w83627ehf_data *data, int nr)
562{
563 u8 reg;
564
565 switch (nr) {
566 case 0:
567 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
568 | (data->fan_div[0] & 0x7);
569 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
570 break;
571 case 1:
572 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
573 | ((data->fan_div[1] << 4) & 0x70);
574 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
575 case 2:
576 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
577 | (data->fan_div[2] & 0x7);
578 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
579 break;
580 case 3:
581 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
582 | ((data->fan_div[3] << 4) & 0x70);
583 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
584 break;
585 }
586}
587
08e7e278 588/* This function assumes that the caller holds data->update_lock */
1ea6dd38 589static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
08e7e278 590{
08e7e278
JD		 591 u8 reg;
592
593 switch (nr) {
594 case 0:
1ea6dd38 595 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
08e7e278 596 | ((data->fan_div[0] & 0x03) << 4);
14992c7e
RM		 597 /* fan5 input control bit is write only, compute the value */
598 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 599 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
600 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
08e7e278 601 | ((data->fan_div[0] & 0x04) << 3);
1ea6dd38 602 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 603 break;
604 case 1:
1ea6dd38 605 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
08e7e278 606 | ((data->fan_div[1] & 0x03) << 6);
14992c7e
RM		 607 /* fan5 input control bit is write only, compute the value */
608 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 609 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
610 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
08e7e278 611 | ((data->fan_div[1] & 0x04) << 4);
1ea6dd38 612 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 613 break;
614 case 2:
1ea6dd38 615 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
08e7e278 616 | ((data->fan_div[2] & 0x03) << 6);
1ea6dd38
DH		 617 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
618 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
08e7e278 619 | ((data->fan_div[2] & 0x04) << 5);
1ea6dd38 620 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 621 break;
622 case 3:
1ea6dd38 623 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
08e7e278 624 | (data->fan_div[3] & 0x03);
1ea6dd38
DH		 625 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
626 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
08e7e278 627 | ((data->fan_div[3] & 0x04) << 5);
1ea6dd38 628 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
08e7e278
JD		 629 break;
630 case 4:
1ea6dd38 631 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
33725ad3 632 | ((data->fan_div[4] & 0x03) << 2)
08e7e278 633 | ((data->fan_div[4] & 0x04) << 5);
1ea6dd38 634 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
08e7e278
JD		 635 break;
636 }
637}
638
ec3e5a16
GR		 639static void w83627ehf_write_fan_div_common(struct device *dev,
640 struct w83627ehf_data *data, int nr)
641{
642 struct w83627ehf_sio_data *sio_data = dev->platform_data;
643
644 if (sio_data->kind == nct6776)
645 ; /* no dividers, do nothing */
646 else if (sio_data->kind == nct6775)
647 nct6775_write_fan_div(data, nr);
648 else
649 w83627ehf_write_fan_div(data, nr);
650}
651
652static void nct6775_update_fan_div(struct w83627ehf_data *data)
653{
654 u8 i;
655
656 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV1);
657 data->fan_div[0] = i & 0x7;
658 data->fan_div[1] = (i & 0x70) >> 4;
659 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV2);
660 data->fan_div[2] = i & 0x7;
661 if (data->has_fan & (1<<3))
662 data->fan_div[3] = (i & 0x70) >> 4;
663}
664
ea7be66c
MH		 665static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
666{
667 int i;
668
669 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
670 data->fan_div[0] = (i >> 4) & 0x03;
671 data->fan_div[1] = (i >> 6) & 0x03;
672 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
673 data->fan_div[2] = (i >> 6) & 0x03;
674 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
675 data->fan_div[0] |= (i >> 3) & 0x04;
676 data->fan_div[1] |= (i >> 4) & 0x04;
677 data->fan_div[2] |= (i >> 5) & 0x04;
678 if (data->has_fan & ((1 << 3) | (1 << 4))) {
679 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
680 data->fan_div[3] = i & 0x03;
681 data->fan_div[4] = ((i >> 2) & 0x03)
682 | ((i >> 5) & 0x04);
683 }
684 if (data->has_fan & (1 << 3)) {
685 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
686 data->fan_div[3] |= (i >> 5) & 0x04;
687 }
688}
689
ec3e5a16
GR		 690static void w83627ehf_update_fan_div_common(struct device *dev,
691 struct w83627ehf_data *data)
692{
693 struct w83627ehf_sio_data *sio_data = dev->platform_data;
694
695 if (sio_data->kind == nct6776)
696 ; /* no dividers, do nothing */
697 else if (sio_data->kind == nct6775)
698 nct6775_update_fan_div(data);
699 else
700 w83627ehf_update_fan_div(data);
701}
702
703static void nct6775_update_pwm(struct w83627ehf_data *data)
704{
705 int i;
706 int pwmcfg, fanmodecfg;
707
708 for (i = 0; i < data->pwm_num; i++) {
709 pwmcfg = w83627ehf_read_value(data,
710 W83627EHF_REG_PWM_ENABLE[i]);
711 fanmodecfg = w83627ehf_read_value(data,
712 NCT6775_REG_FAN_MODE[i]);
713 data->pwm_mode[i] =
714 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
715 data->pwm_enable[i] = ((fanmodecfg >> 4) & 7) + 1;
716 data->tolerance[i] = fanmodecfg & 0x0f;
717 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
718 }
719}
720
721static void w83627ehf_update_pwm(struct w83627ehf_data *data)
722{
723 int i;
724 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
725
726 for (i = 0; i < data->pwm_num; i++) {
727 if (!(data->has_fan & (1 << i)))
728 continue;
729
730 /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
731 if (i != 1) {
732 pwmcfg = w83627ehf_read_value(data,
733 W83627EHF_REG_PWM_ENABLE[i]);
734 tolerance = w83627ehf_read_value(data,
735 W83627EHF_REG_TOLERANCE[i]);
736 }
737 data->pwm_mode[i] =
738 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
739 data->pwm_enable[i] = ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
740 & 3) + 1;
741 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
742
743 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0)) & 0x0f;
744 }
745}
746
747static void w83627ehf_update_pwm_common(struct device *dev,
748 struct w83627ehf_data *data)
749{
750 struct w83627ehf_sio_data *sio_data = dev->platform_data;
751
752 if (sio_data->kind == nct6775 || sio_data->kind == nct6776)
753 nct6775_update_pwm(data);
754 else
755 w83627ehf_update_pwm(data);
756}
757
08e7e278
JD		 758static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
759{
1ea6dd38 760 struct w83627ehf_data *data = dev_get_drvdata(dev);
ec3e5a16
GR		 761 struct w83627ehf_sio_data *sio_data = dev->platform_data;
762
08e7e278
JD		 763 int i;
764
9a61bf63 765 mutex_lock(&data->update_lock);
08e7e278 766
6b3e4645 767 if (time_after(jiffies, data->last_updated + HZ + HZ/2)
08e7e278
JD		 768 || !data->valid) {
769 /* Fan clock dividers */
ec3e5a16 770 w83627ehf_update_fan_div_common(dev, data);
08e7e278 771
cf0676fe 772 /* Measured voltages and limits */
1ea6dd38
DH		 773 for (i = 0; i < data->in_num; i++) {
774 data->in[i] = w83627ehf_read_value(data,
cf0676fe 775 W83627EHF_REG_IN(i));
1ea6dd38 776 data->in_min[i] = w83627ehf_read_value(data,
cf0676fe 777 W83627EHF_REG_IN_MIN(i));
1ea6dd38 778 data->in_max[i] = w83627ehf_read_value(data,
cf0676fe
RM		 779 W83627EHF_REG_IN_MAX(i));
780 }
781
08e7e278
JD		 782 /* Measured fan speeds and limits */
783 for (i = 0; i < 5; i++) {
3382a918
GR		 784 u16 reg;
785
08e7e278
JD		 786 if (!(data->has_fan & (1 << i)))
787 continue;
788
3382a918
GR		 789 reg = w83627ehf_read_value(data, data->REG_FAN[i]);
790 data->rpm[i] = data->fan_from_reg(reg,
791 data->fan_div[i]);
ec3e5a16
GR		 792
793 if (data->has_fan_min & (1 << i))
794 data->fan_min[i] = w83627ehf_read_value(data,
279af1a9 795 data->REG_FAN_MIN[i]);
08e7e278
JD		 796
797 /* If we failed to measure the fan speed and clock
798 divider can be increased, let's try that for next
799 time */
26bc440e 800 if (data->has_fan_div
3382a918
GR		 801 && (reg >= 0xff || (sio_data->kind == nct6775
802 && reg == 0x00))
ec3e5a16 803 && data->fan_div[i] < 0x07) {
e7e1ca6e 804 dev_dbg(dev, "Increasing fan%d "
08e7e278 805 "clock divider from %u to %u\n",
33725ad3 806 i + 1, div_from_reg(data->fan_div[i]),
08e7e278
JD		 807 div_from_reg(data->fan_div[i] + 1));
808 data->fan_div[i]++;
ec3e5a16 809 w83627ehf_write_fan_div_common(dev, data, i);
08e7e278 810 /* Preserve min limit if possible */
ec3e5a16
GR		 811 if ((data->has_fan_min & (1 << i))
812 && data->fan_min[i] >= 2
08e7e278 813 && data->fan_min[i] != 255)
1ea6dd38 814 w83627ehf_write_value(data,
279af1a9 815 data->REG_FAN_MIN[i],
08e7e278
JD		 816 (data->fan_min[i] /= 2));
817 }
818 }
819
ec3e5a16
GR		 820 w83627ehf_update_pwm_common(dev, data);
821
da2e0255
GR		 822 for (i = 0; i < data->pwm_num; i++) {
823 if (!(data->has_fan & (1 << i)))
824 continue;
825
ec3e5a16
GR		 826 data->fan_start_output[i] =
827 w83627ehf_read_value(data,
828 data->REG_FAN_START_OUTPUT[i]);
829 data->fan_stop_output[i] =
830 w83627ehf_read_value(data,
831 data->REG_FAN_STOP_OUTPUT[i]);
832 data->fan_stop_time[i] =
833 w83627ehf_read_value(data,
834 data->REG_FAN_STOP_TIME[i]);
835
836 if (data->REG_FAN_MAX_OUTPUT &&
837 data->REG_FAN_MAX_OUTPUT[i] != 0xff)
da2e0255
GR		 838 data->fan_max_output[i] =
839 w83627ehf_read_value(data,
ec3e5a16 840 data->REG_FAN_MAX_OUTPUT[i]);
da2e0255 841
ec3e5a16
GR		 842 if (data->REG_FAN_STEP_OUTPUT &&
843 data->REG_FAN_STEP_OUTPUT[i] != 0xff)
da2e0255
GR		 844 data->fan_step_output[i] =
845 w83627ehf_read_value(data,
ec3e5a16 846 data->REG_FAN_STEP_OUTPUT[i]);
da2e0255 847
08c79950 848 data->target_temp[i] =
1ea6dd38 849 w83627ehf_read_value(data,
279af1a9 850 data->REG_TARGET[i]) &
08c79950 851 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
08c79950
RM		 852 }
853
08e7e278 854 /* Measured temperatures and limits */
d36cf32c
GR		 855 for (i = 0; i < NUM_REG_TEMP; i++) {
856 if (!(data->have_temp & (1 << i)))
857 continue;
ec3e5a16
GR		 858 data->temp[i] = w83627ehf_read_value(data,
859 data->reg_temp[i]);
860 if (data->reg_temp_over[i])
861 data->temp_max[i]
862 = w83627ehf_read_value(data,
863 data->reg_temp_over[i]);
864 if (data->reg_temp_hyst[i])
865 data->temp_max_hyst[i]
866 = w83627ehf_read_value(data,
867 data->reg_temp_hyst[i]);
08e7e278
JD		 868 }
869
1ea6dd38 870 data->alarms = w83627ehf_read_value(data,
a4589dbb 871 W83627EHF_REG_ALARM1) |
1ea6dd38 872 (w83627ehf_read_value(data,
a4589dbb 873 W83627EHF_REG_ALARM2) << 8) |
1ea6dd38 874 (w83627ehf_read_value(data,
a4589dbb
JD		 875 W83627EHF_REG_ALARM3) << 16);
876
08e7e278
JD		 877 data->last_updated = jiffies;
878 data->valid = 1;
879 }
880
9a61bf63 881 mutex_unlock(&data->update_lock);
08e7e278
JD		 882 return data;
883}
884
885/*
886 * Sysfs callback functions
887 */
cf0676fe
RM		 888#define show_in_reg(reg) \
889static ssize_t \
890show_##reg(struct device *dev, struct device_attribute *attr, \
891 char *buf) \
892{ \
893 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 894 struct sensor_device_attribute *sensor_attr = \
895 to_sensor_dev_attr(attr); \
cf0676fe
RM		 896 int nr = sensor_attr->index; \
897 return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr)); \
898}
899show_in_reg(in)
900show_in_reg(in_min)
901show_in_reg(in_max)
902
903#define store_in_reg(REG, reg) \
904static ssize_t \
e7e1ca6e
GR		 905store_in_##reg(struct device *dev, struct device_attribute *attr, \
906 const char *buf, size_t count) \
cf0676fe 907{ \
1ea6dd38 908 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 909 struct sensor_device_attribute *sensor_attr = \
910 to_sensor_dev_attr(attr); \
cf0676fe 911 int nr = sensor_attr->index; \
bce26c58
GR		 912 unsigned long val; \
913 int err; \
914 err = strict_strtoul(buf, 10, &val); \
915 if (err < 0) \
916 return err; \
cf0676fe
RM		 917 mutex_lock(&data->update_lock); \
918 data->in_##reg[nr] = in_to_reg(val, nr); \
1ea6dd38 919 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \
cf0676fe
RM		 920 data->in_##reg[nr]); \
921 mutex_unlock(&data->update_lock); \
922 return count; \
923}
924
925store_in_reg(MIN, min)
926store_in_reg(MAX, max)
927
e7e1ca6e
GR		 928static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
929 char *buf)
a4589dbb
JD		 930{
931 struct w83627ehf_data *data = w83627ehf_update_device(dev);
932 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
933 int nr = sensor_attr->index;
934 return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01);
935}
936
cf0676fe
RM		 937static struct sensor_device_attribute sda_in_input[] = {
938 SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
939 SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
940 SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
941 SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
942 SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
943 SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
944 SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
945 SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
946 SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
947 SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9),
948};
949
a4589dbb
JD		 950static struct sensor_device_attribute sda_in_alarm[] = {
951 SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0),
952 SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1),
953 SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2),
954 SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3),
955 SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8),
956 SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21),
957 SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20),
958 SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16),
959 SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17),
960 SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19),
961};
962
cf0676fe 963static struct sensor_device_attribute sda_in_min[] = {
e7e1ca6e
GR		 964 SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0),
965 SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1),
966 SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2),
967 SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3),
968 SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4),
969 SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5),
970 SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6),
971 SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7),
972 SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8),
973 SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9),
cf0676fe
RM		 974};
975
976static struct sensor_device_attribute sda_in_max[] = {
e7e1ca6e
GR		 977 SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0),
978 SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1),
979 SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2),
980 SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3),
981 SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4),
982 SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5),
983 SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6),
984 SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7),
985 SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8),
986 SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9),
cf0676fe
RM		 987};
988
ec3e5a16
GR		 989static ssize_t
990show_fan(struct device *dev, struct device_attribute *attr, char *buf)
991{
992 struct w83627ehf_data *data = w83627ehf_update_device(dev);
993 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
994 int nr = sensor_attr->index;
3382a918 995 return sprintf(buf, "%d\n", data->rpm[nr]);
ec3e5a16
GR		 996}
997
998static ssize_t
999show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
1000{
1001 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1002 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1003 int nr = sensor_attr->index;
1004 return sprintf(buf, "%d\n",
26bc440e
GR		 1005 data->fan_from_reg_min(data->fan_min[nr],
1006 data->fan_div[nr]));
08e7e278 1007}
08e7e278
JD		 1008
1009static ssize_t
412fec82
YM		 1010show_fan_div(struct device *dev, struct device_attribute *attr,
1011 char *buf)
08e7e278
JD		 1012{
1013 struct w83627ehf_data *data = w83627ehf_update_device(dev);
412fec82
YM		 1014 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1015 int nr = sensor_attr->index;
1016 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
08e7e278
JD		 1017}
1018
1019static ssize_t
412fec82
YM		 1020store_fan_min(struct device *dev, struct device_attribute *attr,
1021 const char *buf, size_t count)
08e7e278 1022{
1ea6dd38 1023 struct w83627ehf_data *data = dev_get_drvdata(dev);
412fec82
YM		 1024 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1025 int nr = sensor_attr->index;
bce26c58
GR		 1026 unsigned long val;
1027 int err;
08e7e278
JD		 1028 unsigned int reg;
1029 u8 new_div;
1030
bce26c58
GR		 1031 err = strict_strtoul(buf, 10, &val);
1032 if (err < 0)
1033 return err;
1034
9a61bf63 1035 mutex_lock(&data->update_lock);
26bc440e
GR		 1036 if (!data->has_fan_div) {
1037 /*
1038 * Only NCT6776F for now, so we know that this is a 13 bit
1039 * register
1040 */
ec3e5a16
GR		 1041 if (!val) {
1042 val = 0xff1f;
1043 } else {
1044 if (val > 1350000U)
1045 val = 135000U;
1046 val = 1350000U / val;
1047 val = (val & 0x1f) | ((val << 3) & 0xff00);
1048 }
1049 data->fan_min[nr] = val;
1050 goto done; /* Leave fan divider alone */
1051 }
08e7e278
JD		 1052 if (!val) {
1053 /* No min limit, alarm disabled */
1054 data->fan_min[nr] = 255;
1055 new_div = data->fan_div[nr]; /* No change */
1056 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
1057 } else if ((reg = 1350000U / val) >= 128 * 255) {
1058 /* Speed below this value cannot possibly be represented,
1059 even with the highest divider (128) */
1060 data->fan_min[nr] = 254;
1061 new_div = 7; /* 128 == (1 << 7) */
bce26c58 1062 dev_warn(dev, "fan%u low limit %lu below minimum %u, set to "
ec3e5a16 1063 "minimum\n", nr + 1, val,
26bc440e 1064 data->fan_from_reg_min(254, 7));
08e7e278
JD		 1065 } else if (!reg) {
1066 /* Speed above this value cannot possibly be represented,
1067 even with the lowest divider (1) */
1068 data->fan_min[nr] = 1;
1069 new_div = 0; /* 1 == (1 << 0) */
bce26c58 1070 dev_warn(dev, "fan%u low limit %lu above maximum %u, set to "
ec3e5a16 1071 "maximum\n", nr + 1, val,
26bc440e 1072 data->fan_from_reg_min(1, 0));
08e7e278
JD		 1073 } else {
1074 /* Automatically pick the best divider, i.e. the one such
1075 that the min limit will correspond to a register value
1076 in the 96..192 range */
1077 new_div = 0;
1078 while (reg > 192 && new_div < 7) {
1079 reg >>= 1;
1080 new_div++;
1081 }
1082 data->fan_min[nr] = reg;
1083 }
1084
1085 /* Write both the fan clock divider (if it changed) and the new
1086 fan min (unconditionally) */
1087 if (new_div != data->fan_div[nr]) {
08e7e278
JD		 1088 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
1089 nr + 1, div_from_reg(data->fan_div[nr]),
1090 div_from_reg(new_div));
1091 data->fan_div[nr] = new_div;
ec3e5a16 1092 w83627ehf_write_fan_div_common(dev, data, nr);
6b3e4645
JD		 1093 /* Give the chip time to sample a new speed value */
1094 data->last_updated = jiffies;
08e7e278 1095 }
ec3e5a16 1096done:
279af1a9 1097 w83627ehf_write_value(data, data->REG_FAN_MIN[nr],
08e7e278 1098 data->fan_min[nr]);
9a61bf63 1099 mutex_unlock(&data->update_lock);
08e7e278
JD		 1100
1101 return count;
1102}
1103
412fec82
YM		 1104static struct sensor_device_attribute sda_fan_input[] = {
1105 SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
1106 SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
1107 SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
1108 SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
1109 SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4),
1110};
08e7e278 1111
a4589dbb
JD		 1112static struct sensor_device_attribute sda_fan_alarm[] = {
1113 SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6),
1114 SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7),
1115 SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11),
1116 SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10),
1117 SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23),
1118};
1119
412fec82
YM		 1120static struct sensor_device_attribute sda_fan_min[] = {
1121 SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min,
1122 store_fan_min, 0),
1123 SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min,
1124 store_fan_min, 1),
1125 SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min,
1126 store_fan_min, 2),
1127 SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min,
1128 store_fan_min, 3),
1129 SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min,
1130 store_fan_min, 4),
1131};
08e7e278 1132
412fec82
YM		 1133static struct sensor_device_attribute sda_fan_div[] = {
1134 SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0),
1135 SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1),
1136 SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2),
1137 SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3),
1138 SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4),
1139};
1140
d36cf32c
GR		 1141static ssize_t
1142show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
1143{
1144 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1145 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1146 int nr = sensor_attr->index;
1147 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
1148}
1149
ec3e5a16 1150#define show_temp_reg(addr, reg) \
08e7e278 1151static ssize_t \
412fec82
YM		 1152show_##reg(struct device *dev, struct device_attribute *attr, \
1153 char *buf) \
08e7e278
JD		 1154{ \
1155 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1156 struct sensor_device_attribute *sensor_attr = \
1157 to_sensor_dev_attr(attr); \
412fec82 1158 int nr = sensor_attr->index; \
08e7e278 1159 return sprintf(buf, "%d\n", \
ec3e5a16 1160 temp_from_reg(data->addr[nr], data->reg[nr])); \
08e7e278 1161}
ec3e5a16
GR		 1162show_temp_reg(reg_temp, temp);
1163show_temp_reg(reg_temp_over, temp_max);
1164show_temp_reg(reg_temp_hyst, temp_max_hyst);
08e7e278 1165
ec3e5a16 1166#define store_temp_reg(addr, reg) \
08e7e278 1167static ssize_t \
412fec82
YM		 1168store_##reg(struct device *dev, struct device_attribute *attr, \
1169 const char *buf, size_t count) \
08e7e278 1170{ \
1ea6dd38 1171 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1172 struct sensor_device_attribute *sensor_attr = \
1173 to_sensor_dev_attr(attr); \
412fec82 1174 int nr = sensor_attr->index; \
bce26c58
GR		 1175 int err; \
1176 long val; \
1177 err = strict_strtol(buf, 10, &val); \
1178 if (err < 0) \
1179 return err; \
9a61bf63 1180 mutex_lock(&data->update_lock); \
ec3e5a16
GR		 1181 data->reg[nr] = temp_to_reg(data->addr[nr], val); \
1182 w83627ehf_write_value(data, data->addr[nr], \
08e7e278 1183 data->reg[nr]); \
9a61bf63 1184 mutex_unlock(&data->update_lock); \
08e7e278
JD		 1185 return count; \
1186}
ec3e5a16
GR		 1187store_temp_reg(reg_temp_over, temp_max);
1188store_temp_reg(reg_temp_hyst, temp_max_hyst);
08e7e278 1189
da667365
JD		 1190static ssize_t
1191show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
1192{
1193 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1194 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1195 int nr = sensor_attr->index;
1196 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
1197}
1198
a157d06d 1199static struct sensor_device_attribute sda_temp_input[] = {
bce26c58
GR		 1200 SENSOR_ATTR(temp1_input, S_IRUGO, show_temp, NULL, 0),
1201 SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 1),
1202 SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 2),
d36cf32c 1203 SENSOR_ATTR(temp4_input, S_IRUGO, show_temp, NULL, 3),
ec3e5a16
GR		 1204 SENSOR_ATTR(temp5_input, S_IRUGO, show_temp, NULL, 4),
1205 SENSOR_ATTR(temp6_input, S_IRUGO, show_temp, NULL, 5),
1206 SENSOR_ATTR(temp7_input, S_IRUGO, show_temp, NULL, 6),
1207 SENSOR_ATTR(temp8_input, S_IRUGO, show_temp, NULL, 7),
1208 SENSOR_ATTR(temp9_input, S_IRUGO, show_temp, NULL, 8),
d36cf32c
GR		 1209};
1210
1211static struct sensor_device_attribute sda_temp_label[] = {
1212 SENSOR_ATTR(temp1_label, S_IRUGO, show_temp_label, NULL, 0),
1213 SENSOR_ATTR(temp2_label, S_IRUGO, show_temp_label, NULL, 1),
1214 SENSOR_ATTR(temp3_label, S_IRUGO, show_temp_label, NULL, 2),
1215 SENSOR_ATTR(temp4_label, S_IRUGO, show_temp_label, NULL, 3),
ec3e5a16
GR		 1216 SENSOR_ATTR(temp5_label, S_IRUGO, show_temp_label, NULL, 4),
1217 SENSOR_ATTR(temp6_label, S_IRUGO, show_temp_label, NULL, 5),
1218 SENSOR_ATTR(temp7_label, S_IRUGO, show_temp_label, NULL, 6),
1219 SENSOR_ATTR(temp8_label, S_IRUGO, show_temp_label, NULL, 7),
1220 SENSOR_ATTR(temp9_label, S_IRUGO, show_temp_label, NULL, 8),
a157d06d
GJ		 1221};
1222
1223static struct sensor_device_attribute sda_temp_max[] = {
bce26c58 1224 SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp_max,
412fec82 1225 store_temp_max, 0),
bce26c58 1226 SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max,
412fec82 1227 store_temp_max, 1),
bce26c58
GR		 1228 SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max,
1229 store_temp_max, 2),
ec3e5a16
GR		 1230 SENSOR_ATTR(temp4_max, S_IRUGO | S_IWUSR, show_temp_max,
1231 store_temp_max, 3),
1232 SENSOR_ATTR(temp5_max, S_IRUGO | S_IWUSR, show_temp_max,
1233 store_temp_max, 4),
1234 SENSOR_ATTR(temp6_max, S_IRUGO | S_IWUSR, show_temp_max,
1235 store_temp_max, 5),
1236 SENSOR_ATTR(temp7_max, S_IRUGO | S_IWUSR, show_temp_max,
1237 store_temp_max, 6),
1238 SENSOR_ATTR(temp8_max, S_IRUGO | S_IWUSR, show_temp_max,
1239 store_temp_max, 7),
1240 SENSOR_ATTR(temp9_max, S_IRUGO | S_IWUSR, show_temp_max,
1241 store_temp_max, 8),
a157d06d
GJ		 1242};
1243
1244static struct sensor_device_attribute sda_temp_max_hyst[] = {
bce26c58 1245 SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
412fec82 1246 store_temp_max_hyst, 0),
bce26c58 1247 SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
412fec82 1248 store_temp_max_hyst, 1),
bce26c58
GR		 1249 SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1250 store_temp_max_hyst, 2),
ec3e5a16
GR		 1251 SENSOR_ATTR(temp4_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1252 store_temp_max_hyst, 3),
1253 SENSOR_ATTR(temp5_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1254 store_temp_max_hyst, 4),
1255 SENSOR_ATTR(temp6_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1256 store_temp_max_hyst, 5),
1257 SENSOR_ATTR(temp7_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1258 store_temp_max_hyst, 6),
1259 SENSOR_ATTR(temp8_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1260 store_temp_max_hyst, 7),
1261 SENSOR_ATTR(temp9_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1262 store_temp_max_hyst, 8),
a157d06d
GJ		 1263};
1264
1265static struct sensor_device_attribute sda_temp_alarm[] = {
a4589dbb
JD		 1266 SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
1267 SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
1268 SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
a157d06d
GJ		 1269};
1270
1271static struct sensor_device_attribute sda_temp_type[] = {
da667365
JD		 1272 SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0),
1273 SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1),
1274 SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2),
412fec82 1275};
08e7e278 1276
08c79950 1277#define show_pwm_reg(reg) \
e7e1ca6e
GR		 1278static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1279 char *buf) \
08c79950
RM		 1280{ \
1281 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1282 struct sensor_device_attribute *sensor_attr = \
1283 to_sensor_dev_attr(attr); \
08c79950
RM		 1284 int nr = sensor_attr->index; \
1285 return sprintf(buf, "%d\n", data->reg[nr]); \
1286}
1287
1288show_pwm_reg(pwm_mode)
1289show_pwm_reg(pwm_enable)
1290show_pwm_reg(pwm)
1291
1292static ssize_t
1293store_pwm_mode(struct device *dev, struct device_attribute *attr,
1294 const char *buf, size_t count)
1295{
1ea6dd38 1296 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1297 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1298 int nr = sensor_attr->index;
bce26c58
GR		 1299 unsigned long val;
1300 int err;
08c79950
RM		 1301 u16 reg;
1302
bce26c58
GR		 1303 err = strict_strtoul(buf, 10, &val);
1304 if (err < 0)
1305 return err;
1306
08c79950
RM		 1307 if (val > 1)
1308 return -EINVAL;
1309 mutex_lock(&data->update_lock);
1ea6dd38 1310 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 1311 data->pwm_mode[nr] = val;
1312 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]);
1313 if (!val)
1314 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr];
1ea6dd38 1315 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 1316 mutex_unlock(&data->update_lock);
1317 return count;
1318}
1319
1320static ssize_t
1321store_pwm(struct device *dev, struct device_attribute *attr,
1322 const char *buf, size_t count)
1323{
1ea6dd38 1324 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1325 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1326 int nr = sensor_attr->index;
bce26c58
GR		 1327 unsigned long val;
1328 int err;
1329
1330 err = strict_strtoul(buf, 10, &val);
1331 if (err < 0)
1332 return err;
1333
1334 val = SENSORS_LIMIT(val, 0, 255);
08c79950
RM		 1335
1336 mutex_lock(&data->update_lock);
1337 data->pwm[nr] = val;
279af1a9 1338 w83627ehf_write_value(data, data->REG_PWM[nr], val);
08c79950
RM		 1339 mutex_unlock(&data->update_lock);
1340 return count;
1341}
1342
1343static ssize_t
1344store_pwm_enable(struct device *dev, struct device_attribute *attr,
1345 const char *buf, size_t count)
1346{
1ea6dd38 1347 struct w83627ehf_data *data = dev_get_drvdata(dev);
ec3e5a16 1348 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08c79950
RM		 1349 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1350 int nr = sensor_attr->index;
bce26c58
GR		 1351 unsigned long val;
1352 int err;
08c79950
RM		 1353 u16 reg;
1354
bce26c58
GR		 1355 err = strict_strtoul(buf, 10, &val);
1356 if (err < 0)
1357 return err;
1358
b84bb518 1359 if (!val || (val > 4 && val != data->pwm_enable_orig[nr]))
08c79950 1360 return -EINVAL;
ec3e5a16
GR		 1361 /* SmartFan III mode is not supported on NCT6776F */
1362 if (sio_data->kind == nct6776 && val == 4)
1363 return -EINVAL;
1364
08c79950 1365 mutex_lock(&data->update_lock);
08c79950 1366 data->pwm_enable[nr] = val;
ec3e5a16
GR		 1367 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1368 reg = w83627ehf_read_value(data,
1369 NCT6775_REG_FAN_MODE[nr]);
1370 reg &= 0x0f;
1371 reg |= (val - 1) << 4;
1372 w83627ehf_write_value(data,
1373 NCT6775_REG_FAN_MODE[nr], reg);
1374 } else {
1375 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
1376 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]);
1377 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr];
1378 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
1379 }
08c79950
RM		 1380 mutex_unlock(&data->update_lock);
1381 return count;
1382}
1383
1384
1385#define show_tol_temp(reg) \
1386static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1387 char *buf) \
1388{ \
1389 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1390 struct sensor_device_attribute *sensor_attr = \
1391 to_sensor_dev_attr(attr); \
08c79950 1392 int nr = sensor_attr->index; \
bce26c58 1393 return sprintf(buf, "%d\n", data->reg[nr] * 1000); \
08c79950
RM		 1394}
1395
1396show_tol_temp(tolerance)
1397show_tol_temp(target_temp)
1398
1399static ssize_t
1400store_target_temp(struct device *dev, struct device_attribute *attr,
1401 const char *buf, size_t count)
1402{
1ea6dd38 1403 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1404 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1405 int nr = sensor_attr->index;
bce26c58
GR		 1406 long val;
1407 int err;
1408
1409 err = strict_strtol(buf, 10, &val);
1410 if (err < 0)
1411 return err;
1412
1413 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 127);
08c79950
RM		 1414
1415 mutex_lock(&data->update_lock);
1416 data->target_temp[nr] = val;
279af1a9 1417 w83627ehf_write_value(data, data->REG_TARGET[nr], val);
08c79950
RM		 1418 mutex_unlock(&data->update_lock);
1419 return count;
1420}
1421
1422static ssize_t
1423store_tolerance(struct device *dev, struct device_attribute *attr,
1424 const char *buf, size_t count)
1425{
1ea6dd38 1426 struct w83627ehf_data *data = dev_get_drvdata(dev);
ec3e5a16 1427 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08c79950
RM		 1428 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1429 int nr = sensor_attr->index;
1430 u16 reg;
bce26c58
GR		 1431 long val;
1432 int err;
1433
1434 err = strict_strtol(buf, 10, &val);
1435 if (err < 0)
1436 return err;
1437
08c79950 1438 /* Limit the temp to 0C - 15C */
bce26c58 1439 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 15);
08c79950
RM		 1440
1441 mutex_lock(&data->update_lock);
ec3e5a16
GR		 1442 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1443 /* Limit tolerance further for NCT6776F */
1444 if (sio_data->kind == nct6776 && val > 7)
1445 val = 7;
1446 reg = w83627ehf_read_value(data, NCT6775_REG_FAN_MODE[nr]);
08c79950 1447 reg = (reg & 0xf0) | val;
ec3e5a16
GR		 1448 w83627ehf_write_value(data, NCT6775_REG_FAN_MODE[nr], reg);
1449 } else {
1450 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
1451 if (nr == 1)
1452 reg = (reg & 0x0f) | (val << 4);
1453 else
1454 reg = (reg & 0xf0) | val;
1455 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
1456 }
1457 data->tolerance[nr] = val;
08c79950
RM		 1458 mutex_unlock(&data->update_lock);
1459 return count;
1460}
1461
1462static struct sensor_device_attribute sda_pwm[] = {
1463 SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0),
1464 SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1),
1465 SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2),
1466 SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3),
1467};
1468
1469static struct sensor_device_attribute sda_pwm_mode[] = {
1470 SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1471 store_pwm_mode, 0),
1472 SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1473 store_pwm_mode, 1),
1474 SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1475 store_pwm_mode, 2),
1476 SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1477 store_pwm_mode, 3),
1478};
1479
1480static struct sensor_device_attribute sda_pwm_enable[] = {
1481 SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1482 store_pwm_enable, 0),
1483 SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1484 store_pwm_enable, 1),
1485 SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1486 store_pwm_enable, 2),
1487 SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1488 store_pwm_enable, 3),
1489};
1490
1491static struct sensor_device_attribute sda_target_temp[] = {
1492 SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp,
1493 store_target_temp, 0),
1494 SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp,
1495 store_target_temp, 1),
1496 SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp,
1497 store_target_temp, 2),
1498 SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp,
1499 store_target_temp, 3),
1500};
1501
1502static struct sensor_device_attribute sda_tolerance[] = {
1503 SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1504 store_tolerance, 0),
1505 SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1506 store_tolerance, 1),
1507 SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1508 store_tolerance, 2),
1509 SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1510 store_tolerance, 3),
1511};
1512
08c79950
RM		 1513/* Smart Fan registers */
1514
1515#define fan_functions(reg, REG) \
1516static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1517 char *buf) \
1518{ \
1519 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1520 struct sensor_device_attribute *sensor_attr = \
1521 to_sensor_dev_attr(attr); \
08c79950
RM		 1522 int nr = sensor_attr->index; \
1523 return sprintf(buf, "%d\n", data->reg[nr]); \
e7e1ca6e 1524} \
08c79950
RM		 1525static ssize_t \
1526store_##reg(struct device *dev, struct device_attribute *attr, \
1527 const char *buf, size_t count) \
e7e1ca6e 1528{ \
1ea6dd38 1529 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1530 struct sensor_device_attribute *sensor_attr = \
1531 to_sensor_dev_attr(attr); \
08c79950 1532 int nr = sensor_attr->index; \
bce26c58
GR		 1533 unsigned long val; \
1534 int err; \
1535 err = strict_strtoul(buf, 10, &val); \
1536 if (err < 0) \
1537 return err; \
1538 val = SENSORS_LIMIT(val, 1, 255); \
08c79950
RM		 1539 mutex_lock(&data->update_lock); \
1540 data->reg[nr] = val; \
da2e0255 1541 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
08c79950
RM		 1542 mutex_unlock(&data->update_lock); \
1543 return count; \
1544}
1545
41e9a062
DB		 1546fan_functions(fan_start_output, FAN_START_OUTPUT)
1547fan_functions(fan_stop_output, FAN_STOP_OUTPUT)
1548fan_functions(fan_max_output, FAN_MAX_OUTPUT)
1549fan_functions(fan_step_output, FAN_STEP_OUTPUT)
08c79950
RM		 1550
1551#define fan_time_functions(reg, REG) \
1552static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1553 char *buf) \
1554{ \
1555 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1556 struct sensor_device_attribute *sensor_attr = \
1557 to_sensor_dev_attr(attr); \
08c79950
RM		 1558 int nr = sensor_attr->index; \
1559 return sprintf(buf, "%d\n", \
e7e1ca6e
GR		 1560 step_time_from_reg(data->reg[nr], \
1561 data->pwm_mode[nr])); \
08c79950
RM		 1562} \
1563\
1564static ssize_t \
1565store_##reg(struct device *dev, struct device_attribute *attr, \
1566 const char *buf, size_t count) \
1567{ \
1ea6dd38 1568 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1569 struct sensor_device_attribute *sensor_attr = \
1570 to_sensor_dev_attr(attr); \
08c79950 1571 int nr = sensor_attr->index; \
bce26c58
GR		 1572 unsigned long val; \
1573 int err; \
1574 err = strict_strtoul(buf, 10, &val); \
1575 if (err < 0) \
1576 return err; \
1577 val = step_time_to_reg(val, data->pwm_mode[nr]); \
08c79950
RM		 1578 mutex_lock(&data->update_lock); \
1579 data->reg[nr] = val; \
1ea6dd38 1580 w83627ehf_write_value(data, W83627EHF_REG_##REG[nr], val); \
08c79950
RM		 1581 mutex_unlock(&data->update_lock); \
1582 return count; \
1583} \
1584
1585fan_time_functions(fan_stop_time, FAN_STOP_TIME)
1586
1ea6dd38
DH		 1587static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1588 char *buf)
1589{
1590 struct w83627ehf_data *data = dev_get_drvdata(dev);
1591
1592 return sprintf(buf, "%s\n", data->name);
1593}
1594static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
08c79950
RM		 1595
1596static struct sensor_device_attribute sda_sf3_arrays_fan4[] = {
1597 SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1598 store_fan_stop_time, 3),
41e9a062
DB		 1599 SENSOR_ATTR(pwm4_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1600 store_fan_start_output, 3),
1601 SENSOR_ATTR(pwm4_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1602 store_fan_stop_output, 3),
1603 SENSOR_ATTR(pwm4_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1604 store_fan_max_output, 3),
1605 SENSOR_ATTR(pwm4_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1606 store_fan_step_output, 3),
08c79950
RM		 1607};
1608
1609static struct sensor_device_attribute sda_sf3_arrays[] = {
1610 SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1611 store_fan_stop_time, 0),
1612 SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1613 store_fan_stop_time, 1),
1614 SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1615 store_fan_stop_time, 2),
41e9a062
DB		 1616 SENSOR_ATTR(pwm1_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1617 store_fan_start_output, 0),
1618 SENSOR_ATTR(pwm2_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1619 store_fan_start_output, 1),
1620 SENSOR_ATTR(pwm3_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1621 store_fan_start_output, 2),
1622 SENSOR_ATTR(pwm1_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1623 store_fan_stop_output, 0),
1624 SENSOR_ATTR(pwm2_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1625 store_fan_stop_output, 1),
1626 SENSOR_ATTR(pwm3_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1627 store_fan_stop_output, 2),
da2e0255 1628};
41e9a062 1629
da2e0255
GR		 1630
1631/*
1632 * pwm1 and pwm3 don't support max and step settings on all chips.
1633 * Need to check support while generating/removing attribute files.
1634 */
1635static struct sensor_device_attribute sda_sf3_max_step_arrays[] = {
1636 SENSOR_ATTR(pwm1_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1637 store_fan_max_output, 0),
1638 SENSOR_ATTR(pwm1_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1639 store_fan_step_output, 0),
41e9a062
DB		 1640 SENSOR_ATTR(pwm2_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1641 store_fan_max_output, 1),
1642 SENSOR_ATTR(pwm2_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1643 store_fan_step_output, 1),
da2e0255
GR		 1644 SENSOR_ATTR(pwm3_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1645 store_fan_max_output, 2),
1646 SENSOR_ATTR(pwm3_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1647 store_fan_step_output, 2),
08c79950
RM		 1648};
1649
fc18d6c0
JD		 1650static ssize_t
1651show_vid(struct device *dev, struct device_attribute *attr, char *buf)
1652{
1653 struct w83627ehf_data *data = dev_get_drvdata(dev);
1654 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1655}
1656static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1657
08e7e278 1658/*
1ea6dd38 1659 * Driver and device management
08e7e278
JD		 1660 */
1661
c18beb5b
DH		 1662static void w83627ehf_device_remove_files(struct device *dev)
1663{
1664 /* some entries in the following arrays may not have been used in
1665 * device_create_file(), but device_remove_file() will ignore them */
1666 int i;
1ea6dd38 1667 struct w83627ehf_data *data = dev_get_drvdata(dev);
c18beb5b
DH		 1668
1669 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
1670 device_remove_file(dev, &sda_sf3_arrays[i].dev_attr);
da2e0255
GR		 1671 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
1672 struct sensor_device_attribute *attr =
1673 &sda_sf3_max_step_arrays[i];
ec3e5a16
GR		 1674 if (data->REG_FAN_STEP_OUTPUT &&
1675 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff)
da2e0255
GR		 1676 device_remove_file(dev, &attr->dev_attr);
1677 }
c18beb5b
DH		 1678 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++)
1679 device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr);
1ea6dd38 1680 for (i = 0; i < data->in_num; i++) {
a157d06d
GJ		 1681 if ((i == 6) && data->in6_skip)
1682 continue;
c18beb5b
DH		 1683 device_remove_file(dev, &sda_in_input[i].dev_attr);
1684 device_remove_file(dev, &sda_in_alarm[i].dev_attr);
1685 device_remove_file(dev, &sda_in_min[i].dev_attr);
1686 device_remove_file(dev, &sda_in_max[i].dev_attr);
1687 }
1688 for (i = 0; i < 5; i++) {
1689 device_remove_file(dev, &sda_fan_input[i].dev_attr);
1690 device_remove_file(dev, &sda_fan_alarm[i].dev_attr);
1691 device_remove_file(dev, &sda_fan_div[i].dev_attr);
1692 device_remove_file(dev, &sda_fan_min[i].dev_attr);
1693 }
237c8d2f 1694 for (i = 0; i < data->pwm_num; i++) {
c18beb5b
DH		 1695 device_remove_file(dev, &sda_pwm[i].dev_attr);
1696 device_remove_file(dev, &sda_pwm_mode[i].dev_attr);
1697 device_remove_file(dev, &sda_pwm_enable[i].dev_attr);
1698 device_remove_file(dev, &sda_target_temp[i].dev_attr);
1699 device_remove_file(dev, &sda_tolerance[i].dev_attr);
1700 }
d36cf32c
GR		 1701 for (i = 0; i < NUM_REG_TEMP; i++) {
1702 if (!(data->have_temp & (1 << i)))
a157d06d
GJ		 1703 continue;
1704 device_remove_file(dev, &sda_temp_input[i].dev_attr);
d36cf32c 1705 device_remove_file(dev, &sda_temp_label[i].dev_attr);
a157d06d
GJ		 1706 device_remove_file(dev, &sda_temp_max[i].dev_attr);
1707 device_remove_file(dev, &sda_temp_max_hyst[i].dev_attr);
ec3e5a16
GR		 1708 if (i > 2)
1709 continue;
a157d06d
GJ		 1710 device_remove_file(dev, &sda_temp_alarm[i].dev_attr);
1711 device_remove_file(dev, &sda_temp_type[i].dev_attr);
1712 }
c18beb5b 1713
1ea6dd38 1714 device_remove_file(dev, &dev_attr_name);
cbe311f2 1715 device_remove_file(dev, &dev_attr_cpu0_vid);
1ea6dd38 1716}
08e7e278 1717
1ea6dd38 1718/* Get the monitoring functions started */
bf164c58
JD		 1719static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data,
1720 enum kinds kind)
08e7e278
JD		 1721{
1722 int i;
da667365 1723 u8 tmp, diode;
08e7e278
JD		 1724
1725 /* Start monitoring is needed */
1ea6dd38 1726 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
08e7e278 1727 if (!(tmp & 0x01))
1ea6dd38 1728 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
08e7e278
JD		 1729 tmp | 0x01);
1730
d36cf32c
GR		 1731 /* Enable temperature sensors if needed */
1732 for (i = 0; i < NUM_REG_TEMP; i++) {
1733 if (!(data->have_temp & (1 << i)))
1734 continue;
ec3e5a16 1735 if (!data->reg_temp_config[i])
d36cf32c 1736 continue;
1ea6dd38 1737 tmp = w83627ehf_read_value(data,
ec3e5a16 1738 data->reg_temp_config[i]);
08e7e278 1739 if (tmp & 0x01)
1ea6dd38 1740 w83627ehf_write_value(data,
ec3e5a16 1741 data->reg_temp_config[i],
08e7e278
JD		 1742 tmp & 0xfe);
1743 }
d3130f0e
JD		 1744
1745 /* Enable VBAT monitoring if needed */
1746 tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1747 if (!(tmp & 0x01))
1748 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
da667365
JD		 1749
1750 /* Get thermal sensor types */
bf164c58
JD		 1751 switch (kind) {
1752 case w83627ehf:
1753 diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
1754 break;
1755 default:
1756 diode = 0x70;
1757 }
da667365
JD		 1758 for (i = 0; i < 3; i++) {
1759 if ((tmp & (0x02 << i)))
bf164c58 1760 data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 3;
da667365
JD		 1761 else
1762 data->temp_type[i] = 4; /* thermistor */
1763 }
08e7e278
JD		 1764}
1765
ec3e5a16
GR		 1766static void w82627ehf_swap_tempreg(struct w83627ehf_data *data,
1767 int r1, int r2)
1768{
1769 u16 tmp;
1770
1771 tmp = data->temp_src[r1];
1772 data->temp_src[r1] = data->temp_src[r2];
1773 data->temp_src[r2] = tmp;
1774
1775 tmp = data->reg_temp[r1];
1776 data->reg_temp[r1] = data->reg_temp[r2];
1777 data->reg_temp[r2] = tmp;
1778
1779 tmp = data->reg_temp_over[r1];
1780 data->reg_temp_over[r1] = data->reg_temp_over[r2];
1781 data->reg_temp_over[r2] = tmp;
1782
1783 tmp = data->reg_temp_hyst[r1];
1784 data->reg_temp_hyst[r1] = data->reg_temp_hyst[r2];
1785 data->reg_temp_hyst[r2] = tmp;
1786
1787 tmp = data->reg_temp_config[r1];
1788 data->reg_temp_config[r1] = data->reg_temp_config[r2];
1789 data->reg_temp_config[r2] = tmp;
1790}
1791
1ea6dd38 1792static int __devinit w83627ehf_probe(struct platform_device *pdev)
08e7e278 1793{
1ea6dd38
DH		 1794 struct device *dev = &pdev->dev;
1795 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08e7e278 1796 struct w83627ehf_data *data;
1ea6dd38 1797 struct resource *res;
ec3e5a16 1798 u8 fan3pin, fan4pin, fan4min, fan5pin, en_vrm10;
08e7e278
JD		 1799 int i, err = 0;
1800
1ea6dd38
DH		 1801 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1802 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
08e7e278 1803 err = -EBUSY;
1ea6dd38
DH		 1804 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
1805 (unsigned long)res->start,
1806 (unsigned long)res->start + IOREGION_LENGTH - 1);
08e7e278
JD		 1807 goto exit;
1808 }
1809
e7e1ca6e
GR		 1810 data = kzalloc(sizeof(struct w83627ehf_data), GFP_KERNEL);
1811 if (!data) {
08e7e278
JD		 1812 err = -ENOMEM;
1813 goto exit_release;
1814 }
08e7e278 1815
1ea6dd38 1816 data->addr = res->start;
9a61bf63 1817 mutex_init(&data->lock);
9a61bf63 1818 mutex_init(&data->update_lock);
1ea6dd38
DH		 1819 data->name = w83627ehf_device_names[sio_data->kind];
1820 platform_set_drvdata(pdev, data);
08e7e278 1821
237c8d2f
GJ		 1822 /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
1823 data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
ec3e5a16 1824 /* 667HG, NCT6775F, and NCT6776F have 3 pwms */
c39aedaf 1825 data->pwm_num = (sio_data->kind == w83667hg
ec3e5a16
GR		 1826 || sio_data->kind == w83667hg_b
1827 || sio_data->kind == nct6775
1828 || sio_data->kind == nct6776) ? 3 : 4;
08e7e278 1829
d36cf32c 1830 data->have_temp = 0x07;
a157d06d 1831 /* Check temp3 configuration bit for 667HG */
d36cf32c
GR		 1832 if (sio_data->kind == w83667hg) {
1833 u8 reg;
1834
1835 reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
1836 if (reg & 0x01)
1837 data->have_temp &= ~(1 << 2);
1838 else
ec3e5a16
GR		 1839 data->in6_skip = 1; /* either temp3 or in6 */
1840 }
1841
1842 /* Deal with temperature register setup first. */
1843 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1844 int mask = 0;
1845
1846 /*
1847 * Display temperature sensor output only if it monitors
1848 * a source other than one already reported. Always display
1849 * first three temperature registers, though.
1850 */
1851 for (i = 0; i < NUM_REG_TEMP; i++) {
1852 u8 src;
1853
1854 data->reg_temp[i] = NCT6775_REG_TEMP[i];
1855 data->reg_temp_over[i] = NCT6775_REG_TEMP_OVER[i];
1856 data->reg_temp_hyst[i] = NCT6775_REG_TEMP_HYST[i];
1857 data->reg_temp_config[i] = NCT6775_REG_TEMP_CONFIG[i];
1858
1859 src = w83627ehf_read_value(data,
1860 NCT6775_REG_TEMP_SOURCE[i]);
1861 src &= 0x1f;
1862 if (src && !(mask & (1 << src))) {
1863 data->have_temp |= 1 << i;
1864 mask |= 1 << src;
1865 }
1866
1867 data->temp_src[i] = src;
1868
1869 /*
1870 * Now do some register swapping if index 0..2 don't
1871 * point to SYSTIN(1), CPUIN(2), and AUXIN(3).
1872 * Idea is to have the first three attributes
1873 * report SYSTIN, CPUIN, and AUXIN if possible
1874 * without overriding the basic system configuration.
1875 */
1876 if (i > 0 && data->temp_src[0] != 1
1877 && data->temp_src[i] == 1)
1878 w82627ehf_swap_tempreg(data, 0, i);
1879 if (i > 1 && data->temp_src[1] != 2
1880 && data->temp_src[i] == 2)
1881 w82627ehf_swap_tempreg(data, 1, i);
1882 if (i > 2 && data->temp_src[2] != 3
1883 && data->temp_src[i] == 3)
1884 w82627ehf_swap_tempreg(data, 2, i);
1885 }
1886 if (sio_data->kind == nct6776) {
1887 /*
1888 * On NCT6776, AUXTIN and VIN3 pins are shared.
1889 * Only way to detect it is to check if AUXTIN is used
1890 * as a temperature source, and if that source is
1891 * enabled.
1892 *
1893 * If that is the case, disable in6, which reports VIN3.
1894 * Otherwise disable temp3.
1895 */
1896 if (data->temp_src[2] == 3) {
1897 u8 reg;
1898
1899 if (data->reg_temp_config[2])
1900 reg = w83627ehf_read_value(data,
1901 data->reg_temp_config[2]);
1902 else
1903 reg = 0; /* Assume AUXTIN is used */
1904
1905 if (reg & 0x01)
1906 data->have_temp &= ~(1 << 2);
1907 else
1908 data->in6_skip = 1;
1909 }
02309ad2
GR		 1910 data->temp_label = nct6776_temp_label;
1911 } else {
1912 data->temp_label = nct6775_temp_label;
ec3e5a16 1913 }
d36cf32c
GR		 1914 } else if (sio_data->kind == w83667hg_b) {
1915 u8 reg;
1916
ec3e5a16
GR		 1917 /*
1918 * Temperature sources are selected with bank 0, registers 0x49
1919 * and 0x4a.
1920 */
1921 for (i = 0; i < ARRAY_SIZE(W83627EHF_REG_TEMP); i++) {
1922 data->reg_temp[i] = W83627EHF_REG_TEMP[i];
1923 data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
1924 data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
1925 data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
1926 }
d36cf32c
GR		 1927 reg = w83627ehf_read_value(data, 0x4a);
1928 data->temp_src[0] = reg >> 5;
1929 reg = w83627ehf_read_value(data, 0x49);
1930 data->temp_src[1] = reg & 0x07;
ec3e5a16 1931 data->temp_src[2] = (reg >> 4) & 0x07;
d36cf32c
GR		 1932
1933 /*
1934 * W83667HG-B has another temperature register at 0x7e.
1935 * The temperature source is selected with register 0x7d.
1936 * Support it if the source differs from already reported
1937 * sources.
1938 */
1939 reg = w83627ehf_read_value(data, 0x7d);
1940 reg &= 0x07;
1941 if (reg != data->temp_src[0] && reg != data->temp_src[1]
1942 && reg != data->temp_src[2]) {
1943 data->temp_src[3] = reg;
1944 data->have_temp |= 1 << 3;
1945 }
1946
1947 /*
1948 * Chip supports either AUXTIN or VIN3. Try to find out which
1949 * one.
1950 */
1951 reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
1952 if (data->temp_src[2] == 2 && (reg & 0x01))
1953 data->have_temp &= ~(1 << 2);
1954
1955 if ((data->temp_src[2] == 2 && (data->have_temp & (1 << 2)))
1956 || (data->temp_src[3] == 2 && (data->have_temp & (1 << 3))))
1957 data->in6_skip = 1;
1958
1959 data->temp_label = w83667hg_b_temp_label;
ec3e5a16
GR		 1960 } else {
1961 /* Temperature sources are fixed */
1962 for (i = 0; i < 3; i++) {
1963 data->reg_temp[i] = W83627EHF_REG_TEMP[i];
1964 data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
1965 data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
1966 data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
1967 }
a157d06d
GJ		 1968 }
1969
ec3e5a16 1970 if (sio_data->kind == nct6775) {
26bc440e
GR		 1971 data->has_fan_div = true;
1972 data->fan_from_reg = fan_from_reg16;
1973 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 1974 data->REG_PWM = NCT6775_REG_PWM;
1975 data->REG_TARGET = NCT6775_REG_TARGET;
26bc440e 1976 data->REG_FAN = NCT6775_REG_FAN;
ec3e5a16
GR		 1977 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
1978 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
1979 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
1980 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
1981 data->REG_FAN_MAX_OUTPUT = NCT6775_REG_FAN_MAX_OUTPUT;
1982 data->REG_FAN_STEP_OUTPUT = NCT6775_REG_FAN_STEP_OUTPUT;
1983 } else if (sio_data->kind == nct6776) {
26bc440e
GR		 1984 data->has_fan_div = false;
1985 data->fan_from_reg = fan_from_reg13;
1986 data->fan_from_reg_min = fan_from_reg13;
ec3e5a16
GR		 1987 data->REG_PWM = NCT6775_REG_PWM;
1988 data->REG_TARGET = NCT6775_REG_TARGET;
26bc440e 1989 data->REG_FAN = NCT6775_REG_FAN;
ec3e5a16
GR		 1990 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
1991 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
1992 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
1993 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
1994 } else if (sio_data->kind == w83667hg_b) {
26bc440e
GR		 1995 data->has_fan_div = true;
1996 data->fan_from_reg = fan_from_reg8;
1997 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 1998 data->REG_PWM = W83627EHF_REG_PWM;
1999 data->REG_TARGET = W83627EHF_REG_TARGET;
2000 data->REG_FAN = W83627EHF_REG_FAN;
2001 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2002 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2003 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2004 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
c39aedaf
GR		 2005 data->REG_FAN_MAX_OUTPUT =
2006 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B;
2007 data->REG_FAN_STEP_OUTPUT =
2008 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B;
2009 } else {
26bc440e
GR		 2010 data->has_fan_div = true;
2011 data->fan_from_reg = fan_from_reg8;
2012 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2013 data->REG_PWM = W83627EHF_REG_PWM;
2014 data->REG_TARGET = W83627EHF_REG_TARGET;
2015 data->REG_FAN = W83627EHF_REG_FAN;
2016 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2017 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2018 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2019 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
c39aedaf
GR		 2020 data->REG_FAN_MAX_OUTPUT =
2021 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON;
2022 data->REG_FAN_STEP_OUTPUT =
2023 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON;
2024 }
da2e0255 2025
08e7e278 2026 /* Initialize the chip */
bf164c58 2027 w83627ehf_init_device(data, sio_data->kind);
08e7e278 2028
fc18d6c0
JD		 2029 data->vrm = vid_which_vrm();
2030 superio_enter(sio_data->sioreg);
fc18d6c0 2031 /* Read VID value */
ec3e5a16
GR		 2032 if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b ||
2033 sio_data->kind == nct6775 || sio_data->kind == nct6776) {
237c8d2f
GJ		 2034 /* W83667HG has different pins for VID input and output, so
2035 we can get the VID input values directly at logical device D
2036 0xe3. */
2037 superio_select(sio_data->sioreg, W83667HG_LD_VID);
2038 data->vid = superio_inb(sio_data->sioreg, 0xe3);
cbe311f2
JD		 2039 err = device_create_file(dev, &dev_attr_cpu0_vid);
2040 if (err)
2041 goto exit_release;
58e6e781 2042 } else {
237c8d2f
GJ		 2043 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2044 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
2045 /* Set VID input sensibility if needed. In theory the
2046 BIOS should have set it, but in practice it's not
2047 always the case. We only do it for the W83627EHF/EHG
2048 because the W83627DHG is more complex in this
2049 respect. */
2050 if (sio_data->kind == w83627ehf) {
2051 en_vrm10 = superio_inb(sio_data->sioreg,
2052 SIO_REG_EN_VRM10);
2053 if ((en_vrm10 & 0x08) && data->vrm == 90) {
2054 dev_warn(dev, "Setting VID input "
2055 "voltage to TTL\n");
2056 superio_outb(sio_data->sioreg,
2057 SIO_REG_EN_VRM10,
2058 en_vrm10 & ~0x08);
2059 } else if (!(en_vrm10 & 0x08)
2060 && data->vrm == 100) {
2061 dev_warn(dev, "Setting VID input "
2062 "voltage to VRM10\n");
2063 superio_outb(sio_data->sioreg,
2064 SIO_REG_EN_VRM10,
2065 en_vrm10 | 0x08);
2066 }
2067 }
2068
2069 data->vid = superio_inb(sio_data->sioreg,
2070 SIO_REG_VID_DATA);
2071 if (sio_data->kind == w83627ehf) /* 6 VID pins only */
2072 data->vid &= 0x3f;
2073
2074 err = device_create_file(dev, &dev_attr_cpu0_vid);
2075 if (err)
2076 goto exit_release;
2077 } else {
2078 dev_info(dev, "VID pins in output mode, CPU VID not "
2079 "available\n");
2080 }
fc18d6c0
JD		 2081 }
2082
08c79950 2083 /* fan4 and fan5 share some pins with the GPIO and serial flash */
ec3e5a16
GR		 2084 if (sio_data->kind == nct6775) {
2085 /* On NCT6775, fan4 shares pins with the fdc interface */
2086 fan3pin = 1;
2087 fan4pin = !(superio_inb(sio_data->sioreg, 0x2A) & 0x80);
2088 fan4min = 0;
2089 fan5pin = 0;
2090 } else if (sio_data->kind == nct6776) {
2091 fan3pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x40);
2092 fan4pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x01);
2093 fan5pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x02);
2094 fan4min = fan4pin;
2095 } else if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
2096 fan3pin = 1;
237c8d2f 2097 fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
ec3e5a16
GR		 2098 fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
2099 fan4min = fan4pin;
237c8d2f 2100 } else {
ec3e5a16 2101 fan3pin = 1;
237c8d2f 2102 fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
ec3e5a16
GR		 2103 fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
2104 fan4min = fan4pin;
237c8d2f 2105 }
d42e869a
ID		 2106
2107 if (fan_debounce &&
2108 (sio_data->kind == nct6775 || sio_data->kind == nct6776)) {
2109 u8 tmp;
2110
2111 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2112 tmp = superio_inb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE);
2113 if (sio_data->kind == nct6776)
2114 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2115 0x3e | tmp);
2116 else
2117 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2118 0x1e | tmp);
2119 pr_info("Enabled fan debounce for chip %s\n", data->name);
2120 }
2121
1ea6dd38 2122 superio_exit(sio_data->sioreg);
08c79950 2123
08e7e278 2124 /* It looks like fan4 and fan5 pins can be alternatively used
14992c7e
RM		 2125 as fan on/off switches, but fan5 control is write only :/
2126 We assume that if the serial interface is disabled, designers
2127 connected fan5 as input unless they are emitting log 1, which
2128 is not the default. */
08c79950 2129
ec3e5a16
GR		 2130 data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
2131
2132 data->has_fan |= (fan3pin << 2);
2133 data->has_fan_min |= (fan3pin << 2);
2134
2135 /*
2136 * NCT6775F and NCT6776F don't have the W83627EHF_REG_FANDIV1 register
2137 */
2138 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
2139 data->has_fan |= (fan4pin << 3) | (fan5pin << 4);
2140 data->has_fan_min |= (fan4min << 3) | (fan5pin << 4);
2141 } else {
2142 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
2143 if ((i & (1 << 2)) && fan4pin) {
2144 data->has_fan |= (1 << 3);
2145 data->has_fan_min |= (1 << 3);
2146 }
2147 if (!(i & (1 << 1)) && fan5pin) {
2148 data->has_fan |= (1 << 4);
2149 data->has_fan_min |= (1 << 4);
2150 }
2151 }
08e7e278 2152
ea7be66c 2153 /* Read fan clock dividers immediately */
ec3e5a16
GR		 2154 w83627ehf_update_fan_div_common(dev, data);
2155
2156 /* Read pwm data to save original values */
2157 w83627ehf_update_pwm_common(dev, data);
2158 for (i = 0; i < data->pwm_num; i++)
2159 data->pwm_enable_orig[i] = data->pwm_enable[i];
ea7be66c 2160
b84bb518
GR		 2161 /* Read pwm data to save original values */
2162 w83627ehf_update_pwm_common(dev, data);
2163 for (i = 0; i < data->pwm_num; i++)
2164 data->pwm_enable_orig[i] = data->pwm_enable[i];
2165
08e7e278 2166 /* Register sysfs hooks */
e7e1ca6e
GR		 2167 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++) {
2168 err = device_create_file(dev, &sda_sf3_arrays[i].dev_attr);
2169 if (err)
c18beb5b 2170 goto exit_remove;
e7e1ca6e 2171 }
08c79950 2172
da2e0255
GR		 2173 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
2174 struct sensor_device_attribute *attr =
2175 &sda_sf3_max_step_arrays[i];
ec3e5a16
GR		 2176 if (data->REG_FAN_STEP_OUTPUT &&
2177 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff) {
da2e0255
GR		 2178 err = device_create_file(dev, &attr->dev_attr);
2179 if (err)
2180 goto exit_remove;
2181 }
2182 }
08c79950 2183 /* if fan4 is enabled create the sf3 files for it */
237c8d2f 2184 if ((data->has_fan & (1 << 3)) && data->pwm_num >= 4)
c18beb5b 2185 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) {
e7e1ca6e
GR		 2186 err = device_create_file(dev,
2187 &sda_sf3_arrays_fan4[i].dev_attr);
2188 if (err)
c18beb5b
DH		 2189 goto exit_remove;
2190 }
08c79950 2191
a157d06d
GJ		 2192 for (i = 0; i < data->in_num; i++) {
2193 if ((i == 6) && data->in6_skip)
2194 continue;
c18beb5b
DH		 2195 if ((err = device_create_file(dev, &sda_in_input[i].dev_attr))
2196 || (err = device_create_file(dev,
2197 &sda_in_alarm[i].dev_attr))
2198 || (err = device_create_file(dev,
2199 &sda_in_min[i].dev_attr))
2200 || (err = device_create_file(dev,
2201 &sda_in_max[i].dev_attr)))
2202 goto exit_remove;
a157d06d 2203 }
cf0676fe 2204
412fec82 2205 for (i = 0; i < 5; i++) {
08c79950 2206 if (data->has_fan & (1 << i)) {
c18beb5b
DH		 2207 if ((err = device_create_file(dev,
2208 &sda_fan_input[i].dev_attr))
2209 || (err = device_create_file(dev,
ec3e5a16 2210 &sda_fan_alarm[i].dev_attr)))
c18beb5b 2211 goto exit_remove;
ec3e5a16
GR		 2212 if (sio_data->kind != nct6776) {
2213 err = device_create_file(dev,
2214 &sda_fan_div[i].dev_attr);
2215 if (err)
2216 goto exit_remove;
2217 }
2218 if (data->has_fan_min & (1 << i)) {
2219 err = device_create_file(dev,
2220 &sda_fan_min[i].dev_attr);
2221 if (err)
2222 goto exit_remove;
2223 }
237c8d2f 2224 if (i < data->pwm_num &&
c18beb5b
DH		 2225 ((err = device_create_file(dev,
2226 &sda_pwm[i].dev_attr))
2227 || (err = device_create_file(dev,
2228 &sda_pwm_mode[i].dev_attr))
2229 || (err = device_create_file(dev,
2230 &sda_pwm_enable[i].dev_attr))
2231 || (err = device_create_file(dev,
2232 &sda_target_temp[i].dev_attr))
2233 || (err = device_create_file(dev,
2234 &sda_tolerance[i].dev_attr))))
2235 goto exit_remove;
08c79950 2236 }
08e7e278 2237 }
08c79950 2238
d36cf32c
GR		 2239 for (i = 0; i < NUM_REG_TEMP; i++) {
2240 if (!(data->have_temp & (1 << i)))
a157d06d 2241 continue;
d36cf32c
GR		 2242 err = device_create_file(dev, &sda_temp_input[i].dev_attr);
2243 if (err)
2244 goto exit_remove;
2245 if (data->temp_label) {
2246 err = device_create_file(dev,
2247 &sda_temp_label[i].dev_attr);
2248 if (err)
2249 goto exit_remove;
2250 }
ec3e5a16
GR		 2251 if (data->reg_temp_over[i]) {
2252 err = device_create_file(dev,
2253 &sda_temp_max[i].dev_attr);
2254 if (err)
2255 goto exit_remove;
2256 }
2257 if (data->reg_temp_hyst[i]) {
2258 err = device_create_file(dev,
2259 &sda_temp_max_hyst[i].dev_attr);
2260 if (err)
2261 goto exit_remove;
2262 }
d36cf32c 2263 if (i > 2)
ec3e5a16
GR		 2264 continue;
2265 if ((err = device_create_file(dev,
a157d06d
GJ		 2266 &sda_temp_alarm[i].dev_attr))
2267 || (err = device_create_file(dev,
2268 &sda_temp_type[i].dev_attr)))
c18beb5b 2269 goto exit_remove;
a157d06d 2270 }
c18beb5b 2271
1ea6dd38
DH		 2272 err = device_create_file(dev, &dev_attr_name);
2273 if (err)
2274 goto exit_remove;
2275
1beeffe4
TJ		 2276 data->hwmon_dev = hwmon_device_register(dev);
2277 if (IS_ERR(data->hwmon_dev)) {
2278 err = PTR_ERR(data->hwmon_dev);
c18beb5b
DH		 2279 goto exit_remove;
2280 }
08e7e278
JD		 2281
2282 return 0;
2283
c18beb5b
DH		 2284exit_remove:
2285 w83627ehf_device_remove_files(dev);
08e7e278 2286 kfree(data);
1ea6dd38 2287 platform_set_drvdata(pdev, NULL);
08e7e278 2288exit_release:
1ea6dd38 2289 release_region(res->start, IOREGION_LENGTH);
08e7e278
JD		 2290exit:
2291 return err;
2292}
2293
1ea6dd38 2294static int __devexit w83627ehf_remove(struct platform_device *pdev)
08e7e278 2295{
1ea6dd38 2296 struct w83627ehf_data *data = platform_get_drvdata(pdev);
08e7e278 2297
1beeffe4 2298 hwmon_device_unregister(data->hwmon_dev);
1ea6dd38
DH		 2299 w83627ehf_device_remove_files(&pdev->dev);
2300 release_region(data->addr, IOREGION_LENGTH);
2301 platform_set_drvdata(pdev, NULL);
943b0830 2302 kfree(data);
08e7e278
JD		 2303
2304 return 0;
2305}
2306
1ea6dd38 2307static struct platform_driver w83627ehf_driver = {
cdaf7934 2308 .driver = {
87218842 2309 .owner = THIS_MODULE,
1ea6dd38 2310 .name = DRVNAME,
cdaf7934 2311 },
1ea6dd38
DH		 2312 .probe = w83627ehf_probe,
2313 .remove = __devexit_p(w83627ehf_remove),
08e7e278
JD		 2314};
2315
1ea6dd38
DH		 2316/* w83627ehf_find() looks for a '627 in the Super-I/O config space */
2317static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
2318 struct w83627ehf_sio_data *sio_data)
08e7e278 2319{
1ea6dd38
DH		 2320 static const char __initdata sio_name_W83627EHF[] = "W83627EHF";
2321 static const char __initdata sio_name_W83627EHG[] = "W83627EHG";
2322 static const char __initdata sio_name_W83627DHG[] = "W83627DHG";
c1e48dce 2323 static const char __initdata sio_name_W83627DHG_P[] = "W83627DHG-P";
237c8d2f 2324 static const char __initdata sio_name_W83667HG[] = "W83667HG";
c39aedaf 2325 static const char __initdata sio_name_W83667HG_B[] = "W83667HG-B";
ec3e5a16
GR		 2326 static const char __initdata sio_name_NCT6775[] = "NCT6775F";
2327 static const char __initdata sio_name_NCT6776[] = "NCT6776F";
1ea6dd38 2328
08e7e278 2329 u16 val;
1ea6dd38 2330 const char *sio_name;
08e7e278 2331
1ea6dd38 2332 superio_enter(sioaddr);
08e7e278 2333
67b671bc
JD		 2334 if (force_id)
2335 val = force_id;
2336 else
2337 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
2338 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
657c93b1 2339 switch (val & SIO_ID_MASK) {
657c93b1 2340 case SIO_W83627EHF_ID:
1ea6dd38
DH		 2341 sio_data->kind = w83627ehf;
2342 sio_name = sio_name_W83627EHF;
2343 break;
657c93b1 2344 case SIO_W83627EHG_ID:
1ea6dd38
DH		 2345 sio_data->kind = w83627ehf;
2346 sio_name = sio_name_W83627EHG;
2347 break;
2348 case SIO_W83627DHG_ID:
2349 sio_data->kind = w83627dhg;
2350 sio_name = sio_name_W83627DHG;
657c93b1 2351 break;
c1e48dce
JD		 2352 case SIO_W83627DHG_P_ID:
2353 sio_data->kind = w83627dhg_p;
2354 sio_name = sio_name_W83627DHG_P;
2355 break;
237c8d2f
GJ		 2356 case SIO_W83667HG_ID:
2357 sio_data->kind = w83667hg;
2358 sio_name = sio_name_W83667HG;
2359 break;
c39aedaf
GR		 2360 case SIO_W83667HG_B_ID:
2361 sio_data->kind = w83667hg_b;
2362 sio_name = sio_name_W83667HG_B;
2363 break;
ec3e5a16
GR		 2364 case SIO_NCT6775_ID:
2365 sio_data->kind = nct6775;
2366 sio_name = sio_name_NCT6775;
2367 break;
2368 case SIO_NCT6776_ID:
2369 sio_data->kind = nct6776;
2370 sio_name = sio_name_NCT6776;
2371 break;
657c93b1 2372 default:
9f66036b 2373 if (val != 0xffff)
abdc6fd1 2374 pr_debug("unsupported chip ID: 0x%04x\n", val);
1ea6dd38 2375 superio_exit(sioaddr);
08e7e278
JD		 2376 return -ENODEV;
2377 }
2378
1ea6dd38
DH		 2379 /* We have a known chip, find the HWM I/O address */
2380 superio_select(sioaddr, W83627EHF_LD_HWM);
2381 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
2382 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
1a641fce 2383 *addr = val & IOREGION_ALIGNMENT;
2d8672c5 2384 if (*addr == 0) {
abdc6fd1 2385 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
1ea6dd38 2386 superio_exit(sioaddr);
08e7e278
JD		 2387 return -ENODEV;
2388 }
2389
2390 /* Activate logical device if needed */
1ea6dd38 2391 val = superio_inb(sioaddr, SIO_REG_ENABLE);
475ef855 2392 if (!(val & 0x01)) {
e7e1ca6e
GR		 2393 pr_warn("Forcibly enabling Super-I/O. "
2394 "Sensor is probably unusable.\n");
1ea6dd38 2395 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
475ef855 2396 }
1ea6dd38
DH		 2397
2398 superio_exit(sioaddr);
abdc6fd1 2399 pr_info("Found %s chip at %#x\n", sio_name, *addr);
1ea6dd38 2400 sio_data->sioreg = sioaddr;
08e7e278 2401
08e7e278
JD		 2402 return 0;
2403}
2404
1ea6dd38
DH		 2405/* when Super-I/O functions move to a separate file, the Super-I/O
2406 * bus will manage the lifetime of the device and this module will only keep
2407 * track of the w83627ehf driver. But since we platform_device_alloc(), we
2408 * must keep track of the device */
2409static struct platform_device *pdev;
2410
08e7e278
JD		 2411static int __init sensors_w83627ehf_init(void)
2412{
1ea6dd38
DH		 2413 int err;
2414 unsigned short address;
2415 struct resource res;
2416 struct w83627ehf_sio_data sio_data;
2417
2418 /* initialize sio_data->kind and sio_data->sioreg.
2419 *
2420 * when Super-I/O functions move to a separate file, the Super-I/O
2421 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
2422 * w83627ehf hardware monitor, and call probe() */
2423 if (w83627ehf_find(0x2e, &address, &sio_data) &&
2424 w83627ehf_find(0x4e, &address, &sio_data))
08e7e278
JD		 2425 return -ENODEV;
2426
1ea6dd38
DH		 2427 err = platform_driver_register(&w83627ehf_driver);
2428 if (err)
2429 goto exit;
2430
e7e1ca6e
GR		 2431 pdev = platform_device_alloc(DRVNAME, address);
2432 if (!pdev) {
1ea6dd38 2433 err = -ENOMEM;
abdc6fd1 2434 pr_err("Device allocation failed\n");
1ea6dd38
DH		 2435 goto exit_unregister;
2436 }
2437
2438 err = platform_device_add_data(pdev, &sio_data,
2439 sizeof(struct w83627ehf_sio_data));
2440 if (err) {
abdc6fd1 2441 pr_err("Platform data allocation failed\n");
1ea6dd38
DH		 2442 goto exit_device_put;
2443 }
2444
2445 memset(&res, 0, sizeof(res));
2446 res.name = DRVNAME;
2447 res.start = address + IOREGION_OFFSET;
2448 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
2449 res.flags = IORESOURCE_IO;
b9acb64a
JD		 2450
2451 err = acpi_check_resource_conflict(&res);
2452 if (err)
18632f84 2453 goto exit_device_put;
b9acb64a 2454
1ea6dd38
DH		 2455 err = platform_device_add_resources(pdev, &res, 1);
2456 if (err) {
abdc6fd1 2457 pr_err("Device resource addition failed (%d)\n", err);
1ea6dd38
DH		 2458 goto exit_device_put;
2459 }
2460
2461 /* platform_device_add calls probe() */
2462 err = platform_device_add(pdev);
2463 if (err) {
abdc6fd1 2464 pr_err("Device addition failed (%d)\n", err);
1ea6dd38
DH		 2465 goto exit_device_put;
2466 }
2467
2468 return 0;
2469
2470exit_device_put:
2471 platform_device_put(pdev);
2472exit_unregister:
2473 platform_driver_unregister(&w83627ehf_driver);
2474exit:
2475 return err;
08e7e278
JD		 2476}
2477
2478static void __exit sensors_w83627ehf_exit(void)
2479{
1ea6dd38
DH		 2480 platform_device_unregister(pdev);
2481 platform_driver_unregister(&w83627ehf_driver);
08e7e278
JD		 2482}
2483
2484MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
2485MODULE_DESCRIPTION("W83627EHF driver");
2486MODULE_LICENSE("GPL");
2487
2488module_init(sensors_w83627ehf_init);
2489module_exit(sensors_w83627ehf_exit);
Linux kernel - Deliverables
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