Commit | Line | Data |
---|---|---|
08e7e278 JD |
1 | /* |
2 | w83627ehf - Driver for the hardware monitoring functionality of | |
e7e1ca6e | 3 | the Winbond W83627EHF Super-I/O chip |
08e7e278 | 4 | Copyright (C) 2005 Jean Delvare <khali@linux-fr.org> |
3379ceee | 5 | Copyright (C) 2006 Yuan Mu (Winbond), |
e7e1ca6e GR |
6 | Rudolf Marek <r.marek@assembler.cz> |
7 | David Hubbard <david.c.hubbard@gmail.com> | |
41e9a062 | 8 | Daniel J Blueman <daniel.blueman@gmail.com> |
ec3e5a16 | 9 | Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00) |
08e7e278 JD |
10 | |
11 | Shamelessly ripped from the w83627hf driver | |
12 | Copyright (C) 2003 Mark Studebaker | |
13 | ||
14 | Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help | |
15 | in testing and debugging this driver. | |
16 | ||
8dd2d2ca JD |
17 | This driver also supports the W83627EHG, which is the lead-free |
18 | version of the W83627EHF. | |
19 | ||
08e7e278 JD |
20 | This program is free software; you can redistribute it and/or modify |
21 | it under the terms of the GNU General Public License as published by | |
22 | the Free Software Foundation; either version 2 of the License, or | |
23 | (at your option) any later version. | |
24 | ||
25 | This program is distributed in the hope that it will be useful, | |
26 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | GNU General Public License for more details. | |
29 | ||
30 | You should have received a copy of the GNU General Public License | |
31 | along with this program; if not, write to the Free Software | |
32 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
33 | ||
34 | ||
35 | Supports the following chips: | |
36 | ||
657c93b1 DH |
37 | Chip #vin #fan #pwm #temp chip IDs man ID |
38 | w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3 | |
e7e1ca6e | 39 | 0x8860 0xa1 |
657c93b1 | 40 | w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3 |
c1e48dce | 41 | w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3 |
237c8d2f | 42 | w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3 |
d36cf32c | 43 | w83667hg-b 9 5 3 4 0xb350 0xc1 0x5ca3 |
ec3e5a16 GR |
44 | nct6775f 9 4 3 9 0xb470 0xc1 0x5ca3 |
45 | nct6776f 9 5 3 9 0xC330 0xc1 0x5ca3 | |
08e7e278 JD |
46 | */ |
47 | ||
abdc6fd1 JP |
48 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
49 | ||
08e7e278 JD |
50 | #include <linux/module.h> |
51 | #include <linux/init.h> | |
52 | #include <linux/slab.h> | |
1ea6dd38 DH |
53 | #include <linux/jiffies.h> |
54 | #include <linux/platform_device.h> | |
943b0830 | 55 | #include <linux/hwmon.h> |
412fec82 | 56 | #include <linux/hwmon-sysfs.h> |
fc18d6c0 | 57 | #include <linux/hwmon-vid.h> |
943b0830 | 58 | #include <linux/err.h> |
9a61bf63 | 59 | #include <linux/mutex.h> |
b9acb64a | 60 | #include <linux/acpi.h> |
6055fae8 | 61 | #include <linux/io.h> |
08e7e278 JD |
62 | #include "lm75.h" |
63 | ||
ec3e5a16 GR |
64 | enum kinds { w83627ehf, w83627dhg, w83627dhg_p, w83667hg, w83667hg_b, nct6775, |
65 | nct6776 }; | |
08e7e278 | 66 | |
1ea6dd38 | 67 | /* used to set data->name = w83627ehf_device_names[data->sio_kind] */ |
e7e1ca6e | 68 | static const char * const w83627ehf_device_names[] = { |
1ea6dd38 DH |
69 | "w83627ehf", |
70 | "w83627dhg", | |
c1e48dce | 71 | "w83627dhg", |
237c8d2f | 72 | "w83667hg", |
c39aedaf | 73 | "w83667hg", |
ec3e5a16 GR |
74 | "nct6775", |
75 | "nct6776", | |
1ea6dd38 DH |
76 | }; |
77 | ||
67b671bc JD |
78 | static unsigned short force_id; |
79 | module_param(force_id, ushort, 0); | |
80 | MODULE_PARM_DESC(force_id, "Override the detected device ID"); | |
81 | ||
d42e869a ID |
82 | static unsigned short fan_debounce; |
83 | module_param(fan_debounce, ushort, 0); | |
84 | MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal"); | |
85 | ||
1ea6dd38 | 86 | #define DRVNAME "w83627ehf" |
08e7e278 | 87 | |
657c93b1 | 88 | /* |
1ea6dd38 | 89 | * Super-I/O constants and functions |
657c93b1 | 90 | */ |
08e7e278 JD |
91 | |
92 | #define W83627EHF_LD_HWM 0x0b | |
e7e1ca6e | 93 | #define W83667HG_LD_VID 0x0d |
08e7e278 JD |
94 | |
95 | #define SIO_REG_LDSEL 0x07 /* Logical device select */ | |
96 | #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */ | |
fc18d6c0 | 97 | #define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */ |
08e7e278 JD |
98 | #define SIO_REG_ENABLE 0x30 /* Logical device enable */ |
99 | #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */ | |
fc18d6c0 JD |
100 | #define SIO_REG_VID_CTRL 0xF0 /* VID control */ |
101 | #define SIO_REG_VID_DATA 0xF1 /* VID data */ | |
08e7e278 | 102 | |
657c93b1 DH |
103 | #define SIO_W83627EHF_ID 0x8850 |
104 | #define SIO_W83627EHG_ID 0x8860 | |
105 | #define SIO_W83627DHG_ID 0xa020 | |
c1e48dce | 106 | #define SIO_W83627DHG_P_ID 0xb070 |
e7e1ca6e | 107 | #define SIO_W83667HG_ID 0xa510 |
c39aedaf | 108 | #define SIO_W83667HG_B_ID 0xb350 |
ec3e5a16 GR |
109 | #define SIO_NCT6775_ID 0xb470 |
110 | #define SIO_NCT6776_ID 0xc330 | |
657c93b1 | 111 | #define SIO_ID_MASK 0xFFF0 |
08e7e278 JD |
112 | |
113 | static inline void | |
1ea6dd38 | 114 | superio_outb(int ioreg, int reg, int val) |
08e7e278 | 115 | { |
1ea6dd38 DH |
116 | outb(reg, ioreg); |
117 | outb(val, ioreg + 1); | |
08e7e278 JD |
118 | } |
119 | ||
120 | static inline int | |
1ea6dd38 | 121 | superio_inb(int ioreg, int reg) |
08e7e278 | 122 | { |
1ea6dd38 DH |
123 | outb(reg, ioreg); |
124 | return inb(ioreg + 1); | |
08e7e278 JD |
125 | } |
126 | ||
127 | static inline void | |
1ea6dd38 | 128 | superio_select(int ioreg, int ld) |
08e7e278 | 129 | { |
1ea6dd38 DH |
130 | outb(SIO_REG_LDSEL, ioreg); |
131 | outb(ld, ioreg + 1); | |
08e7e278 JD |
132 | } |
133 | ||
134 | static inline void | |
1ea6dd38 | 135 | superio_enter(int ioreg) |
08e7e278 | 136 | { |
1ea6dd38 DH |
137 | outb(0x87, ioreg); |
138 | outb(0x87, ioreg); | |
08e7e278 JD |
139 | } |
140 | ||
141 | static inline void | |
1ea6dd38 | 142 | superio_exit(int ioreg) |
08e7e278 | 143 | { |
022b75a3 | 144 | outb(0xaa, ioreg); |
1ea6dd38 DH |
145 | outb(0x02, ioreg); |
146 | outb(0x02, ioreg + 1); | |
08e7e278 JD |
147 | } |
148 | ||
149 | /* | |
150 | * ISA constants | |
151 | */ | |
152 | ||
e7e1ca6e | 153 | #define IOREGION_ALIGNMENT (~7) |
1a641fce JD |
154 | #define IOREGION_OFFSET 5 |
155 | #define IOREGION_LENGTH 2 | |
1ea6dd38 DH |
156 | #define ADDR_REG_OFFSET 0 |
157 | #define DATA_REG_OFFSET 1 | |
08e7e278 JD |
158 | |
159 | #define W83627EHF_REG_BANK 0x4E | |
160 | #define W83627EHF_REG_CONFIG 0x40 | |
657c93b1 DH |
161 | |
162 | /* Not currently used: | |
163 | * REG_MAN_ID has the value 0x5ca3 for all supported chips. | |
164 | * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model. | |
165 | * REG_MAN_ID is at port 0x4f | |
166 | * REG_CHIP_ID is at port 0x58 */ | |
08e7e278 JD |
167 | |
168 | static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 }; | |
169 | static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c }; | |
170 | ||
cf0676fe RM |
171 | /* The W83627EHF registers for nr=7,8,9 are in bank 5 */ |
172 | #define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \ | |
173 | (0x554 + (((nr) - 7) * 2))) | |
174 | #define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \ | |
175 | (0x555 + (((nr) - 7) * 2))) | |
176 | #define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \ | |
177 | (0x550 + (nr) - 7)) | |
178 | ||
d36cf32c GR |
179 | static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250, 0x7e }; |
180 | static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253, 0 }; | |
181 | static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255, 0 }; | |
182 | static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252, 0 }; | |
08e7e278 JD |
183 | |
184 | /* Fan clock dividers are spread over the following five registers */ | |
185 | #define W83627EHF_REG_FANDIV1 0x47 | |
186 | #define W83627EHF_REG_FANDIV2 0x4B | |
187 | #define W83627EHF_REG_VBAT 0x5D | |
188 | #define W83627EHF_REG_DIODE 0x59 | |
189 | #define W83627EHF_REG_SMI_OVT 0x4C | |
190 | ||
ec3e5a16 GR |
191 | /* NCT6775F has its own fan divider registers */ |
192 | #define NCT6775_REG_FANDIV1 0x506 | |
193 | #define NCT6775_REG_FANDIV2 0x507 | |
d42e869a | 194 | #define NCT6775_REG_FAN_DEBOUNCE 0xf0 |
ec3e5a16 | 195 | |
a4589dbb JD |
196 | #define W83627EHF_REG_ALARM1 0x459 |
197 | #define W83627EHF_REG_ALARM2 0x45A | |
198 | #define W83627EHF_REG_ALARM3 0x45B | |
199 | ||
363a12a4 DA |
200 | #define W83627EHF_REG_CASEOPEN_DET 0x42 /* SMI STATUS #2 */ |
201 | #define W83627EHF_REG_CASEOPEN_CLR 0x46 /* SMI MASK #3 */ | |
202 | ||
08c79950 | 203 | /* SmartFan registers */ |
41e9a062 DB |
204 | #define W83627EHF_REG_FAN_STEPUP_TIME 0x0f |
205 | #define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e | |
206 | ||
08c79950 RM |
207 | /* DC or PWM output fan configuration */ |
208 | static const u8 W83627EHF_REG_PWM_ENABLE[] = { | |
209 | 0x04, /* SYS FAN0 output mode and PWM mode */ | |
210 | 0x04, /* CPU FAN0 output mode and PWM mode */ | |
211 | 0x12, /* AUX FAN mode */ | |
41e9a062 | 212 | 0x62, /* CPU FAN1 mode */ |
08c79950 RM |
213 | }; |
214 | ||
215 | static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 }; | |
216 | static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 }; | |
217 | ||
218 | /* FAN Duty Cycle, be used to control */ | |
279af1a9 GR |
219 | static const u16 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 }; |
220 | static const u16 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 }; | |
08c79950 RM |
221 | static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 }; |
222 | ||
08c79950 | 223 | /* Advanced Fan control, some values are common for all fans */ |
279af1a9 GR |
224 | static const u16 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 }; |
225 | static const u16 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 }; | |
226 | static const u16 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 }; | |
c39aedaf | 227 | |
279af1a9 | 228 | static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[] |
c39aedaf | 229 | = { 0xff, 0x67, 0xff, 0x69 }; |
279af1a9 | 230 | static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[] |
c39aedaf GR |
231 | = { 0xff, 0x68, 0xff, 0x6a }; |
232 | ||
279af1a9 GR |
233 | static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b }; |
234 | static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[] | |
235 | = { 0x68, 0x6a, 0x6c }; | |
08c79950 | 236 | |
ec3e5a16 GR |
237 | static const u16 NCT6775_REG_TARGET[] = { 0x101, 0x201, 0x301 }; |
238 | static const u16 NCT6775_REG_FAN_MODE[] = { 0x102, 0x202, 0x302 }; | |
239 | static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = { 0x105, 0x205, 0x305 }; | |
240 | static const u16 NCT6775_REG_FAN_START_OUTPUT[] = { 0x106, 0x206, 0x306 }; | |
241 | static const u16 NCT6775_REG_FAN_STOP_TIME[] = { 0x107, 0x207, 0x307 }; | |
242 | static const u16 NCT6775_REG_PWM[] = { 0x109, 0x209, 0x309 }; | |
243 | static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a }; | |
244 | static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b }; | |
26bc440e | 245 | static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 }; |
ec3e5a16 GR |
246 | static const u16 NCT6776_REG_FAN_MIN[] = { 0x63a, 0x63c, 0x63e, 0x640, 0x642}; |
247 | ||
248 | static const u16 NCT6775_REG_TEMP[] | |
249 | = { 0x27, 0x150, 0x250, 0x73, 0x75, 0x77, 0x62b, 0x62c, 0x62d }; | |
250 | static const u16 NCT6775_REG_TEMP_CONFIG[] | |
251 | = { 0, 0x152, 0x252, 0, 0, 0, 0x628, 0x629, 0x62A }; | |
252 | static const u16 NCT6775_REG_TEMP_HYST[] | |
253 | = { 0x3a, 0x153, 0x253, 0, 0, 0, 0x673, 0x678, 0x67D }; | |
254 | static const u16 NCT6775_REG_TEMP_OVER[] | |
255 | = { 0x39, 0x155, 0x255, 0, 0, 0, 0x672, 0x677, 0x67C }; | |
256 | static const u16 NCT6775_REG_TEMP_SOURCE[] | |
257 | = { 0x621, 0x622, 0x623, 0x100, 0x200, 0x300, 0x624, 0x625, 0x626 }; | |
258 | ||
d36cf32c GR |
259 | static const char *const w83667hg_b_temp_label[] = { |
260 | "SYSTIN", | |
261 | "CPUTIN", | |
262 | "AUXTIN", | |
263 | "AMDTSI", | |
264 | "PECI Agent 1", | |
265 | "PECI Agent 2", | |
266 | "PECI Agent 3", | |
267 | "PECI Agent 4" | |
268 | }; | |
269 | ||
ec3e5a16 GR |
270 | static const char *const nct6775_temp_label[] = { |
271 | "", | |
272 | "SYSTIN", | |
273 | "CPUTIN", | |
274 | "AUXTIN", | |
275 | "AMD SB-TSI", | |
276 | "PECI Agent 0", | |
277 | "PECI Agent 1", | |
278 | "PECI Agent 2", | |
279 | "PECI Agent 3", | |
280 | "PECI Agent 4", | |
281 | "PECI Agent 5", | |
282 | "PECI Agent 6", | |
283 | "PECI Agent 7", | |
284 | "PCH_CHIP_CPU_MAX_TEMP", | |
285 | "PCH_CHIP_TEMP", | |
286 | "PCH_CPU_TEMP", | |
287 | "PCH_MCH_TEMP", | |
288 | "PCH_DIM0_TEMP", | |
289 | "PCH_DIM1_TEMP", | |
290 | "PCH_DIM2_TEMP", | |
291 | "PCH_DIM3_TEMP" | |
292 | }; | |
293 | ||
294 | static const char *const nct6776_temp_label[] = { | |
295 | "", | |
296 | "SYSTIN", | |
297 | "CPUTIN", | |
298 | "AUXTIN", | |
299 | "SMBUSMASTER 0", | |
300 | "SMBUSMASTER 1", | |
301 | "SMBUSMASTER 2", | |
302 | "SMBUSMASTER 3", | |
303 | "SMBUSMASTER 4", | |
304 | "SMBUSMASTER 5", | |
305 | "SMBUSMASTER 6", | |
306 | "SMBUSMASTER 7", | |
307 | "PECI Agent 0", | |
308 | "PECI Agent 1", | |
309 | "PCH_CHIP_CPU_MAX_TEMP", | |
310 | "PCH_CHIP_TEMP", | |
311 | "PCH_CPU_TEMP", | |
312 | "PCH_MCH_TEMP", | |
313 | "PCH_DIM0_TEMP", | |
314 | "PCH_DIM1_TEMP", | |
315 | "PCH_DIM2_TEMP", | |
316 | "PCH_DIM3_TEMP", | |
317 | "BYTE_TEMP" | |
318 | }; | |
319 | ||
320 | #define NUM_REG_TEMP ARRAY_SIZE(NCT6775_REG_TEMP) | |
d36cf32c | 321 | |
17296feb | 322 | static int is_word_sized(u16 reg) |
bce26c58 | 323 | { |
ec3e5a16 | 324 | return ((((reg & 0xff00) == 0x100 |
bce26c58 GR |
325 | || (reg & 0xff00) == 0x200) |
326 | && ((reg & 0x00ff) == 0x50 | |
327 | || (reg & 0x00ff) == 0x53 | |
ec3e5a16 GR |
328 | || (reg & 0x00ff) == 0x55)) |
329 | || (reg & 0xfff0) == 0x630 | |
330 | || reg == 0x640 || reg == 0x642 | |
331 | || ((reg & 0xfff0) == 0x650 | |
332 | && (reg & 0x000f) >= 0x06) | |
333 | || reg == 0x73 || reg == 0x75 || reg == 0x77 | |
334 | ); | |
bce26c58 GR |
335 | } |
336 | ||
08e7e278 JD |
337 | /* |
338 | * Conversions | |
339 | */ | |
340 | ||
08c79950 RM |
341 | /* 1 is PWM mode, output in ms */ |
342 | static inline unsigned int step_time_from_reg(u8 reg, u8 mode) | |
343 | { | |
344 | return mode ? 100 * reg : 400 * reg; | |
345 | } | |
346 | ||
347 | static inline u8 step_time_to_reg(unsigned int msec, u8 mode) | |
348 | { | |
349 | return SENSORS_LIMIT((mode ? (msec + 50) / 100 : | |
350 | (msec + 200) / 400), 1, 255); | |
351 | } | |
352 | ||
26bc440e | 353 | static unsigned int fan_from_reg8(u16 reg, unsigned int divreg) |
08e7e278 | 354 | { |
26bc440e | 355 | if (reg == 0 || reg == 255) |
08e7e278 | 356 | return 0; |
26bc440e GR |
357 | return 1350000U / (reg << divreg); |
358 | } | |
359 | ||
360 | static unsigned int fan_from_reg13(u16 reg, unsigned int divreg) | |
361 | { | |
362 | if ((reg & 0xff1f) == 0xff1f) | |
363 | return 0; | |
364 | ||
365 | reg = (reg & 0x1f) | ((reg & 0xff00) >> 3); | |
366 | ||
367 | if (reg == 0) | |
368 | return 0; | |
369 | ||
370 | return 1350000U / reg; | |
371 | } | |
372 | ||
373 | static unsigned int fan_from_reg16(u16 reg, unsigned int divreg) | |
374 | { | |
375 | if (reg == 0 || reg == 0xffff) | |
376 | return 0; | |
377 | ||
378 | /* | |
379 | * Even though the registers are 16 bit wide, the fan divisor | |
380 | * still applies. | |
381 | */ | |
382 | return 1350000U / (reg << divreg); | |
08e7e278 JD |
383 | } |
384 | ||
385 | static inline unsigned int | |
386 | div_from_reg(u8 reg) | |
387 | { | |
388 | return 1 << reg; | |
389 | } | |
390 | ||
cf0676fe RM |
391 | /* Some of analog inputs have internal scaling (2x), 8mV is ADC LSB */ |
392 | ||
393 | static u8 scale_in[10] = { 8, 8, 16, 16, 8, 8, 8, 16, 16, 8 }; | |
394 | ||
395 | static inline long in_from_reg(u8 reg, u8 nr) | |
396 | { | |
397 | return reg * scale_in[nr]; | |
398 | } | |
399 | ||
400 | static inline u8 in_to_reg(u32 val, u8 nr) | |
401 | { | |
e7e1ca6e GR |
402 | return SENSORS_LIMIT(((val + (scale_in[nr] / 2)) / scale_in[nr]), 0, |
403 | 255); | |
cf0676fe RM |
404 | } |
405 | ||
08e7e278 JD |
406 | /* |
407 | * Data structures and manipulation thereof | |
408 | */ | |
409 | ||
410 | struct w83627ehf_data { | |
1ea6dd38 DH |
411 | int addr; /* IO base of hw monitor block */ |
412 | const char *name; | |
413 | ||
1beeffe4 | 414 | struct device *hwmon_dev; |
9a61bf63 | 415 | struct mutex lock; |
08e7e278 | 416 | |
ec3e5a16 GR |
417 | u16 reg_temp[NUM_REG_TEMP]; |
418 | u16 reg_temp_over[NUM_REG_TEMP]; | |
419 | u16 reg_temp_hyst[NUM_REG_TEMP]; | |
420 | u16 reg_temp_config[NUM_REG_TEMP]; | |
d36cf32c GR |
421 | u8 temp_src[NUM_REG_TEMP]; |
422 | const char * const *temp_label; | |
423 | ||
279af1a9 GR |
424 | const u16 *REG_PWM; |
425 | const u16 *REG_TARGET; | |
426 | const u16 *REG_FAN; | |
427 | const u16 *REG_FAN_MIN; | |
428 | const u16 *REG_FAN_START_OUTPUT; | |
429 | const u16 *REG_FAN_STOP_OUTPUT; | |
430 | const u16 *REG_FAN_STOP_TIME; | |
431 | const u16 *REG_FAN_MAX_OUTPUT; | |
432 | const u16 *REG_FAN_STEP_OUTPUT; | |
da2e0255 | 433 | |
26bc440e GR |
434 | unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg); |
435 | unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg); | |
436 | ||
9a61bf63 | 437 | struct mutex update_lock; |
08e7e278 JD |
438 | char valid; /* !=0 if following fields are valid */ |
439 | unsigned long last_updated; /* In jiffies */ | |
440 | ||
441 | /* Register values */ | |
83cc8985 | 442 | u8 bank; /* current register bank */ |
1ea6dd38 | 443 | u8 in_num; /* number of in inputs we have */ |
cf0676fe RM |
444 | u8 in[10]; /* Register value */ |
445 | u8 in_max[10]; /* Register value */ | |
446 | u8 in_min[10]; /* Register value */ | |
3382a918 | 447 | unsigned int rpm[5]; |
ec3e5a16 | 448 | u16 fan_min[5]; |
08e7e278 JD |
449 | u8 fan_div[5]; |
450 | u8 has_fan; /* some fan inputs can be disabled */ | |
ec3e5a16 | 451 | u8 has_fan_min; /* some fans don't have min register */ |
26bc440e | 452 | bool has_fan_div; |
da667365 | 453 | u8 temp_type[3]; |
ec3e5a16 GR |
454 | s16 temp[9]; |
455 | s16 temp_max[9]; | |
456 | s16 temp_max_hyst[9]; | |
a4589dbb | 457 | u32 alarms; |
363a12a4 | 458 | u8 caseopen; |
08c79950 RM |
459 | |
460 | u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */ | |
461 | u8 pwm_enable[4]; /* 1->manual | |
41e9a062 DB |
462 | 2->thermal cruise mode (also called SmartFan I) |
463 | 3->fan speed cruise mode | |
e7e1ca6e | 464 | 4->variable thermal cruise (also called |
b84bb518 GR |
465 | SmartFan III) |
466 | 5->enhanced variable thermal cruise (also called | |
467 | SmartFan IV) */ | |
468 | u8 pwm_enable_orig[4]; /* original value of pwm_enable */ | |
237c8d2f | 469 | u8 pwm_num; /* number of pwm */ |
08c79950 RM |
470 | u8 pwm[4]; |
471 | u8 target_temp[4]; | |
472 | u8 tolerance[4]; | |
473 | ||
41e9a062 DB |
474 | u8 fan_start_output[4]; /* minimum fan speed when spinning up */ |
475 | u8 fan_stop_output[4]; /* minimum fan speed when spinning down */ | |
476 | u8 fan_stop_time[4]; /* time at minimum before disabling fan */ | |
477 | u8 fan_max_output[4]; /* maximum fan speed */ | |
478 | u8 fan_step_output[4]; /* rate of change output value */ | |
fc18d6c0 JD |
479 | |
480 | u8 vid; | |
481 | u8 vrm; | |
a157d06d | 482 | |
ec3e5a16 | 483 | u16 have_temp; |
a157d06d | 484 | u8 in6_skip; |
08e7e278 JD |
485 | }; |
486 | ||
1ea6dd38 DH |
487 | struct w83627ehf_sio_data { |
488 | int sioreg; | |
489 | enum kinds kind; | |
490 | }; | |
491 | ||
83cc8985 GR |
492 | /* |
493 | * On older chips, only registers 0x50-0x5f are banked. | |
494 | * On more recent chips, all registers are banked. | |
495 | * Assume that is the case and set the bank number for each access. | |
496 | * Cache the bank number so it only needs to be set if it changes. | |
497 | */ | |
1ea6dd38 | 498 | static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg) |
08e7e278 | 499 | { |
83cc8985 GR |
500 | u8 bank = reg >> 8; |
501 | if (data->bank != bank) { | |
1ea6dd38 | 502 | outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET); |
83cc8985 GR |
503 | outb_p(bank, data->addr + DATA_REG_OFFSET); |
504 | data->bank = bank; | |
08e7e278 JD |
505 | } |
506 | } | |
507 | ||
1ea6dd38 | 508 | static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg) |
08e7e278 | 509 | { |
08e7e278 JD |
510 | int res, word_sized = is_word_sized(reg); |
511 | ||
9a61bf63 | 512 | mutex_lock(&data->lock); |
08e7e278 | 513 | |
1ea6dd38 DH |
514 | w83627ehf_set_bank(data, reg); |
515 | outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET); | |
516 | res = inb_p(data->addr + DATA_REG_OFFSET); | |
08e7e278 JD |
517 | if (word_sized) { |
518 | outb_p((reg & 0xff) + 1, | |
1ea6dd38 DH |
519 | data->addr + ADDR_REG_OFFSET); |
520 | res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET); | |
08e7e278 | 521 | } |
08e7e278 | 522 | |
9a61bf63 | 523 | mutex_unlock(&data->lock); |
08e7e278 JD |
524 | return res; |
525 | } | |
526 | ||
e7e1ca6e GR |
527 | static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg, |
528 | u16 value) | |
08e7e278 | 529 | { |
08e7e278 JD |
530 | int word_sized = is_word_sized(reg); |
531 | ||
9a61bf63 | 532 | mutex_lock(&data->lock); |
08e7e278 | 533 | |
1ea6dd38 DH |
534 | w83627ehf_set_bank(data, reg); |
535 | outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET); | |
08e7e278 | 536 | if (word_sized) { |
1ea6dd38 | 537 | outb_p(value >> 8, data->addr + DATA_REG_OFFSET); |
08e7e278 | 538 | outb_p((reg & 0xff) + 1, |
1ea6dd38 | 539 | data->addr + ADDR_REG_OFFSET); |
08e7e278 | 540 | } |
1ea6dd38 | 541 | outb_p(value & 0xff, data->addr + DATA_REG_OFFSET); |
08e7e278 | 542 | |
9a61bf63 | 543 | mutex_unlock(&data->lock); |
08e7e278 JD |
544 | return 0; |
545 | } | |
546 | ||
c5794cfa JD |
547 | /* We left-align 8-bit temperature values to make the code simpler */ |
548 | static u16 w83627ehf_read_temp(struct w83627ehf_data *data, u16 reg) | |
549 | { | |
550 | u16 res; | |
551 | ||
552 | res = w83627ehf_read_value(data, reg); | |
553 | if (!is_word_sized(reg)) | |
554 | res <<= 8; | |
555 | ||
556 | return res; | |
557 | } | |
558 | ||
559 | static int w83627ehf_write_temp(struct w83627ehf_data *data, u16 reg, | |
560 | u16 value) | |
561 | { | |
562 | if (!is_word_sized(reg)) | |
563 | value >>= 8; | |
564 | return w83627ehf_write_value(data, reg, value); | |
565 | } | |
566 | ||
ec3e5a16 GR |
567 | /* This function assumes that the caller holds data->update_lock */ |
568 | static void nct6775_write_fan_div(struct w83627ehf_data *data, int nr) | |
569 | { | |
570 | u8 reg; | |
571 | ||
572 | switch (nr) { | |
573 | case 0: | |
574 | reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x70) | |
575 | | (data->fan_div[0] & 0x7); | |
576 | w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg); | |
577 | break; | |
578 | case 1: | |
579 | reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x7) | |
580 | | ((data->fan_div[1] << 4) & 0x70); | |
581 | w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg); | |
582 | case 2: | |
583 | reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x70) | |
584 | | (data->fan_div[2] & 0x7); | |
585 | w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg); | |
586 | break; | |
587 | case 3: | |
588 | reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x7) | |
589 | | ((data->fan_div[3] << 4) & 0x70); | |
590 | w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg); | |
591 | break; | |
592 | } | |
593 | } | |
594 | ||
08e7e278 | 595 | /* This function assumes that the caller holds data->update_lock */ |
1ea6dd38 | 596 | static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr) |
08e7e278 | 597 | { |
08e7e278 JD |
598 | u8 reg; |
599 | ||
600 | switch (nr) { | |
601 | case 0: | |
1ea6dd38 | 602 | reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf) |
08e7e278 | 603 | | ((data->fan_div[0] & 0x03) << 4); |
14992c7e RM |
604 | /* fan5 input control bit is write only, compute the value */ |
605 | reg |= (data->has_fan & (1 << 4)) ? 1 : 0; | |
1ea6dd38 DH |
606 | w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg); |
607 | reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf) | |
08e7e278 | 608 | | ((data->fan_div[0] & 0x04) << 3); |
1ea6dd38 | 609 | w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg); |
08e7e278 JD |
610 | break; |
611 | case 1: | |
1ea6dd38 | 612 | reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f) |
08e7e278 | 613 | | ((data->fan_div[1] & 0x03) << 6); |
14992c7e RM |
614 | /* fan5 input control bit is write only, compute the value */ |
615 | reg |= (data->has_fan & (1 << 4)) ? 1 : 0; | |
1ea6dd38 DH |
616 | w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg); |
617 | reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf) | |
08e7e278 | 618 | | ((data->fan_div[1] & 0x04) << 4); |
1ea6dd38 | 619 | w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg); |
08e7e278 JD |
620 | break; |
621 | case 2: | |
1ea6dd38 | 622 | reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f) |
08e7e278 | 623 | | ((data->fan_div[2] & 0x03) << 6); |
1ea6dd38 DH |
624 | w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg); |
625 | reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f) | |
08e7e278 | 626 | | ((data->fan_div[2] & 0x04) << 5); |
1ea6dd38 | 627 | w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg); |
08e7e278 JD |
628 | break; |
629 | case 3: | |
1ea6dd38 | 630 | reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc) |
08e7e278 | 631 | | (data->fan_div[3] & 0x03); |
1ea6dd38 DH |
632 | w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg); |
633 | reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f) | |
08e7e278 | 634 | | ((data->fan_div[3] & 0x04) << 5); |
1ea6dd38 | 635 | w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg); |
08e7e278 JD |
636 | break; |
637 | case 4: | |
1ea6dd38 | 638 | reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73) |
33725ad3 | 639 | | ((data->fan_div[4] & 0x03) << 2) |
08e7e278 | 640 | | ((data->fan_div[4] & 0x04) << 5); |
1ea6dd38 | 641 | w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg); |
08e7e278 JD |
642 | break; |
643 | } | |
644 | } | |
645 | ||
ec3e5a16 GR |
646 | static void w83627ehf_write_fan_div_common(struct device *dev, |
647 | struct w83627ehf_data *data, int nr) | |
648 | { | |
649 | struct w83627ehf_sio_data *sio_data = dev->platform_data; | |
650 | ||
651 | if (sio_data->kind == nct6776) | |
652 | ; /* no dividers, do nothing */ | |
653 | else if (sio_data->kind == nct6775) | |
654 | nct6775_write_fan_div(data, nr); | |
655 | else | |
656 | w83627ehf_write_fan_div(data, nr); | |
657 | } | |
658 | ||
659 | static void nct6775_update_fan_div(struct w83627ehf_data *data) | |
660 | { | |
661 | u8 i; | |
662 | ||
663 | i = w83627ehf_read_value(data, NCT6775_REG_FANDIV1); | |
664 | data->fan_div[0] = i & 0x7; | |
665 | data->fan_div[1] = (i & 0x70) >> 4; | |
666 | i = w83627ehf_read_value(data, NCT6775_REG_FANDIV2); | |
667 | data->fan_div[2] = i & 0x7; | |
668 | if (data->has_fan & (1<<3)) | |
669 | data->fan_div[3] = (i & 0x70) >> 4; | |
670 | } | |
671 | ||
ea7be66c MH |
672 | static void w83627ehf_update_fan_div(struct w83627ehf_data *data) |
673 | { | |
674 | int i; | |
675 | ||
676 | i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1); | |
677 | data->fan_div[0] = (i >> 4) & 0x03; | |
678 | data->fan_div[1] = (i >> 6) & 0x03; | |
679 | i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2); | |
680 | data->fan_div[2] = (i >> 6) & 0x03; | |
681 | i = w83627ehf_read_value(data, W83627EHF_REG_VBAT); | |
682 | data->fan_div[0] |= (i >> 3) & 0x04; | |
683 | data->fan_div[1] |= (i >> 4) & 0x04; | |
684 | data->fan_div[2] |= (i >> 5) & 0x04; | |
685 | if (data->has_fan & ((1 << 3) | (1 << 4))) { | |
686 | i = w83627ehf_read_value(data, W83627EHF_REG_DIODE); | |
687 | data->fan_div[3] = i & 0x03; | |
688 | data->fan_div[4] = ((i >> 2) & 0x03) | |
689 | | ((i >> 5) & 0x04); | |
690 | } | |
691 | if (data->has_fan & (1 << 3)) { | |
692 | i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT); | |
693 | data->fan_div[3] |= (i >> 5) & 0x04; | |
694 | } | |
695 | } | |
696 | ||
ec3e5a16 GR |
697 | static void w83627ehf_update_fan_div_common(struct device *dev, |
698 | struct w83627ehf_data *data) | |
699 | { | |
700 | struct w83627ehf_sio_data *sio_data = dev->platform_data; | |
701 | ||
702 | if (sio_data->kind == nct6776) | |
703 | ; /* no dividers, do nothing */ | |
704 | else if (sio_data->kind == nct6775) | |
705 | nct6775_update_fan_div(data); | |
706 | else | |
707 | w83627ehf_update_fan_div(data); | |
708 | } | |
709 | ||
710 | static void nct6775_update_pwm(struct w83627ehf_data *data) | |
711 | { | |
712 | int i; | |
713 | int pwmcfg, fanmodecfg; | |
714 | ||
715 | for (i = 0; i < data->pwm_num; i++) { | |
716 | pwmcfg = w83627ehf_read_value(data, | |
717 | W83627EHF_REG_PWM_ENABLE[i]); | |
718 | fanmodecfg = w83627ehf_read_value(data, | |
719 | NCT6775_REG_FAN_MODE[i]); | |
720 | data->pwm_mode[i] = | |
721 | ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1; | |
722 | data->pwm_enable[i] = ((fanmodecfg >> 4) & 7) + 1; | |
723 | data->tolerance[i] = fanmodecfg & 0x0f; | |
724 | data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]); | |
725 | } | |
726 | } | |
727 | ||
728 | static void w83627ehf_update_pwm(struct w83627ehf_data *data) | |
729 | { | |
730 | int i; | |
731 | int pwmcfg = 0, tolerance = 0; /* shut up the compiler */ | |
732 | ||
733 | for (i = 0; i < data->pwm_num; i++) { | |
734 | if (!(data->has_fan & (1 << i))) | |
735 | continue; | |
736 | ||
737 | /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */ | |
738 | if (i != 1) { | |
739 | pwmcfg = w83627ehf_read_value(data, | |
740 | W83627EHF_REG_PWM_ENABLE[i]); | |
741 | tolerance = w83627ehf_read_value(data, | |
742 | W83627EHF_REG_TOLERANCE[i]); | |
743 | } | |
744 | data->pwm_mode[i] = | |
745 | ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1; | |
746 | data->pwm_enable[i] = ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i]) | |
747 | & 3) + 1; | |
748 | data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]); | |
749 | ||
750 | data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0)) & 0x0f; | |
751 | } | |
752 | } | |
753 | ||
754 | static void w83627ehf_update_pwm_common(struct device *dev, | |
755 | struct w83627ehf_data *data) | |
756 | { | |
757 | struct w83627ehf_sio_data *sio_data = dev->platform_data; | |
758 | ||
759 | if (sio_data->kind == nct6775 || sio_data->kind == nct6776) | |
760 | nct6775_update_pwm(data); | |
761 | else | |
762 | w83627ehf_update_pwm(data); | |
763 | } | |
764 | ||
08e7e278 JD |
765 | static struct w83627ehf_data *w83627ehf_update_device(struct device *dev) |
766 | { | |
1ea6dd38 | 767 | struct w83627ehf_data *data = dev_get_drvdata(dev); |
ec3e5a16 GR |
768 | struct w83627ehf_sio_data *sio_data = dev->platform_data; |
769 | ||
08e7e278 JD |
770 | int i; |
771 | ||
9a61bf63 | 772 | mutex_lock(&data->update_lock); |
08e7e278 | 773 | |
6b3e4645 | 774 | if (time_after(jiffies, data->last_updated + HZ + HZ/2) |
08e7e278 JD |
775 | || !data->valid) { |
776 | /* Fan clock dividers */ | |
ec3e5a16 | 777 | w83627ehf_update_fan_div_common(dev, data); |
08e7e278 | 778 | |
cf0676fe | 779 | /* Measured voltages and limits */ |
1ea6dd38 | 780 | for (i = 0; i < data->in_num; i++) { |
389ef65d JD |
781 | if ((i == 6) && data->in6_skip) |
782 | continue; | |
783 | ||
1ea6dd38 | 784 | data->in[i] = w83627ehf_read_value(data, |
cf0676fe | 785 | W83627EHF_REG_IN(i)); |
1ea6dd38 | 786 | data->in_min[i] = w83627ehf_read_value(data, |
cf0676fe | 787 | W83627EHF_REG_IN_MIN(i)); |
1ea6dd38 | 788 | data->in_max[i] = w83627ehf_read_value(data, |
cf0676fe RM |
789 | W83627EHF_REG_IN_MAX(i)); |
790 | } | |
791 | ||
08e7e278 JD |
792 | /* Measured fan speeds and limits */ |
793 | for (i = 0; i < 5; i++) { | |
3382a918 GR |
794 | u16 reg; |
795 | ||
08e7e278 JD |
796 | if (!(data->has_fan & (1 << i))) |
797 | continue; | |
798 | ||
3382a918 GR |
799 | reg = w83627ehf_read_value(data, data->REG_FAN[i]); |
800 | data->rpm[i] = data->fan_from_reg(reg, | |
801 | data->fan_div[i]); | |
ec3e5a16 GR |
802 | |
803 | if (data->has_fan_min & (1 << i)) | |
804 | data->fan_min[i] = w83627ehf_read_value(data, | |
279af1a9 | 805 | data->REG_FAN_MIN[i]); |
08e7e278 JD |
806 | |
807 | /* If we failed to measure the fan speed and clock | |
808 | divider can be increased, let's try that for next | |
809 | time */ | |
26bc440e | 810 | if (data->has_fan_div |
3382a918 GR |
811 | && (reg >= 0xff || (sio_data->kind == nct6775 |
812 | && reg == 0x00)) | |
ec3e5a16 | 813 | && data->fan_div[i] < 0x07) { |
e7e1ca6e | 814 | dev_dbg(dev, "Increasing fan%d " |
08e7e278 | 815 | "clock divider from %u to %u\n", |
33725ad3 | 816 | i + 1, div_from_reg(data->fan_div[i]), |
08e7e278 JD |
817 | div_from_reg(data->fan_div[i] + 1)); |
818 | data->fan_div[i]++; | |
ec3e5a16 | 819 | w83627ehf_write_fan_div_common(dev, data, i); |
08e7e278 | 820 | /* Preserve min limit if possible */ |
ec3e5a16 GR |
821 | if ((data->has_fan_min & (1 << i)) |
822 | && data->fan_min[i] >= 2 | |
08e7e278 | 823 | && data->fan_min[i] != 255) |
1ea6dd38 | 824 | w83627ehf_write_value(data, |
279af1a9 | 825 | data->REG_FAN_MIN[i], |
08e7e278 JD |
826 | (data->fan_min[i] /= 2)); |
827 | } | |
828 | } | |
829 | ||
ec3e5a16 GR |
830 | w83627ehf_update_pwm_common(dev, data); |
831 | ||
da2e0255 GR |
832 | for (i = 0; i < data->pwm_num; i++) { |
833 | if (!(data->has_fan & (1 << i))) | |
834 | continue; | |
835 | ||
ec3e5a16 GR |
836 | data->fan_start_output[i] = |
837 | w83627ehf_read_value(data, | |
838 | data->REG_FAN_START_OUTPUT[i]); | |
839 | data->fan_stop_output[i] = | |
840 | w83627ehf_read_value(data, | |
841 | data->REG_FAN_STOP_OUTPUT[i]); | |
842 | data->fan_stop_time[i] = | |
843 | w83627ehf_read_value(data, | |
844 | data->REG_FAN_STOP_TIME[i]); | |
845 | ||
846 | if (data->REG_FAN_MAX_OUTPUT && | |
847 | data->REG_FAN_MAX_OUTPUT[i] != 0xff) | |
da2e0255 GR |
848 | data->fan_max_output[i] = |
849 | w83627ehf_read_value(data, | |
ec3e5a16 | 850 | data->REG_FAN_MAX_OUTPUT[i]); |
da2e0255 | 851 | |
ec3e5a16 GR |
852 | if (data->REG_FAN_STEP_OUTPUT && |
853 | data->REG_FAN_STEP_OUTPUT[i] != 0xff) | |
da2e0255 GR |
854 | data->fan_step_output[i] = |
855 | w83627ehf_read_value(data, | |
ec3e5a16 | 856 | data->REG_FAN_STEP_OUTPUT[i]); |
da2e0255 | 857 | |
08c79950 | 858 | data->target_temp[i] = |
1ea6dd38 | 859 | w83627ehf_read_value(data, |
279af1a9 | 860 | data->REG_TARGET[i]) & |
08c79950 | 861 | (data->pwm_mode[i] == 1 ? 0x7f : 0xff); |
08c79950 RM |
862 | } |
863 | ||
08e7e278 | 864 | /* Measured temperatures and limits */ |
d36cf32c GR |
865 | for (i = 0; i < NUM_REG_TEMP; i++) { |
866 | if (!(data->have_temp & (1 << i))) | |
867 | continue; | |
c5794cfa | 868 | data->temp[i] = w83627ehf_read_temp(data, |
ec3e5a16 GR |
869 | data->reg_temp[i]); |
870 | if (data->reg_temp_over[i]) | |
871 | data->temp_max[i] | |
c5794cfa | 872 | = w83627ehf_read_temp(data, |
ec3e5a16 GR |
873 | data->reg_temp_over[i]); |
874 | if (data->reg_temp_hyst[i]) | |
875 | data->temp_max_hyst[i] | |
c5794cfa | 876 | = w83627ehf_read_temp(data, |
ec3e5a16 | 877 | data->reg_temp_hyst[i]); |
08e7e278 JD |
878 | } |
879 | ||
1ea6dd38 | 880 | data->alarms = w83627ehf_read_value(data, |
a4589dbb | 881 | W83627EHF_REG_ALARM1) | |
1ea6dd38 | 882 | (w83627ehf_read_value(data, |
a4589dbb | 883 | W83627EHF_REG_ALARM2) << 8) | |
1ea6dd38 | 884 | (w83627ehf_read_value(data, |
a4589dbb JD |
885 | W83627EHF_REG_ALARM3) << 16); |
886 | ||
363a12a4 DA |
887 | data->caseopen = w83627ehf_read_value(data, |
888 | W83627EHF_REG_CASEOPEN_DET); | |
889 | ||
08e7e278 JD |
890 | data->last_updated = jiffies; |
891 | data->valid = 1; | |
892 | } | |
893 | ||
9a61bf63 | 894 | mutex_unlock(&data->update_lock); |
08e7e278 JD |
895 | return data; |
896 | } | |
897 | ||
898 | /* | |
899 | * Sysfs callback functions | |
900 | */ | |
cf0676fe RM |
901 | #define show_in_reg(reg) \ |
902 | static ssize_t \ | |
903 | show_##reg(struct device *dev, struct device_attribute *attr, \ | |
904 | char *buf) \ | |
905 | { \ | |
906 | struct w83627ehf_data *data = w83627ehf_update_device(dev); \ | |
e7e1ca6e GR |
907 | struct sensor_device_attribute *sensor_attr = \ |
908 | to_sensor_dev_attr(attr); \ | |
cf0676fe RM |
909 | int nr = sensor_attr->index; \ |
910 | return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr)); \ | |
911 | } | |
912 | show_in_reg(in) | |
913 | show_in_reg(in_min) | |
914 | show_in_reg(in_max) | |
915 | ||
916 | #define store_in_reg(REG, reg) \ | |
917 | static ssize_t \ | |
e7e1ca6e GR |
918 | store_in_##reg(struct device *dev, struct device_attribute *attr, \ |
919 | const char *buf, size_t count) \ | |
cf0676fe | 920 | { \ |
1ea6dd38 | 921 | struct w83627ehf_data *data = dev_get_drvdata(dev); \ |
e7e1ca6e GR |
922 | struct sensor_device_attribute *sensor_attr = \ |
923 | to_sensor_dev_attr(attr); \ | |
cf0676fe | 924 | int nr = sensor_attr->index; \ |
bce26c58 GR |
925 | unsigned long val; \ |
926 | int err; \ | |
927 | err = strict_strtoul(buf, 10, &val); \ | |
928 | if (err < 0) \ | |
929 | return err; \ | |
cf0676fe RM |
930 | mutex_lock(&data->update_lock); \ |
931 | data->in_##reg[nr] = in_to_reg(val, nr); \ | |
1ea6dd38 | 932 | w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \ |
cf0676fe RM |
933 | data->in_##reg[nr]); \ |
934 | mutex_unlock(&data->update_lock); \ | |
935 | return count; \ | |
936 | } | |
937 | ||
938 | store_in_reg(MIN, min) | |
939 | store_in_reg(MAX, max) | |
940 | ||
e7e1ca6e GR |
941 | static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, |
942 | char *buf) | |
a4589dbb JD |
943 | { |
944 | struct w83627ehf_data *data = w83627ehf_update_device(dev); | |
945 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
946 | int nr = sensor_attr->index; | |
947 | return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01); | |
948 | } | |
949 | ||
cf0676fe RM |
950 | static struct sensor_device_attribute sda_in_input[] = { |
951 | SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0), | |
952 | SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1), | |
953 | SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2), | |
954 | SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3), | |
955 | SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4), | |
956 | SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5), | |
957 | SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6), | |
958 | SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7), | |
959 | SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8), | |
960 | SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9), | |
961 | }; | |
962 | ||
a4589dbb JD |
963 | static struct sensor_device_attribute sda_in_alarm[] = { |
964 | SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0), | |
965 | SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1), | |
966 | SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2), | |
967 | SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3), | |
968 | SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8), | |
969 | SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21), | |
970 | SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20), | |
971 | SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16), | |
972 | SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17), | |
973 | SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19), | |
974 | }; | |
975 | ||
cf0676fe | 976 | static struct sensor_device_attribute sda_in_min[] = { |
e7e1ca6e GR |
977 | SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0), |
978 | SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1), | |
979 | SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2), | |
980 | SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3), | |
981 | SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4), | |
982 | SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5), | |
983 | SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6), | |
984 | SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7), | |
985 | SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8), | |
986 | SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9), | |
cf0676fe RM |
987 | }; |
988 | ||
989 | static struct sensor_device_attribute sda_in_max[] = { | |
e7e1ca6e GR |
990 | SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0), |
991 | SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1), | |
992 | SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2), | |
993 | SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3), | |
994 | SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4), | |
995 | SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5), | |
996 | SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6), | |
997 | SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7), | |
998 | SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8), | |
999 | SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9), | |
cf0676fe RM |
1000 | }; |
1001 | ||
ec3e5a16 GR |
1002 | static ssize_t |
1003 | show_fan(struct device *dev, struct device_attribute *attr, char *buf) | |
1004 | { | |
1005 | struct w83627ehf_data *data = w83627ehf_update_device(dev); | |
1006 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
1007 | int nr = sensor_attr->index; | |
3382a918 | 1008 | return sprintf(buf, "%d\n", data->rpm[nr]); |
ec3e5a16 GR |
1009 | } |
1010 | ||
1011 | static ssize_t | |
1012 | show_fan_min(struct device *dev, struct device_attribute *attr, char *buf) | |
1013 | { | |
1014 | struct w83627ehf_data *data = w83627ehf_update_device(dev); | |
1015 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
1016 | int nr = sensor_attr->index; | |
1017 | return sprintf(buf, "%d\n", | |
26bc440e GR |
1018 | data->fan_from_reg_min(data->fan_min[nr], |
1019 | data->fan_div[nr])); | |
08e7e278 | 1020 | } |
08e7e278 JD |
1021 | |
1022 | static ssize_t | |
412fec82 YM |
1023 | show_fan_div(struct device *dev, struct device_attribute *attr, |
1024 | char *buf) | |
08e7e278 JD |
1025 | { |
1026 | struct w83627ehf_data *data = w83627ehf_update_device(dev); | |
412fec82 YM |
1027 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
1028 | int nr = sensor_attr->index; | |
1029 | return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr])); | |
08e7e278 JD |
1030 | } |
1031 | ||
1032 | static ssize_t | |
412fec82 YM |
1033 | store_fan_min(struct device *dev, struct device_attribute *attr, |
1034 | const char *buf, size_t count) | |
08e7e278 | 1035 | { |
1ea6dd38 | 1036 | struct w83627ehf_data *data = dev_get_drvdata(dev); |
412fec82 YM |
1037 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
1038 | int nr = sensor_attr->index; | |
bce26c58 GR |
1039 | unsigned long val; |
1040 | int err; | |
08e7e278 JD |
1041 | unsigned int reg; |
1042 | u8 new_div; | |
1043 | ||
bce26c58 GR |
1044 | err = strict_strtoul(buf, 10, &val); |
1045 | if (err < 0) | |
1046 | return err; | |
1047 | ||
9a61bf63 | 1048 | mutex_lock(&data->update_lock); |
26bc440e GR |
1049 | if (!data->has_fan_div) { |
1050 | /* | |
1051 | * Only NCT6776F for now, so we know that this is a 13 bit | |
1052 | * register | |
1053 | */ | |
ec3e5a16 GR |
1054 | if (!val) { |
1055 | val = 0xff1f; | |
1056 | } else { | |
1057 | if (val > 1350000U) | |
1058 | val = 135000U; | |
1059 | val = 1350000U / val; | |
1060 | val = (val & 0x1f) | ((val << 3) & 0xff00); | |
1061 | } | |
1062 | data->fan_min[nr] = val; | |
1063 | goto done; /* Leave fan divider alone */ | |
1064 | } | |
08e7e278 JD |
1065 | if (!val) { |
1066 | /* No min limit, alarm disabled */ | |
1067 | data->fan_min[nr] = 255; | |
1068 | new_div = data->fan_div[nr]; /* No change */ | |
1069 | dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1); | |
1070 | } else if ((reg = 1350000U / val) >= 128 * 255) { | |
1071 | /* Speed below this value cannot possibly be represented, | |
1072 | even with the highest divider (128) */ | |
1073 | data->fan_min[nr] = 254; | |
1074 | new_div = 7; /* 128 == (1 << 7) */ | |
bce26c58 | 1075 | dev_warn(dev, "fan%u low limit %lu below minimum %u, set to " |
ec3e5a16 | 1076 | "minimum\n", nr + 1, val, |
26bc440e | 1077 | data->fan_from_reg_min(254, 7)); |
08e7e278 JD |
1078 | } else if (!reg) { |
1079 | /* Speed above this value cannot possibly be represented, | |
1080 | even with the lowest divider (1) */ | |
1081 | data->fan_min[nr] = 1; | |
1082 | new_div = 0; /* 1 == (1 << 0) */ | |
bce26c58 | 1083 | dev_warn(dev, "fan%u low limit %lu above maximum %u, set to " |
ec3e5a16 | 1084 | "maximum\n", nr + 1, val, |
26bc440e | 1085 | data->fan_from_reg_min(1, 0)); |
08e7e278 JD |
1086 | } else { |
1087 | /* Automatically pick the best divider, i.e. the one such | |
1088 | that the min limit will correspond to a register value | |
1089 | in the 96..192 range */ | |
1090 | new_div = 0; | |
1091 | while (reg > 192 && new_div < 7) { | |
1092 | reg >>= 1; | |
1093 | new_div++; | |
1094 | } | |
1095 | data->fan_min[nr] = reg; | |
1096 | } | |
1097 | ||
1098 | /* Write both the fan clock divider (if it changed) and the new | |
1099 | fan min (unconditionally) */ | |
1100 | if (new_div != data->fan_div[nr]) { | |
08e7e278 JD |
1101 | dev_dbg(dev, "fan%u clock divider changed from %u to %u\n", |
1102 | nr + 1, div_from_reg(data->fan_div[nr]), | |
1103 | div_from_reg(new_div)); | |
1104 | data->fan_div[nr] = new_div; | |
ec3e5a16 | 1105 | w83627ehf_write_fan_div_common(dev, data, nr); |
6b3e4645 JD |
1106 | /* Give the chip time to sample a new speed value */ |
1107 | data->last_updated = jiffies; | |
08e7e278 | 1108 | } |
ec3e5a16 | 1109 | done: |
279af1a9 | 1110 | w83627ehf_write_value(data, data->REG_FAN_MIN[nr], |
08e7e278 | 1111 | data->fan_min[nr]); |
9a61bf63 | 1112 | mutex_unlock(&data->update_lock); |
08e7e278 JD |
1113 | |
1114 | return count; | |
1115 | } | |
1116 | ||
412fec82 YM |
1117 | static struct sensor_device_attribute sda_fan_input[] = { |
1118 | SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0), | |
1119 | SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1), | |
1120 | SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2), | |
1121 | SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3), | |
1122 | SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4), | |
1123 | }; | |
08e7e278 | 1124 | |
a4589dbb JD |
1125 | static struct sensor_device_attribute sda_fan_alarm[] = { |
1126 | SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6), | |
1127 | SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7), | |
1128 | SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11), | |
1129 | SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10), | |
1130 | SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23), | |
1131 | }; | |
1132 | ||
412fec82 YM |
1133 | static struct sensor_device_attribute sda_fan_min[] = { |
1134 | SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min, | |
1135 | store_fan_min, 0), | |
1136 | SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min, | |
1137 | store_fan_min, 1), | |
1138 | SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min, | |
1139 | store_fan_min, 2), | |
1140 | SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min, | |
1141 | store_fan_min, 3), | |
1142 | SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min, | |
1143 | store_fan_min, 4), | |
1144 | }; | |
08e7e278 | 1145 | |
412fec82 YM |
1146 | static struct sensor_device_attribute sda_fan_div[] = { |
1147 | SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0), | |
1148 | SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1), | |
1149 | SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2), | |
1150 | SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3), | |
1151 | SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4), | |
1152 | }; | |
1153 | ||
d36cf32c GR |
1154 | static ssize_t |
1155 | show_temp_label(struct device *dev, struct device_attribute *attr, char *buf) | |
1156 | { | |
1157 | struct w83627ehf_data *data = w83627ehf_update_device(dev); | |
1158 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
1159 | int nr = sensor_attr->index; | |
1160 | return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]); | |
1161 | } | |
1162 | ||
ec3e5a16 | 1163 | #define show_temp_reg(addr, reg) \ |
08e7e278 | 1164 | static ssize_t \ |
412fec82 YM |
1165 | show_##reg(struct device *dev, struct device_attribute *attr, \ |
1166 | char *buf) \ | |
08e7e278 JD |
1167 | { \ |
1168 | struct w83627ehf_data *data = w83627ehf_update_device(dev); \ | |
e7e1ca6e GR |
1169 | struct sensor_device_attribute *sensor_attr = \ |
1170 | to_sensor_dev_attr(attr); \ | |
412fec82 | 1171 | int nr = sensor_attr->index; \ |
c5794cfa | 1172 | return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->reg[nr])); \ |
08e7e278 | 1173 | } |
ec3e5a16 GR |
1174 | show_temp_reg(reg_temp, temp); |
1175 | show_temp_reg(reg_temp_over, temp_max); | |
1176 | show_temp_reg(reg_temp_hyst, temp_max_hyst); | |
08e7e278 | 1177 | |
ec3e5a16 | 1178 | #define store_temp_reg(addr, reg) \ |
08e7e278 | 1179 | static ssize_t \ |
412fec82 YM |
1180 | store_##reg(struct device *dev, struct device_attribute *attr, \ |
1181 | const char *buf, size_t count) \ | |
08e7e278 | 1182 | { \ |
1ea6dd38 | 1183 | struct w83627ehf_data *data = dev_get_drvdata(dev); \ |
e7e1ca6e GR |
1184 | struct sensor_device_attribute *sensor_attr = \ |
1185 | to_sensor_dev_attr(attr); \ | |
412fec82 | 1186 | int nr = sensor_attr->index; \ |
bce26c58 GR |
1187 | int err; \ |
1188 | long val; \ | |
1189 | err = strict_strtol(buf, 10, &val); \ | |
1190 | if (err < 0) \ | |
1191 | return err; \ | |
9a61bf63 | 1192 | mutex_lock(&data->update_lock); \ |
c5794cfa JD |
1193 | data->reg[nr] = LM75_TEMP_TO_REG(val); \ |
1194 | w83627ehf_write_temp(data, data->addr[nr], data->reg[nr]); \ | |
9a61bf63 | 1195 | mutex_unlock(&data->update_lock); \ |
08e7e278 JD |
1196 | return count; \ |
1197 | } | |
ec3e5a16 GR |
1198 | store_temp_reg(reg_temp_over, temp_max); |
1199 | store_temp_reg(reg_temp_hyst, temp_max_hyst); | |
08e7e278 | 1200 | |
da667365 JD |
1201 | static ssize_t |
1202 | show_temp_type(struct device *dev, struct device_attribute *attr, char *buf) | |
1203 | { | |
1204 | struct w83627ehf_data *data = w83627ehf_update_device(dev); | |
1205 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
1206 | int nr = sensor_attr->index; | |
1207 | return sprintf(buf, "%d\n", (int)data->temp_type[nr]); | |
1208 | } | |
1209 | ||
a157d06d | 1210 | static struct sensor_device_attribute sda_temp_input[] = { |
bce26c58 GR |
1211 | SENSOR_ATTR(temp1_input, S_IRUGO, show_temp, NULL, 0), |
1212 | SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 1), | |
1213 | SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 2), | |
d36cf32c | 1214 | SENSOR_ATTR(temp4_input, S_IRUGO, show_temp, NULL, 3), |
ec3e5a16 GR |
1215 | SENSOR_ATTR(temp5_input, S_IRUGO, show_temp, NULL, 4), |
1216 | SENSOR_ATTR(temp6_input, S_IRUGO, show_temp, NULL, 5), | |
1217 | SENSOR_ATTR(temp7_input, S_IRUGO, show_temp, NULL, 6), | |
1218 | SENSOR_ATTR(temp8_input, S_IRUGO, show_temp, NULL, 7), | |
1219 | SENSOR_ATTR(temp9_input, S_IRUGO, show_temp, NULL, 8), | |
d36cf32c GR |
1220 | }; |
1221 | ||
1222 | static struct sensor_device_attribute sda_temp_label[] = { | |
1223 | SENSOR_ATTR(temp1_label, S_IRUGO, show_temp_label, NULL, 0), | |
1224 | SENSOR_ATTR(temp2_label, S_IRUGO, show_temp_label, NULL, 1), | |
1225 | SENSOR_ATTR(temp3_label, S_IRUGO, show_temp_label, NULL, 2), | |
1226 | SENSOR_ATTR(temp4_label, S_IRUGO, show_temp_label, NULL, 3), | |
ec3e5a16 GR |
1227 | SENSOR_ATTR(temp5_label, S_IRUGO, show_temp_label, NULL, 4), |
1228 | SENSOR_ATTR(temp6_label, S_IRUGO, show_temp_label, NULL, 5), | |
1229 | SENSOR_ATTR(temp7_label, S_IRUGO, show_temp_label, NULL, 6), | |
1230 | SENSOR_ATTR(temp8_label, S_IRUGO, show_temp_label, NULL, 7), | |
1231 | SENSOR_ATTR(temp9_label, S_IRUGO, show_temp_label, NULL, 8), | |
a157d06d GJ |
1232 | }; |
1233 | ||
1234 | static struct sensor_device_attribute sda_temp_max[] = { | |
bce26c58 | 1235 | SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp_max, |
412fec82 | 1236 | store_temp_max, 0), |
bce26c58 | 1237 | SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max, |
412fec82 | 1238 | store_temp_max, 1), |
bce26c58 GR |
1239 | SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max, |
1240 | store_temp_max, 2), | |
ec3e5a16 GR |
1241 | SENSOR_ATTR(temp4_max, S_IRUGO | S_IWUSR, show_temp_max, |
1242 | store_temp_max, 3), | |
1243 | SENSOR_ATTR(temp5_max, S_IRUGO | S_IWUSR, show_temp_max, | |
1244 | store_temp_max, 4), | |
1245 | SENSOR_ATTR(temp6_max, S_IRUGO | S_IWUSR, show_temp_max, | |
1246 | store_temp_max, 5), | |
1247 | SENSOR_ATTR(temp7_max, S_IRUGO | S_IWUSR, show_temp_max, | |
1248 | store_temp_max, 6), | |
1249 | SENSOR_ATTR(temp8_max, S_IRUGO | S_IWUSR, show_temp_max, | |
1250 | store_temp_max, 7), | |
1251 | SENSOR_ATTR(temp9_max, S_IRUGO | S_IWUSR, show_temp_max, | |
1252 | store_temp_max, 8), | |
a157d06d GJ |
1253 | }; |
1254 | ||
1255 | static struct sensor_device_attribute sda_temp_max_hyst[] = { | |
bce26c58 | 1256 | SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst, |
412fec82 | 1257 | store_temp_max_hyst, 0), |
bce26c58 | 1258 | SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst, |
412fec82 | 1259 | store_temp_max_hyst, 1), |
bce26c58 GR |
1260 | SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst, |
1261 | store_temp_max_hyst, 2), | |
ec3e5a16 GR |
1262 | SENSOR_ATTR(temp4_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst, |
1263 | store_temp_max_hyst, 3), | |
1264 | SENSOR_ATTR(temp5_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst, | |
1265 | store_temp_max_hyst, 4), | |
1266 | SENSOR_ATTR(temp6_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst, | |
1267 | store_temp_max_hyst, 5), | |
1268 | SENSOR_ATTR(temp7_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst, | |
1269 | store_temp_max_hyst, 6), | |
1270 | SENSOR_ATTR(temp8_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst, | |
1271 | store_temp_max_hyst, 7), | |
1272 | SENSOR_ATTR(temp9_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst, | |
1273 | store_temp_max_hyst, 8), | |
a157d06d GJ |
1274 | }; |
1275 | ||
1276 | static struct sensor_device_attribute sda_temp_alarm[] = { | |
a4589dbb JD |
1277 | SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4), |
1278 | SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5), | |
1279 | SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13), | |
a157d06d GJ |
1280 | }; |
1281 | ||
1282 | static struct sensor_device_attribute sda_temp_type[] = { | |
da667365 JD |
1283 | SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0), |
1284 | SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1), | |
1285 | SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2), | |
412fec82 | 1286 | }; |
08e7e278 | 1287 | |
08c79950 | 1288 | #define show_pwm_reg(reg) \ |
e7e1ca6e GR |
1289 | static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \ |
1290 | char *buf) \ | |
08c79950 RM |
1291 | { \ |
1292 | struct w83627ehf_data *data = w83627ehf_update_device(dev); \ | |
e7e1ca6e GR |
1293 | struct sensor_device_attribute *sensor_attr = \ |
1294 | to_sensor_dev_attr(attr); \ | |
08c79950 RM |
1295 | int nr = sensor_attr->index; \ |
1296 | return sprintf(buf, "%d\n", data->reg[nr]); \ | |
1297 | } | |
1298 | ||
1299 | show_pwm_reg(pwm_mode) | |
1300 | show_pwm_reg(pwm_enable) | |
1301 | show_pwm_reg(pwm) | |
1302 | ||
1303 | static ssize_t | |
1304 | store_pwm_mode(struct device *dev, struct device_attribute *attr, | |
1305 | const char *buf, size_t count) | |
1306 | { | |
1ea6dd38 | 1307 | struct w83627ehf_data *data = dev_get_drvdata(dev); |
08c79950 RM |
1308 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
1309 | int nr = sensor_attr->index; | |
bce26c58 GR |
1310 | unsigned long val; |
1311 | int err; | |
08c79950 RM |
1312 | u16 reg; |
1313 | ||
bce26c58 GR |
1314 | err = strict_strtoul(buf, 10, &val); |
1315 | if (err < 0) | |
1316 | return err; | |
1317 | ||
08c79950 RM |
1318 | if (val > 1) |
1319 | return -EINVAL; | |
1320 | mutex_lock(&data->update_lock); | |
1ea6dd38 | 1321 | reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]); |
08c79950 RM |
1322 | data->pwm_mode[nr] = val; |
1323 | reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]); | |
1324 | if (!val) | |
1325 | reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr]; | |
1ea6dd38 | 1326 | w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg); |
08c79950 RM |
1327 | mutex_unlock(&data->update_lock); |
1328 | return count; | |
1329 | } | |
1330 | ||
1331 | static ssize_t | |
1332 | store_pwm(struct device *dev, struct device_attribute *attr, | |
1333 | const char *buf, size_t count) | |
1334 | { | |
1ea6dd38 | 1335 | struct w83627ehf_data *data = dev_get_drvdata(dev); |
08c79950 RM |
1336 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
1337 | int nr = sensor_attr->index; | |
bce26c58 GR |
1338 | unsigned long val; |
1339 | int err; | |
1340 | ||
1341 | err = strict_strtoul(buf, 10, &val); | |
1342 | if (err < 0) | |
1343 | return err; | |
1344 | ||
1345 | val = SENSORS_LIMIT(val, 0, 255); | |
08c79950 RM |
1346 | |
1347 | mutex_lock(&data->update_lock); | |
1348 | data->pwm[nr] = val; | |
279af1a9 | 1349 | w83627ehf_write_value(data, data->REG_PWM[nr], val); |
08c79950 RM |
1350 | mutex_unlock(&data->update_lock); |
1351 | return count; | |
1352 | } | |
1353 | ||
1354 | static ssize_t | |
1355 | store_pwm_enable(struct device *dev, struct device_attribute *attr, | |
1356 | const char *buf, size_t count) | |
1357 | { | |
1ea6dd38 | 1358 | struct w83627ehf_data *data = dev_get_drvdata(dev); |
ec3e5a16 | 1359 | struct w83627ehf_sio_data *sio_data = dev->platform_data; |
08c79950 RM |
1360 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
1361 | int nr = sensor_attr->index; | |
bce26c58 GR |
1362 | unsigned long val; |
1363 | int err; | |
08c79950 RM |
1364 | u16 reg; |
1365 | ||
bce26c58 GR |
1366 | err = strict_strtoul(buf, 10, &val); |
1367 | if (err < 0) | |
1368 | return err; | |
1369 | ||
b84bb518 | 1370 | if (!val || (val > 4 && val != data->pwm_enable_orig[nr])) |
08c79950 | 1371 | return -EINVAL; |
ec3e5a16 GR |
1372 | /* SmartFan III mode is not supported on NCT6776F */ |
1373 | if (sio_data->kind == nct6776 && val == 4) | |
1374 | return -EINVAL; | |
1375 | ||
08c79950 | 1376 | mutex_lock(&data->update_lock); |
08c79950 | 1377 | data->pwm_enable[nr] = val; |
ec3e5a16 GR |
1378 | if (sio_data->kind == nct6775 || sio_data->kind == nct6776) { |
1379 | reg = w83627ehf_read_value(data, | |
1380 | NCT6775_REG_FAN_MODE[nr]); | |
1381 | reg &= 0x0f; | |
1382 | reg |= (val - 1) << 4; | |
1383 | w83627ehf_write_value(data, | |
1384 | NCT6775_REG_FAN_MODE[nr], reg); | |
1385 | } else { | |
1386 | reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]); | |
1387 | reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]); | |
1388 | reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr]; | |
1389 | w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg); | |
1390 | } | |
08c79950 RM |
1391 | mutex_unlock(&data->update_lock); |
1392 | return count; | |
1393 | } | |
1394 | ||
1395 | ||
1396 | #define show_tol_temp(reg) \ | |
1397 | static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \ | |
1398 | char *buf) \ | |
1399 | { \ | |
1400 | struct w83627ehf_data *data = w83627ehf_update_device(dev); \ | |
e7e1ca6e GR |
1401 | struct sensor_device_attribute *sensor_attr = \ |
1402 | to_sensor_dev_attr(attr); \ | |
08c79950 | 1403 | int nr = sensor_attr->index; \ |
bce26c58 | 1404 | return sprintf(buf, "%d\n", data->reg[nr] * 1000); \ |
08c79950 RM |
1405 | } |
1406 | ||
1407 | show_tol_temp(tolerance) | |
1408 | show_tol_temp(target_temp) | |
1409 | ||
1410 | static ssize_t | |
1411 | store_target_temp(struct device *dev, struct device_attribute *attr, | |
1412 | const char *buf, size_t count) | |
1413 | { | |
1ea6dd38 | 1414 | struct w83627ehf_data *data = dev_get_drvdata(dev); |
08c79950 RM |
1415 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
1416 | int nr = sensor_attr->index; | |
bce26c58 GR |
1417 | long val; |
1418 | int err; | |
1419 | ||
1420 | err = strict_strtol(buf, 10, &val); | |
1421 | if (err < 0) | |
1422 | return err; | |
1423 | ||
1424 | val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 127); | |
08c79950 RM |
1425 | |
1426 | mutex_lock(&data->update_lock); | |
1427 | data->target_temp[nr] = val; | |
279af1a9 | 1428 | w83627ehf_write_value(data, data->REG_TARGET[nr], val); |
08c79950 RM |
1429 | mutex_unlock(&data->update_lock); |
1430 | return count; | |
1431 | } | |
1432 | ||
1433 | static ssize_t | |
1434 | store_tolerance(struct device *dev, struct device_attribute *attr, | |
1435 | const char *buf, size_t count) | |
1436 | { | |
1ea6dd38 | 1437 | struct w83627ehf_data *data = dev_get_drvdata(dev); |
ec3e5a16 | 1438 | struct w83627ehf_sio_data *sio_data = dev->platform_data; |
08c79950 RM |
1439 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
1440 | int nr = sensor_attr->index; | |
1441 | u16 reg; | |
bce26c58 GR |
1442 | long val; |
1443 | int err; | |
1444 | ||
1445 | err = strict_strtol(buf, 10, &val); | |
1446 | if (err < 0) | |
1447 | return err; | |
1448 | ||
08c79950 | 1449 | /* Limit the temp to 0C - 15C */ |
bce26c58 | 1450 | val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 15); |
08c79950 RM |
1451 | |
1452 | mutex_lock(&data->update_lock); | |
ec3e5a16 GR |
1453 | if (sio_data->kind == nct6775 || sio_data->kind == nct6776) { |
1454 | /* Limit tolerance further for NCT6776F */ | |
1455 | if (sio_data->kind == nct6776 && val > 7) | |
1456 | val = 7; | |
1457 | reg = w83627ehf_read_value(data, NCT6775_REG_FAN_MODE[nr]); | |
08c79950 | 1458 | reg = (reg & 0xf0) | val; |
ec3e5a16 GR |
1459 | w83627ehf_write_value(data, NCT6775_REG_FAN_MODE[nr], reg); |
1460 | } else { | |
1461 | reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]); | |
1462 | if (nr == 1) | |
1463 | reg = (reg & 0x0f) | (val << 4); | |
1464 | else | |
1465 | reg = (reg & 0xf0) | val; | |
1466 | w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg); | |
1467 | } | |
1468 | data->tolerance[nr] = val; | |
08c79950 RM |
1469 | mutex_unlock(&data->update_lock); |
1470 | return count; | |
1471 | } | |
1472 | ||
1473 | static struct sensor_device_attribute sda_pwm[] = { | |
1474 | SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0), | |
1475 | SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1), | |
1476 | SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2), | |
1477 | SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3), | |
1478 | }; | |
1479 | ||
1480 | static struct sensor_device_attribute sda_pwm_mode[] = { | |
1481 | SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode, | |
1482 | store_pwm_mode, 0), | |
1483 | SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode, | |
1484 | store_pwm_mode, 1), | |
1485 | SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode, | |
1486 | store_pwm_mode, 2), | |
1487 | SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode, | |
1488 | store_pwm_mode, 3), | |
1489 | }; | |
1490 | ||
1491 | static struct sensor_device_attribute sda_pwm_enable[] = { | |
1492 | SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable, | |
1493 | store_pwm_enable, 0), | |
1494 | SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable, | |
1495 | store_pwm_enable, 1), | |
1496 | SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable, | |
1497 | store_pwm_enable, 2), | |
1498 | SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable, | |
1499 | store_pwm_enable, 3), | |
1500 | }; | |
1501 | ||
1502 | static struct sensor_device_attribute sda_target_temp[] = { | |
1503 | SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp, | |
1504 | store_target_temp, 0), | |
1505 | SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp, | |
1506 | store_target_temp, 1), | |
1507 | SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp, | |
1508 | store_target_temp, 2), | |
1509 | SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp, | |
1510 | store_target_temp, 3), | |
1511 | }; | |
1512 | ||
1513 | static struct sensor_device_attribute sda_tolerance[] = { | |
1514 | SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance, | |
1515 | store_tolerance, 0), | |
1516 | SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance, | |
1517 | store_tolerance, 1), | |
1518 | SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance, | |
1519 | store_tolerance, 2), | |
1520 | SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance, | |
1521 | store_tolerance, 3), | |
1522 | }; | |
1523 | ||
08c79950 RM |
1524 | /* Smart Fan registers */ |
1525 | ||
1526 | #define fan_functions(reg, REG) \ | |
1527 | static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \ | |
1528 | char *buf) \ | |
1529 | { \ | |
1530 | struct w83627ehf_data *data = w83627ehf_update_device(dev); \ | |
e7e1ca6e GR |
1531 | struct sensor_device_attribute *sensor_attr = \ |
1532 | to_sensor_dev_attr(attr); \ | |
08c79950 RM |
1533 | int nr = sensor_attr->index; \ |
1534 | return sprintf(buf, "%d\n", data->reg[nr]); \ | |
e7e1ca6e | 1535 | } \ |
08c79950 RM |
1536 | static ssize_t \ |
1537 | store_##reg(struct device *dev, struct device_attribute *attr, \ | |
1538 | const char *buf, size_t count) \ | |
e7e1ca6e | 1539 | { \ |
1ea6dd38 | 1540 | struct w83627ehf_data *data = dev_get_drvdata(dev); \ |
e7e1ca6e GR |
1541 | struct sensor_device_attribute *sensor_attr = \ |
1542 | to_sensor_dev_attr(attr); \ | |
08c79950 | 1543 | int nr = sensor_attr->index; \ |
bce26c58 GR |
1544 | unsigned long val; \ |
1545 | int err; \ | |
1546 | err = strict_strtoul(buf, 10, &val); \ | |
1547 | if (err < 0) \ | |
1548 | return err; \ | |
1549 | val = SENSORS_LIMIT(val, 1, 255); \ | |
08c79950 RM |
1550 | mutex_lock(&data->update_lock); \ |
1551 | data->reg[nr] = val; \ | |
da2e0255 | 1552 | w83627ehf_write_value(data, data->REG_##REG[nr], val); \ |
08c79950 RM |
1553 | mutex_unlock(&data->update_lock); \ |
1554 | return count; \ | |
1555 | } | |
1556 | ||
41e9a062 DB |
1557 | fan_functions(fan_start_output, FAN_START_OUTPUT) |
1558 | fan_functions(fan_stop_output, FAN_STOP_OUTPUT) | |
1559 | fan_functions(fan_max_output, FAN_MAX_OUTPUT) | |
1560 | fan_functions(fan_step_output, FAN_STEP_OUTPUT) | |
08c79950 RM |
1561 | |
1562 | #define fan_time_functions(reg, REG) \ | |
1563 | static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \ | |
1564 | char *buf) \ | |
1565 | { \ | |
1566 | struct w83627ehf_data *data = w83627ehf_update_device(dev); \ | |
e7e1ca6e GR |
1567 | struct sensor_device_attribute *sensor_attr = \ |
1568 | to_sensor_dev_attr(attr); \ | |
08c79950 RM |
1569 | int nr = sensor_attr->index; \ |
1570 | return sprintf(buf, "%d\n", \ | |
e7e1ca6e GR |
1571 | step_time_from_reg(data->reg[nr], \ |
1572 | data->pwm_mode[nr])); \ | |
08c79950 RM |
1573 | } \ |
1574 | \ | |
1575 | static ssize_t \ | |
1576 | store_##reg(struct device *dev, struct device_attribute *attr, \ | |
1577 | const char *buf, size_t count) \ | |
1578 | { \ | |
1ea6dd38 | 1579 | struct w83627ehf_data *data = dev_get_drvdata(dev); \ |
e7e1ca6e GR |
1580 | struct sensor_device_attribute *sensor_attr = \ |
1581 | to_sensor_dev_attr(attr); \ | |
08c79950 | 1582 | int nr = sensor_attr->index; \ |
bce26c58 GR |
1583 | unsigned long val; \ |
1584 | int err; \ | |
1585 | err = strict_strtoul(buf, 10, &val); \ | |
1586 | if (err < 0) \ | |
1587 | return err; \ | |
1588 | val = step_time_to_reg(val, data->pwm_mode[nr]); \ | |
08c79950 RM |
1589 | mutex_lock(&data->update_lock); \ |
1590 | data->reg[nr] = val; \ | |
1ea6dd38 | 1591 | w83627ehf_write_value(data, W83627EHF_REG_##REG[nr], val); \ |
08c79950 RM |
1592 | mutex_unlock(&data->update_lock); \ |
1593 | return count; \ | |
1594 | } \ | |
1595 | ||
1596 | fan_time_functions(fan_stop_time, FAN_STOP_TIME) | |
1597 | ||
1ea6dd38 DH |
1598 | static ssize_t show_name(struct device *dev, struct device_attribute *attr, |
1599 | char *buf) | |
1600 | { | |
1601 | struct w83627ehf_data *data = dev_get_drvdata(dev); | |
1602 | ||
1603 | return sprintf(buf, "%s\n", data->name); | |
1604 | } | |
1605 | static DEVICE_ATTR(name, S_IRUGO, show_name, NULL); | |
08c79950 RM |
1606 | |
1607 | static struct sensor_device_attribute sda_sf3_arrays_fan4[] = { | |
1608 | SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time, | |
1609 | store_fan_stop_time, 3), | |
41e9a062 DB |
1610 | SENSOR_ATTR(pwm4_start_output, S_IWUSR | S_IRUGO, show_fan_start_output, |
1611 | store_fan_start_output, 3), | |
1612 | SENSOR_ATTR(pwm4_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output, | |
1613 | store_fan_stop_output, 3), | |
1614 | SENSOR_ATTR(pwm4_max_output, S_IWUSR | S_IRUGO, show_fan_max_output, | |
1615 | store_fan_max_output, 3), | |
1616 | SENSOR_ATTR(pwm4_step_output, S_IWUSR | S_IRUGO, show_fan_step_output, | |
1617 | store_fan_step_output, 3), | |
08c79950 RM |
1618 | }; |
1619 | ||
1620 | static struct sensor_device_attribute sda_sf3_arrays[] = { | |
1621 | SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time, | |
1622 | store_fan_stop_time, 0), | |
1623 | SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time, | |
1624 | store_fan_stop_time, 1), | |
1625 | SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time, | |
1626 | store_fan_stop_time, 2), | |
41e9a062 DB |
1627 | SENSOR_ATTR(pwm1_start_output, S_IWUSR | S_IRUGO, show_fan_start_output, |
1628 | store_fan_start_output, 0), | |
1629 | SENSOR_ATTR(pwm2_start_output, S_IWUSR | S_IRUGO, show_fan_start_output, | |
1630 | store_fan_start_output, 1), | |
1631 | SENSOR_ATTR(pwm3_start_output, S_IWUSR | S_IRUGO, show_fan_start_output, | |
1632 | store_fan_start_output, 2), | |
1633 | SENSOR_ATTR(pwm1_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output, | |
1634 | store_fan_stop_output, 0), | |
1635 | SENSOR_ATTR(pwm2_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output, | |
1636 | store_fan_stop_output, 1), | |
1637 | SENSOR_ATTR(pwm3_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output, | |
1638 | store_fan_stop_output, 2), | |
da2e0255 | 1639 | }; |
41e9a062 | 1640 | |
da2e0255 GR |
1641 | |
1642 | /* | |
1643 | * pwm1 and pwm3 don't support max and step settings on all chips. | |
1644 | * Need to check support while generating/removing attribute files. | |
1645 | */ | |
1646 | static struct sensor_device_attribute sda_sf3_max_step_arrays[] = { | |
1647 | SENSOR_ATTR(pwm1_max_output, S_IWUSR | S_IRUGO, show_fan_max_output, | |
1648 | store_fan_max_output, 0), | |
1649 | SENSOR_ATTR(pwm1_step_output, S_IWUSR | S_IRUGO, show_fan_step_output, | |
1650 | store_fan_step_output, 0), | |
41e9a062 DB |
1651 | SENSOR_ATTR(pwm2_max_output, S_IWUSR | S_IRUGO, show_fan_max_output, |
1652 | store_fan_max_output, 1), | |
1653 | SENSOR_ATTR(pwm2_step_output, S_IWUSR | S_IRUGO, show_fan_step_output, | |
1654 | store_fan_step_output, 1), | |
da2e0255 GR |
1655 | SENSOR_ATTR(pwm3_max_output, S_IWUSR | S_IRUGO, show_fan_max_output, |
1656 | store_fan_max_output, 2), | |
1657 | SENSOR_ATTR(pwm3_step_output, S_IWUSR | S_IRUGO, show_fan_step_output, | |
1658 | store_fan_step_output, 2), | |
08c79950 RM |
1659 | }; |
1660 | ||
fc18d6c0 JD |
1661 | static ssize_t |
1662 | show_vid(struct device *dev, struct device_attribute *attr, char *buf) | |
1663 | { | |
1664 | struct w83627ehf_data *data = dev_get_drvdata(dev); | |
1665 | return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm)); | |
1666 | } | |
1667 | static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL); | |
1668 | ||
363a12a4 DA |
1669 | |
1670 | /* Case open detection */ | |
1671 | ||
1672 | static ssize_t | |
1673 | show_caseopen(struct device *dev, struct device_attribute *attr, char *buf) | |
1674 | { | |
1675 | struct w83627ehf_data *data = w83627ehf_update_device(dev); | |
1676 | ||
1677 | return sprintf(buf, "%d\n", | |
1678 | !!(data->caseopen & to_sensor_dev_attr_2(attr)->index)); | |
1679 | } | |
1680 | ||
1681 | static ssize_t | |
1682 | clear_caseopen(struct device *dev, struct device_attribute *attr, | |
1683 | const char *buf, size_t count) | |
1684 | { | |
1685 | struct w83627ehf_data *data = dev_get_drvdata(dev); | |
1686 | unsigned long val; | |
1687 | u16 reg, mask; | |
1688 | ||
1689 | if (strict_strtoul(buf, 10, &val) || val != 0) | |
1690 | return -EINVAL; | |
1691 | ||
1692 | mask = to_sensor_dev_attr_2(attr)->nr; | |
1693 | ||
1694 | mutex_lock(&data->update_lock); | |
1695 | reg = w83627ehf_read_value(data, W83627EHF_REG_CASEOPEN_CLR); | |
1696 | w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg | mask); | |
1697 | w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg & ~mask); | |
1698 | data->valid = 0; /* Force cache refresh */ | |
1699 | mutex_unlock(&data->update_lock); | |
1700 | ||
1701 | return count; | |
1702 | } | |
1703 | ||
1704 | static struct sensor_device_attribute_2 sda_caseopen[] = { | |
1705 | SENSOR_ATTR_2(intrusion0_alarm, S_IWUSR | S_IRUGO, show_caseopen, | |
1706 | clear_caseopen, 0x80, 0x10), | |
1707 | SENSOR_ATTR_2(intrusion1_alarm, S_IWUSR | S_IRUGO, show_caseopen, | |
1708 | clear_caseopen, 0x40, 0x40), | |
1709 | }; | |
1710 | ||
08e7e278 | 1711 | /* |
1ea6dd38 | 1712 | * Driver and device management |
08e7e278 JD |
1713 | */ |
1714 | ||
c18beb5b DH |
1715 | static void w83627ehf_device_remove_files(struct device *dev) |
1716 | { | |
1717 | /* some entries in the following arrays may not have been used in | |
1718 | * device_create_file(), but device_remove_file() will ignore them */ | |
1719 | int i; | |
1ea6dd38 | 1720 | struct w83627ehf_data *data = dev_get_drvdata(dev); |
c18beb5b DH |
1721 | |
1722 | for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++) | |
1723 | device_remove_file(dev, &sda_sf3_arrays[i].dev_attr); | |
da2e0255 GR |
1724 | for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) { |
1725 | struct sensor_device_attribute *attr = | |
1726 | &sda_sf3_max_step_arrays[i]; | |
ec3e5a16 GR |
1727 | if (data->REG_FAN_STEP_OUTPUT && |
1728 | data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff) | |
da2e0255 GR |
1729 | device_remove_file(dev, &attr->dev_attr); |
1730 | } | |
c18beb5b DH |
1731 | for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) |
1732 | device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr); | |
1ea6dd38 | 1733 | for (i = 0; i < data->in_num; i++) { |
a157d06d GJ |
1734 | if ((i == 6) && data->in6_skip) |
1735 | continue; | |
c18beb5b DH |
1736 | device_remove_file(dev, &sda_in_input[i].dev_attr); |
1737 | device_remove_file(dev, &sda_in_alarm[i].dev_attr); | |
1738 | device_remove_file(dev, &sda_in_min[i].dev_attr); | |
1739 | device_remove_file(dev, &sda_in_max[i].dev_attr); | |
1740 | } | |
1741 | for (i = 0; i < 5; i++) { | |
1742 | device_remove_file(dev, &sda_fan_input[i].dev_attr); | |
1743 | device_remove_file(dev, &sda_fan_alarm[i].dev_attr); | |
1744 | device_remove_file(dev, &sda_fan_div[i].dev_attr); | |
1745 | device_remove_file(dev, &sda_fan_min[i].dev_attr); | |
1746 | } | |
237c8d2f | 1747 | for (i = 0; i < data->pwm_num; i++) { |
c18beb5b DH |
1748 | device_remove_file(dev, &sda_pwm[i].dev_attr); |
1749 | device_remove_file(dev, &sda_pwm_mode[i].dev_attr); | |
1750 | device_remove_file(dev, &sda_pwm_enable[i].dev_attr); | |
1751 | device_remove_file(dev, &sda_target_temp[i].dev_attr); | |
1752 | device_remove_file(dev, &sda_tolerance[i].dev_attr); | |
1753 | } | |
d36cf32c GR |
1754 | for (i = 0; i < NUM_REG_TEMP; i++) { |
1755 | if (!(data->have_temp & (1 << i))) | |
a157d06d GJ |
1756 | continue; |
1757 | device_remove_file(dev, &sda_temp_input[i].dev_attr); | |
d36cf32c | 1758 | device_remove_file(dev, &sda_temp_label[i].dev_attr); |
a157d06d GJ |
1759 | device_remove_file(dev, &sda_temp_max[i].dev_attr); |
1760 | device_remove_file(dev, &sda_temp_max_hyst[i].dev_attr); | |
ec3e5a16 GR |
1761 | if (i > 2) |
1762 | continue; | |
a157d06d GJ |
1763 | device_remove_file(dev, &sda_temp_alarm[i].dev_attr); |
1764 | device_remove_file(dev, &sda_temp_type[i].dev_attr); | |
1765 | } | |
c18beb5b | 1766 | |
363a12a4 DA |
1767 | device_remove_file(dev, &sda_caseopen[0].dev_attr); |
1768 | device_remove_file(dev, &sda_caseopen[1].dev_attr); | |
1769 | ||
1ea6dd38 | 1770 | device_remove_file(dev, &dev_attr_name); |
cbe311f2 | 1771 | device_remove_file(dev, &dev_attr_cpu0_vid); |
1ea6dd38 | 1772 | } |
08e7e278 | 1773 | |
1ea6dd38 | 1774 | /* Get the monitoring functions started */ |
bf164c58 JD |
1775 | static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data, |
1776 | enum kinds kind) | |
08e7e278 JD |
1777 | { |
1778 | int i; | |
da667365 | 1779 | u8 tmp, diode; |
08e7e278 JD |
1780 | |
1781 | /* Start monitoring is needed */ | |
1ea6dd38 | 1782 | tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG); |
08e7e278 | 1783 | if (!(tmp & 0x01)) |
1ea6dd38 | 1784 | w83627ehf_write_value(data, W83627EHF_REG_CONFIG, |
08e7e278 JD |
1785 | tmp | 0x01); |
1786 | ||
d36cf32c GR |
1787 | /* Enable temperature sensors if needed */ |
1788 | for (i = 0; i < NUM_REG_TEMP; i++) { | |
1789 | if (!(data->have_temp & (1 << i))) | |
1790 | continue; | |
ec3e5a16 | 1791 | if (!data->reg_temp_config[i]) |
d36cf32c | 1792 | continue; |
1ea6dd38 | 1793 | tmp = w83627ehf_read_value(data, |
ec3e5a16 | 1794 | data->reg_temp_config[i]); |
08e7e278 | 1795 | if (tmp & 0x01) |
1ea6dd38 | 1796 | w83627ehf_write_value(data, |
ec3e5a16 | 1797 | data->reg_temp_config[i], |
08e7e278 JD |
1798 | tmp & 0xfe); |
1799 | } | |
d3130f0e JD |
1800 | |
1801 | /* Enable VBAT monitoring if needed */ | |
1802 | tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT); | |
1803 | if (!(tmp & 0x01)) | |
1804 | w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01); | |
da667365 JD |
1805 | |
1806 | /* Get thermal sensor types */ | |
bf164c58 JD |
1807 | switch (kind) { |
1808 | case w83627ehf: | |
1809 | diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE); | |
1810 | break; | |
1811 | default: | |
1812 | diode = 0x70; | |
1813 | } | |
da667365 JD |
1814 | for (i = 0; i < 3; i++) { |
1815 | if ((tmp & (0x02 << i))) | |
bf164c58 | 1816 | data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 3; |
da667365 JD |
1817 | else |
1818 | data->temp_type[i] = 4; /* thermistor */ | |
1819 | } | |
08e7e278 JD |
1820 | } |
1821 | ||
ec3e5a16 GR |
1822 | static void w82627ehf_swap_tempreg(struct w83627ehf_data *data, |
1823 | int r1, int r2) | |
1824 | { | |
1825 | u16 tmp; | |
1826 | ||
1827 | tmp = data->temp_src[r1]; | |
1828 | data->temp_src[r1] = data->temp_src[r2]; | |
1829 | data->temp_src[r2] = tmp; | |
1830 | ||
1831 | tmp = data->reg_temp[r1]; | |
1832 | data->reg_temp[r1] = data->reg_temp[r2]; | |
1833 | data->reg_temp[r2] = tmp; | |
1834 | ||
1835 | tmp = data->reg_temp_over[r1]; | |
1836 | data->reg_temp_over[r1] = data->reg_temp_over[r2]; | |
1837 | data->reg_temp_over[r2] = tmp; | |
1838 | ||
1839 | tmp = data->reg_temp_hyst[r1]; | |
1840 | data->reg_temp_hyst[r1] = data->reg_temp_hyst[r2]; | |
1841 | data->reg_temp_hyst[r2] = tmp; | |
1842 | ||
1843 | tmp = data->reg_temp_config[r1]; | |
1844 | data->reg_temp_config[r1] = data->reg_temp_config[r2]; | |
1845 | data->reg_temp_config[r2] = tmp; | |
1846 | } | |
1847 | ||
03f5de2b JD |
1848 | static void __devinit |
1849 | w83627ehf_check_fan_inputs(const struct w83627ehf_sio_data *sio_data, | |
1850 | struct w83627ehf_data *data) | |
1851 | { | |
1852 | int fan3pin, fan4pin, fan4min, fan5pin, regval; | |
1853 | ||
1854 | superio_enter(sio_data->sioreg); | |
1855 | ||
1856 | /* fan4 and fan5 share some pins with the GPIO and serial flash */ | |
1857 | if (sio_data->kind == nct6775) { | |
1858 | /* On NCT6775, fan4 shares pins with the fdc interface */ | |
1859 | fan3pin = 1; | |
1860 | fan4pin = !(superio_inb(sio_data->sioreg, 0x2A) & 0x80); | |
1861 | fan4min = 0; | |
1862 | fan5pin = 0; | |
1863 | } else if (sio_data->kind == nct6776) { | |
1864 | fan3pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x40); | |
1865 | fan4pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x01); | |
1866 | fan5pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x02); | |
1867 | fan4min = fan4pin; | |
1868 | } else if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) { | |
1869 | fan3pin = 1; | |
1870 | fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40; | |
1871 | fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20; | |
1872 | fan4min = fan4pin; | |
1873 | } else { | |
1874 | fan3pin = 1; | |
1875 | fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06); | |
1876 | fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02); | |
1877 | fan4min = fan4pin; | |
1878 | } | |
1879 | ||
1880 | superio_exit(sio_data->sioreg); | |
1881 | ||
1882 | data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */ | |
1883 | data->has_fan |= (fan3pin << 2); | |
1884 | data->has_fan_min |= (fan3pin << 2); | |
1885 | ||
1886 | if (sio_data->kind == nct6775 || sio_data->kind == nct6776) { | |
1887 | /* | |
1888 | * NCT6775F and NCT6776F don't have the W83627EHF_REG_FANDIV1 | |
1889 | * register | |
1890 | */ | |
1891 | data->has_fan |= (fan4pin << 3) | (fan5pin << 4); | |
1892 | data->has_fan_min |= (fan4min << 3) | (fan5pin << 4); | |
1893 | } else { | |
1894 | /* | |
1895 | * It looks like fan4 and fan5 pins can be alternatively used | |
1896 | * as fan on/off switches, but fan5 control is write only :/ | |
1897 | * We assume that if the serial interface is disabled, designers | |
1898 | * connected fan5 as input unless they are emitting log 1, which | |
1899 | * is not the default. | |
1900 | */ | |
1901 | regval = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1); | |
1902 | if ((regval & (1 << 2)) && fan4pin) { | |
1903 | data->has_fan |= (1 << 3); | |
1904 | data->has_fan_min |= (1 << 3); | |
1905 | } | |
1906 | if (!(regval & (1 << 1)) && fan5pin) { | |
1907 | data->has_fan |= (1 << 4); | |
1908 | data->has_fan_min |= (1 << 4); | |
1909 | } | |
1910 | } | |
1911 | } | |
1912 | ||
1ea6dd38 | 1913 | static int __devinit w83627ehf_probe(struct platform_device *pdev) |
08e7e278 | 1914 | { |
1ea6dd38 DH |
1915 | struct device *dev = &pdev->dev; |
1916 | struct w83627ehf_sio_data *sio_data = dev->platform_data; | |
08e7e278 | 1917 | struct w83627ehf_data *data; |
1ea6dd38 | 1918 | struct resource *res; |
03f5de2b | 1919 | u8 en_vrm10; |
08e7e278 JD |
1920 | int i, err = 0; |
1921 | ||
1ea6dd38 DH |
1922 | res = platform_get_resource(pdev, IORESOURCE_IO, 0); |
1923 | if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) { | |
08e7e278 | 1924 | err = -EBUSY; |
1ea6dd38 DH |
1925 | dev_err(dev, "Failed to request region 0x%lx-0x%lx\n", |
1926 | (unsigned long)res->start, | |
1927 | (unsigned long)res->start + IOREGION_LENGTH - 1); | |
08e7e278 JD |
1928 | goto exit; |
1929 | } | |
1930 | ||
e7e1ca6e GR |
1931 | data = kzalloc(sizeof(struct w83627ehf_data), GFP_KERNEL); |
1932 | if (!data) { | |
08e7e278 JD |
1933 | err = -ENOMEM; |
1934 | goto exit_release; | |
1935 | } | |
08e7e278 | 1936 | |
1ea6dd38 | 1937 | data->addr = res->start; |
9a61bf63 | 1938 | mutex_init(&data->lock); |
9a61bf63 | 1939 | mutex_init(&data->update_lock); |
1ea6dd38 DH |
1940 | data->name = w83627ehf_device_names[sio_data->kind]; |
1941 | platform_set_drvdata(pdev, data); | |
08e7e278 | 1942 | |
237c8d2f GJ |
1943 | /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */ |
1944 | data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9; | |
ec3e5a16 | 1945 | /* 667HG, NCT6775F, and NCT6776F have 3 pwms */ |
c39aedaf | 1946 | data->pwm_num = (sio_data->kind == w83667hg |
ec3e5a16 GR |
1947 | || sio_data->kind == w83667hg_b |
1948 | || sio_data->kind == nct6775 | |
1949 | || sio_data->kind == nct6776) ? 3 : 4; | |
08e7e278 | 1950 | |
d36cf32c | 1951 | data->have_temp = 0x07; |
a157d06d | 1952 | /* Check temp3 configuration bit for 667HG */ |
d36cf32c GR |
1953 | if (sio_data->kind == w83667hg) { |
1954 | u8 reg; | |
1955 | ||
1956 | reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]); | |
1957 | if (reg & 0x01) | |
1958 | data->have_temp &= ~(1 << 2); | |
1959 | else | |
ec3e5a16 GR |
1960 | data->in6_skip = 1; /* either temp3 or in6 */ |
1961 | } | |
1962 | ||
1963 | /* Deal with temperature register setup first. */ | |
1964 | if (sio_data->kind == nct6775 || sio_data->kind == nct6776) { | |
1965 | int mask = 0; | |
1966 | ||
1967 | /* | |
1968 | * Display temperature sensor output only if it monitors | |
1969 | * a source other than one already reported. Always display | |
1970 | * first three temperature registers, though. | |
1971 | */ | |
1972 | for (i = 0; i < NUM_REG_TEMP; i++) { | |
1973 | u8 src; | |
1974 | ||
1975 | data->reg_temp[i] = NCT6775_REG_TEMP[i]; | |
1976 | data->reg_temp_over[i] = NCT6775_REG_TEMP_OVER[i]; | |
1977 | data->reg_temp_hyst[i] = NCT6775_REG_TEMP_HYST[i]; | |
1978 | data->reg_temp_config[i] = NCT6775_REG_TEMP_CONFIG[i]; | |
1979 | ||
1980 | src = w83627ehf_read_value(data, | |
1981 | NCT6775_REG_TEMP_SOURCE[i]); | |
1982 | src &= 0x1f; | |
1983 | if (src && !(mask & (1 << src))) { | |
1984 | data->have_temp |= 1 << i; | |
1985 | mask |= 1 << src; | |
1986 | } | |
1987 | ||
1988 | data->temp_src[i] = src; | |
1989 | ||
1990 | /* | |
1991 | * Now do some register swapping if index 0..2 don't | |
1992 | * point to SYSTIN(1), CPUIN(2), and AUXIN(3). | |
1993 | * Idea is to have the first three attributes | |
1994 | * report SYSTIN, CPUIN, and AUXIN if possible | |
1995 | * without overriding the basic system configuration. | |
1996 | */ | |
1997 | if (i > 0 && data->temp_src[0] != 1 | |
1998 | && data->temp_src[i] == 1) | |
1999 | w82627ehf_swap_tempreg(data, 0, i); | |
2000 | if (i > 1 && data->temp_src[1] != 2 | |
2001 | && data->temp_src[i] == 2) | |
2002 | w82627ehf_swap_tempreg(data, 1, i); | |
2003 | if (i > 2 && data->temp_src[2] != 3 | |
2004 | && data->temp_src[i] == 3) | |
2005 | w82627ehf_swap_tempreg(data, 2, i); | |
2006 | } | |
2007 | if (sio_data->kind == nct6776) { | |
2008 | /* | |
2009 | * On NCT6776, AUXTIN and VIN3 pins are shared. | |
2010 | * Only way to detect it is to check if AUXTIN is used | |
2011 | * as a temperature source, and if that source is | |
2012 | * enabled. | |
2013 | * | |
2014 | * If that is the case, disable in6, which reports VIN3. | |
2015 | * Otherwise disable temp3. | |
2016 | */ | |
2017 | if (data->temp_src[2] == 3) { | |
2018 | u8 reg; | |
2019 | ||
2020 | if (data->reg_temp_config[2]) | |
2021 | reg = w83627ehf_read_value(data, | |
2022 | data->reg_temp_config[2]); | |
2023 | else | |
2024 | reg = 0; /* Assume AUXTIN is used */ | |
2025 | ||
2026 | if (reg & 0x01) | |
2027 | data->have_temp &= ~(1 << 2); | |
2028 | else | |
2029 | data->in6_skip = 1; | |
2030 | } | |
02309ad2 GR |
2031 | data->temp_label = nct6776_temp_label; |
2032 | } else { | |
2033 | data->temp_label = nct6775_temp_label; | |
ec3e5a16 | 2034 | } |
d36cf32c GR |
2035 | } else if (sio_data->kind == w83667hg_b) { |
2036 | u8 reg; | |
2037 | ||
ec3e5a16 GR |
2038 | /* |
2039 | * Temperature sources are selected with bank 0, registers 0x49 | |
2040 | * and 0x4a. | |
2041 | */ | |
2042 | for (i = 0; i < ARRAY_SIZE(W83627EHF_REG_TEMP); i++) { | |
2043 | data->reg_temp[i] = W83627EHF_REG_TEMP[i]; | |
2044 | data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i]; | |
2045 | data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i]; | |
2046 | data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i]; | |
2047 | } | |
d36cf32c GR |
2048 | reg = w83627ehf_read_value(data, 0x4a); |
2049 | data->temp_src[0] = reg >> 5; | |
2050 | reg = w83627ehf_read_value(data, 0x49); | |
2051 | data->temp_src[1] = reg & 0x07; | |
ec3e5a16 | 2052 | data->temp_src[2] = (reg >> 4) & 0x07; |
d36cf32c GR |
2053 | |
2054 | /* | |
2055 | * W83667HG-B has another temperature register at 0x7e. | |
2056 | * The temperature source is selected with register 0x7d. | |
2057 | * Support it if the source differs from already reported | |
2058 | * sources. | |
2059 | */ | |
2060 | reg = w83627ehf_read_value(data, 0x7d); | |
2061 | reg &= 0x07; | |
2062 | if (reg != data->temp_src[0] && reg != data->temp_src[1] | |
2063 | && reg != data->temp_src[2]) { | |
2064 | data->temp_src[3] = reg; | |
2065 | data->have_temp |= 1 << 3; | |
2066 | } | |
2067 | ||
2068 | /* | |
2069 | * Chip supports either AUXTIN or VIN3. Try to find out which | |
2070 | * one. | |
2071 | */ | |
2072 | reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]); | |
2073 | if (data->temp_src[2] == 2 && (reg & 0x01)) | |
2074 | data->have_temp &= ~(1 << 2); | |
2075 | ||
2076 | if ((data->temp_src[2] == 2 && (data->have_temp & (1 << 2))) | |
2077 | || (data->temp_src[3] == 2 && (data->have_temp & (1 << 3)))) | |
2078 | data->in6_skip = 1; | |
2079 | ||
2080 | data->temp_label = w83667hg_b_temp_label; | |
ec3e5a16 GR |
2081 | } else { |
2082 | /* Temperature sources are fixed */ | |
2083 | for (i = 0; i < 3; i++) { | |
2084 | data->reg_temp[i] = W83627EHF_REG_TEMP[i]; | |
2085 | data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i]; | |
2086 | data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i]; | |
2087 | data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i]; | |
2088 | } | |
a157d06d GJ |
2089 | } |
2090 | ||
ec3e5a16 | 2091 | if (sio_data->kind == nct6775) { |
26bc440e GR |
2092 | data->has_fan_div = true; |
2093 | data->fan_from_reg = fan_from_reg16; | |
2094 | data->fan_from_reg_min = fan_from_reg8; | |
ec3e5a16 GR |
2095 | data->REG_PWM = NCT6775_REG_PWM; |
2096 | data->REG_TARGET = NCT6775_REG_TARGET; | |
26bc440e | 2097 | data->REG_FAN = NCT6775_REG_FAN; |
ec3e5a16 GR |
2098 | data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN; |
2099 | data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT; | |
2100 | data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT; | |
2101 | data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME; | |
2102 | data->REG_FAN_MAX_OUTPUT = NCT6775_REG_FAN_MAX_OUTPUT; | |
2103 | data->REG_FAN_STEP_OUTPUT = NCT6775_REG_FAN_STEP_OUTPUT; | |
2104 | } else if (sio_data->kind == nct6776) { | |
26bc440e GR |
2105 | data->has_fan_div = false; |
2106 | data->fan_from_reg = fan_from_reg13; | |
2107 | data->fan_from_reg_min = fan_from_reg13; | |
ec3e5a16 GR |
2108 | data->REG_PWM = NCT6775_REG_PWM; |
2109 | data->REG_TARGET = NCT6775_REG_TARGET; | |
26bc440e | 2110 | data->REG_FAN = NCT6775_REG_FAN; |
ec3e5a16 GR |
2111 | data->REG_FAN_MIN = NCT6776_REG_FAN_MIN; |
2112 | data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT; | |
2113 | data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT; | |
2114 | data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME; | |
2115 | } else if (sio_data->kind == w83667hg_b) { | |
26bc440e GR |
2116 | data->has_fan_div = true; |
2117 | data->fan_from_reg = fan_from_reg8; | |
2118 | data->fan_from_reg_min = fan_from_reg8; | |
ec3e5a16 GR |
2119 | data->REG_PWM = W83627EHF_REG_PWM; |
2120 | data->REG_TARGET = W83627EHF_REG_TARGET; | |
2121 | data->REG_FAN = W83627EHF_REG_FAN; | |
2122 | data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN; | |
2123 | data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT; | |
2124 | data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT; | |
2125 | data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME; | |
c39aedaf GR |
2126 | data->REG_FAN_MAX_OUTPUT = |
2127 | W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B; | |
2128 | data->REG_FAN_STEP_OUTPUT = | |
2129 | W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B; | |
2130 | } else { | |
26bc440e GR |
2131 | data->has_fan_div = true; |
2132 | data->fan_from_reg = fan_from_reg8; | |
2133 | data->fan_from_reg_min = fan_from_reg8; | |
ec3e5a16 GR |
2134 | data->REG_PWM = W83627EHF_REG_PWM; |
2135 | data->REG_TARGET = W83627EHF_REG_TARGET; | |
2136 | data->REG_FAN = W83627EHF_REG_FAN; | |
2137 | data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN; | |
2138 | data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT; | |
2139 | data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT; | |
2140 | data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME; | |
c39aedaf GR |
2141 | data->REG_FAN_MAX_OUTPUT = |
2142 | W83627EHF_REG_FAN_MAX_OUTPUT_COMMON; | |
2143 | data->REG_FAN_STEP_OUTPUT = | |
2144 | W83627EHF_REG_FAN_STEP_OUTPUT_COMMON; | |
2145 | } | |
da2e0255 | 2146 | |
08e7e278 | 2147 | /* Initialize the chip */ |
bf164c58 | 2148 | w83627ehf_init_device(data, sio_data->kind); |
08e7e278 | 2149 | |
fc18d6c0 JD |
2150 | data->vrm = vid_which_vrm(); |
2151 | superio_enter(sio_data->sioreg); | |
fc18d6c0 | 2152 | /* Read VID value */ |
ec3e5a16 GR |
2153 | if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b || |
2154 | sio_data->kind == nct6775 || sio_data->kind == nct6776) { | |
237c8d2f GJ |
2155 | /* W83667HG has different pins for VID input and output, so |
2156 | we can get the VID input values directly at logical device D | |
2157 | 0xe3. */ | |
2158 | superio_select(sio_data->sioreg, W83667HG_LD_VID); | |
2159 | data->vid = superio_inb(sio_data->sioreg, 0xe3); | |
cbe311f2 JD |
2160 | err = device_create_file(dev, &dev_attr_cpu0_vid); |
2161 | if (err) | |
2162 | goto exit_release; | |
58e6e781 | 2163 | } else { |
237c8d2f GJ |
2164 | superio_select(sio_data->sioreg, W83627EHF_LD_HWM); |
2165 | if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) { | |
2166 | /* Set VID input sensibility if needed. In theory the | |
2167 | BIOS should have set it, but in practice it's not | |
2168 | always the case. We only do it for the W83627EHF/EHG | |
2169 | because the W83627DHG is more complex in this | |
2170 | respect. */ | |
2171 | if (sio_data->kind == w83627ehf) { | |
2172 | en_vrm10 = superio_inb(sio_data->sioreg, | |
2173 | SIO_REG_EN_VRM10); | |
2174 | if ((en_vrm10 & 0x08) && data->vrm == 90) { | |
2175 | dev_warn(dev, "Setting VID input " | |
2176 | "voltage to TTL\n"); | |
2177 | superio_outb(sio_data->sioreg, | |
2178 | SIO_REG_EN_VRM10, | |
2179 | en_vrm10 & ~0x08); | |
2180 | } else if (!(en_vrm10 & 0x08) | |
2181 | && data->vrm == 100) { | |
2182 | dev_warn(dev, "Setting VID input " | |
2183 | "voltage to VRM10\n"); | |
2184 | superio_outb(sio_data->sioreg, | |
2185 | SIO_REG_EN_VRM10, | |
2186 | en_vrm10 | 0x08); | |
2187 | } | |
2188 | } | |
2189 | ||
2190 | data->vid = superio_inb(sio_data->sioreg, | |
2191 | SIO_REG_VID_DATA); | |
2192 | if (sio_data->kind == w83627ehf) /* 6 VID pins only */ | |
2193 | data->vid &= 0x3f; | |
2194 | ||
2195 | err = device_create_file(dev, &dev_attr_cpu0_vid); | |
2196 | if (err) | |
2197 | goto exit_release; | |
2198 | } else { | |
2199 | dev_info(dev, "VID pins in output mode, CPU VID not " | |
2200 | "available\n"); | |
2201 | } | |
fc18d6c0 JD |
2202 | } |
2203 | ||
d42e869a ID |
2204 | if (fan_debounce && |
2205 | (sio_data->kind == nct6775 || sio_data->kind == nct6776)) { | |
2206 | u8 tmp; | |
2207 | ||
2208 | superio_select(sio_data->sioreg, W83627EHF_LD_HWM); | |
2209 | tmp = superio_inb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE); | |
2210 | if (sio_data->kind == nct6776) | |
2211 | superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE, | |
2212 | 0x3e | tmp); | |
2213 | else | |
2214 | superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE, | |
2215 | 0x1e | tmp); | |
2216 | pr_info("Enabled fan debounce for chip %s\n", data->name); | |
2217 | } | |
2218 | ||
1ea6dd38 | 2219 | superio_exit(sio_data->sioreg); |
08c79950 | 2220 | |
03f5de2b | 2221 | w83627ehf_check_fan_inputs(sio_data, data); |
08e7e278 | 2222 | |
ea7be66c | 2223 | /* Read fan clock dividers immediately */ |
ec3e5a16 GR |
2224 | w83627ehf_update_fan_div_common(dev, data); |
2225 | ||
2226 | /* Read pwm data to save original values */ | |
2227 | w83627ehf_update_pwm_common(dev, data); | |
2228 | for (i = 0; i < data->pwm_num; i++) | |
2229 | data->pwm_enable_orig[i] = data->pwm_enable[i]; | |
ea7be66c | 2230 | |
b84bb518 GR |
2231 | /* Read pwm data to save original values */ |
2232 | w83627ehf_update_pwm_common(dev, data); | |
2233 | for (i = 0; i < data->pwm_num; i++) | |
2234 | data->pwm_enable_orig[i] = data->pwm_enable[i]; | |
2235 | ||
08e7e278 | 2236 | /* Register sysfs hooks */ |
e7e1ca6e GR |
2237 | for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++) { |
2238 | err = device_create_file(dev, &sda_sf3_arrays[i].dev_attr); | |
2239 | if (err) | |
c18beb5b | 2240 | goto exit_remove; |
e7e1ca6e | 2241 | } |
08c79950 | 2242 | |
da2e0255 GR |
2243 | for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) { |
2244 | struct sensor_device_attribute *attr = | |
2245 | &sda_sf3_max_step_arrays[i]; | |
ec3e5a16 GR |
2246 | if (data->REG_FAN_STEP_OUTPUT && |
2247 | data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff) { | |
da2e0255 GR |
2248 | err = device_create_file(dev, &attr->dev_attr); |
2249 | if (err) | |
2250 | goto exit_remove; | |
2251 | } | |
2252 | } | |
08c79950 | 2253 | /* if fan4 is enabled create the sf3 files for it */ |
237c8d2f | 2254 | if ((data->has_fan & (1 << 3)) && data->pwm_num >= 4) |
c18beb5b | 2255 | for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) { |
e7e1ca6e GR |
2256 | err = device_create_file(dev, |
2257 | &sda_sf3_arrays_fan4[i].dev_attr); | |
2258 | if (err) | |
c18beb5b DH |
2259 | goto exit_remove; |
2260 | } | |
08c79950 | 2261 | |
a157d06d GJ |
2262 | for (i = 0; i < data->in_num; i++) { |
2263 | if ((i == 6) && data->in6_skip) | |
2264 | continue; | |
c18beb5b DH |
2265 | if ((err = device_create_file(dev, &sda_in_input[i].dev_attr)) |
2266 | || (err = device_create_file(dev, | |
2267 | &sda_in_alarm[i].dev_attr)) | |
2268 | || (err = device_create_file(dev, | |
2269 | &sda_in_min[i].dev_attr)) | |
2270 | || (err = device_create_file(dev, | |
2271 | &sda_in_max[i].dev_attr))) | |
2272 | goto exit_remove; | |
a157d06d | 2273 | } |
cf0676fe | 2274 | |
412fec82 | 2275 | for (i = 0; i < 5; i++) { |
08c79950 | 2276 | if (data->has_fan & (1 << i)) { |
c18beb5b DH |
2277 | if ((err = device_create_file(dev, |
2278 | &sda_fan_input[i].dev_attr)) | |
2279 | || (err = device_create_file(dev, | |
ec3e5a16 | 2280 | &sda_fan_alarm[i].dev_attr))) |
c18beb5b | 2281 | goto exit_remove; |
ec3e5a16 GR |
2282 | if (sio_data->kind != nct6776) { |
2283 | err = device_create_file(dev, | |
2284 | &sda_fan_div[i].dev_attr); | |
2285 | if (err) | |
2286 | goto exit_remove; | |
2287 | } | |
2288 | if (data->has_fan_min & (1 << i)) { | |
2289 | err = device_create_file(dev, | |
2290 | &sda_fan_min[i].dev_attr); | |
2291 | if (err) | |
2292 | goto exit_remove; | |
2293 | } | |
237c8d2f | 2294 | if (i < data->pwm_num && |
c18beb5b DH |
2295 | ((err = device_create_file(dev, |
2296 | &sda_pwm[i].dev_attr)) | |
2297 | || (err = device_create_file(dev, | |
2298 | &sda_pwm_mode[i].dev_attr)) | |
2299 | || (err = device_create_file(dev, | |
2300 | &sda_pwm_enable[i].dev_attr)) | |
2301 | || (err = device_create_file(dev, | |
2302 | &sda_target_temp[i].dev_attr)) | |
2303 | || (err = device_create_file(dev, | |
2304 | &sda_tolerance[i].dev_attr)))) | |
2305 | goto exit_remove; | |
08c79950 | 2306 | } |
08e7e278 | 2307 | } |
08c79950 | 2308 | |
d36cf32c GR |
2309 | for (i = 0; i < NUM_REG_TEMP; i++) { |
2310 | if (!(data->have_temp & (1 << i))) | |
a157d06d | 2311 | continue; |
d36cf32c GR |
2312 | err = device_create_file(dev, &sda_temp_input[i].dev_attr); |
2313 | if (err) | |
2314 | goto exit_remove; | |
2315 | if (data->temp_label) { | |
2316 | err = device_create_file(dev, | |
2317 | &sda_temp_label[i].dev_attr); | |
2318 | if (err) | |
2319 | goto exit_remove; | |
2320 | } | |
ec3e5a16 GR |
2321 | if (data->reg_temp_over[i]) { |
2322 | err = device_create_file(dev, | |
2323 | &sda_temp_max[i].dev_attr); | |
2324 | if (err) | |
2325 | goto exit_remove; | |
2326 | } | |
2327 | if (data->reg_temp_hyst[i]) { | |
2328 | err = device_create_file(dev, | |
2329 | &sda_temp_max_hyst[i].dev_attr); | |
2330 | if (err) | |
2331 | goto exit_remove; | |
2332 | } | |
d36cf32c | 2333 | if (i > 2) |
ec3e5a16 GR |
2334 | continue; |
2335 | if ((err = device_create_file(dev, | |
a157d06d GJ |
2336 | &sda_temp_alarm[i].dev_attr)) |
2337 | || (err = device_create_file(dev, | |
2338 | &sda_temp_type[i].dev_attr))) | |
c18beb5b | 2339 | goto exit_remove; |
a157d06d | 2340 | } |
c18beb5b | 2341 | |
363a12a4 DA |
2342 | err = device_create_file(dev, &sda_caseopen[0].dev_attr); |
2343 | if (err) | |
2344 | goto exit_remove; | |
2345 | ||
2346 | if (sio_data->kind == nct6776) { | |
2347 | err = device_create_file(dev, &sda_caseopen[1].dev_attr); | |
2348 | if (err) | |
2349 | goto exit_remove; | |
2350 | } | |
2351 | ||
1ea6dd38 DH |
2352 | err = device_create_file(dev, &dev_attr_name); |
2353 | if (err) | |
2354 | goto exit_remove; | |
2355 | ||
1beeffe4 TJ |
2356 | data->hwmon_dev = hwmon_device_register(dev); |
2357 | if (IS_ERR(data->hwmon_dev)) { | |
2358 | err = PTR_ERR(data->hwmon_dev); | |
c18beb5b DH |
2359 | goto exit_remove; |
2360 | } | |
08e7e278 JD |
2361 | |
2362 | return 0; | |
2363 | ||
c18beb5b DH |
2364 | exit_remove: |
2365 | w83627ehf_device_remove_files(dev); | |
08e7e278 | 2366 | kfree(data); |
1ea6dd38 | 2367 | platform_set_drvdata(pdev, NULL); |
08e7e278 | 2368 | exit_release: |
1ea6dd38 | 2369 | release_region(res->start, IOREGION_LENGTH); |
08e7e278 JD |
2370 | exit: |
2371 | return err; | |
2372 | } | |
2373 | ||
1ea6dd38 | 2374 | static int __devexit w83627ehf_remove(struct platform_device *pdev) |
08e7e278 | 2375 | { |
1ea6dd38 | 2376 | struct w83627ehf_data *data = platform_get_drvdata(pdev); |
08e7e278 | 2377 | |
1beeffe4 | 2378 | hwmon_device_unregister(data->hwmon_dev); |
1ea6dd38 DH |
2379 | w83627ehf_device_remove_files(&pdev->dev); |
2380 | release_region(data->addr, IOREGION_LENGTH); | |
2381 | platform_set_drvdata(pdev, NULL); | |
943b0830 | 2382 | kfree(data); |
08e7e278 JD |
2383 | |
2384 | return 0; | |
2385 | } | |
2386 | ||
1ea6dd38 | 2387 | static struct platform_driver w83627ehf_driver = { |
cdaf7934 | 2388 | .driver = { |
87218842 | 2389 | .owner = THIS_MODULE, |
1ea6dd38 | 2390 | .name = DRVNAME, |
cdaf7934 | 2391 | }, |
1ea6dd38 DH |
2392 | .probe = w83627ehf_probe, |
2393 | .remove = __devexit_p(w83627ehf_remove), | |
08e7e278 JD |
2394 | }; |
2395 | ||
1ea6dd38 DH |
2396 | /* w83627ehf_find() looks for a '627 in the Super-I/O config space */ |
2397 | static int __init w83627ehf_find(int sioaddr, unsigned short *addr, | |
2398 | struct w83627ehf_sio_data *sio_data) | |
08e7e278 | 2399 | { |
1ea6dd38 DH |
2400 | static const char __initdata sio_name_W83627EHF[] = "W83627EHF"; |
2401 | static const char __initdata sio_name_W83627EHG[] = "W83627EHG"; | |
2402 | static const char __initdata sio_name_W83627DHG[] = "W83627DHG"; | |
c1e48dce | 2403 | static const char __initdata sio_name_W83627DHG_P[] = "W83627DHG-P"; |
237c8d2f | 2404 | static const char __initdata sio_name_W83667HG[] = "W83667HG"; |
c39aedaf | 2405 | static const char __initdata sio_name_W83667HG_B[] = "W83667HG-B"; |
ec3e5a16 GR |
2406 | static const char __initdata sio_name_NCT6775[] = "NCT6775F"; |
2407 | static const char __initdata sio_name_NCT6776[] = "NCT6776F"; | |
1ea6dd38 | 2408 | |
08e7e278 | 2409 | u16 val; |
1ea6dd38 | 2410 | const char *sio_name; |
08e7e278 | 2411 | |
1ea6dd38 | 2412 | superio_enter(sioaddr); |
08e7e278 | 2413 | |
67b671bc JD |
2414 | if (force_id) |
2415 | val = force_id; | |
2416 | else | |
2417 | val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8) | |
2418 | | superio_inb(sioaddr, SIO_REG_DEVID + 1); | |
657c93b1 | 2419 | switch (val & SIO_ID_MASK) { |
657c93b1 | 2420 | case SIO_W83627EHF_ID: |
1ea6dd38 DH |
2421 | sio_data->kind = w83627ehf; |
2422 | sio_name = sio_name_W83627EHF; | |
2423 | break; | |
657c93b1 | 2424 | case SIO_W83627EHG_ID: |
1ea6dd38 DH |
2425 | sio_data->kind = w83627ehf; |
2426 | sio_name = sio_name_W83627EHG; | |
2427 | break; | |
2428 | case SIO_W83627DHG_ID: | |
2429 | sio_data->kind = w83627dhg; | |
2430 | sio_name = sio_name_W83627DHG; | |
657c93b1 | 2431 | break; |
c1e48dce JD |
2432 | case SIO_W83627DHG_P_ID: |
2433 | sio_data->kind = w83627dhg_p; | |
2434 | sio_name = sio_name_W83627DHG_P; | |
2435 | break; | |
237c8d2f GJ |
2436 | case SIO_W83667HG_ID: |
2437 | sio_data->kind = w83667hg; | |
2438 | sio_name = sio_name_W83667HG; | |
2439 | break; | |
c39aedaf GR |
2440 | case SIO_W83667HG_B_ID: |
2441 | sio_data->kind = w83667hg_b; | |
2442 | sio_name = sio_name_W83667HG_B; | |
2443 | break; | |
ec3e5a16 GR |
2444 | case SIO_NCT6775_ID: |
2445 | sio_data->kind = nct6775; | |
2446 | sio_name = sio_name_NCT6775; | |
2447 | break; | |
2448 | case SIO_NCT6776_ID: | |
2449 | sio_data->kind = nct6776; | |
2450 | sio_name = sio_name_NCT6776; | |
2451 | break; | |
657c93b1 | 2452 | default: |
9f66036b | 2453 | if (val != 0xffff) |
abdc6fd1 | 2454 | pr_debug("unsupported chip ID: 0x%04x\n", val); |
1ea6dd38 | 2455 | superio_exit(sioaddr); |
08e7e278 JD |
2456 | return -ENODEV; |
2457 | } | |
2458 | ||
1ea6dd38 DH |
2459 | /* We have a known chip, find the HWM I/O address */ |
2460 | superio_select(sioaddr, W83627EHF_LD_HWM); | |
2461 | val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8) | |
2462 | | superio_inb(sioaddr, SIO_REG_ADDR + 1); | |
1a641fce | 2463 | *addr = val & IOREGION_ALIGNMENT; |
2d8672c5 | 2464 | if (*addr == 0) { |
abdc6fd1 | 2465 | pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n"); |
1ea6dd38 | 2466 | superio_exit(sioaddr); |
08e7e278 JD |
2467 | return -ENODEV; |
2468 | } | |
2469 | ||
2470 | /* Activate logical device if needed */ | |
1ea6dd38 | 2471 | val = superio_inb(sioaddr, SIO_REG_ENABLE); |
475ef855 | 2472 | if (!(val & 0x01)) { |
e7e1ca6e GR |
2473 | pr_warn("Forcibly enabling Super-I/O. " |
2474 | "Sensor is probably unusable.\n"); | |
1ea6dd38 | 2475 | superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01); |
475ef855 | 2476 | } |
1ea6dd38 DH |
2477 | |
2478 | superio_exit(sioaddr); | |
abdc6fd1 | 2479 | pr_info("Found %s chip at %#x\n", sio_name, *addr); |
1ea6dd38 | 2480 | sio_data->sioreg = sioaddr; |
08e7e278 | 2481 | |
08e7e278 JD |
2482 | return 0; |
2483 | } | |
2484 | ||
1ea6dd38 DH |
2485 | /* when Super-I/O functions move to a separate file, the Super-I/O |
2486 | * bus will manage the lifetime of the device and this module will only keep | |
2487 | * track of the w83627ehf driver. But since we platform_device_alloc(), we | |
2488 | * must keep track of the device */ | |
2489 | static struct platform_device *pdev; | |
2490 | ||
08e7e278 JD |
2491 | static int __init sensors_w83627ehf_init(void) |
2492 | { | |
1ea6dd38 DH |
2493 | int err; |
2494 | unsigned short address; | |
2495 | struct resource res; | |
2496 | struct w83627ehf_sio_data sio_data; | |
2497 | ||
2498 | /* initialize sio_data->kind and sio_data->sioreg. | |
2499 | * | |
2500 | * when Super-I/O functions move to a separate file, the Super-I/O | |
2501 | * driver will probe 0x2e and 0x4e and auto-detect the presence of a | |
2502 | * w83627ehf hardware monitor, and call probe() */ | |
2503 | if (w83627ehf_find(0x2e, &address, &sio_data) && | |
2504 | w83627ehf_find(0x4e, &address, &sio_data)) | |
08e7e278 JD |
2505 | return -ENODEV; |
2506 | ||
1ea6dd38 DH |
2507 | err = platform_driver_register(&w83627ehf_driver); |
2508 | if (err) | |
2509 | goto exit; | |
2510 | ||
e7e1ca6e GR |
2511 | pdev = platform_device_alloc(DRVNAME, address); |
2512 | if (!pdev) { | |
1ea6dd38 | 2513 | err = -ENOMEM; |
abdc6fd1 | 2514 | pr_err("Device allocation failed\n"); |
1ea6dd38 DH |
2515 | goto exit_unregister; |
2516 | } | |
2517 | ||
2518 | err = platform_device_add_data(pdev, &sio_data, | |
2519 | sizeof(struct w83627ehf_sio_data)); | |
2520 | if (err) { | |
abdc6fd1 | 2521 | pr_err("Platform data allocation failed\n"); |
1ea6dd38 DH |
2522 | goto exit_device_put; |
2523 | } | |
2524 | ||
2525 | memset(&res, 0, sizeof(res)); | |
2526 | res.name = DRVNAME; | |
2527 | res.start = address + IOREGION_OFFSET; | |
2528 | res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1; | |
2529 | res.flags = IORESOURCE_IO; | |
b9acb64a JD |
2530 | |
2531 | err = acpi_check_resource_conflict(&res); | |
2532 | if (err) | |
18632f84 | 2533 | goto exit_device_put; |
b9acb64a | 2534 | |
1ea6dd38 DH |
2535 | err = platform_device_add_resources(pdev, &res, 1); |
2536 | if (err) { | |
abdc6fd1 | 2537 | pr_err("Device resource addition failed (%d)\n", err); |
1ea6dd38 DH |
2538 | goto exit_device_put; |
2539 | } | |
2540 | ||
2541 | /* platform_device_add calls probe() */ | |
2542 | err = platform_device_add(pdev); | |
2543 | if (err) { | |
abdc6fd1 | 2544 | pr_err("Device addition failed (%d)\n", err); |
1ea6dd38 DH |
2545 | goto exit_device_put; |
2546 | } | |
2547 | ||
2548 | return 0; | |
2549 | ||
2550 | exit_device_put: | |
2551 | platform_device_put(pdev); | |
2552 | exit_unregister: | |
2553 | platform_driver_unregister(&w83627ehf_driver); | |
2554 | exit: | |
2555 | return err; | |
08e7e278 JD |
2556 | } |
2557 | ||
2558 | static void __exit sensors_w83627ehf_exit(void) | |
2559 | { | |
1ea6dd38 DH |
2560 | platform_device_unregister(pdev); |
2561 | platform_driver_unregister(&w83627ehf_driver); | |
08e7e278 JD |
2562 | } |
2563 | ||
2564 | MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>"); | |
2565 | MODULE_DESCRIPTION("W83627EHF driver"); | |
2566 | MODULE_LICENSE("GPL"); | |
2567 | ||
2568 | module_init(sensors_w83627ehf_init); | |
2569 | module_exit(sensors_w83627ehf_exit); |