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hwmon: (w83627ehf) Skip reading unused voltage registers
[deliverable/linux.git] / drivers / hwmon / w83627ehf.c
CommitLineData
08e7e278
JD		 1/*
2 w83627ehf - Driver for the hardware monitoring functionality of
e7e1ca6e 3 the Winbond W83627EHF Super-I/O chip
08e7e278 4 Copyright (C) 2005 Jean Delvare <khali@linux-fr.org>
3379ceee 5 Copyright (C) 2006 Yuan Mu (Winbond),
e7e1ca6e
GR		 6 Rudolf Marek <r.marek@assembler.cz>
7 David Hubbard <david.c.hubbard@gmail.com>
41e9a062 8 Daniel J Blueman <daniel.blueman@gmail.com>
ec3e5a16 9 Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
08e7e278
JD		 10
11 Shamelessly ripped from the w83627hf driver
12 Copyright (C) 2003 Mark Studebaker
13
14 Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
15 in testing and debugging this driver.
16
8dd2d2ca
JD		 17 This driver also supports the W83627EHG, which is the lead-free
18 version of the W83627EHF.
19
08e7e278
JD		 20 This program is free software; you can redistribute it and/or modify
21 it under the terms of the GNU General Public License as published by
22 the Free Software Foundation; either version 2 of the License, or
23 (at your option) any later version.
24
25 This program is distributed in the hope that it will be useful,
26 but WITHOUT ANY WARRANTY; without even the implied warranty of
27 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 GNU General Public License for more details.
29
30 You should have received a copy of the GNU General Public License
31 along with this program; if not, write to the Free Software
32 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
33
34
35 Supports the following chips:
36
657c93b1
DH		 37 Chip #vin #fan #pwm #temp chip IDs man ID
38 w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
e7e1ca6e 39 0x8860 0xa1
657c93b1 40 w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
c1e48dce 41 w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
237c8d2f 42 w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
d36cf32c 43 w83667hg-b 9 5 3 4 0xb350 0xc1 0x5ca3
ec3e5a16
GR		 44 nct6775f 9 4 3 9 0xb470 0xc1 0x5ca3
45 nct6776f 9 5 3 9 0xC330 0xc1 0x5ca3
08e7e278
JD		 46*/
47
abdc6fd1
JP		 48#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
08e7e278
JD		 50#include <linux/module.h>
51#include <linux/init.h>
52#include <linux/slab.h>
1ea6dd38
DH		 53#include <linux/jiffies.h>
54#include <linux/platform_device.h>
943b0830 55#include <linux/hwmon.h>
412fec82 56#include <linux/hwmon-sysfs.h>
fc18d6c0 57#include <linux/hwmon-vid.h>
943b0830 58#include <linux/err.h>
9a61bf63 59#include <linux/mutex.h>
b9acb64a 60#include <linux/acpi.h>
6055fae8 61#include <linux/io.h>
08e7e278
JD		 62#include "lm75.h"
63
ec3e5a16
GR		 64enum kinds { w83627ehf, w83627dhg, w83627dhg_p, w83667hg, w83667hg_b, nct6775,
65 nct6776 };
08e7e278 66
1ea6dd38 67/* used to set data->name = w83627ehf_device_names[data->sio_kind] */
e7e1ca6e 68static const char * const w83627ehf_device_names[] = {
1ea6dd38
DH		 69 "w83627ehf",
70 "w83627dhg",
c1e48dce 71 "w83627dhg",
237c8d2f 72 "w83667hg",
c39aedaf 73 "w83667hg",
ec3e5a16
GR		 74 "nct6775",
75 "nct6776",
1ea6dd38
DH		 76};
77
67b671bc
JD		 78static unsigned short force_id;
79module_param(force_id, ushort, 0);
80MODULE_PARM_DESC(force_id, "Override the detected device ID");
81
d42e869a
ID		 82static unsigned short fan_debounce;
83module_param(fan_debounce, ushort, 0);
84MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
85
1ea6dd38 86#define DRVNAME "w83627ehf"
08e7e278 87
657c93b1 88/*
1ea6dd38 89 * Super-I/O constants and functions
657c93b1 90 */
08e7e278
JD		 91
92#define W83627EHF_LD_HWM 0x0b
e7e1ca6e 93#define W83667HG_LD_VID 0x0d
08e7e278
JD		 94
95#define SIO_REG_LDSEL 0x07 /* Logical device select */
96#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
fc18d6c0 97#define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
08e7e278
JD		 98#define SIO_REG_ENABLE 0x30 /* Logical device enable */
99#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
fc18d6c0
JD		 100#define SIO_REG_VID_CTRL 0xF0 /* VID control */
101#define SIO_REG_VID_DATA 0xF1 /* VID data */
08e7e278 102
657c93b1
DH		 103#define SIO_W83627EHF_ID 0x8850
104#define SIO_W83627EHG_ID 0x8860
105#define SIO_W83627DHG_ID 0xa020
c1e48dce 106#define SIO_W83627DHG_P_ID 0xb070
e7e1ca6e 107#define SIO_W83667HG_ID 0xa510
c39aedaf 108#define SIO_W83667HG_B_ID 0xb350
ec3e5a16
GR		 109#define SIO_NCT6775_ID 0xb470
110#define SIO_NCT6776_ID 0xc330
657c93b1 111#define SIO_ID_MASK 0xFFF0
08e7e278
JD		 112
113static inline void
1ea6dd38 114superio_outb(int ioreg, int reg, int val)
08e7e278 115{
1ea6dd38
DH		 116 outb(reg, ioreg);
117 outb(val, ioreg + 1);
08e7e278
JD		 118}
119
120static inline int
1ea6dd38 121superio_inb(int ioreg, int reg)
08e7e278 122{
1ea6dd38
DH		 123 outb(reg, ioreg);
124 return inb(ioreg + 1);
08e7e278
JD		 125}
126
127static inline void
1ea6dd38 128superio_select(int ioreg, int ld)
08e7e278 129{
1ea6dd38
DH		 130 outb(SIO_REG_LDSEL, ioreg);
131 outb(ld, ioreg + 1);
08e7e278
JD		 132}
133
134static inline void
1ea6dd38 135superio_enter(int ioreg)
08e7e278 136{
1ea6dd38
DH		 137 outb(0x87, ioreg);
138 outb(0x87, ioreg);
08e7e278
JD		 139}
140
141static inline void
1ea6dd38 142superio_exit(int ioreg)
08e7e278 143{
022b75a3 144 outb(0xaa, ioreg);
1ea6dd38
DH		 145 outb(0x02, ioreg);
146 outb(0x02, ioreg + 1);
08e7e278
JD		 147}
148
149/*
150 * ISA constants
151 */
152
e7e1ca6e 153#define IOREGION_ALIGNMENT (~7)
1a641fce
JD		 154#define IOREGION_OFFSET 5
155#define IOREGION_LENGTH 2
1ea6dd38
DH		 156#define ADDR_REG_OFFSET 0
157#define DATA_REG_OFFSET 1
08e7e278
JD		 158
159#define W83627EHF_REG_BANK 0x4E
160#define W83627EHF_REG_CONFIG 0x40
657c93b1
DH		 161
162/* Not currently used:
163 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
164 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
165 * REG_MAN_ID is at port 0x4f
166 * REG_CHIP_ID is at port 0x58 */
08e7e278
JD		 167
168static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
169static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
170
cf0676fe
RM		 171/* The W83627EHF registers for nr=7,8,9 are in bank 5 */
172#define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
173 (0x554 + (((nr) - 7) * 2)))
174#define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
175 (0x555 + (((nr) - 7) * 2)))
176#define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
177 (0x550 + (nr) - 7))
178
d36cf32c
GR		 179static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250, 0x7e };
180static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253, 0 };
181static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255, 0 };
182static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252, 0 };
08e7e278
JD		 183
184/* Fan clock dividers are spread over the following five registers */
185#define W83627EHF_REG_FANDIV1 0x47
186#define W83627EHF_REG_FANDIV2 0x4B
187#define W83627EHF_REG_VBAT 0x5D
188#define W83627EHF_REG_DIODE 0x59
189#define W83627EHF_REG_SMI_OVT 0x4C
190
ec3e5a16
GR		 191/* NCT6775F has its own fan divider registers */
192#define NCT6775_REG_FANDIV1 0x506
193#define NCT6775_REG_FANDIV2 0x507
d42e869a 194#define NCT6775_REG_FAN_DEBOUNCE 0xf0
ec3e5a16 195
a4589dbb
JD		 196#define W83627EHF_REG_ALARM1 0x459
197#define W83627EHF_REG_ALARM2 0x45A
198#define W83627EHF_REG_ALARM3 0x45B
199
363a12a4
DA		 200#define W83627EHF_REG_CASEOPEN_DET 0x42 /* SMI STATUS #2 */
201#define W83627EHF_REG_CASEOPEN_CLR 0x46 /* SMI MASK #3 */
202
08c79950 203/* SmartFan registers */
41e9a062
DB		 204#define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
205#define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
206
08c79950
RM		 207/* DC or PWM output fan configuration */
208static const u8 W83627EHF_REG_PWM_ENABLE[] = {
209 0x04, /* SYS FAN0 output mode and PWM mode */
210 0x04, /* CPU FAN0 output mode and PWM mode */
211 0x12, /* AUX FAN mode */
41e9a062 212 0x62, /* CPU FAN1 mode */
08c79950
RM		 213};
214
215static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
216static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
217
218/* FAN Duty Cycle, be used to control */
279af1a9
GR		 219static const u16 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
220static const u16 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
08c79950
RM		 221static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
222
08c79950 223/* Advanced Fan control, some values are common for all fans */
279af1a9
GR		 224static const u16 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
225static const u16 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
226static const u16 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
c39aedaf 227
279af1a9 228static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[]
c39aedaf 229 = { 0xff, 0x67, 0xff, 0x69 };
279af1a9 230static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[]
c39aedaf
GR		 231 = { 0xff, 0x68, 0xff, 0x6a };
232
279af1a9
GR		 233static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b };
234static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[]
235 = { 0x68, 0x6a, 0x6c };
08c79950 236
ec3e5a16
GR		 237static const u16 NCT6775_REG_TARGET[] = { 0x101, 0x201, 0x301 };
238static const u16 NCT6775_REG_FAN_MODE[] = { 0x102, 0x202, 0x302 };
239static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = { 0x105, 0x205, 0x305 };
240static const u16 NCT6775_REG_FAN_START_OUTPUT[] = { 0x106, 0x206, 0x306 };
241static const u16 NCT6775_REG_FAN_STOP_TIME[] = { 0x107, 0x207, 0x307 };
242static const u16 NCT6775_REG_PWM[] = { 0x109, 0x209, 0x309 };
243static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
244static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
26bc440e 245static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
ec3e5a16
GR		 246static const u16 NCT6776_REG_FAN_MIN[] = { 0x63a, 0x63c, 0x63e, 0x640, 0x642};
247
248static const u16 NCT6775_REG_TEMP[]
249 = { 0x27, 0x150, 0x250, 0x73, 0x75, 0x77, 0x62b, 0x62c, 0x62d };
250static const u16 NCT6775_REG_TEMP_CONFIG[]
251 = { 0, 0x152, 0x252, 0, 0, 0, 0x628, 0x629, 0x62A };
252static const u16 NCT6775_REG_TEMP_HYST[]
253 = { 0x3a, 0x153, 0x253, 0, 0, 0, 0x673, 0x678, 0x67D };
254static const u16 NCT6775_REG_TEMP_OVER[]
255 = { 0x39, 0x155, 0x255, 0, 0, 0, 0x672, 0x677, 0x67C };
256static const u16 NCT6775_REG_TEMP_SOURCE[]
257 = { 0x621, 0x622, 0x623, 0x100, 0x200, 0x300, 0x624, 0x625, 0x626 };
258
d36cf32c
GR		 259static const char *const w83667hg_b_temp_label[] = {
260 "SYSTIN",
261 "CPUTIN",
262 "AUXTIN",
263 "AMDTSI",
264 "PECI Agent 1",
265 "PECI Agent 2",
266 "PECI Agent 3",
267 "PECI Agent 4"
268};
269
ec3e5a16
GR		 270static const char *const nct6775_temp_label[] = {
271 "",
272 "SYSTIN",
273 "CPUTIN",
274 "AUXTIN",
275 "AMD SB-TSI",
276 "PECI Agent 0",
277 "PECI Agent 1",
278 "PECI Agent 2",
279 "PECI Agent 3",
280 "PECI Agent 4",
281 "PECI Agent 5",
282 "PECI Agent 6",
283 "PECI Agent 7",
284 "PCH_CHIP_CPU_MAX_TEMP",
285 "PCH_CHIP_TEMP",
286 "PCH_CPU_TEMP",
287 "PCH_MCH_TEMP",
288 "PCH_DIM0_TEMP",
289 "PCH_DIM1_TEMP",
290 "PCH_DIM2_TEMP",
291 "PCH_DIM3_TEMP"
292};
293
294static const char *const nct6776_temp_label[] = {
295 "",
296 "SYSTIN",
297 "CPUTIN",
298 "AUXTIN",
299 "SMBUSMASTER 0",
300 "SMBUSMASTER 1",
301 "SMBUSMASTER 2",
302 "SMBUSMASTER 3",
303 "SMBUSMASTER 4",
304 "SMBUSMASTER 5",
305 "SMBUSMASTER 6",
306 "SMBUSMASTER 7",
307 "PECI Agent 0",
308 "PECI Agent 1",
309 "PCH_CHIP_CPU_MAX_TEMP",
310 "PCH_CHIP_TEMP",
311 "PCH_CPU_TEMP",
312 "PCH_MCH_TEMP",
313 "PCH_DIM0_TEMP",
314 "PCH_DIM1_TEMP",
315 "PCH_DIM2_TEMP",
316 "PCH_DIM3_TEMP",
317 "BYTE_TEMP"
318};
319
320#define NUM_REG_TEMP ARRAY_SIZE(NCT6775_REG_TEMP)
d36cf32c 321
bce26c58
GR		 322static inline int is_word_sized(u16 reg)
323{
ec3e5a16 324 return ((((reg & 0xff00) == 0x100
bce26c58
GR		 325 || (reg & 0xff00) == 0x200)
326 && ((reg & 0x00ff) == 0x50
327 || (reg & 0x00ff) == 0x53
ec3e5a16
GR		 328 || (reg & 0x00ff) == 0x55))
329 || (reg & 0xfff0) == 0x630
330 || reg == 0x640 || reg == 0x642
331 || ((reg & 0xfff0) == 0x650
332 && (reg & 0x000f) >= 0x06)
333 || reg == 0x73 || reg == 0x75 || reg == 0x77
334 );
bce26c58
GR		 335}
336
08e7e278
JD		 337/*
338 * Conversions
339 */
340
08c79950
RM		 341/* 1 is PWM mode, output in ms */
342static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
343{
344 return mode ? 100 * reg : 400 * reg;
345}
346
347static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
348{
349 return SENSORS_LIMIT((mode ? (msec + 50) / 100 :
350 (msec + 200) / 400), 1, 255);
351}
352
26bc440e 353static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
08e7e278 354{
26bc440e 355 if (reg == 0 || reg == 255)
08e7e278 356 return 0;
26bc440e
GR		 357 return 1350000U / (reg << divreg);
358}
359
360static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
361{
362 if ((reg & 0xff1f) == 0xff1f)
363 return 0;
364
365 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
366
367 if (reg == 0)
368 return 0;
369
370 return 1350000U / reg;
371}
372
373static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
374{
375 if (reg == 0 || reg == 0xffff)
376 return 0;
377
378 /*
379 * Even though the registers are 16 bit wide, the fan divisor
380 * still applies.
381 */
382 return 1350000U / (reg << divreg);
08e7e278
JD		 383}
384
385static inline unsigned int
386div_from_reg(u8 reg)
387{
388 return 1 << reg;
389}
390
391static inline int
bce26c58 392temp_from_reg(u16 reg, s16 regval)
08e7e278 393{
bce26c58
GR		 394 if (is_word_sized(reg))
395 return LM75_TEMP_FROM_REG(regval);
133d324d 396 return ((s8)regval) * 1000;
08e7e278
JD		 397}
398
ec3e5a16 399static inline u16
bce26c58 400temp_to_reg(u16 reg, long temp)
08e7e278 401{
bce26c58
GR		 402 if (is_word_sized(reg))
403 return LM75_TEMP_TO_REG(temp);
133d324d
JD		 404 return (s8)DIV_ROUND_CLOSEST(SENSORS_LIMIT(temp, -127000, 128000),
405 1000);
08e7e278
JD		 406}
407
cf0676fe
RM		 408/* Some of analog inputs have internal scaling (2x), 8mV is ADC LSB */
409
410static u8 scale_in[10] = { 8, 8, 16, 16, 8, 8, 8, 16, 16, 8 };
411
412static inline long in_from_reg(u8 reg, u8 nr)
413{
414 return reg * scale_in[nr];
415}
416
417static inline u8 in_to_reg(u32 val, u8 nr)
418{
e7e1ca6e
GR		 419 return SENSORS_LIMIT(((val + (scale_in[nr] / 2)) / scale_in[nr]), 0,
420 255);
cf0676fe
RM		 421}
422
08e7e278
JD		 423/*
424 * Data structures and manipulation thereof
425 */
426
427struct w83627ehf_data {
1ea6dd38
DH		 428 int addr; /* IO base of hw monitor block */
429 const char *name;
430
1beeffe4 431 struct device *hwmon_dev;
9a61bf63 432 struct mutex lock;
08e7e278 433
ec3e5a16
GR		 434 u16 reg_temp[NUM_REG_TEMP];
435 u16 reg_temp_over[NUM_REG_TEMP];
436 u16 reg_temp_hyst[NUM_REG_TEMP];
437 u16 reg_temp_config[NUM_REG_TEMP];
d36cf32c
GR		 438 u8 temp_src[NUM_REG_TEMP];
439 const char * const *temp_label;
440
279af1a9
GR		 441 const u16 *REG_PWM;
442 const u16 *REG_TARGET;
443 const u16 *REG_FAN;
444 const u16 *REG_FAN_MIN;
445 const u16 *REG_FAN_START_OUTPUT;
446 const u16 *REG_FAN_STOP_OUTPUT;
447 const u16 *REG_FAN_STOP_TIME;
448 const u16 *REG_FAN_MAX_OUTPUT;
449 const u16 *REG_FAN_STEP_OUTPUT;
da2e0255 450
26bc440e
GR		 451 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
452 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
453
9a61bf63 454 struct mutex update_lock;
08e7e278
JD		 455 char valid; /* !=0 if following fields are valid */
456 unsigned long last_updated; /* In jiffies */
457
458 /* Register values */
83cc8985 459 u8 bank; /* current register bank */
1ea6dd38 460 u8 in_num; /* number of in inputs we have */
cf0676fe
RM		 461 u8 in[10]; /* Register value */
462 u8 in_max[10]; /* Register value */
463 u8 in_min[10]; /* Register value */
3382a918 464 unsigned int rpm[5];
ec3e5a16 465 u16 fan_min[5];
08e7e278
JD		 466 u8 fan_div[5];
467 u8 has_fan; /* some fan inputs can be disabled */
ec3e5a16 468 u8 has_fan_min; /* some fans don't have min register */
26bc440e 469 bool has_fan_div;
da667365 470 u8 temp_type[3];
ec3e5a16
GR		 471 s16 temp[9];
472 s16 temp_max[9];
473 s16 temp_max_hyst[9];
a4589dbb 474 u32 alarms;
363a12a4 475 u8 caseopen;
08c79950
RM		 476
477 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
478 u8 pwm_enable[4]; /* 1->manual
41e9a062
DB		 479 2->thermal cruise mode (also called SmartFan I)
480 3->fan speed cruise mode
e7e1ca6e 481 4->variable thermal cruise (also called
b84bb518
GR		 482 SmartFan III)
483 5->enhanced variable thermal cruise (also called
484 SmartFan IV) */
485 u8 pwm_enable_orig[4]; /* original value of pwm_enable */
237c8d2f 486 u8 pwm_num; /* number of pwm */
08c79950
RM		 487 u8 pwm[4];
488 u8 target_temp[4];
489 u8 tolerance[4];
490
41e9a062
DB		 491 u8 fan_start_output[4]; /* minimum fan speed when spinning up */
492 u8 fan_stop_output[4]; /* minimum fan speed when spinning down */
493 u8 fan_stop_time[4]; /* time at minimum before disabling fan */
494 u8 fan_max_output[4]; /* maximum fan speed */
495 u8 fan_step_output[4]; /* rate of change output value */
fc18d6c0
JD		 496
497 u8 vid;
498 u8 vrm;
a157d06d 499
ec3e5a16 500 u16 have_temp;
a157d06d 501 u8 in6_skip;
08e7e278
JD		 502};
503
1ea6dd38
DH		 504struct w83627ehf_sio_data {
505 int sioreg;
506 enum kinds kind;
507};
508
83cc8985
GR		 509/*
510 * On older chips, only registers 0x50-0x5f are banked.
511 * On more recent chips, all registers are banked.
512 * Assume that is the case and set the bank number for each access.
513 * Cache the bank number so it only needs to be set if it changes.
514 */
1ea6dd38 515static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
08e7e278 516{
83cc8985
GR		 517 u8 bank = reg >> 8;
518 if (data->bank != bank) {
1ea6dd38 519 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
83cc8985
GR		 520 outb_p(bank, data->addr + DATA_REG_OFFSET);
521 data->bank = bank;
08e7e278
JD		 522 }
523}
524
1ea6dd38 525static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
08e7e278 526{
08e7e278
JD		 527 int res, word_sized = is_word_sized(reg);
528
9a61bf63 529 mutex_lock(&data->lock);
08e7e278 530
1ea6dd38
DH		 531 w83627ehf_set_bank(data, reg);
532 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
533 res = inb_p(data->addr + DATA_REG_OFFSET);
08e7e278
JD		 534 if (word_sized) {
535 outb_p((reg & 0xff) + 1,
1ea6dd38
DH		 536 data->addr + ADDR_REG_OFFSET);
537 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
08e7e278 538 }
08e7e278 539
9a61bf63 540 mutex_unlock(&data->lock);
08e7e278
JD		 541 return res;
542}
543
e7e1ca6e
GR		 544static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg,
545 u16 value)
08e7e278 546{
08e7e278
JD		 547 int word_sized = is_word_sized(reg);
548
9a61bf63 549 mutex_lock(&data->lock);
08e7e278 550
1ea6dd38
DH		 551 w83627ehf_set_bank(data, reg);
552 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
08e7e278 553 if (word_sized) {
1ea6dd38 554 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
08e7e278 555 outb_p((reg & 0xff) + 1,
1ea6dd38 556 data->addr + ADDR_REG_OFFSET);
08e7e278 557 }
1ea6dd38 558 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
08e7e278 559
9a61bf63 560 mutex_unlock(&data->lock);
08e7e278
JD		 561 return 0;
562}
563
ec3e5a16
GR		 564/* This function assumes that the caller holds data->update_lock */
565static void nct6775_write_fan_div(struct w83627ehf_data *data, int nr)
566{
567 u8 reg;
568
569 switch (nr) {
570 case 0:
571 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
572 | (data->fan_div[0] & 0x7);
573 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
574 break;
575 case 1:
576 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
577 | ((data->fan_div[1] << 4) & 0x70);
578 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
579 case 2:
580 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
581 | (data->fan_div[2] & 0x7);
582 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
583 break;
584 case 3:
585 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
586 | ((data->fan_div[3] << 4) & 0x70);
587 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
588 break;
589 }
590}
591
08e7e278 592/* This function assumes that the caller holds data->update_lock */
1ea6dd38 593static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
08e7e278 594{
08e7e278
JD		 595 u8 reg;
596
597 switch (nr) {
598 case 0:
1ea6dd38 599 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
08e7e278 600 | ((data->fan_div[0] & 0x03) << 4);
14992c7e
RM		 601 /* fan5 input control bit is write only, compute the value */
602 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 603 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
604 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
08e7e278 605 | ((data->fan_div[0] & 0x04) << 3);
1ea6dd38 606 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 607 break;
608 case 1:
1ea6dd38 609 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
08e7e278 610 | ((data->fan_div[1] & 0x03) << 6);
14992c7e
RM		 611 /* fan5 input control bit is write only, compute the value */
612 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 613 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
614 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
08e7e278 615 | ((data->fan_div[1] & 0x04) << 4);
1ea6dd38 616 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 617 break;
618 case 2:
1ea6dd38 619 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
08e7e278 620 | ((data->fan_div[2] & 0x03) << 6);
1ea6dd38
DH		 621 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
622 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
08e7e278 623 | ((data->fan_div[2] & 0x04) << 5);
1ea6dd38 624 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 625 break;
626 case 3:
1ea6dd38 627 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
08e7e278 628 | (data->fan_div[3] & 0x03);
1ea6dd38
DH		 629 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
630 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
08e7e278 631 | ((data->fan_div[3] & 0x04) << 5);
1ea6dd38 632 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
08e7e278
JD		 633 break;
634 case 4:
1ea6dd38 635 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
33725ad3 636 | ((data->fan_div[4] & 0x03) << 2)
08e7e278 637 | ((data->fan_div[4] & 0x04) << 5);
1ea6dd38 638 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
08e7e278
JD		 639 break;
640 }
641}
642
ec3e5a16
GR		 643static void w83627ehf_write_fan_div_common(struct device *dev,
644 struct w83627ehf_data *data, int nr)
645{
646 struct w83627ehf_sio_data *sio_data = dev->platform_data;
647
648 if (sio_data->kind == nct6776)
649 ; /* no dividers, do nothing */
650 else if (sio_data->kind == nct6775)
651 nct6775_write_fan_div(data, nr);
652 else
653 w83627ehf_write_fan_div(data, nr);
654}
655
656static void nct6775_update_fan_div(struct w83627ehf_data *data)
657{
658 u8 i;
659
660 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV1);
661 data->fan_div[0] = i & 0x7;
662 data->fan_div[1] = (i & 0x70) >> 4;
663 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV2);
664 data->fan_div[2] = i & 0x7;
665 if (data->has_fan & (1<<3))
666 data->fan_div[3] = (i & 0x70) >> 4;
667}
668
ea7be66c
MH		 669static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
670{
671 int i;
672
673 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
674 data->fan_div[0] = (i >> 4) & 0x03;
675 data->fan_div[1] = (i >> 6) & 0x03;
676 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
677 data->fan_div[2] = (i >> 6) & 0x03;
678 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
679 data->fan_div[0] |= (i >> 3) & 0x04;
680 data->fan_div[1] |= (i >> 4) & 0x04;
681 data->fan_div[2] |= (i >> 5) & 0x04;
682 if (data->has_fan & ((1 << 3) | (1 << 4))) {
683 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
684 data->fan_div[3] = i & 0x03;
685 data->fan_div[4] = ((i >> 2) & 0x03)
686 | ((i >> 5) & 0x04);
687 }
688 if (data->has_fan & (1 << 3)) {
689 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
690 data->fan_div[3] |= (i >> 5) & 0x04;
691 }
692}
693
ec3e5a16
GR		 694static void w83627ehf_update_fan_div_common(struct device *dev,
695 struct w83627ehf_data *data)
696{
697 struct w83627ehf_sio_data *sio_data = dev->platform_data;
698
699 if (sio_data->kind == nct6776)
700 ; /* no dividers, do nothing */
701 else if (sio_data->kind == nct6775)
702 nct6775_update_fan_div(data);
703 else
704 w83627ehf_update_fan_div(data);
705}
706
707static void nct6775_update_pwm(struct w83627ehf_data *data)
708{
709 int i;
710 int pwmcfg, fanmodecfg;
711
712 for (i = 0; i < data->pwm_num; i++) {
713 pwmcfg = w83627ehf_read_value(data,
714 W83627EHF_REG_PWM_ENABLE[i]);
715 fanmodecfg = w83627ehf_read_value(data,
716 NCT6775_REG_FAN_MODE[i]);
717 data->pwm_mode[i] =
718 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
719 data->pwm_enable[i] = ((fanmodecfg >> 4) & 7) + 1;
720 data->tolerance[i] = fanmodecfg & 0x0f;
721 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
722 }
723}
724
725static void w83627ehf_update_pwm(struct w83627ehf_data *data)
726{
727 int i;
728 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
729
730 for (i = 0; i < data->pwm_num; i++) {
731 if (!(data->has_fan & (1 << i)))
732 continue;
733
734 /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
735 if (i != 1) {
736 pwmcfg = w83627ehf_read_value(data,
737 W83627EHF_REG_PWM_ENABLE[i]);
738 tolerance = w83627ehf_read_value(data,
739 W83627EHF_REG_TOLERANCE[i]);
740 }
741 data->pwm_mode[i] =
742 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
743 data->pwm_enable[i] = ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
744 & 3) + 1;
745 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
746
747 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0)) & 0x0f;
748 }
749}
750
751static void w83627ehf_update_pwm_common(struct device *dev,
752 struct w83627ehf_data *data)
753{
754 struct w83627ehf_sio_data *sio_data = dev->platform_data;
755
756 if (sio_data->kind == nct6775 || sio_data->kind == nct6776)
757 nct6775_update_pwm(data);
758 else
759 w83627ehf_update_pwm(data);
760}
761
08e7e278
JD		 762static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
763{
1ea6dd38 764 struct w83627ehf_data *data = dev_get_drvdata(dev);
ec3e5a16
GR		 765 struct w83627ehf_sio_data *sio_data = dev->platform_data;
766
08e7e278
JD		 767 int i;
768
9a61bf63 769 mutex_lock(&data->update_lock);
08e7e278 770
6b3e4645 771 if (time_after(jiffies, data->last_updated + HZ + HZ/2)
08e7e278
JD		 772 || !data->valid) {
773 /* Fan clock dividers */
ec3e5a16 774 w83627ehf_update_fan_div_common(dev, data);
08e7e278 775
cf0676fe 776 /* Measured voltages and limits */
1ea6dd38 777 for (i = 0; i < data->in_num; i++) {
389ef65d
JD		 778 if ((i == 6) && data->in6_skip)
779 continue;
780
1ea6dd38 781 data->in[i] = w83627ehf_read_value(data,
cf0676fe 782 W83627EHF_REG_IN(i));
1ea6dd38 783 data->in_min[i] = w83627ehf_read_value(data,
cf0676fe 784 W83627EHF_REG_IN_MIN(i));
1ea6dd38 785 data->in_max[i] = w83627ehf_read_value(data,
cf0676fe
RM		 786 W83627EHF_REG_IN_MAX(i));
787 }
788
08e7e278
JD		 789 /* Measured fan speeds and limits */
790 for (i = 0; i < 5; i++) {
3382a918
GR		 791 u16 reg;
792
08e7e278
JD		 793 if (!(data->has_fan & (1 << i)))
794 continue;
795
3382a918
GR		 796 reg = w83627ehf_read_value(data, data->REG_FAN[i]);
797 data->rpm[i] = data->fan_from_reg(reg,
798 data->fan_div[i]);
ec3e5a16
GR		 799
800 if (data->has_fan_min & (1 << i))
801 data->fan_min[i] = w83627ehf_read_value(data,
279af1a9 802 data->REG_FAN_MIN[i]);
08e7e278
JD		 803
804 /* If we failed to measure the fan speed and clock
805 divider can be increased, let's try that for next
806 time */
26bc440e 807 if (data->has_fan_div
3382a918
GR		 808 && (reg >= 0xff || (sio_data->kind == nct6775
809 && reg == 0x00))
ec3e5a16 810 && data->fan_div[i] < 0x07) {
e7e1ca6e 811 dev_dbg(dev, "Increasing fan%d "
08e7e278 812 "clock divider from %u to %u\n",
33725ad3 813 i + 1, div_from_reg(data->fan_div[i]),
08e7e278
JD		 814 div_from_reg(data->fan_div[i] + 1));
815 data->fan_div[i]++;
ec3e5a16 816 w83627ehf_write_fan_div_common(dev, data, i);
08e7e278 817 /* Preserve min limit if possible */
ec3e5a16
GR		 818 if ((data->has_fan_min & (1 << i))
819 && data->fan_min[i] >= 2
08e7e278 820 && data->fan_min[i] != 255)
1ea6dd38 821 w83627ehf_write_value(data,
279af1a9 822 data->REG_FAN_MIN[i],
08e7e278
JD		 823 (data->fan_min[i] /= 2));
824 }
825 }
826
ec3e5a16
GR		 827 w83627ehf_update_pwm_common(dev, data);
828
da2e0255
GR		 829 for (i = 0; i < data->pwm_num; i++) {
830 if (!(data->has_fan & (1 << i)))
831 continue;
832
ec3e5a16
GR		 833 data->fan_start_output[i] =
834 w83627ehf_read_value(data,
835 data->REG_FAN_START_OUTPUT[i]);
836 data->fan_stop_output[i] =
837 w83627ehf_read_value(data,
838 data->REG_FAN_STOP_OUTPUT[i]);
839 data->fan_stop_time[i] =
840 w83627ehf_read_value(data,
841 data->REG_FAN_STOP_TIME[i]);
842
843 if (data->REG_FAN_MAX_OUTPUT &&
844 data->REG_FAN_MAX_OUTPUT[i] != 0xff)
da2e0255
GR		 845 data->fan_max_output[i] =
846 w83627ehf_read_value(data,
ec3e5a16 847 data->REG_FAN_MAX_OUTPUT[i]);
da2e0255 848
ec3e5a16
GR		 849 if (data->REG_FAN_STEP_OUTPUT &&
850 data->REG_FAN_STEP_OUTPUT[i] != 0xff)
da2e0255
GR		 851 data->fan_step_output[i] =
852 w83627ehf_read_value(data,
ec3e5a16 853 data->REG_FAN_STEP_OUTPUT[i]);
da2e0255 854
08c79950 855 data->target_temp[i] =
1ea6dd38 856 w83627ehf_read_value(data,
279af1a9 857 data->REG_TARGET[i]) &
08c79950 858 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
08c79950
RM		 859 }
860
08e7e278 861 /* Measured temperatures and limits */
d36cf32c
GR		 862 for (i = 0; i < NUM_REG_TEMP; i++) {
863 if (!(data->have_temp & (1 << i)))
864 continue;
ec3e5a16
GR		 865 data->temp[i] = w83627ehf_read_value(data,
866 data->reg_temp[i]);
867 if (data->reg_temp_over[i])
868 data->temp_max[i]
869 = w83627ehf_read_value(data,
870 data->reg_temp_over[i]);
871 if (data->reg_temp_hyst[i])
872 data->temp_max_hyst[i]
873 = w83627ehf_read_value(data,
874 data->reg_temp_hyst[i]);
08e7e278
JD		 875 }
876
1ea6dd38 877 data->alarms = w83627ehf_read_value(data,
a4589dbb 878 W83627EHF_REG_ALARM1) |
1ea6dd38 879 (w83627ehf_read_value(data,
a4589dbb 880 W83627EHF_REG_ALARM2) << 8) |
1ea6dd38 881 (w83627ehf_read_value(data,
a4589dbb
JD		 882 W83627EHF_REG_ALARM3) << 16);
883
363a12a4
DA		 884 data->caseopen = w83627ehf_read_value(data,
885 W83627EHF_REG_CASEOPEN_DET);
886
08e7e278
JD		 887 data->last_updated = jiffies;
888 data->valid = 1;
889 }
890
9a61bf63 891 mutex_unlock(&data->update_lock);
08e7e278
JD		 892 return data;
893}
894
895/*
896 * Sysfs callback functions
897 */
cf0676fe
RM		 898#define show_in_reg(reg) \
899static ssize_t \
900show_##reg(struct device *dev, struct device_attribute *attr, \
901 char *buf) \
902{ \
903 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 904 struct sensor_device_attribute *sensor_attr = \
905 to_sensor_dev_attr(attr); \
cf0676fe
RM		 906 int nr = sensor_attr->index; \
907 return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr)); \
908}
909show_in_reg(in)
910show_in_reg(in_min)
911show_in_reg(in_max)
912
913#define store_in_reg(REG, reg) \
914static ssize_t \
e7e1ca6e
GR		 915store_in_##reg(struct device *dev, struct device_attribute *attr, \
916 const char *buf, size_t count) \
cf0676fe 917{ \
1ea6dd38 918 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 919 struct sensor_device_attribute *sensor_attr = \
920 to_sensor_dev_attr(attr); \
cf0676fe 921 int nr = sensor_attr->index; \
bce26c58
GR		 922 unsigned long val; \
923 int err; \
924 err = strict_strtoul(buf, 10, &val); \
925 if (err < 0) \
926 return err; \
cf0676fe
RM		 927 mutex_lock(&data->update_lock); \
928 data->in_##reg[nr] = in_to_reg(val, nr); \
1ea6dd38 929 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \
cf0676fe
RM		 930 data->in_##reg[nr]); \
931 mutex_unlock(&data->update_lock); \
932 return count; \
933}
934
935store_in_reg(MIN, min)
936store_in_reg(MAX, max)
937
e7e1ca6e
GR		 938static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
939 char *buf)
a4589dbb
JD		 940{
941 struct w83627ehf_data *data = w83627ehf_update_device(dev);
942 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
943 int nr = sensor_attr->index;
944 return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01);
945}
946
cf0676fe
RM		 947static struct sensor_device_attribute sda_in_input[] = {
948 SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
949 SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
950 SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
951 SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
952 SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
953 SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
954 SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
955 SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
956 SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
957 SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9),
958};
959
a4589dbb
JD		 960static struct sensor_device_attribute sda_in_alarm[] = {
961 SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0),
962 SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1),
963 SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2),
964 SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3),
965 SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8),
966 SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21),
967 SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20),
968 SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16),
969 SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17),
970 SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19),
971};
972
cf0676fe 973static struct sensor_device_attribute sda_in_min[] = {
e7e1ca6e
GR		 974 SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0),
975 SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1),
976 SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2),
977 SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3),
978 SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4),
979 SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5),
980 SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6),
981 SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7),
982 SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8),
983 SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9),
cf0676fe
RM		 984};
985
986static struct sensor_device_attribute sda_in_max[] = {
e7e1ca6e
GR		 987 SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0),
988 SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1),
989 SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2),
990 SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3),
991 SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4),
992 SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5),
993 SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6),
994 SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7),
995 SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8),
996 SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9),
cf0676fe
RM		 997};
998
ec3e5a16
GR		 999static ssize_t
1000show_fan(struct device *dev, struct device_attribute *attr, char *buf)
1001{
1002 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1003 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1004 int nr = sensor_attr->index;
3382a918 1005 return sprintf(buf, "%d\n", data->rpm[nr]);
ec3e5a16
GR		 1006}
1007
1008static ssize_t
1009show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
1010{
1011 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1012 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1013 int nr = sensor_attr->index;
1014 return sprintf(buf, "%d\n",
26bc440e
GR		 1015 data->fan_from_reg_min(data->fan_min[nr],
1016 data->fan_div[nr]));
08e7e278 1017}
08e7e278
JD		 1018
1019static ssize_t
412fec82
YM		 1020show_fan_div(struct device *dev, struct device_attribute *attr,
1021 char *buf)
08e7e278
JD		 1022{
1023 struct w83627ehf_data *data = w83627ehf_update_device(dev);
412fec82
YM		 1024 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1025 int nr = sensor_attr->index;
1026 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
08e7e278
JD		 1027}
1028
1029static ssize_t
412fec82
YM		 1030store_fan_min(struct device *dev, struct device_attribute *attr,
1031 const char *buf, size_t count)
08e7e278 1032{
1ea6dd38 1033 struct w83627ehf_data *data = dev_get_drvdata(dev);
412fec82
YM		 1034 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1035 int nr = sensor_attr->index;
bce26c58
GR		 1036 unsigned long val;
1037 int err;
08e7e278
JD		 1038 unsigned int reg;
1039 u8 new_div;
1040
bce26c58
GR		 1041 err = strict_strtoul(buf, 10, &val);
1042 if (err < 0)
1043 return err;
1044
9a61bf63 1045 mutex_lock(&data->update_lock);
26bc440e
GR		 1046 if (!data->has_fan_div) {
1047 /*
1048 * Only NCT6776F for now, so we know that this is a 13 bit
1049 * register
1050 */
ec3e5a16
GR		 1051 if (!val) {
1052 val = 0xff1f;
1053 } else {
1054 if (val > 1350000U)
1055 val = 135000U;
1056 val = 1350000U / val;
1057 val = (val & 0x1f) | ((val << 3) & 0xff00);
1058 }
1059 data->fan_min[nr] = val;
1060 goto done; /* Leave fan divider alone */
1061 }
08e7e278
JD		 1062 if (!val) {
1063 /* No min limit, alarm disabled */
1064 data->fan_min[nr] = 255;
1065 new_div = data->fan_div[nr]; /* No change */
1066 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
1067 } else if ((reg = 1350000U / val) >= 128 * 255) {
1068 /* Speed below this value cannot possibly be represented,
1069 even with the highest divider (128) */
1070 data->fan_min[nr] = 254;
1071 new_div = 7; /* 128 == (1 << 7) */
bce26c58 1072 dev_warn(dev, "fan%u low limit %lu below minimum %u, set to "
ec3e5a16 1073 "minimum\n", nr + 1, val,
26bc440e 1074 data->fan_from_reg_min(254, 7));
08e7e278
JD		 1075 } else if (!reg) {
1076 /* Speed above this value cannot possibly be represented,
1077 even with the lowest divider (1) */
1078 data->fan_min[nr] = 1;
1079 new_div = 0; /* 1 == (1 << 0) */
bce26c58 1080 dev_warn(dev, "fan%u low limit %lu above maximum %u, set to "
ec3e5a16 1081 "maximum\n", nr + 1, val,
26bc440e 1082 data->fan_from_reg_min(1, 0));
08e7e278
JD		 1083 } else {
1084 /* Automatically pick the best divider, i.e. the one such
1085 that the min limit will correspond to a register value
1086 in the 96..192 range */
1087 new_div = 0;
1088 while (reg > 192 && new_div < 7) {
1089 reg >>= 1;
1090 new_div++;
1091 }
1092 data->fan_min[nr] = reg;
1093 }
1094
1095 /* Write both the fan clock divider (if it changed) and the new
1096 fan min (unconditionally) */
1097 if (new_div != data->fan_div[nr]) {
08e7e278
JD		 1098 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
1099 nr + 1, div_from_reg(data->fan_div[nr]),
1100 div_from_reg(new_div));
1101 data->fan_div[nr] = new_div;
ec3e5a16 1102 w83627ehf_write_fan_div_common(dev, data, nr);
6b3e4645
JD		 1103 /* Give the chip time to sample a new speed value */
1104 data->last_updated = jiffies;
08e7e278 1105 }
ec3e5a16 1106done:
279af1a9 1107 w83627ehf_write_value(data, data->REG_FAN_MIN[nr],
08e7e278 1108 data->fan_min[nr]);
9a61bf63 1109 mutex_unlock(&data->update_lock);
08e7e278
JD		 1110
1111 return count;
1112}
1113
412fec82
YM		 1114static struct sensor_device_attribute sda_fan_input[] = {
1115 SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
1116 SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
1117 SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
1118 SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
1119 SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4),
1120};
08e7e278 1121
a4589dbb
JD		 1122static struct sensor_device_attribute sda_fan_alarm[] = {
1123 SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6),
1124 SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7),
1125 SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11),
1126 SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10),
1127 SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23),
1128};
1129
412fec82
YM		 1130static struct sensor_device_attribute sda_fan_min[] = {
1131 SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min,
1132 store_fan_min, 0),
1133 SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min,
1134 store_fan_min, 1),
1135 SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min,
1136 store_fan_min, 2),
1137 SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min,
1138 store_fan_min, 3),
1139 SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min,
1140 store_fan_min, 4),
1141};
08e7e278 1142
412fec82
YM		 1143static struct sensor_device_attribute sda_fan_div[] = {
1144 SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0),
1145 SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1),
1146 SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2),
1147 SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3),
1148 SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4),
1149};
1150
d36cf32c
GR		 1151static ssize_t
1152show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
1153{
1154 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1155 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1156 int nr = sensor_attr->index;
1157 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
1158}
1159
ec3e5a16 1160#define show_temp_reg(addr, reg) \
08e7e278 1161static ssize_t \
412fec82
YM		 1162show_##reg(struct device *dev, struct device_attribute *attr, \
1163 char *buf) \
08e7e278
JD		 1164{ \
1165 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1166 struct sensor_device_attribute *sensor_attr = \
1167 to_sensor_dev_attr(attr); \
412fec82 1168 int nr = sensor_attr->index; \
08e7e278 1169 return sprintf(buf, "%d\n", \
ec3e5a16 1170 temp_from_reg(data->addr[nr], data->reg[nr])); \
08e7e278 1171}
ec3e5a16
GR		 1172show_temp_reg(reg_temp, temp);
1173show_temp_reg(reg_temp_over, temp_max);
1174show_temp_reg(reg_temp_hyst, temp_max_hyst);
08e7e278 1175
ec3e5a16 1176#define store_temp_reg(addr, reg) \
08e7e278 1177static ssize_t \
412fec82
YM		 1178store_##reg(struct device *dev, struct device_attribute *attr, \
1179 const char *buf, size_t count) \
08e7e278 1180{ \
1ea6dd38 1181 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1182 struct sensor_device_attribute *sensor_attr = \
1183 to_sensor_dev_attr(attr); \
412fec82 1184 int nr = sensor_attr->index; \
bce26c58
GR		 1185 int err; \
1186 long val; \
1187 err = strict_strtol(buf, 10, &val); \
1188 if (err < 0) \
1189 return err; \
9a61bf63 1190 mutex_lock(&data->update_lock); \
ec3e5a16
GR		 1191 data->reg[nr] = temp_to_reg(data->addr[nr], val); \
1192 w83627ehf_write_value(data, data->addr[nr], \
08e7e278 1193 data->reg[nr]); \
9a61bf63 1194 mutex_unlock(&data->update_lock); \
08e7e278
JD		 1195 return count; \
1196}
ec3e5a16
GR		 1197store_temp_reg(reg_temp_over, temp_max);
1198store_temp_reg(reg_temp_hyst, temp_max_hyst);
08e7e278 1199
da667365
JD		 1200static ssize_t
1201show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
1202{
1203 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1204 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1205 int nr = sensor_attr->index;
1206 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
1207}
1208
a157d06d 1209static struct sensor_device_attribute sda_temp_input[] = {
bce26c58
GR		 1210 SENSOR_ATTR(temp1_input, S_IRUGO, show_temp, NULL, 0),
1211 SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 1),
1212 SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 2),
d36cf32c 1213 SENSOR_ATTR(temp4_input, S_IRUGO, show_temp, NULL, 3),
ec3e5a16
GR		 1214 SENSOR_ATTR(temp5_input, S_IRUGO, show_temp, NULL, 4),
1215 SENSOR_ATTR(temp6_input, S_IRUGO, show_temp, NULL, 5),
1216 SENSOR_ATTR(temp7_input, S_IRUGO, show_temp, NULL, 6),
1217 SENSOR_ATTR(temp8_input, S_IRUGO, show_temp, NULL, 7),
1218 SENSOR_ATTR(temp9_input, S_IRUGO, show_temp, NULL, 8),
d36cf32c
GR		 1219};
1220
1221static struct sensor_device_attribute sda_temp_label[] = {
1222 SENSOR_ATTR(temp1_label, S_IRUGO, show_temp_label, NULL, 0),
1223 SENSOR_ATTR(temp2_label, S_IRUGO, show_temp_label, NULL, 1),
1224 SENSOR_ATTR(temp3_label, S_IRUGO, show_temp_label, NULL, 2),
1225 SENSOR_ATTR(temp4_label, S_IRUGO, show_temp_label, NULL, 3),
ec3e5a16
GR		 1226 SENSOR_ATTR(temp5_label, S_IRUGO, show_temp_label, NULL, 4),
1227 SENSOR_ATTR(temp6_label, S_IRUGO, show_temp_label, NULL, 5),
1228 SENSOR_ATTR(temp7_label, S_IRUGO, show_temp_label, NULL, 6),
1229 SENSOR_ATTR(temp8_label, S_IRUGO, show_temp_label, NULL, 7),
1230 SENSOR_ATTR(temp9_label, S_IRUGO, show_temp_label, NULL, 8),
a157d06d
GJ		 1231};
1232
1233static struct sensor_device_attribute sda_temp_max[] = {
bce26c58 1234 SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp_max,
412fec82 1235 store_temp_max, 0),
bce26c58 1236 SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max,
412fec82 1237 store_temp_max, 1),
bce26c58
GR		 1238 SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max,
1239 store_temp_max, 2),
ec3e5a16
GR		 1240 SENSOR_ATTR(temp4_max, S_IRUGO | S_IWUSR, show_temp_max,
1241 store_temp_max, 3),
1242 SENSOR_ATTR(temp5_max, S_IRUGO | S_IWUSR, show_temp_max,
1243 store_temp_max, 4),
1244 SENSOR_ATTR(temp6_max, S_IRUGO | S_IWUSR, show_temp_max,
1245 store_temp_max, 5),
1246 SENSOR_ATTR(temp7_max, S_IRUGO | S_IWUSR, show_temp_max,
1247 store_temp_max, 6),
1248 SENSOR_ATTR(temp8_max, S_IRUGO | S_IWUSR, show_temp_max,
1249 store_temp_max, 7),
1250 SENSOR_ATTR(temp9_max, S_IRUGO | S_IWUSR, show_temp_max,
1251 store_temp_max, 8),
a157d06d
GJ		 1252};
1253
1254static struct sensor_device_attribute sda_temp_max_hyst[] = {
bce26c58 1255 SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
412fec82 1256 store_temp_max_hyst, 0),
bce26c58 1257 SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
412fec82 1258 store_temp_max_hyst, 1),
bce26c58
GR		 1259 SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1260 store_temp_max_hyst, 2),
ec3e5a16
GR		 1261 SENSOR_ATTR(temp4_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1262 store_temp_max_hyst, 3),
1263 SENSOR_ATTR(temp5_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1264 store_temp_max_hyst, 4),
1265 SENSOR_ATTR(temp6_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1266 store_temp_max_hyst, 5),
1267 SENSOR_ATTR(temp7_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1268 store_temp_max_hyst, 6),
1269 SENSOR_ATTR(temp8_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1270 store_temp_max_hyst, 7),
1271 SENSOR_ATTR(temp9_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1272 store_temp_max_hyst, 8),
a157d06d
GJ		 1273};
1274
1275static struct sensor_device_attribute sda_temp_alarm[] = {
a4589dbb
JD		 1276 SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
1277 SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
1278 SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
a157d06d
GJ		 1279};
1280
1281static struct sensor_device_attribute sda_temp_type[] = {
da667365
JD		 1282 SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0),
1283 SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1),
1284 SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2),
412fec82 1285};
08e7e278 1286
08c79950 1287#define show_pwm_reg(reg) \
e7e1ca6e
GR		 1288static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1289 char *buf) \
08c79950
RM		 1290{ \
1291 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1292 struct sensor_device_attribute *sensor_attr = \
1293 to_sensor_dev_attr(attr); \
08c79950
RM		 1294 int nr = sensor_attr->index; \
1295 return sprintf(buf, "%d\n", data->reg[nr]); \
1296}
1297
1298show_pwm_reg(pwm_mode)
1299show_pwm_reg(pwm_enable)
1300show_pwm_reg(pwm)
1301
1302static ssize_t
1303store_pwm_mode(struct device *dev, struct device_attribute *attr,
1304 const char *buf, size_t count)
1305{
1ea6dd38 1306 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1307 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1308 int nr = sensor_attr->index;
bce26c58
GR		 1309 unsigned long val;
1310 int err;
08c79950
RM		 1311 u16 reg;
1312
bce26c58
GR		 1313 err = strict_strtoul(buf, 10, &val);
1314 if (err < 0)
1315 return err;
1316
08c79950
RM		 1317 if (val > 1)
1318 return -EINVAL;
1319 mutex_lock(&data->update_lock);
1ea6dd38 1320 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 1321 data->pwm_mode[nr] = val;
1322 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]);
1323 if (!val)
1324 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr];
1ea6dd38 1325 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 1326 mutex_unlock(&data->update_lock);
1327 return count;
1328}
1329
1330static ssize_t
1331store_pwm(struct device *dev, struct device_attribute *attr,
1332 const char *buf, size_t count)
1333{
1ea6dd38 1334 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1335 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1336 int nr = sensor_attr->index;
bce26c58
GR		 1337 unsigned long val;
1338 int err;
1339
1340 err = strict_strtoul(buf, 10, &val);
1341 if (err < 0)
1342 return err;
1343
1344 val = SENSORS_LIMIT(val, 0, 255);
08c79950
RM		 1345
1346 mutex_lock(&data->update_lock);
1347 data->pwm[nr] = val;
279af1a9 1348 w83627ehf_write_value(data, data->REG_PWM[nr], val);
08c79950
RM		 1349 mutex_unlock(&data->update_lock);
1350 return count;
1351}
1352
1353static ssize_t
1354store_pwm_enable(struct device *dev, struct device_attribute *attr,
1355 const char *buf, size_t count)
1356{
1ea6dd38 1357 struct w83627ehf_data *data = dev_get_drvdata(dev);
ec3e5a16 1358 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08c79950
RM		 1359 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1360 int nr = sensor_attr->index;
bce26c58
GR		 1361 unsigned long val;
1362 int err;
08c79950
RM		 1363 u16 reg;
1364
bce26c58
GR		 1365 err = strict_strtoul(buf, 10, &val);
1366 if (err < 0)
1367 return err;
1368
b84bb518 1369 if (!val || (val > 4 && val != data->pwm_enable_orig[nr]))
08c79950 1370 return -EINVAL;
ec3e5a16
GR		 1371 /* SmartFan III mode is not supported on NCT6776F */
1372 if (sio_data->kind == nct6776 && val == 4)
1373 return -EINVAL;
1374
08c79950 1375 mutex_lock(&data->update_lock);
08c79950 1376 data->pwm_enable[nr] = val;
ec3e5a16
GR		 1377 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1378 reg = w83627ehf_read_value(data,
1379 NCT6775_REG_FAN_MODE[nr]);
1380 reg &= 0x0f;
1381 reg |= (val - 1) << 4;
1382 w83627ehf_write_value(data,
1383 NCT6775_REG_FAN_MODE[nr], reg);
1384 } else {
1385 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
1386 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]);
1387 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr];
1388 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
1389 }
08c79950
RM		 1390 mutex_unlock(&data->update_lock);
1391 return count;
1392}
1393
1394
1395#define show_tol_temp(reg) \
1396static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1397 char *buf) \
1398{ \
1399 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1400 struct sensor_device_attribute *sensor_attr = \
1401 to_sensor_dev_attr(attr); \
08c79950 1402 int nr = sensor_attr->index; \
bce26c58 1403 return sprintf(buf, "%d\n", data->reg[nr] * 1000); \
08c79950
RM		 1404}
1405
1406show_tol_temp(tolerance)
1407show_tol_temp(target_temp)
1408
1409static ssize_t
1410store_target_temp(struct device *dev, struct device_attribute *attr,
1411 const char *buf, size_t count)
1412{
1ea6dd38 1413 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1414 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1415 int nr = sensor_attr->index;
bce26c58
GR		 1416 long val;
1417 int err;
1418
1419 err = strict_strtol(buf, 10, &val);
1420 if (err < 0)
1421 return err;
1422
1423 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 127);
08c79950
RM		 1424
1425 mutex_lock(&data->update_lock);
1426 data->target_temp[nr] = val;
279af1a9 1427 w83627ehf_write_value(data, data->REG_TARGET[nr], val);
08c79950
RM		 1428 mutex_unlock(&data->update_lock);
1429 return count;
1430}
1431
1432static ssize_t
1433store_tolerance(struct device *dev, struct device_attribute *attr,
1434 const char *buf, size_t count)
1435{
1ea6dd38 1436 struct w83627ehf_data *data = dev_get_drvdata(dev);
ec3e5a16 1437 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08c79950
RM		 1438 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1439 int nr = sensor_attr->index;
1440 u16 reg;
bce26c58
GR		 1441 long val;
1442 int err;
1443
1444 err = strict_strtol(buf, 10, &val);
1445 if (err < 0)
1446 return err;
1447
08c79950 1448 /* Limit the temp to 0C - 15C */
bce26c58 1449 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 15);
08c79950
RM		 1450
1451 mutex_lock(&data->update_lock);
ec3e5a16
GR		 1452 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1453 /* Limit tolerance further for NCT6776F */
1454 if (sio_data->kind == nct6776 && val > 7)
1455 val = 7;
1456 reg = w83627ehf_read_value(data, NCT6775_REG_FAN_MODE[nr]);
08c79950 1457 reg = (reg & 0xf0) | val;
ec3e5a16
GR		 1458 w83627ehf_write_value(data, NCT6775_REG_FAN_MODE[nr], reg);
1459 } else {
1460 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
1461 if (nr == 1)
1462 reg = (reg & 0x0f) | (val << 4);
1463 else
1464 reg = (reg & 0xf0) | val;
1465 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
1466 }
1467 data->tolerance[nr] = val;
08c79950
RM		 1468 mutex_unlock(&data->update_lock);
1469 return count;
1470}
1471
1472static struct sensor_device_attribute sda_pwm[] = {
1473 SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0),
1474 SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1),
1475 SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2),
1476 SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3),
1477};
1478
1479static struct sensor_device_attribute sda_pwm_mode[] = {
1480 SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1481 store_pwm_mode, 0),
1482 SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1483 store_pwm_mode, 1),
1484 SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1485 store_pwm_mode, 2),
1486 SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1487 store_pwm_mode, 3),
1488};
1489
1490static struct sensor_device_attribute sda_pwm_enable[] = {
1491 SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1492 store_pwm_enable, 0),
1493 SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1494 store_pwm_enable, 1),
1495 SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1496 store_pwm_enable, 2),
1497 SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1498 store_pwm_enable, 3),
1499};
1500
1501static struct sensor_device_attribute sda_target_temp[] = {
1502 SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp,
1503 store_target_temp, 0),
1504 SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp,
1505 store_target_temp, 1),
1506 SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp,
1507 store_target_temp, 2),
1508 SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp,
1509 store_target_temp, 3),
1510};
1511
1512static struct sensor_device_attribute sda_tolerance[] = {
1513 SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1514 store_tolerance, 0),
1515 SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1516 store_tolerance, 1),
1517 SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1518 store_tolerance, 2),
1519 SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1520 store_tolerance, 3),
1521};
1522
08c79950
RM		 1523/* Smart Fan registers */
1524
1525#define fan_functions(reg, REG) \
1526static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1527 char *buf) \
1528{ \
1529 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1530 struct sensor_device_attribute *sensor_attr = \
1531 to_sensor_dev_attr(attr); \
08c79950
RM		 1532 int nr = sensor_attr->index; \
1533 return sprintf(buf, "%d\n", data->reg[nr]); \
e7e1ca6e 1534} \
08c79950
RM		 1535static ssize_t \
1536store_##reg(struct device *dev, struct device_attribute *attr, \
1537 const char *buf, size_t count) \
e7e1ca6e 1538{ \
1ea6dd38 1539 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1540 struct sensor_device_attribute *sensor_attr = \
1541 to_sensor_dev_attr(attr); \
08c79950 1542 int nr = sensor_attr->index; \
bce26c58
GR		 1543 unsigned long val; \
1544 int err; \
1545 err = strict_strtoul(buf, 10, &val); \
1546 if (err < 0) \
1547 return err; \
1548 val = SENSORS_LIMIT(val, 1, 255); \
08c79950
RM		 1549 mutex_lock(&data->update_lock); \
1550 data->reg[nr] = val; \
da2e0255 1551 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
08c79950
RM		 1552 mutex_unlock(&data->update_lock); \
1553 return count; \
1554}
1555
41e9a062
DB		 1556fan_functions(fan_start_output, FAN_START_OUTPUT)
1557fan_functions(fan_stop_output, FAN_STOP_OUTPUT)
1558fan_functions(fan_max_output, FAN_MAX_OUTPUT)
1559fan_functions(fan_step_output, FAN_STEP_OUTPUT)
08c79950
RM		 1560
1561#define fan_time_functions(reg, REG) \
1562static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1563 char *buf) \
1564{ \
1565 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1566 struct sensor_device_attribute *sensor_attr = \
1567 to_sensor_dev_attr(attr); \
08c79950
RM		 1568 int nr = sensor_attr->index; \
1569 return sprintf(buf, "%d\n", \
e7e1ca6e
GR		 1570 step_time_from_reg(data->reg[nr], \
1571 data->pwm_mode[nr])); \
08c79950
RM		 1572} \
1573\
1574static ssize_t \
1575store_##reg(struct device *dev, struct device_attribute *attr, \
1576 const char *buf, size_t count) \
1577{ \
1ea6dd38 1578 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1579 struct sensor_device_attribute *sensor_attr = \
1580 to_sensor_dev_attr(attr); \
08c79950 1581 int nr = sensor_attr->index; \
bce26c58
GR		 1582 unsigned long val; \
1583 int err; \
1584 err = strict_strtoul(buf, 10, &val); \
1585 if (err < 0) \
1586 return err; \
1587 val = step_time_to_reg(val, data->pwm_mode[nr]); \
08c79950
RM		 1588 mutex_lock(&data->update_lock); \
1589 data->reg[nr] = val; \
1ea6dd38 1590 w83627ehf_write_value(data, W83627EHF_REG_##REG[nr], val); \
08c79950
RM		 1591 mutex_unlock(&data->update_lock); \
1592 return count; \
1593} \
1594
1595fan_time_functions(fan_stop_time, FAN_STOP_TIME)
1596
1ea6dd38
DH		 1597static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1598 char *buf)
1599{
1600 struct w83627ehf_data *data = dev_get_drvdata(dev);
1601
1602 return sprintf(buf, "%s\n", data->name);
1603}
1604static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
08c79950
RM		 1605
1606static struct sensor_device_attribute sda_sf3_arrays_fan4[] = {
1607 SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1608 store_fan_stop_time, 3),
41e9a062
DB		 1609 SENSOR_ATTR(pwm4_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1610 store_fan_start_output, 3),
1611 SENSOR_ATTR(pwm4_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1612 store_fan_stop_output, 3),
1613 SENSOR_ATTR(pwm4_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1614 store_fan_max_output, 3),
1615 SENSOR_ATTR(pwm4_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1616 store_fan_step_output, 3),
08c79950
RM		 1617};
1618
1619static struct sensor_device_attribute sda_sf3_arrays[] = {
1620 SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1621 store_fan_stop_time, 0),
1622 SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1623 store_fan_stop_time, 1),
1624 SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1625 store_fan_stop_time, 2),
41e9a062
DB		 1626 SENSOR_ATTR(pwm1_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1627 store_fan_start_output, 0),
1628 SENSOR_ATTR(pwm2_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1629 store_fan_start_output, 1),
1630 SENSOR_ATTR(pwm3_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1631 store_fan_start_output, 2),
1632 SENSOR_ATTR(pwm1_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1633 store_fan_stop_output, 0),
1634 SENSOR_ATTR(pwm2_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1635 store_fan_stop_output, 1),
1636 SENSOR_ATTR(pwm3_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1637 store_fan_stop_output, 2),
da2e0255 1638};
41e9a062 1639
da2e0255
GR		 1640
1641/*
1642 * pwm1 and pwm3 don't support max and step settings on all chips.
1643 * Need to check support while generating/removing attribute files.
1644 */
1645static struct sensor_device_attribute sda_sf3_max_step_arrays[] = {
1646 SENSOR_ATTR(pwm1_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1647 store_fan_max_output, 0),
1648 SENSOR_ATTR(pwm1_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1649 store_fan_step_output, 0),
41e9a062
DB		 1650 SENSOR_ATTR(pwm2_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1651 store_fan_max_output, 1),
1652 SENSOR_ATTR(pwm2_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1653 store_fan_step_output, 1),
da2e0255
GR		 1654 SENSOR_ATTR(pwm3_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1655 store_fan_max_output, 2),
1656 SENSOR_ATTR(pwm3_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1657 store_fan_step_output, 2),
08c79950
RM		 1658};
1659
fc18d6c0
JD		 1660static ssize_t
1661show_vid(struct device *dev, struct device_attribute *attr, char *buf)
1662{
1663 struct w83627ehf_data *data = dev_get_drvdata(dev);
1664 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1665}
1666static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1667
363a12a4
DA		 1668
1669/* Case open detection */
1670
1671static ssize_t
1672show_caseopen(struct device *dev, struct device_attribute *attr, char *buf)
1673{
1674 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1675
1676 return sprintf(buf, "%d\n",
1677 !!(data->caseopen & to_sensor_dev_attr_2(attr)->index));
1678}
1679
1680static ssize_t
1681clear_caseopen(struct device *dev, struct device_attribute *attr,
1682 const char *buf, size_t count)
1683{
1684 struct w83627ehf_data *data = dev_get_drvdata(dev);
1685 unsigned long val;
1686 u16 reg, mask;
1687
1688 if (strict_strtoul(buf, 10, &val) || val != 0)
1689 return -EINVAL;
1690
1691 mask = to_sensor_dev_attr_2(attr)->nr;
1692
1693 mutex_lock(&data->update_lock);
1694 reg = w83627ehf_read_value(data, W83627EHF_REG_CASEOPEN_CLR);
1695 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg | mask);
1696 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg & ~mask);
1697 data->valid = 0; /* Force cache refresh */
1698 mutex_unlock(&data->update_lock);
1699
1700 return count;
1701}
1702
1703static struct sensor_device_attribute_2 sda_caseopen[] = {
1704 SENSOR_ATTR_2(intrusion0_alarm, S_IWUSR | S_IRUGO, show_caseopen,
1705 clear_caseopen, 0x80, 0x10),
1706 SENSOR_ATTR_2(intrusion1_alarm, S_IWUSR | S_IRUGO, show_caseopen,
1707 clear_caseopen, 0x40, 0x40),
1708};
1709
08e7e278 1710/*
1ea6dd38 1711 * Driver and device management
08e7e278
JD		 1712 */
1713
c18beb5b
DH		 1714static void w83627ehf_device_remove_files(struct device *dev)
1715{
1716 /* some entries in the following arrays may not have been used in
1717 * device_create_file(), but device_remove_file() will ignore them */
1718 int i;
1ea6dd38 1719 struct w83627ehf_data *data = dev_get_drvdata(dev);
c18beb5b
DH		 1720
1721 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
1722 device_remove_file(dev, &sda_sf3_arrays[i].dev_attr);
da2e0255
GR		 1723 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
1724 struct sensor_device_attribute *attr =
1725 &sda_sf3_max_step_arrays[i];
ec3e5a16
GR		 1726 if (data->REG_FAN_STEP_OUTPUT &&
1727 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff)
da2e0255
GR		 1728 device_remove_file(dev, &attr->dev_attr);
1729 }
c18beb5b
DH		 1730 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++)
1731 device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr);
1ea6dd38 1732 for (i = 0; i < data->in_num; i++) {
a157d06d
GJ		 1733 if ((i == 6) && data->in6_skip)
1734 continue;
c18beb5b
DH		 1735 device_remove_file(dev, &sda_in_input[i].dev_attr);
1736 device_remove_file(dev, &sda_in_alarm[i].dev_attr);
1737 device_remove_file(dev, &sda_in_min[i].dev_attr);
1738 device_remove_file(dev, &sda_in_max[i].dev_attr);
1739 }
1740 for (i = 0; i < 5; i++) {
1741 device_remove_file(dev, &sda_fan_input[i].dev_attr);
1742 device_remove_file(dev, &sda_fan_alarm[i].dev_attr);
1743 device_remove_file(dev, &sda_fan_div[i].dev_attr);
1744 device_remove_file(dev, &sda_fan_min[i].dev_attr);
1745 }
237c8d2f 1746 for (i = 0; i < data->pwm_num; i++) {
c18beb5b
DH		 1747 device_remove_file(dev, &sda_pwm[i].dev_attr);
1748 device_remove_file(dev, &sda_pwm_mode[i].dev_attr);
1749 device_remove_file(dev, &sda_pwm_enable[i].dev_attr);
1750 device_remove_file(dev, &sda_target_temp[i].dev_attr);
1751 device_remove_file(dev, &sda_tolerance[i].dev_attr);
1752 }
d36cf32c
GR		 1753 for (i = 0; i < NUM_REG_TEMP; i++) {
1754 if (!(data->have_temp & (1 << i)))
a157d06d
GJ		 1755 continue;
1756 device_remove_file(dev, &sda_temp_input[i].dev_attr);
d36cf32c 1757 device_remove_file(dev, &sda_temp_label[i].dev_attr);
a157d06d
GJ		 1758 device_remove_file(dev, &sda_temp_max[i].dev_attr);
1759 device_remove_file(dev, &sda_temp_max_hyst[i].dev_attr);
ec3e5a16
GR		 1760 if (i > 2)
1761 continue;
a157d06d
GJ		 1762 device_remove_file(dev, &sda_temp_alarm[i].dev_attr);
1763 device_remove_file(dev, &sda_temp_type[i].dev_attr);
1764 }
c18beb5b 1765
363a12a4
DA		 1766 device_remove_file(dev, &sda_caseopen[0].dev_attr);
1767 device_remove_file(dev, &sda_caseopen[1].dev_attr);
1768
1ea6dd38 1769 device_remove_file(dev, &dev_attr_name);
cbe311f2 1770 device_remove_file(dev, &dev_attr_cpu0_vid);
1ea6dd38 1771}
08e7e278 1772
1ea6dd38 1773/* Get the monitoring functions started */
bf164c58
JD		 1774static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data,
1775 enum kinds kind)
08e7e278
JD		 1776{
1777 int i;
da667365 1778 u8 tmp, diode;
08e7e278
JD		 1779
1780 /* Start monitoring is needed */
1ea6dd38 1781 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
08e7e278 1782 if (!(tmp & 0x01))
1ea6dd38 1783 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
08e7e278
JD		 1784 tmp | 0x01);
1785
d36cf32c
GR		 1786 /* Enable temperature sensors if needed */
1787 for (i = 0; i < NUM_REG_TEMP; i++) {
1788 if (!(data->have_temp & (1 << i)))
1789 continue;
ec3e5a16 1790 if (!data->reg_temp_config[i])
d36cf32c 1791 continue;
1ea6dd38 1792 tmp = w83627ehf_read_value(data,
ec3e5a16 1793 data->reg_temp_config[i]);
08e7e278 1794 if (tmp & 0x01)
1ea6dd38 1795 w83627ehf_write_value(data,
ec3e5a16 1796 data->reg_temp_config[i],
08e7e278
JD		 1797 tmp & 0xfe);
1798 }
d3130f0e
JD		 1799
1800 /* Enable VBAT monitoring if needed */
1801 tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1802 if (!(tmp & 0x01))
1803 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
da667365
JD		 1804
1805 /* Get thermal sensor types */
bf164c58
JD		 1806 switch (kind) {
1807 case w83627ehf:
1808 diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
1809 break;
1810 default:
1811 diode = 0x70;
1812 }
da667365
JD		 1813 for (i = 0; i < 3; i++) {
1814 if ((tmp & (0x02 << i)))
bf164c58 1815 data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 3;
da667365
JD		 1816 else
1817 data->temp_type[i] = 4; /* thermistor */
1818 }
08e7e278
JD		 1819}
1820
ec3e5a16
GR		 1821static void w82627ehf_swap_tempreg(struct w83627ehf_data *data,
1822 int r1, int r2)
1823{
1824 u16 tmp;
1825
1826 tmp = data->temp_src[r1];
1827 data->temp_src[r1] = data->temp_src[r2];
1828 data->temp_src[r2] = tmp;
1829
1830 tmp = data->reg_temp[r1];
1831 data->reg_temp[r1] = data->reg_temp[r2];
1832 data->reg_temp[r2] = tmp;
1833
1834 tmp = data->reg_temp_over[r1];
1835 data->reg_temp_over[r1] = data->reg_temp_over[r2];
1836 data->reg_temp_over[r2] = tmp;
1837
1838 tmp = data->reg_temp_hyst[r1];
1839 data->reg_temp_hyst[r1] = data->reg_temp_hyst[r2];
1840 data->reg_temp_hyst[r2] = tmp;
1841
1842 tmp = data->reg_temp_config[r1];
1843 data->reg_temp_config[r1] = data->reg_temp_config[r2];
1844 data->reg_temp_config[r2] = tmp;
1845}
1846
1ea6dd38 1847static int __devinit w83627ehf_probe(struct platform_device *pdev)
08e7e278 1848{
1ea6dd38
DH		 1849 struct device *dev = &pdev->dev;
1850 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08e7e278 1851 struct w83627ehf_data *data;
1ea6dd38 1852 struct resource *res;
ec3e5a16 1853 u8 fan3pin, fan4pin, fan4min, fan5pin, en_vrm10;
08e7e278
JD		 1854 int i, err = 0;
1855
1ea6dd38
DH		 1856 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1857 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
08e7e278 1858 err = -EBUSY;
1ea6dd38
DH		 1859 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
1860 (unsigned long)res->start,
1861 (unsigned long)res->start + IOREGION_LENGTH - 1);
08e7e278
JD		 1862 goto exit;
1863 }
1864
e7e1ca6e
GR		 1865 data = kzalloc(sizeof(struct w83627ehf_data), GFP_KERNEL);
1866 if (!data) {
08e7e278
JD		 1867 err = -ENOMEM;
1868 goto exit_release;
1869 }
08e7e278 1870
1ea6dd38 1871 data->addr = res->start;
9a61bf63 1872 mutex_init(&data->lock);
9a61bf63 1873 mutex_init(&data->update_lock);
1ea6dd38
DH		 1874 data->name = w83627ehf_device_names[sio_data->kind];
1875 platform_set_drvdata(pdev, data);
08e7e278 1876
237c8d2f
GJ		 1877 /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
1878 data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
ec3e5a16 1879 /* 667HG, NCT6775F, and NCT6776F have 3 pwms */
c39aedaf 1880 data->pwm_num = (sio_data->kind == w83667hg
ec3e5a16
GR		 1881 || sio_data->kind == w83667hg_b
1882 || sio_data->kind == nct6775
1883 || sio_data->kind == nct6776) ? 3 : 4;
08e7e278 1884
d36cf32c 1885 data->have_temp = 0x07;
a157d06d 1886 /* Check temp3 configuration bit for 667HG */
d36cf32c
GR		 1887 if (sio_data->kind == w83667hg) {
1888 u8 reg;
1889
1890 reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
1891 if (reg & 0x01)
1892 data->have_temp &= ~(1 << 2);
1893 else
ec3e5a16
GR		 1894 data->in6_skip = 1; /* either temp3 or in6 */
1895 }
1896
1897 /* Deal with temperature register setup first. */
1898 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1899 int mask = 0;
1900
1901 /*
1902 * Display temperature sensor output only if it monitors
1903 * a source other than one already reported. Always display
1904 * first three temperature registers, though.
1905 */
1906 for (i = 0; i < NUM_REG_TEMP; i++) {
1907 u8 src;
1908
1909 data->reg_temp[i] = NCT6775_REG_TEMP[i];
1910 data->reg_temp_over[i] = NCT6775_REG_TEMP_OVER[i];
1911 data->reg_temp_hyst[i] = NCT6775_REG_TEMP_HYST[i];
1912 data->reg_temp_config[i] = NCT6775_REG_TEMP_CONFIG[i];
1913
1914 src = w83627ehf_read_value(data,
1915 NCT6775_REG_TEMP_SOURCE[i]);
1916 src &= 0x1f;
1917 if (src && !(mask & (1 << src))) {
1918 data->have_temp |= 1 << i;
1919 mask |= 1 << src;
1920 }
1921
1922 data->temp_src[i] = src;
1923
1924 /*
1925 * Now do some register swapping if index 0..2 don't
1926 * point to SYSTIN(1), CPUIN(2), and AUXIN(3).
1927 * Idea is to have the first three attributes
1928 * report SYSTIN, CPUIN, and AUXIN if possible
1929 * without overriding the basic system configuration.
1930 */
1931 if (i > 0 && data->temp_src[0] != 1
1932 && data->temp_src[i] == 1)
1933 w82627ehf_swap_tempreg(data, 0, i);
1934 if (i > 1 && data->temp_src[1] != 2
1935 && data->temp_src[i] == 2)
1936 w82627ehf_swap_tempreg(data, 1, i);
1937 if (i > 2 && data->temp_src[2] != 3
1938 && data->temp_src[i] == 3)
1939 w82627ehf_swap_tempreg(data, 2, i);
1940 }
1941 if (sio_data->kind == nct6776) {
1942 /*
1943 * On NCT6776, AUXTIN and VIN3 pins are shared.
1944 * Only way to detect it is to check if AUXTIN is used
1945 * as a temperature source, and if that source is
1946 * enabled.
1947 *
1948 * If that is the case, disable in6, which reports VIN3.
1949 * Otherwise disable temp3.
1950 */
1951 if (data->temp_src[2] == 3) {
1952 u8 reg;
1953
1954 if (data->reg_temp_config[2])
1955 reg = w83627ehf_read_value(data,
1956 data->reg_temp_config[2]);
1957 else
1958 reg = 0; /* Assume AUXTIN is used */
1959
1960 if (reg & 0x01)
1961 data->have_temp &= ~(1 << 2);
1962 else
1963 data->in6_skip = 1;
1964 }
02309ad2
GR		 1965 data->temp_label = nct6776_temp_label;
1966 } else {
1967 data->temp_label = nct6775_temp_label;
ec3e5a16 1968 }
d36cf32c
GR		 1969 } else if (sio_data->kind == w83667hg_b) {
1970 u8 reg;
1971
ec3e5a16
GR		 1972 /*
1973 * Temperature sources are selected with bank 0, registers 0x49
1974 * and 0x4a.
1975 */
1976 for (i = 0; i < ARRAY_SIZE(W83627EHF_REG_TEMP); i++) {
1977 data->reg_temp[i] = W83627EHF_REG_TEMP[i];
1978 data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
1979 data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
1980 data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
1981 }
d36cf32c
GR		 1982 reg = w83627ehf_read_value(data, 0x4a);
1983 data->temp_src[0] = reg >> 5;
1984 reg = w83627ehf_read_value(data, 0x49);
1985 data->temp_src[1] = reg & 0x07;
ec3e5a16 1986 data->temp_src[2] = (reg >> 4) & 0x07;
d36cf32c
GR		 1987
1988 /*
1989 * W83667HG-B has another temperature register at 0x7e.
1990 * The temperature source is selected with register 0x7d.
1991 * Support it if the source differs from already reported
1992 * sources.
1993 */
1994 reg = w83627ehf_read_value(data, 0x7d);
1995 reg &= 0x07;
1996 if (reg != data->temp_src[0] && reg != data->temp_src[1]
1997 && reg != data->temp_src[2]) {
1998 data->temp_src[3] = reg;
1999 data->have_temp |= 1 << 3;
2000 }
2001
2002 /*
2003 * Chip supports either AUXTIN or VIN3. Try to find out which
2004 * one.
2005 */
2006 reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
2007 if (data->temp_src[2] == 2 && (reg & 0x01))
2008 data->have_temp &= ~(1 << 2);
2009
2010 if ((data->temp_src[2] == 2 && (data->have_temp & (1 << 2)))
2011 || (data->temp_src[3] == 2 && (data->have_temp & (1 << 3))))
2012 data->in6_skip = 1;
2013
2014 data->temp_label = w83667hg_b_temp_label;
ec3e5a16
GR		 2015 } else {
2016 /* Temperature sources are fixed */
2017 for (i = 0; i < 3; i++) {
2018 data->reg_temp[i] = W83627EHF_REG_TEMP[i];
2019 data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
2020 data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
2021 data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
2022 }
a157d06d
GJ		 2023 }
2024
ec3e5a16 2025 if (sio_data->kind == nct6775) {
26bc440e
GR		 2026 data->has_fan_div = true;
2027 data->fan_from_reg = fan_from_reg16;
2028 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2029 data->REG_PWM = NCT6775_REG_PWM;
2030 data->REG_TARGET = NCT6775_REG_TARGET;
26bc440e 2031 data->REG_FAN = NCT6775_REG_FAN;
ec3e5a16
GR		 2032 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2033 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
2034 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
2035 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
2036 data->REG_FAN_MAX_OUTPUT = NCT6775_REG_FAN_MAX_OUTPUT;
2037 data->REG_FAN_STEP_OUTPUT = NCT6775_REG_FAN_STEP_OUTPUT;
2038 } else if (sio_data->kind == nct6776) {
26bc440e
GR		 2039 data->has_fan_div = false;
2040 data->fan_from_reg = fan_from_reg13;
2041 data->fan_from_reg_min = fan_from_reg13;
ec3e5a16
GR		 2042 data->REG_PWM = NCT6775_REG_PWM;
2043 data->REG_TARGET = NCT6775_REG_TARGET;
26bc440e 2044 data->REG_FAN = NCT6775_REG_FAN;
ec3e5a16
GR		 2045 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
2046 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
2047 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
2048 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
2049 } else if (sio_data->kind == w83667hg_b) {
26bc440e
GR		 2050 data->has_fan_div = true;
2051 data->fan_from_reg = fan_from_reg8;
2052 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2053 data->REG_PWM = W83627EHF_REG_PWM;
2054 data->REG_TARGET = W83627EHF_REG_TARGET;
2055 data->REG_FAN = W83627EHF_REG_FAN;
2056 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2057 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2058 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2059 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
c39aedaf
GR		 2060 data->REG_FAN_MAX_OUTPUT =
2061 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B;
2062 data->REG_FAN_STEP_OUTPUT =
2063 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B;
2064 } else {
26bc440e
GR		 2065 data->has_fan_div = true;
2066 data->fan_from_reg = fan_from_reg8;
2067 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2068 data->REG_PWM = W83627EHF_REG_PWM;
2069 data->REG_TARGET = W83627EHF_REG_TARGET;
2070 data->REG_FAN = W83627EHF_REG_FAN;
2071 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2072 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2073 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2074 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
c39aedaf
GR		 2075 data->REG_FAN_MAX_OUTPUT =
2076 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON;
2077 data->REG_FAN_STEP_OUTPUT =
2078 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON;
2079 }
da2e0255 2080
08e7e278 2081 /* Initialize the chip */
bf164c58 2082 w83627ehf_init_device(data, sio_data->kind);
08e7e278 2083
fc18d6c0
JD		 2084 data->vrm = vid_which_vrm();
2085 superio_enter(sio_data->sioreg);
fc18d6c0 2086 /* Read VID value */
ec3e5a16
GR		 2087 if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b ||
2088 sio_data->kind == nct6775 || sio_data->kind == nct6776) {
237c8d2f
GJ		 2089 /* W83667HG has different pins for VID input and output, so
2090 we can get the VID input values directly at logical device D
2091 0xe3. */
2092 superio_select(sio_data->sioreg, W83667HG_LD_VID);
2093 data->vid = superio_inb(sio_data->sioreg, 0xe3);
cbe311f2
JD		 2094 err = device_create_file(dev, &dev_attr_cpu0_vid);
2095 if (err)
2096 goto exit_release;
58e6e781 2097 } else {
237c8d2f
GJ		 2098 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2099 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
2100 /* Set VID input sensibility if needed. In theory the
2101 BIOS should have set it, but in practice it's not
2102 always the case. We only do it for the W83627EHF/EHG
2103 because the W83627DHG is more complex in this
2104 respect. */
2105 if (sio_data->kind == w83627ehf) {
2106 en_vrm10 = superio_inb(sio_data->sioreg,
2107 SIO_REG_EN_VRM10);
2108 if ((en_vrm10 & 0x08) && data->vrm == 90) {
2109 dev_warn(dev, "Setting VID input "
2110 "voltage to TTL\n");
2111 superio_outb(sio_data->sioreg,
2112 SIO_REG_EN_VRM10,
2113 en_vrm10 & ~0x08);
2114 } else if (!(en_vrm10 & 0x08)
2115 && data->vrm == 100) {
2116 dev_warn(dev, "Setting VID input "
2117 "voltage to VRM10\n");
2118 superio_outb(sio_data->sioreg,
2119 SIO_REG_EN_VRM10,
2120 en_vrm10 | 0x08);
2121 }
2122 }
2123
2124 data->vid = superio_inb(sio_data->sioreg,
2125 SIO_REG_VID_DATA);
2126 if (sio_data->kind == w83627ehf) /* 6 VID pins only */
2127 data->vid &= 0x3f;
2128
2129 err = device_create_file(dev, &dev_attr_cpu0_vid);
2130 if (err)
2131 goto exit_release;
2132 } else {
2133 dev_info(dev, "VID pins in output mode, CPU VID not "
2134 "available\n");
2135 }
fc18d6c0
JD		 2136 }
2137
08c79950 2138 /* fan4 and fan5 share some pins with the GPIO and serial flash */
ec3e5a16
GR		 2139 if (sio_data->kind == nct6775) {
2140 /* On NCT6775, fan4 shares pins with the fdc interface */
2141 fan3pin = 1;
2142 fan4pin = !(superio_inb(sio_data->sioreg, 0x2A) & 0x80);
2143 fan4min = 0;
2144 fan5pin = 0;
2145 } else if (sio_data->kind == nct6776) {
2146 fan3pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x40);
2147 fan4pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x01);
2148 fan5pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x02);
2149 fan4min = fan4pin;
2150 } else if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
2151 fan3pin = 1;
237c8d2f 2152 fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
ec3e5a16
GR		 2153 fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
2154 fan4min = fan4pin;
237c8d2f 2155 } else {
ec3e5a16 2156 fan3pin = 1;
237c8d2f 2157 fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
ec3e5a16
GR		 2158 fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
2159 fan4min = fan4pin;
237c8d2f 2160 }
d42e869a
ID		 2161
2162 if (fan_debounce &&
2163 (sio_data->kind == nct6775 || sio_data->kind == nct6776)) {
2164 u8 tmp;
2165
2166 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2167 tmp = superio_inb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE);
2168 if (sio_data->kind == nct6776)
2169 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2170 0x3e | tmp);
2171 else
2172 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2173 0x1e | tmp);
2174 pr_info("Enabled fan debounce for chip %s\n", data->name);
2175 }
2176
1ea6dd38 2177 superio_exit(sio_data->sioreg);
08c79950 2178
08e7e278 2179 /* It looks like fan4 and fan5 pins can be alternatively used
14992c7e
RM		 2180 as fan on/off switches, but fan5 control is write only :/
2181 We assume that if the serial interface is disabled, designers
2182 connected fan5 as input unless they are emitting log 1, which
2183 is not the default. */
08c79950 2184
ec3e5a16
GR		 2185 data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
2186
2187 data->has_fan |= (fan3pin << 2);
2188 data->has_fan_min |= (fan3pin << 2);
2189
2190 /*
2191 * NCT6775F and NCT6776F don't have the W83627EHF_REG_FANDIV1 register
2192 */
2193 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
2194 data->has_fan |= (fan4pin << 3) | (fan5pin << 4);
2195 data->has_fan_min |= (fan4min << 3) | (fan5pin << 4);
2196 } else {
2197 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
2198 if ((i & (1 << 2)) && fan4pin) {
2199 data->has_fan |= (1 << 3);
2200 data->has_fan_min |= (1 << 3);
2201 }
2202 if (!(i & (1 << 1)) && fan5pin) {
2203 data->has_fan |= (1 << 4);
2204 data->has_fan_min |= (1 << 4);
2205 }
2206 }
08e7e278 2207
ea7be66c 2208 /* Read fan clock dividers immediately */
ec3e5a16
GR		 2209 w83627ehf_update_fan_div_common(dev, data);
2210
2211 /* Read pwm data to save original values */
2212 w83627ehf_update_pwm_common(dev, data);
2213 for (i = 0; i < data->pwm_num; i++)
2214 data->pwm_enable_orig[i] = data->pwm_enable[i];
ea7be66c 2215
b84bb518
GR		 2216 /* Read pwm data to save original values */
2217 w83627ehf_update_pwm_common(dev, data);
2218 for (i = 0; i < data->pwm_num; i++)
2219 data->pwm_enable_orig[i] = data->pwm_enable[i];
2220
08e7e278 2221 /* Register sysfs hooks */
e7e1ca6e
GR		 2222 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++) {
2223 err = device_create_file(dev, &sda_sf3_arrays[i].dev_attr);
2224 if (err)
c18beb5b 2225 goto exit_remove;
e7e1ca6e 2226 }
08c79950 2227
da2e0255
GR		 2228 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
2229 struct sensor_device_attribute *attr =
2230 &sda_sf3_max_step_arrays[i];
ec3e5a16
GR		 2231 if (data->REG_FAN_STEP_OUTPUT &&
2232 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff) {
da2e0255
GR		 2233 err = device_create_file(dev, &attr->dev_attr);
2234 if (err)
2235 goto exit_remove;
2236 }
2237 }
08c79950 2238 /* if fan4 is enabled create the sf3 files for it */
237c8d2f 2239 if ((data->has_fan & (1 << 3)) && data->pwm_num >= 4)
c18beb5b 2240 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) {
e7e1ca6e
GR		 2241 err = device_create_file(dev,
2242 &sda_sf3_arrays_fan4[i].dev_attr);
2243 if (err)
c18beb5b
DH		 2244 goto exit_remove;
2245 }
08c79950 2246
a157d06d
GJ		 2247 for (i = 0; i < data->in_num; i++) {
2248 if ((i == 6) && data->in6_skip)
2249 continue;
c18beb5b
DH		 2250 if ((err = device_create_file(dev, &sda_in_input[i].dev_attr))
2251 || (err = device_create_file(dev,
2252 &sda_in_alarm[i].dev_attr))
2253 || (err = device_create_file(dev,
2254 &sda_in_min[i].dev_attr))
2255 || (err = device_create_file(dev,
2256 &sda_in_max[i].dev_attr)))
2257 goto exit_remove;
a157d06d 2258 }
cf0676fe 2259
412fec82 2260 for (i = 0; i < 5; i++) {
08c79950 2261 if (data->has_fan & (1 << i)) {
c18beb5b
DH		 2262 if ((err = device_create_file(dev,
2263 &sda_fan_input[i].dev_attr))
2264 || (err = device_create_file(dev,
ec3e5a16 2265 &sda_fan_alarm[i].dev_attr)))
c18beb5b 2266 goto exit_remove;
ec3e5a16
GR		 2267 if (sio_data->kind != nct6776) {
2268 err = device_create_file(dev,
2269 &sda_fan_div[i].dev_attr);
2270 if (err)
2271 goto exit_remove;
2272 }
2273 if (data->has_fan_min & (1 << i)) {
2274 err = device_create_file(dev,
2275 &sda_fan_min[i].dev_attr);
2276 if (err)
2277 goto exit_remove;
2278 }
237c8d2f 2279 if (i < data->pwm_num &&
c18beb5b
DH		 2280 ((err = device_create_file(dev,
2281 &sda_pwm[i].dev_attr))
2282 || (err = device_create_file(dev,
2283 &sda_pwm_mode[i].dev_attr))
2284 || (err = device_create_file(dev,
2285 &sda_pwm_enable[i].dev_attr))
2286 || (err = device_create_file(dev,
2287 &sda_target_temp[i].dev_attr))
2288 || (err = device_create_file(dev,
2289 &sda_tolerance[i].dev_attr))))
2290 goto exit_remove;
08c79950 2291 }
08e7e278 2292 }
08c79950 2293
d36cf32c
GR		 2294 for (i = 0; i < NUM_REG_TEMP; i++) {
2295 if (!(data->have_temp & (1 << i)))
a157d06d 2296 continue;
d36cf32c
GR		 2297 err = device_create_file(dev, &sda_temp_input[i].dev_attr);
2298 if (err)
2299 goto exit_remove;
2300 if (data->temp_label) {
2301 err = device_create_file(dev,
2302 &sda_temp_label[i].dev_attr);
2303 if (err)
2304 goto exit_remove;
2305 }
ec3e5a16
GR		 2306 if (data->reg_temp_over[i]) {
2307 err = device_create_file(dev,
2308 &sda_temp_max[i].dev_attr);
2309 if (err)
2310 goto exit_remove;
2311 }
2312 if (data->reg_temp_hyst[i]) {
2313 err = device_create_file(dev,
2314 &sda_temp_max_hyst[i].dev_attr);
2315 if (err)
2316 goto exit_remove;
2317 }
d36cf32c 2318 if (i > 2)
ec3e5a16
GR		 2319 continue;
2320 if ((err = device_create_file(dev,
a157d06d
GJ		 2321 &sda_temp_alarm[i].dev_attr))
2322 || (err = device_create_file(dev,
2323 &sda_temp_type[i].dev_attr)))
c18beb5b 2324 goto exit_remove;
a157d06d 2325 }
c18beb5b 2326
363a12a4
DA		 2327 err = device_create_file(dev, &sda_caseopen[0].dev_attr);
2328 if (err)
2329 goto exit_remove;
2330
2331 if (sio_data->kind == nct6776) {
2332 err = device_create_file(dev, &sda_caseopen[1].dev_attr);
2333 if (err)
2334 goto exit_remove;
2335 }
2336
1ea6dd38
DH		 2337 err = device_create_file(dev, &dev_attr_name);
2338 if (err)
2339 goto exit_remove;
2340
1beeffe4
TJ		 2341 data->hwmon_dev = hwmon_device_register(dev);
2342 if (IS_ERR(data->hwmon_dev)) {
2343 err = PTR_ERR(data->hwmon_dev);
c18beb5b
DH		 2344 goto exit_remove;
2345 }
08e7e278
JD		 2346
2347 return 0;
2348
c18beb5b
DH		 2349exit_remove:
2350 w83627ehf_device_remove_files(dev);
08e7e278 2351 kfree(data);
1ea6dd38 2352 platform_set_drvdata(pdev, NULL);
08e7e278 2353exit_release:
1ea6dd38 2354 release_region(res->start, IOREGION_LENGTH);
08e7e278
JD		 2355exit:
2356 return err;
2357}
2358
1ea6dd38 2359static int __devexit w83627ehf_remove(struct platform_device *pdev)
08e7e278 2360{
1ea6dd38 2361 struct w83627ehf_data *data = platform_get_drvdata(pdev);
08e7e278 2362
1beeffe4 2363 hwmon_device_unregister(data->hwmon_dev);
1ea6dd38
DH		 2364 w83627ehf_device_remove_files(&pdev->dev);
2365 release_region(data->addr, IOREGION_LENGTH);
2366 platform_set_drvdata(pdev, NULL);
943b0830 2367 kfree(data);
08e7e278
JD		 2368
2369 return 0;
2370}
2371
1ea6dd38 2372static struct platform_driver w83627ehf_driver = {
cdaf7934 2373 .driver = {
87218842 2374 .owner = THIS_MODULE,
1ea6dd38 2375 .name = DRVNAME,
cdaf7934 2376 },
1ea6dd38
DH		 2377 .probe = w83627ehf_probe,
2378 .remove = __devexit_p(w83627ehf_remove),
08e7e278
JD		 2379};
2380
1ea6dd38
DH		 2381/* w83627ehf_find() looks for a '627 in the Super-I/O config space */
2382static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
2383 struct w83627ehf_sio_data *sio_data)
08e7e278 2384{
1ea6dd38
DH		 2385 static const char __initdata sio_name_W83627EHF[] = "W83627EHF";
2386 static const char __initdata sio_name_W83627EHG[] = "W83627EHG";
2387 static const char __initdata sio_name_W83627DHG[] = "W83627DHG";
c1e48dce 2388 static const char __initdata sio_name_W83627DHG_P[] = "W83627DHG-P";
237c8d2f 2389 static const char __initdata sio_name_W83667HG[] = "W83667HG";
c39aedaf 2390 static const char __initdata sio_name_W83667HG_B[] = "W83667HG-B";
ec3e5a16
GR		 2391 static const char __initdata sio_name_NCT6775[] = "NCT6775F";
2392 static const char __initdata sio_name_NCT6776[] = "NCT6776F";
1ea6dd38 2393
08e7e278 2394 u16 val;
1ea6dd38 2395 const char *sio_name;
08e7e278 2396
1ea6dd38 2397 superio_enter(sioaddr);
08e7e278 2398
67b671bc
JD		 2399 if (force_id)
2400 val = force_id;
2401 else
2402 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
2403 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
657c93b1 2404 switch (val & SIO_ID_MASK) {
657c93b1 2405 case SIO_W83627EHF_ID:
1ea6dd38
DH		 2406 sio_data->kind = w83627ehf;
2407 sio_name = sio_name_W83627EHF;
2408 break;
657c93b1 2409 case SIO_W83627EHG_ID:
1ea6dd38
DH		 2410 sio_data->kind = w83627ehf;
2411 sio_name = sio_name_W83627EHG;
2412 break;
2413 case SIO_W83627DHG_ID:
2414 sio_data->kind = w83627dhg;
2415 sio_name = sio_name_W83627DHG;
657c93b1 2416 break;
c1e48dce
JD		 2417 case SIO_W83627DHG_P_ID:
2418 sio_data->kind = w83627dhg_p;
2419 sio_name = sio_name_W83627DHG_P;
2420 break;
237c8d2f
GJ		 2421 case SIO_W83667HG_ID:
2422 sio_data->kind = w83667hg;
2423 sio_name = sio_name_W83667HG;
2424 break;
c39aedaf
GR		 2425 case SIO_W83667HG_B_ID:
2426 sio_data->kind = w83667hg_b;
2427 sio_name = sio_name_W83667HG_B;
2428 break;
ec3e5a16
GR		 2429 case SIO_NCT6775_ID:
2430 sio_data->kind = nct6775;
2431 sio_name = sio_name_NCT6775;
2432 break;
2433 case SIO_NCT6776_ID:
2434 sio_data->kind = nct6776;
2435 sio_name = sio_name_NCT6776;
2436 break;
657c93b1 2437 default:
9f66036b 2438 if (val != 0xffff)
abdc6fd1 2439 pr_debug("unsupported chip ID: 0x%04x\n", val);
1ea6dd38 2440 superio_exit(sioaddr);
08e7e278
JD		 2441 return -ENODEV;
2442 }
2443
1ea6dd38
DH		 2444 /* We have a known chip, find the HWM I/O address */
2445 superio_select(sioaddr, W83627EHF_LD_HWM);
2446 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
2447 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
1a641fce 2448 *addr = val & IOREGION_ALIGNMENT;
2d8672c5 2449 if (*addr == 0) {
abdc6fd1 2450 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
1ea6dd38 2451 superio_exit(sioaddr);
08e7e278
JD		 2452 return -ENODEV;
2453 }
2454
2455 /* Activate logical device if needed */
1ea6dd38 2456 val = superio_inb(sioaddr, SIO_REG_ENABLE);
475ef855 2457 if (!(val & 0x01)) {
e7e1ca6e
GR		 2458 pr_warn("Forcibly enabling Super-I/O. "
2459 "Sensor is probably unusable.\n");
1ea6dd38 2460 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
475ef855 2461 }
1ea6dd38
DH		 2462
2463 superio_exit(sioaddr);
abdc6fd1 2464 pr_info("Found %s chip at %#x\n", sio_name, *addr);
1ea6dd38 2465 sio_data->sioreg = sioaddr;
08e7e278 2466
08e7e278
JD		 2467 return 0;
2468}
2469
1ea6dd38
DH		 2470/* when Super-I/O functions move to a separate file, the Super-I/O
2471 * bus will manage the lifetime of the device and this module will only keep
2472 * track of the w83627ehf driver. But since we platform_device_alloc(), we
2473 * must keep track of the device */
2474static struct platform_device *pdev;
2475
08e7e278
JD		 2476static int __init sensors_w83627ehf_init(void)
2477{
1ea6dd38
DH		 2478 int err;
2479 unsigned short address;
2480 struct resource res;
2481 struct w83627ehf_sio_data sio_data;
2482
2483 /* initialize sio_data->kind and sio_data->sioreg.
2484 *
2485 * when Super-I/O functions move to a separate file, the Super-I/O
2486 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
2487 * w83627ehf hardware monitor, and call probe() */
2488 if (w83627ehf_find(0x2e, &address, &sio_data) &&
2489 w83627ehf_find(0x4e, &address, &sio_data))
08e7e278
JD		 2490 return -ENODEV;
2491
1ea6dd38
DH		 2492 err = platform_driver_register(&w83627ehf_driver);
2493 if (err)
2494 goto exit;
2495
e7e1ca6e
GR		 2496 pdev = platform_device_alloc(DRVNAME, address);
2497 if (!pdev) {
1ea6dd38 2498 err = -ENOMEM;
abdc6fd1 2499 pr_err("Device allocation failed\n");
1ea6dd38
DH		 2500 goto exit_unregister;
2501 }
2502
2503 err = platform_device_add_data(pdev, &sio_data,
2504 sizeof(struct w83627ehf_sio_data));
2505 if (err) {
abdc6fd1 2506 pr_err("Platform data allocation failed\n");
1ea6dd38
DH		 2507 goto exit_device_put;
2508 }
2509
2510 memset(&res, 0, sizeof(res));
2511 res.name = DRVNAME;
2512 res.start = address + IOREGION_OFFSET;
2513 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
2514 res.flags = IORESOURCE_IO;
b9acb64a
JD		 2515
2516 err = acpi_check_resource_conflict(&res);
2517 if (err)
18632f84 2518 goto exit_device_put;
b9acb64a 2519
1ea6dd38
DH		 2520 err = platform_device_add_resources(pdev, &res, 1);
2521 if (err) {
abdc6fd1 2522 pr_err("Device resource addition failed (%d)\n", err);
1ea6dd38
DH		 2523 goto exit_device_put;
2524 }
2525
2526 /* platform_device_add calls probe() */
2527 err = platform_device_add(pdev);
2528 if (err) {
abdc6fd1 2529 pr_err("Device addition failed (%d)\n", err);
1ea6dd38
DH		 2530 goto exit_device_put;
2531 }
2532
2533 return 0;
2534
2535exit_device_put:
2536 platform_device_put(pdev);
2537exit_unregister:
2538 platform_driver_unregister(&w83627ehf_driver);
2539exit:
2540 return err;
08e7e278
JD		 2541}
2542
2543static void __exit sensors_w83627ehf_exit(void)
2544{
1ea6dd38
DH		 2545 platform_device_unregister(pdev);
2546 platform_driver_unregister(&w83627ehf_driver);
08e7e278
JD		 2547}
2548
2549MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
2550MODULE_DESCRIPTION("W83627EHF driver");
2551MODULE_LICENSE("GPL");
2552
2553module_init(sensors_w83627ehf_init);
2554module_exit(sensors_w83627ehf_exit);
Linux kernel - Deliverables
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