projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
hwmon: (w83627ehf) Add support for Nuvoton NCT6775F and NCT6776F
[deliverable/linux.git] / drivers / hwmon / w83627ehf.c
CommitLineData
08e7e278
JD		 1/*
2 w83627ehf - Driver for the hardware monitoring functionality of
e7e1ca6e 3 the Winbond W83627EHF Super-I/O chip
08e7e278 4 Copyright (C) 2005 Jean Delvare <khali@linux-fr.org>
3379ceee 5 Copyright (C) 2006 Yuan Mu (Winbond),
e7e1ca6e
GR		 6 Rudolf Marek <r.marek@assembler.cz>
7 David Hubbard <david.c.hubbard@gmail.com>
41e9a062 8 Daniel J Blueman <daniel.blueman@gmail.com>
ec3e5a16 9 Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
08e7e278
JD		 10
11 Shamelessly ripped from the w83627hf driver
12 Copyright (C) 2003 Mark Studebaker
13
14 Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
15 in testing and debugging this driver.
16
8dd2d2ca
JD		 17 This driver also supports the W83627EHG, which is the lead-free
18 version of the W83627EHF.
19
08e7e278
JD		 20 This program is free software; you can redistribute it and/or modify
21 it under the terms of the GNU General Public License as published by
22 the Free Software Foundation; either version 2 of the License, or
23 (at your option) any later version.
24
25 This program is distributed in the hope that it will be useful,
26 but WITHOUT ANY WARRANTY; without even the implied warranty of
27 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 GNU General Public License for more details.
29
30 You should have received a copy of the GNU General Public License
31 along with this program; if not, write to the Free Software
32 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
33
34
35 Supports the following chips:
36
657c93b1
DH		 37 Chip #vin #fan #pwm #temp chip IDs man ID
38 w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
e7e1ca6e 39 0x8860 0xa1
657c93b1 40 w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
c1e48dce 41 w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
237c8d2f 42 w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
d36cf32c 43 w83667hg-b 9 5 3 4 0xb350 0xc1 0x5ca3
ec3e5a16
GR		 44 nct6775f 9 4 3 9 0xb470 0xc1 0x5ca3
45 nct6776f 9 5 3 9 0xC330 0xc1 0x5ca3
08e7e278
JD		 46*/
47
abdc6fd1
JP		 48#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
08e7e278
JD		 50#include <linux/module.h>
51#include <linux/init.h>
52#include <linux/slab.h>
1ea6dd38
DH		 53#include <linux/jiffies.h>
54#include <linux/platform_device.h>
943b0830 55#include <linux/hwmon.h>
412fec82 56#include <linux/hwmon-sysfs.h>
fc18d6c0 57#include <linux/hwmon-vid.h>
943b0830 58#include <linux/err.h>
9a61bf63 59#include <linux/mutex.h>
b9acb64a 60#include <linux/acpi.h>
6055fae8 61#include <linux/io.h>
08e7e278
JD		 62#include "lm75.h"
63
ec3e5a16
GR		 64enum kinds { w83627ehf, w83627dhg, w83627dhg_p, w83667hg, w83667hg_b, nct6775,
65 nct6776 };
08e7e278 66
1ea6dd38 67/* used to set data->name = w83627ehf_device_names[data->sio_kind] */
e7e1ca6e 68static const char * const w83627ehf_device_names[] = {
1ea6dd38
DH		 69 "w83627ehf",
70 "w83627dhg",
c1e48dce 71 "w83627dhg",
237c8d2f 72 "w83667hg",
c39aedaf 73 "w83667hg",
ec3e5a16
GR		 74 "nct6775",
75 "nct6776",
1ea6dd38
DH		 76};
77
67b671bc
JD		 78static unsigned short force_id;
79module_param(force_id, ushort, 0);
80MODULE_PARM_DESC(force_id, "Override the detected device ID");
81
1ea6dd38 82#define DRVNAME "w83627ehf"
08e7e278 83
657c93b1 84/*
1ea6dd38 85 * Super-I/O constants and functions
657c93b1 86 */
08e7e278
JD		 87
88#define W83627EHF_LD_HWM 0x0b
e7e1ca6e 89#define W83667HG_LD_VID 0x0d
08e7e278
JD		 90
91#define SIO_REG_LDSEL 0x07 /* Logical device select */
92#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
fc18d6c0 93#define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
08e7e278
JD		 94#define SIO_REG_ENABLE 0x30 /* Logical device enable */
95#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
fc18d6c0
JD		 96#define SIO_REG_VID_CTRL 0xF0 /* VID control */
97#define SIO_REG_VID_DATA 0xF1 /* VID data */
08e7e278 98
657c93b1
DH		 99#define SIO_W83627EHF_ID 0x8850
100#define SIO_W83627EHG_ID 0x8860
101#define SIO_W83627DHG_ID 0xa020
c1e48dce 102#define SIO_W83627DHG_P_ID 0xb070
e7e1ca6e 103#define SIO_W83667HG_ID 0xa510
c39aedaf 104#define SIO_W83667HG_B_ID 0xb350
ec3e5a16
GR		 105#define SIO_NCT6775_ID 0xb470
106#define SIO_NCT6776_ID 0xc330
657c93b1 107#define SIO_ID_MASK 0xFFF0
08e7e278
JD		 108
109static inline void
1ea6dd38 110superio_outb(int ioreg, int reg, int val)
08e7e278 111{
1ea6dd38
DH		 112 outb(reg, ioreg);
113 outb(val, ioreg + 1);
08e7e278
JD		 114}
115
116static inline int
1ea6dd38 117superio_inb(int ioreg, int reg)
08e7e278 118{
1ea6dd38
DH		 119 outb(reg, ioreg);
120 return inb(ioreg + 1);
08e7e278
JD		 121}
122
123static inline void
1ea6dd38 124superio_select(int ioreg, int ld)
08e7e278 125{
1ea6dd38
DH		 126 outb(SIO_REG_LDSEL, ioreg);
127 outb(ld, ioreg + 1);
08e7e278
JD		 128}
129
130static inline void
1ea6dd38 131superio_enter(int ioreg)
08e7e278 132{
1ea6dd38
DH		 133 outb(0x87, ioreg);
134 outb(0x87, ioreg);
08e7e278
JD		 135}
136
137static inline void
1ea6dd38 138superio_exit(int ioreg)
08e7e278 139{
022b75a3 140 outb(0xaa, ioreg);
1ea6dd38
DH		 141 outb(0x02, ioreg);
142 outb(0x02, ioreg + 1);
08e7e278
JD		 143}
144
145/*
146 * ISA constants
147 */
148
e7e1ca6e 149#define IOREGION_ALIGNMENT (~7)
1a641fce
JD		 150#define IOREGION_OFFSET 5
151#define IOREGION_LENGTH 2
1ea6dd38
DH		 152#define ADDR_REG_OFFSET 0
153#define DATA_REG_OFFSET 1
08e7e278
JD		 154
155#define W83627EHF_REG_BANK 0x4E
156#define W83627EHF_REG_CONFIG 0x40
657c93b1
DH		 157
158/* Not currently used:
159 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
160 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
161 * REG_MAN_ID is at port 0x4f
162 * REG_CHIP_ID is at port 0x58 */
08e7e278
JD		 163
164static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
165static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
166
cf0676fe
RM		 167/* The W83627EHF registers for nr=7,8,9 are in bank 5 */
168#define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
169 (0x554 + (((nr) - 7) * 2)))
170#define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
171 (0x555 + (((nr) - 7) * 2)))
172#define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
173 (0x550 + (nr) - 7))
174
d36cf32c
GR		 175static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250, 0x7e };
176static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253, 0 };
177static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255, 0 };
178static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252, 0 };
08e7e278
JD		 179
180/* Fan clock dividers are spread over the following five registers */
181#define W83627EHF_REG_FANDIV1 0x47
182#define W83627EHF_REG_FANDIV2 0x4B
183#define W83627EHF_REG_VBAT 0x5D
184#define W83627EHF_REG_DIODE 0x59
185#define W83627EHF_REG_SMI_OVT 0x4C
186
ec3e5a16
GR		 187/* NCT6775F has its own fan divider registers */
188#define NCT6775_REG_FANDIV1 0x506
189#define NCT6775_REG_FANDIV2 0x507
190
a4589dbb
JD		 191#define W83627EHF_REG_ALARM1 0x459
192#define W83627EHF_REG_ALARM2 0x45A
193#define W83627EHF_REG_ALARM3 0x45B
194
08c79950 195/* SmartFan registers */
41e9a062
DB		 196#define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
197#define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
198
08c79950
RM		 199/* DC or PWM output fan configuration */
200static const u8 W83627EHF_REG_PWM_ENABLE[] = {
201 0x04, /* SYS FAN0 output mode and PWM mode */
202 0x04, /* CPU FAN0 output mode and PWM mode */
203 0x12, /* AUX FAN mode */
41e9a062 204 0x62, /* CPU FAN1 mode */
08c79950
RM		 205};
206
207static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
208static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
209
210/* FAN Duty Cycle, be used to control */
279af1a9
GR		 211static const u16 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
212static const u16 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
08c79950
RM		 213static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
214
08c79950 215/* Advanced Fan control, some values are common for all fans */
279af1a9
GR		 216static const u16 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
217static const u16 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
218static const u16 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
c39aedaf 219
279af1a9 220static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[]
c39aedaf 221 = { 0xff, 0x67, 0xff, 0x69 };
279af1a9 222static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[]
c39aedaf
GR		 223 = { 0xff, 0x68, 0xff, 0x6a };
224
279af1a9
GR		 225static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b };
226static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[]
227 = { 0x68, 0x6a, 0x6c };
08c79950 228
ec3e5a16
GR		 229static const u16 NCT6775_REG_TARGET[] = { 0x101, 0x201, 0x301 };
230static const u16 NCT6775_REG_FAN_MODE[] = { 0x102, 0x202, 0x302 };
231static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = { 0x105, 0x205, 0x305 };
232static const u16 NCT6775_REG_FAN_START_OUTPUT[] = { 0x106, 0x206, 0x306 };
233static const u16 NCT6775_REG_FAN_STOP_TIME[] = { 0x107, 0x207, 0x307 };
234static const u16 NCT6775_REG_PWM[] = { 0x109, 0x209, 0x309 };
235static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
236static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
237static const u16 NCT6776_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
238static const u16 NCT6776_REG_FAN_MIN[] = { 0x63a, 0x63c, 0x63e, 0x640, 0x642};
239
240static const u16 NCT6775_REG_TEMP[]
241 = { 0x27, 0x150, 0x250, 0x73, 0x75, 0x77, 0x62b, 0x62c, 0x62d };
242static const u16 NCT6775_REG_TEMP_CONFIG[]
243 = { 0, 0x152, 0x252, 0, 0, 0, 0x628, 0x629, 0x62A };
244static const u16 NCT6775_REG_TEMP_HYST[]
245 = { 0x3a, 0x153, 0x253, 0, 0, 0, 0x673, 0x678, 0x67D };
246static const u16 NCT6775_REG_TEMP_OVER[]
247 = { 0x39, 0x155, 0x255, 0, 0, 0, 0x672, 0x677, 0x67C };
248static const u16 NCT6775_REG_TEMP_SOURCE[]
249 = { 0x621, 0x622, 0x623, 0x100, 0x200, 0x300, 0x624, 0x625, 0x626 };
250
d36cf32c
GR		 251static const char *const w83667hg_b_temp_label[] = {
252 "SYSTIN",
253 "CPUTIN",
254 "AUXTIN",
255 "AMDTSI",
256 "PECI Agent 1",
257 "PECI Agent 2",
258 "PECI Agent 3",
259 "PECI Agent 4"
260};
261
ec3e5a16
GR		 262static const char *const nct6775_temp_label[] = {
263 "",
264 "SYSTIN",
265 "CPUTIN",
266 "AUXTIN",
267 "AMD SB-TSI",
268 "PECI Agent 0",
269 "PECI Agent 1",
270 "PECI Agent 2",
271 "PECI Agent 3",
272 "PECI Agent 4",
273 "PECI Agent 5",
274 "PECI Agent 6",
275 "PECI Agent 7",
276 "PCH_CHIP_CPU_MAX_TEMP",
277 "PCH_CHIP_TEMP",
278 "PCH_CPU_TEMP",
279 "PCH_MCH_TEMP",
280 "PCH_DIM0_TEMP",
281 "PCH_DIM1_TEMP",
282 "PCH_DIM2_TEMP",
283 "PCH_DIM3_TEMP"
284};
285
286static const char *const nct6776_temp_label[] = {
287 "",
288 "SYSTIN",
289 "CPUTIN",
290 "AUXTIN",
291 "SMBUSMASTER 0",
292 "SMBUSMASTER 1",
293 "SMBUSMASTER 2",
294 "SMBUSMASTER 3",
295 "SMBUSMASTER 4",
296 "SMBUSMASTER 5",
297 "SMBUSMASTER 6",
298 "SMBUSMASTER 7",
299 "PECI Agent 0",
300 "PECI Agent 1",
301 "PCH_CHIP_CPU_MAX_TEMP",
302 "PCH_CHIP_TEMP",
303 "PCH_CPU_TEMP",
304 "PCH_MCH_TEMP",
305 "PCH_DIM0_TEMP",
306 "PCH_DIM1_TEMP",
307 "PCH_DIM2_TEMP",
308 "PCH_DIM3_TEMP",
309 "BYTE_TEMP"
310};
311
312#define NUM_REG_TEMP ARRAY_SIZE(NCT6775_REG_TEMP)
d36cf32c 313
bce26c58
GR		 314static inline int is_word_sized(u16 reg)
315{
ec3e5a16 316 return ((((reg & 0xff00) == 0x100
bce26c58
GR		 317 || (reg & 0xff00) == 0x200)
318 && ((reg & 0x00ff) == 0x50
319 || (reg & 0x00ff) == 0x53
ec3e5a16
GR		 320 || (reg & 0x00ff) == 0x55))
321 || (reg & 0xfff0) == 0x630
322 || reg == 0x640 || reg == 0x642
323 || ((reg & 0xfff0) == 0x650
324 && (reg & 0x000f) >= 0x06)
325 || reg == 0x73 || reg == 0x75 || reg == 0x77
326 );
bce26c58
GR		 327}
328
08e7e278
JD		 329/*
330 * Conversions
331 */
332
08c79950
RM		 333/* 1 is PWM mode, output in ms */
334static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
335{
336 return mode ? 100 * reg : 400 * reg;
337}
338
339static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
340{
341 return SENSORS_LIMIT((mode ? (msec + 50) / 100 :
342 (msec + 200) / 400), 1, 255);
343}
344
08e7e278 345static inline unsigned int
ec3e5a16 346fan_from_reg(int reg, u16 val, unsigned int div)
08e7e278 347{
ec3e5a16 348 if (val == 0)
08e7e278 349 return 0;
ec3e5a16
GR		 350 if (is_word_sized(reg)) {
351 if ((val & 0xff1f) == 0xff1f)
352 return 0;
353 val = (val & 0x1f) | ((val & 0xff00) >> 3);
354 } else {
355 if (val == 255 || div == 0)
356 return 0;
357 val *= div;
358 }
359 return 1350000U / val;
08e7e278
JD		 360}
361
362static inline unsigned int
363div_from_reg(u8 reg)
364{
365 return 1 << reg;
366}
367
368static inline int
bce26c58 369temp_from_reg(u16 reg, s16 regval)
08e7e278 370{
bce26c58
GR		 371 if (is_word_sized(reg))
372 return LM75_TEMP_FROM_REG(regval);
373 return regval * 1000;
08e7e278
JD		 374}
375
ec3e5a16 376static inline u16
bce26c58 377temp_to_reg(u16 reg, long temp)
08e7e278 378{
bce26c58
GR		 379 if (is_word_sized(reg))
380 return LM75_TEMP_TO_REG(temp);
381 return DIV_ROUND_CLOSEST(SENSORS_LIMIT(temp, -127000, 128000), 1000);
08e7e278
JD		 382}
383
cf0676fe
RM		 384/* Some of analog inputs have internal scaling (2x), 8mV is ADC LSB */
385
386static u8 scale_in[10] = { 8, 8, 16, 16, 8, 8, 8, 16, 16, 8 };
387
388static inline long in_from_reg(u8 reg, u8 nr)
389{
390 return reg * scale_in[nr];
391}
392
393static inline u8 in_to_reg(u32 val, u8 nr)
394{
e7e1ca6e
GR		 395 return SENSORS_LIMIT(((val + (scale_in[nr] / 2)) / scale_in[nr]), 0,
396 255);
cf0676fe
RM		 397}
398
08e7e278
JD		 399/*
400 * Data structures and manipulation thereof
401 */
402
403struct w83627ehf_data {
1ea6dd38
DH		 404 int addr; /* IO base of hw monitor block */
405 const char *name;
406
1beeffe4 407 struct device *hwmon_dev;
9a61bf63 408 struct mutex lock;
08e7e278 409
ec3e5a16
GR		 410 u16 reg_temp[NUM_REG_TEMP];
411 u16 reg_temp_over[NUM_REG_TEMP];
412 u16 reg_temp_hyst[NUM_REG_TEMP];
413 u16 reg_temp_config[NUM_REG_TEMP];
d36cf32c
GR		 414 u8 temp_src[NUM_REG_TEMP];
415 const char * const *temp_label;
416
279af1a9
GR		 417 const u16 *REG_PWM;
418 const u16 *REG_TARGET;
419 const u16 *REG_FAN;
420 const u16 *REG_FAN_MIN;
421 const u16 *REG_FAN_START_OUTPUT;
422 const u16 *REG_FAN_STOP_OUTPUT;
423 const u16 *REG_FAN_STOP_TIME;
424 const u16 *REG_FAN_MAX_OUTPUT;
425 const u16 *REG_FAN_STEP_OUTPUT;
da2e0255 426
9a61bf63 427 struct mutex update_lock;
08e7e278
JD		 428 char valid; /* !=0 if following fields are valid */
429 unsigned long last_updated; /* In jiffies */
430
431 /* Register values */
83cc8985 432 u8 bank; /* current register bank */
1ea6dd38 433 u8 in_num; /* number of in inputs we have */
cf0676fe
RM		 434 u8 in[10]; /* Register value */
435 u8 in_max[10]; /* Register value */
436 u8 in_min[10]; /* Register value */
ec3e5a16
GR		 437 u16 fan[5];
438 u16 fan_min[5];
08e7e278
JD		 439 u8 fan_div[5];
440 u8 has_fan; /* some fan inputs can be disabled */
ec3e5a16 441 u8 has_fan_min; /* some fans don't have min register */
da667365 442 u8 temp_type[3];
ec3e5a16
GR		 443 s16 temp[9];
444 s16 temp_max[9];
445 s16 temp_max_hyst[9];
a4589dbb 446 u32 alarms;
08c79950
RM		 447
448 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
449 u8 pwm_enable[4]; /* 1->manual
41e9a062
DB		 450 2->thermal cruise mode (also called SmartFan I)
451 3->fan speed cruise mode
e7e1ca6e 452 4->variable thermal cruise (also called
b84bb518
GR		 453 SmartFan III)
454 5->enhanced variable thermal cruise (also called
455 SmartFan IV) */
456 u8 pwm_enable_orig[4]; /* original value of pwm_enable */
237c8d2f 457 u8 pwm_num; /* number of pwm */
08c79950
RM		 458 u8 pwm[4];
459 u8 target_temp[4];
460 u8 tolerance[4];
461
41e9a062
DB		 462 u8 fan_start_output[4]; /* minimum fan speed when spinning up */
463 u8 fan_stop_output[4]; /* minimum fan speed when spinning down */
464 u8 fan_stop_time[4]; /* time at minimum before disabling fan */
465 u8 fan_max_output[4]; /* maximum fan speed */
466 u8 fan_step_output[4]; /* rate of change output value */
fc18d6c0
JD		 467
468 u8 vid;
469 u8 vrm;
a157d06d 470
ec3e5a16 471 u16 have_temp;
a157d06d 472 u8 in6_skip;
08e7e278
JD		 473};
474
1ea6dd38
DH		 475struct w83627ehf_sio_data {
476 int sioreg;
477 enum kinds kind;
478};
479
83cc8985
GR		 480/*
481 * On older chips, only registers 0x50-0x5f are banked.
482 * On more recent chips, all registers are banked.
483 * Assume that is the case and set the bank number for each access.
484 * Cache the bank number so it only needs to be set if it changes.
485 */
1ea6dd38 486static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
08e7e278 487{
83cc8985
GR		 488 u8 bank = reg >> 8;
489 if (data->bank != bank) {
1ea6dd38 490 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
83cc8985
GR		 491 outb_p(bank, data->addr + DATA_REG_OFFSET);
492 data->bank = bank;
08e7e278
JD		 493 }
494}
495
1ea6dd38 496static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
08e7e278 497{
08e7e278
JD		 498 int res, word_sized = is_word_sized(reg);
499
9a61bf63 500 mutex_lock(&data->lock);
08e7e278 501
1ea6dd38
DH		 502 w83627ehf_set_bank(data, reg);
503 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
504 res = inb_p(data->addr + DATA_REG_OFFSET);
08e7e278
JD		 505 if (word_sized) {
506 outb_p((reg & 0xff) + 1,
1ea6dd38
DH		 507 data->addr + ADDR_REG_OFFSET);
508 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
08e7e278 509 }
08e7e278 510
9a61bf63 511 mutex_unlock(&data->lock);
08e7e278
JD		 512 return res;
513}
514
e7e1ca6e
GR		 515static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg,
516 u16 value)
08e7e278 517{
08e7e278
JD		 518 int word_sized = is_word_sized(reg);
519
9a61bf63 520 mutex_lock(&data->lock);
08e7e278 521
1ea6dd38
DH		 522 w83627ehf_set_bank(data, reg);
523 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
08e7e278 524 if (word_sized) {
1ea6dd38 525 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
08e7e278 526 outb_p((reg & 0xff) + 1,
1ea6dd38 527 data->addr + ADDR_REG_OFFSET);
08e7e278 528 }
1ea6dd38 529 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
08e7e278 530
9a61bf63 531 mutex_unlock(&data->lock);
08e7e278
JD		 532 return 0;
533}
534
ec3e5a16
GR		 535/* This function assumes that the caller holds data->update_lock */
536static void nct6775_write_fan_div(struct w83627ehf_data *data, int nr)
537{
538 u8 reg;
539
540 switch (nr) {
541 case 0:
542 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
543 | (data->fan_div[0] & 0x7);
544 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
545 break;
546 case 1:
547 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
548 | ((data->fan_div[1] << 4) & 0x70);
549 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
550 case 2:
551 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
552 | (data->fan_div[2] & 0x7);
553 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
554 break;
555 case 3:
556 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
557 | ((data->fan_div[3] << 4) & 0x70);
558 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
559 break;
560 }
561}
562
08e7e278 563/* This function assumes that the caller holds data->update_lock */
1ea6dd38 564static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
08e7e278 565{
08e7e278
JD		 566 u8 reg;
567
568 switch (nr) {
569 case 0:
1ea6dd38 570 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
08e7e278 571 | ((data->fan_div[0] & 0x03) << 4);
14992c7e
RM		 572 /* fan5 input control bit is write only, compute the value */
573 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 574 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
575 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
08e7e278 576 | ((data->fan_div[0] & 0x04) << 3);
1ea6dd38 577 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 578 break;
579 case 1:
1ea6dd38 580 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
08e7e278 581 | ((data->fan_div[1] & 0x03) << 6);
14992c7e
RM		 582 /* fan5 input control bit is write only, compute the value */
583 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 584 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
585 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
08e7e278 586 | ((data->fan_div[1] & 0x04) << 4);
1ea6dd38 587 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 588 break;
589 case 2:
1ea6dd38 590 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
08e7e278 591 | ((data->fan_div[2] & 0x03) << 6);
1ea6dd38
DH		 592 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
593 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
08e7e278 594 | ((data->fan_div[2] & 0x04) << 5);
1ea6dd38 595 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 596 break;
597 case 3:
1ea6dd38 598 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
08e7e278 599 | (data->fan_div[3] & 0x03);
1ea6dd38
DH		 600 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
601 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
08e7e278 602 | ((data->fan_div[3] & 0x04) << 5);
1ea6dd38 603 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
08e7e278
JD		 604 break;
605 case 4:
1ea6dd38 606 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
33725ad3 607 | ((data->fan_div[4] & 0x03) << 2)
08e7e278 608 | ((data->fan_div[4] & 0x04) << 5);
1ea6dd38 609 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
08e7e278
JD		 610 break;
611 }
612}
613
ec3e5a16
GR		 614static void w83627ehf_write_fan_div_common(struct device *dev,
615 struct w83627ehf_data *data, int nr)
616{
617 struct w83627ehf_sio_data *sio_data = dev->platform_data;
618
619 if (sio_data->kind == nct6776)
620 ; /* no dividers, do nothing */
621 else if (sio_data->kind == nct6775)
622 nct6775_write_fan_div(data, nr);
623 else
624 w83627ehf_write_fan_div(data, nr);
625}
626
627static void nct6775_update_fan_div(struct w83627ehf_data *data)
628{
629 u8 i;
630
631 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV1);
632 data->fan_div[0] = i & 0x7;
633 data->fan_div[1] = (i & 0x70) >> 4;
634 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV2);
635 data->fan_div[2] = i & 0x7;
636 if (data->has_fan & (1<<3))
637 data->fan_div[3] = (i & 0x70) >> 4;
638}
639
ea7be66c
MH		 640static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
641{
642 int i;
643
644 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
645 data->fan_div[0] = (i >> 4) & 0x03;
646 data->fan_div[1] = (i >> 6) & 0x03;
647 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
648 data->fan_div[2] = (i >> 6) & 0x03;
649 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
650 data->fan_div[0] |= (i >> 3) & 0x04;
651 data->fan_div[1] |= (i >> 4) & 0x04;
652 data->fan_div[2] |= (i >> 5) & 0x04;
653 if (data->has_fan & ((1 << 3) | (1 << 4))) {
654 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
655 data->fan_div[3] = i & 0x03;
656 data->fan_div[4] = ((i >> 2) & 0x03)
657 | ((i >> 5) & 0x04);
658 }
659 if (data->has_fan & (1 << 3)) {
660 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
661 data->fan_div[3] |= (i >> 5) & 0x04;
662 }
663}
664
ec3e5a16
GR		 665static void w83627ehf_update_fan_div_common(struct device *dev,
666 struct w83627ehf_data *data)
667{
668 struct w83627ehf_sio_data *sio_data = dev->platform_data;
669
670 if (sio_data->kind == nct6776)
671 ; /* no dividers, do nothing */
672 else if (sio_data->kind == nct6775)
673 nct6775_update_fan_div(data);
674 else
675 w83627ehf_update_fan_div(data);
676}
677
678static void nct6775_update_pwm(struct w83627ehf_data *data)
679{
680 int i;
681 int pwmcfg, fanmodecfg;
682
683 for (i = 0; i < data->pwm_num; i++) {
684 pwmcfg = w83627ehf_read_value(data,
685 W83627EHF_REG_PWM_ENABLE[i]);
686 fanmodecfg = w83627ehf_read_value(data,
687 NCT6775_REG_FAN_MODE[i]);
688 data->pwm_mode[i] =
689 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
690 data->pwm_enable[i] = ((fanmodecfg >> 4) & 7) + 1;
691 data->tolerance[i] = fanmodecfg & 0x0f;
692 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
693 }
694}
695
696static void w83627ehf_update_pwm(struct w83627ehf_data *data)
697{
698 int i;
699 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
700
701 for (i = 0; i < data->pwm_num; i++) {
702 if (!(data->has_fan & (1 << i)))
703 continue;
704
705 /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
706 if (i != 1) {
707 pwmcfg = w83627ehf_read_value(data,
708 W83627EHF_REG_PWM_ENABLE[i]);
709 tolerance = w83627ehf_read_value(data,
710 W83627EHF_REG_TOLERANCE[i]);
711 }
712 data->pwm_mode[i] =
713 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
714 data->pwm_enable[i] = ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
715 & 3) + 1;
716 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
717
718 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0)) & 0x0f;
719 }
720}
721
722static void w83627ehf_update_pwm_common(struct device *dev,
723 struct w83627ehf_data *data)
724{
725 struct w83627ehf_sio_data *sio_data = dev->platform_data;
726
727 if (sio_data->kind == nct6775 || sio_data->kind == nct6776)
728 nct6775_update_pwm(data);
729 else
730 w83627ehf_update_pwm(data);
731}
732
08e7e278
JD		 733static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
734{
1ea6dd38 735 struct w83627ehf_data *data = dev_get_drvdata(dev);
ec3e5a16
GR		 736 struct w83627ehf_sio_data *sio_data = dev->platform_data;
737
08e7e278
JD		 738 int i;
739
9a61bf63 740 mutex_lock(&data->update_lock);
08e7e278 741
6b3e4645 742 if (time_after(jiffies, data->last_updated + HZ + HZ/2)
08e7e278
JD		 743 || !data->valid) {
744 /* Fan clock dividers */
ec3e5a16 745 w83627ehf_update_fan_div_common(dev, data);
08e7e278 746
cf0676fe 747 /* Measured voltages and limits */
1ea6dd38
DH		 748 for (i = 0; i < data->in_num; i++) {
749 data->in[i] = w83627ehf_read_value(data,
cf0676fe 750 W83627EHF_REG_IN(i));
1ea6dd38 751 data->in_min[i] = w83627ehf_read_value(data,
cf0676fe 752 W83627EHF_REG_IN_MIN(i));
1ea6dd38 753 data->in_max[i] = w83627ehf_read_value(data,
cf0676fe
RM		 754 W83627EHF_REG_IN_MAX(i));
755 }
756
08e7e278
JD		 757 /* Measured fan speeds and limits */
758 for (i = 0; i < 5; i++) {
759 if (!(data->has_fan & (1 << i)))
760 continue;
761
1ea6dd38 762 data->fan[i] = w83627ehf_read_value(data,
ec3e5a16
GR		 763 data->REG_FAN[i]);
764
765 if (data->has_fan_min & (1 << i))
766 data->fan_min[i] = w83627ehf_read_value(data,
279af1a9 767 data->REG_FAN_MIN[i]);
08e7e278
JD		 768
769 /* If we failed to measure the fan speed and clock
770 divider can be increased, let's try that for next
771 time */
ec3e5a16
GR		 772 if (!is_word_sized(data->REG_FAN[i])
773 && (data->fan[i] == 0xff
774 || (sio_data->kind == nct6775
775 && data->fan[i] == 0x00))
776 && data->fan_div[i] < 0x07) {
e7e1ca6e 777 dev_dbg(dev, "Increasing fan%d "
08e7e278 778 "clock divider from %u to %u\n",
33725ad3 779 i + 1, div_from_reg(data->fan_div[i]),
08e7e278
JD		 780 div_from_reg(data->fan_div[i] + 1));
781 data->fan_div[i]++;
ec3e5a16 782 w83627ehf_write_fan_div_common(dev, data, i);
08e7e278 783 /* Preserve min limit if possible */
ec3e5a16
GR		 784 if ((data->has_fan_min & (1 << i))
785 && data->fan_min[i] >= 2
08e7e278 786 && data->fan_min[i] != 255)
1ea6dd38 787 w83627ehf_write_value(data,
279af1a9 788 data->REG_FAN_MIN[i],
08e7e278
JD		 789 (data->fan_min[i] /= 2));
790 }
791 }
792
ec3e5a16
GR		 793 w83627ehf_update_pwm_common(dev, data);
794
da2e0255
GR		 795 for (i = 0; i < data->pwm_num; i++) {
796 if (!(data->has_fan & (1 << i)))
797 continue;
798
ec3e5a16
GR		 799 data->fan_start_output[i] =
800 w83627ehf_read_value(data,
801 data->REG_FAN_START_OUTPUT[i]);
802 data->fan_stop_output[i] =
803 w83627ehf_read_value(data,
804 data->REG_FAN_STOP_OUTPUT[i]);
805 data->fan_stop_time[i] =
806 w83627ehf_read_value(data,
807 data->REG_FAN_STOP_TIME[i]);
808
809 if (data->REG_FAN_MAX_OUTPUT &&
810 data->REG_FAN_MAX_OUTPUT[i] != 0xff)
da2e0255
GR		 811 data->fan_max_output[i] =
812 w83627ehf_read_value(data,
ec3e5a16 813 data->REG_FAN_MAX_OUTPUT[i]);
da2e0255 814
ec3e5a16
GR		 815 if (data->REG_FAN_STEP_OUTPUT &&
816 data->REG_FAN_STEP_OUTPUT[i] != 0xff)
da2e0255
GR		 817 data->fan_step_output[i] =
818 w83627ehf_read_value(data,
ec3e5a16 819 data->REG_FAN_STEP_OUTPUT[i]);
da2e0255 820
08c79950 821 data->target_temp[i] =
1ea6dd38 822 w83627ehf_read_value(data,
279af1a9 823 data->REG_TARGET[i]) &
08c79950 824 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
08c79950
RM		 825 }
826
08e7e278 827 /* Measured temperatures and limits */
d36cf32c
GR		 828 for (i = 0; i < NUM_REG_TEMP; i++) {
829 if (!(data->have_temp & (1 << i)))
830 continue;
ec3e5a16
GR		 831 data->temp[i] = w83627ehf_read_value(data,
832 data->reg_temp[i]);
833 if (data->reg_temp_over[i])
834 data->temp_max[i]
835 = w83627ehf_read_value(data,
836 data->reg_temp_over[i]);
837 if (data->reg_temp_hyst[i])
838 data->temp_max_hyst[i]
839 = w83627ehf_read_value(data,
840 data->reg_temp_hyst[i]);
08e7e278
JD		 841 }
842
1ea6dd38 843 data->alarms = w83627ehf_read_value(data,
a4589dbb 844 W83627EHF_REG_ALARM1) |
1ea6dd38 845 (w83627ehf_read_value(data,
a4589dbb 846 W83627EHF_REG_ALARM2) << 8) |
1ea6dd38 847 (w83627ehf_read_value(data,
a4589dbb
JD		 848 W83627EHF_REG_ALARM3) << 16);
849
08e7e278
JD		 850 data->last_updated = jiffies;
851 data->valid = 1;
852 }
853
9a61bf63 854 mutex_unlock(&data->update_lock);
08e7e278
JD		 855 return data;
856}
857
858/*
859 * Sysfs callback functions
860 */
cf0676fe
RM		 861#define show_in_reg(reg) \
862static ssize_t \
863show_##reg(struct device *dev, struct device_attribute *attr, \
864 char *buf) \
865{ \
866 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 867 struct sensor_device_attribute *sensor_attr = \
868 to_sensor_dev_attr(attr); \
cf0676fe
RM		 869 int nr = sensor_attr->index; \
870 return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr)); \
871}
872show_in_reg(in)
873show_in_reg(in_min)
874show_in_reg(in_max)
875
876#define store_in_reg(REG, reg) \
877static ssize_t \
e7e1ca6e
GR		 878store_in_##reg(struct device *dev, struct device_attribute *attr, \
879 const char *buf, size_t count) \
cf0676fe 880{ \
1ea6dd38 881 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 882 struct sensor_device_attribute *sensor_attr = \
883 to_sensor_dev_attr(attr); \
cf0676fe 884 int nr = sensor_attr->index; \
bce26c58
GR		 885 unsigned long val; \
886 int err; \
887 err = strict_strtoul(buf, 10, &val); \
888 if (err < 0) \
889 return err; \
cf0676fe
RM		 890 mutex_lock(&data->update_lock); \
891 data->in_##reg[nr] = in_to_reg(val, nr); \
1ea6dd38 892 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \
cf0676fe
RM		 893 data->in_##reg[nr]); \
894 mutex_unlock(&data->update_lock); \
895 return count; \
896}
897
898store_in_reg(MIN, min)
899store_in_reg(MAX, max)
900
e7e1ca6e
GR		 901static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
902 char *buf)
a4589dbb
JD		 903{
904 struct w83627ehf_data *data = w83627ehf_update_device(dev);
905 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
906 int nr = sensor_attr->index;
907 return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01);
908}
909
cf0676fe
RM		 910static struct sensor_device_attribute sda_in_input[] = {
911 SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
912 SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
913 SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
914 SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
915 SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
916 SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
917 SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
918 SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
919 SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
920 SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9),
921};
922
a4589dbb
JD		 923static struct sensor_device_attribute sda_in_alarm[] = {
924 SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0),
925 SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1),
926 SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2),
927 SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3),
928 SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8),
929 SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21),
930 SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20),
931 SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16),
932 SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17),
933 SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19),
934};
935
cf0676fe 936static struct sensor_device_attribute sda_in_min[] = {
e7e1ca6e
GR		 937 SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0),
938 SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1),
939 SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2),
940 SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3),
941 SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4),
942 SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5),
943 SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6),
944 SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7),
945 SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8),
946 SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9),
cf0676fe
RM		 947};
948
949static struct sensor_device_attribute sda_in_max[] = {
e7e1ca6e
GR		 950 SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0),
951 SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1),
952 SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2),
953 SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3),
954 SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4),
955 SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5),
956 SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6),
957 SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7),
958 SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8),
959 SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9),
cf0676fe
RM		 960};
961
ec3e5a16
GR		 962static ssize_t
963show_fan(struct device *dev, struct device_attribute *attr, char *buf)
964{
965 struct w83627ehf_data *data = w83627ehf_update_device(dev);
966 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
967 int nr = sensor_attr->index;
968 return sprintf(buf, "%d\n",
969 fan_from_reg(data->REG_FAN[nr],
970 data->fan[nr],
971 div_from_reg(data->fan_div[nr])));
972}
973
974static ssize_t
975show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
976{
977 struct w83627ehf_data *data = w83627ehf_update_device(dev);
978 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
979 int nr = sensor_attr->index;
980 return sprintf(buf, "%d\n",
981 fan_from_reg(data->REG_FAN_MIN[nr],
982 data->fan_min[nr],
983 div_from_reg(data->fan_div[nr])));
08e7e278 984}
08e7e278
JD		 985
986static ssize_t
412fec82
YM		 987show_fan_div(struct device *dev, struct device_attribute *attr,
988 char *buf)
08e7e278
JD		 989{
990 struct w83627ehf_data *data = w83627ehf_update_device(dev);
412fec82
YM		 991 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
992 int nr = sensor_attr->index;
993 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
08e7e278
JD		 994}
995
996static ssize_t
412fec82
YM		 997store_fan_min(struct device *dev, struct device_attribute *attr,
998 const char *buf, size_t count)
08e7e278 999{
1ea6dd38 1000 struct w83627ehf_data *data = dev_get_drvdata(dev);
412fec82
YM		 1001 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1002 int nr = sensor_attr->index;
bce26c58
GR		 1003 unsigned long val;
1004 int err;
08e7e278
JD		 1005 unsigned int reg;
1006 u8 new_div;
1007
bce26c58
GR		 1008 err = strict_strtoul(buf, 10, &val);
1009 if (err < 0)
1010 return err;
1011
9a61bf63 1012 mutex_lock(&data->update_lock);
ec3e5a16
GR		 1013 if (is_word_sized(data->REG_FAN_MIN[nr])) {
1014 if (!val) {
1015 val = 0xff1f;
1016 } else {
1017 if (val > 1350000U)
1018 val = 135000U;
1019 val = 1350000U / val;
1020 val = (val & 0x1f) | ((val << 3) & 0xff00);
1021 }
1022 data->fan_min[nr] = val;
1023 goto done; /* Leave fan divider alone */
1024 }
08e7e278
JD		 1025 if (!val) {
1026 /* No min limit, alarm disabled */
1027 data->fan_min[nr] = 255;
1028 new_div = data->fan_div[nr]; /* No change */
1029 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
1030 } else if ((reg = 1350000U / val) >= 128 * 255) {
1031 /* Speed below this value cannot possibly be represented,
1032 even with the highest divider (128) */
1033 data->fan_min[nr] = 254;
1034 new_div = 7; /* 128 == (1 << 7) */
bce26c58 1035 dev_warn(dev, "fan%u low limit %lu below minimum %u, set to "
ec3e5a16
GR		 1036 "minimum\n", nr + 1, val,
1037 fan_from_reg(data->REG_FAN_MIN[nr], 254, 128));
08e7e278
JD		 1038 } else if (!reg) {
1039 /* Speed above this value cannot possibly be represented,
1040 even with the lowest divider (1) */
1041 data->fan_min[nr] = 1;
1042 new_div = 0; /* 1 == (1 << 0) */
bce26c58 1043 dev_warn(dev, "fan%u low limit %lu above maximum %u, set to "
ec3e5a16
GR		 1044 "maximum\n", nr + 1, val,
1045 fan_from_reg(data->REG_FAN_MIN[nr], 1, 1));
08e7e278
JD		 1046 } else {
1047 /* Automatically pick the best divider, i.e. the one such
1048 that the min limit will correspond to a register value
1049 in the 96..192 range */
1050 new_div = 0;
1051 while (reg > 192 && new_div < 7) {
1052 reg >>= 1;
1053 new_div++;
1054 }
1055 data->fan_min[nr] = reg;
1056 }
1057
1058 /* Write both the fan clock divider (if it changed) and the new
1059 fan min (unconditionally) */
1060 if (new_div != data->fan_div[nr]) {
158ce075
JD		 1061 /* Preserve the fan speed reading */
1062 if (data->fan[nr] != 0xff) {
1063 if (new_div > data->fan_div[nr])
1064 data->fan[nr] >>= new_div - data->fan_div[nr];
1065 else if (data->fan[nr] & 0x80)
1066 data->fan[nr] = 0xff;
1067 else
1068 data->fan[nr] <<= data->fan_div[nr] - new_div;
1069 }
08e7e278
JD		 1070
1071 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
1072 nr + 1, div_from_reg(data->fan_div[nr]),
1073 div_from_reg(new_div));
1074 data->fan_div[nr] = new_div;
ec3e5a16 1075 w83627ehf_write_fan_div_common(dev, data, nr);
6b3e4645
JD		 1076 /* Give the chip time to sample a new speed value */
1077 data->last_updated = jiffies;
08e7e278 1078 }
ec3e5a16 1079done:
279af1a9 1080 w83627ehf_write_value(data, data->REG_FAN_MIN[nr],
08e7e278 1081 data->fan_min[nr]);
9a61bf63 1082 mutex_unlock(&data->update_lock);
08e7e278
JD		 1083
1084 return count;
1085}
1086
412fec82
YM		 1087static struct sensor_device_attribute sda_fan_input[] = {
1088 SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
1089 SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
1090 SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
1091 SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
1092 SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4),
1093};
08e7e278 1094
a4589dbb
JD		 1095static struct sensor_device_attribute sda_fan_alarm[] = {
1096 SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6),
1097 SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7),
1098 SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11),
1099 SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10),
1100 SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23),
1101};
1102
412fec82
YM		 1103static struct sensor_device_attribute sda_fan_min[] = {
1104 SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min,
1105 store_fan_min, 0),
1106 SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min,
1107 store_fan_min, 1),
1108 SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min,
1109 store_fan_min, 2),
1110 SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min,
1111 store_fan_min, 3),
1112 SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min,
1113 store_fan_min, 4),
1114};
08e7e278 1115
412fec82
YM		 1116static struct sensor_device_attribute sda_fan_div[] = {
1117 SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0),
1118 SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1),
1119 SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2),
1120 SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3),
1121 SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4),
1122};
1123
d36cf32c
GR		 1124static ssize_t
1125show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
1126{
1127 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1128 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1129 int nr = sensor_attr->index;
1130 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
1131}
1132
ec3e5a16 1133#define show_temp_reg(addr, reg) \
08e7e278 1134static ssize_t \
412fec82
YM		 1135show_##reg(struct device *dev, struct device_attribute *attr, \
1136 char *buf) \
08e7e278
JD		 1137{ \
1138 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1139 struct sensor_device_attribute *sensor_attr = \
1140 to_sensor_dev_attr(attr); \
412fec82 1141 int nr = sensor_attr->index; \
08e7e278 1142 return sprintf(buf, "%d\n", \
ec3e5a16 1143 temp_from_reg(data->addr[nr], data->reg[nr])); \
08e7e278 1144}
ec3e5a16
GR		 1145show_temp_reg(reg_temp, temp);
1146show_temp_reg(reg_temp_over, temp_max);
1147show_temp_reg(reg_temp_hyst, temp_max_hyst);
08e7e278 1148
ec3e5a16 1149#define store_temp_reg(addr, reg) \
08e7e278 1150static ssize_t \
412fec82
YM		 1151store_##reg(struct device *dev, struct device_attribute *attr, \
1152 const char *buf, size_t count) \
08e7e278 1153{ \
1ea6dd38 1154 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1155 struct sensor_device_attribute *sensor_attr = \
1156 to_sensor_dev_attr(attr); \
412fec82 1157 int nr = sensor_attr->index; \
bce26c58
GR		 1158 int err; \
1159 long val; \
1160 err = strict_strtol(buf, 10, &val); \
1161 if (err < 0) \
1162 return err; \
9a61bf63 1163 mutex_lock(&data->update_lock); \
ec3e5a16
GR		 1164 data->reg[nr] = temp_to_reg(data->addr[nr], val); \
1165 w83627ehf_write_value(data, data->addr[nr], \
08e7e278 1166 data->reg[nr]); \
9a61bf63 1167 mutex_unlock(&data->update_lock); \
08e7e278
JD		 1168 return count; \
1169}
ec3e5a16
GR		 1170store_temp_reg(reg_temp_over, temp_max);
1171store_temp_reg(reg_temp_hyst, temp_max_hyst);
08e7e278 1172
da667365
JD		 1173static ssize_t
1174show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
1175{
1176 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1177 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1178 int nr = sensor_attr->index;
1179 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
1180}
1181
a157d06d 1182static struct sensor_device_attribute sda_temp_input[] = {
bce26c58
GR		 1183 SENSOR_ATTR(temp1_input, S_IRUGO, show_temp, NULL, 0),
1184 SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 1),
1185 SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 2),
d36cf32c 1186 SENSOR_ATTR(temp4_input, S_IRUGO, show_temp, NULL, 3),
ec3e5a16
GR		 1187 SENSOR_ATTR(temp5_input, S_IRUGO, show_temp, NULL, 4),
1188 SENSOR_ATTR(temp6_input, S_IRUGO, show_temp, NULL, 5),
1189 SENSOR_ATTR(temp7_input, S_IRUGO, show_temp, NULL, 6),
1190 SENSOR_ATTR(temp8_input, S_IRUGO, show_temp, NULL, 7),
1191 SENSOR_ATTR(temp9_input, S_IRUGO, show_temp, NULL, 8),
d36cf32c
GR		 1192};
1193
1194static struct sensor_device_attribute sda_temp_label[] = {
1195 SENSOR_ATTR(temp1_label, S_IRUGO, show_temp_label, NULL, 0),
1196 SENSOR_ATTR(temp2_label, S_IRUGO, show_temp_label, NULL, 1),
1197 SENSOR_ATTR(temp3_label, S_IRUGO, show_temp_label, NULL, 2),
1198 SENSOR_ATTR(temp4_label, S_IRUGO, show_temp_label, NULL, 3),
ec3e5a16
GR		 1199 SENSOR_ATTR(temp5_label, S_IRUGO, show_temp_label, NULL, 4),
1200 SENSOR_ATTR(temp6_label, S_IRUGO, show_temp_label, NULL, 5),
1201 SENSOR_ATTR(temp7_label, S_IRUGO, show_temp_label, NULL, 6),
1202 SENSOR_ATTR(temp8_label, S_IRUGO, show_temp_label, NULL, 7),
1203 SENSOR_ATTR(temp9_label, S_IRUGO, show_temp_label, NULL, 8),
a157d06d
GJ		 1204};
1205
1206static struct sensor_device_attribute sda_temp_max[] = {
bce26c58 1207 SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp_max,
412fec82 1208 store_temp_max, 0),
bce26c58 1209 SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max,
412fec82 1210 store_temp_max, 1),
bce26c58
GR		 1211 SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max,
1212 store_temp_max, 2),
ec3e5a16
GR		 1213 SENSOR_ATTR(temp4_max, S_IRUGO | S_IWUSR, show_temp_max,
1214 store_temp_max, 3),
1215 SENSOR_ATTR(temp5_max, S_IRUGO | S_IWUSR, show_temp_max,
1216 store_temp_max, 4),
1217 SENSOR_ATTR(temp6_max, S_IRUGO | S_IWUSR, show_temp_max,
1218 store_temp_max, 5),
1219 SENSOR_ATTR(temp7_max, S_IRUGO | S_IWUSR, show_temp_max,
1220 store_temp_max, 6),
1221 SENSOR_ATTR(temp8_max, S_IRUGO | S_IWUSR, show_temp_max,
1222 store_temp_max, 7),
1223 SENSOR_ATTR(temp9_max, S_IRUGO | S_IWUSR, show_temp_max,
1224 store_temp_max, 8),
a157d06d
GJ		 1225};
1226
1227static struct sensor_device_attribute sda_temp_max_hyst[] = {
bce26c58 1228 SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
412fec82 1229 store_temp_max_hyst, 0),
bce26c58 1230 SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
412fec82 1231 store_temp_max_hyst, 1),
bce26c58
GR		 1232 SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1233 store_temp_max_hyst, 2),
ec3e5a16
GR		 1234 SENSOR_ATTR(temp4_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1235 store_temp_max_hyst, 3),
1236 SENSOR_ATTR(temp5_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1237 store_temp_max_hyst, 4),
1238 SENSOR_ATTR(temp6_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1239 store_temp_max_hyst, 5),
1240 SENSOR_ATTR(temp7_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1241 store_temp_max_hyst, 6),
1242 SENSOR_ATTR(temp8_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1243 store_temp_max_hyst, 7),
1244 SENSOR_ATTR(temp9_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1245 store_temp_max_hyst, 8),
a157d06d
GJ		 1246};
1247
1248static struct sensor_device_attribute sda_temp_alarm[] = {
a4589dbb
JD		 1249 SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
1250 SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
1251 SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
a157d06d
GJ		 1252};
1253
1254static struct sensor_device_attribute sda_temp_type[] = {
da667365
JD		 1255 SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0),
1256 SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1),
1257 SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2),
412fec82 1258};
08e7e278 1259
08c79950 1260#define show_pwm_reg(reg) \
e7e1ca6e
GR		 1261static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1262 char *buf) \
08c79950
RM		 1263{ \
1264 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1265 struct sensor_device_attribute *sensor_attr = \
1266 to_sensor_dev_attr(attr); \
08c79950
RM		 1267 int nr = sensor_attr->index; \
1268 return sprintf(buf, "%d\n", data->reg[nr]); \
1269}
1270
1271show_pwm_reg(pwm_mode)
1272show_pwm_reg(pwm_enable)
1273show_pwm_reg(pwm)
1274
1275static ssize_t
1276store_pwm_mode(struct device *dev, struct device_attribute *attr,
1277 const char *buf, size_t count)
1278{
1ea6dd38 1279 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1280 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1281 int nr = sensor_attr->index;
bce26c58
GR		 1282 unsigned long val;
1283 int err;
08c79950
RM		 1284 u16 reg;
1285
bce26c58
GR		 1286 err = strict_strtoul(buf, 10, &val);
1287 if (err < 0)
1288 return err;
1289
08c79950
RM		 1290 if (val > 1)
1291 return -EINVAL;
1292 mutex_lock(&data->update_lock);
1ea6dd38 1293 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 1294 data->pwm_mode[nr] = val;
1295 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]);
1296 if (!val)
1297 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr];
1ea6dd38 1298 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 1299 mutex_unlock(&data->update_lock);
1300 return count;
1301}
1302
1303static ssize_t
1304store_pwm(struct device *dev, struct device_attribute *attr,
1305 const char *buf, size_t count)
1306{
1ea6dd38 1307 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1308 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1309 int nr = sensor_attr->index;
bce26c58
GR		 1310 unsigned long val;
1311 int err;
1312
1313 err = strict_strtoul(buf, 10, &val);
1314 if (err < 0)
1315 return err;
1316
1317 val = SENSORS_LIMIT(val, 0, 255);
08c79950
RM		 1318
1319 mutex_lock(&data->update_lock);
1320 data->pwm[nr] = val;
279af1a9 1321 w83627ehf_write_value(data, data->REG_PWM[nr], val);
08c79950
RM		 1322 mutex_unlock(&data->update_lock);
1323 return count;
1324}
1325
1326static ssize_t
1327store_pwm_enable(struct device *dev, struct device_attribute *attr,
1328 const char *buf, size_t count)
1329{
1ea6dd38 1330 struct w83627ehf_data *data = dev_get_drvdata(dev);
ec3e5a16 1331 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08c79950
RM		 1332 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1333 int nr = sensor_attr->index;
bce26c58
GR		 1334 unsigned long val;
1335 int err;
08c79950
RM		 1336 u16 reg;
1337
bce26c58
GR		 1338 err = strict_strtoul(buf, 10, &val);
1339 if (err < 0)
1340 return err;
1341
b84bb518 1342 if (!val || (val > 4 && val != data->pwm_enable_orig[nr]))
08c79950 1343 return -EINVAL;
ec3e5a16
GR		 1344 /* SmartFan III mode is not supported on NCT6776F */
1345 if (sio_data->kind == nct6776 && val == 4)
1346 return -EINVAL;
1347
08c79950 1348 mutex_lock(&data->update_lock);
08c79950 1349 data->pwm_enable[nr] = val;
ec3e5a16
GR		 1350 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1351 reg = w83627ehf_read_value(data,
1352 NCT6775_REG_FAN_MODE[nr]);
1353 reg &= 0x0f;
1354 reg |= (val - 1) << 4;
1355 w83627ehf_write_value(data,
1356 NCT6775_REG_FAN_MODE[nr], reg);
1357 } else {
1358 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
1359 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]);
1360 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr];
1361 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
1362 }
08c79950
RM		 1363 mutex_unlock(&data->update_lock);
1364 return count;
1365}
1366
1367
1368#define show_tol_temp(reg) \
1369static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1370 char *buf) \
1371{ \
1372 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1373 struct sensor_device_attribute *sensor_attr = \
1374 to_sensor_dev_attr(attr); \
08c79950 1375 int nr = sensor_attr->index; \
bce26c58 1376 return sprintf(buf, "%d\n", data->reg[nr] * 1000); \
08c79950
RM		 1377}
1378
1379show_tol_temp(tolerance)
1380show_tol_temp(target_temp)
1381
1382static ssize_t
1383store_target_temp(struct device *dev, struct device_attribute *attr,
1384 const char *buf, size_t count)
1385{
1ea6dd38 1386 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1387 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1388 int nr = sensor_attr->index;
bce26c58
GR		 1389 long val;
1390 int err;
1391
1392 err = strict_strtol(buf, 10, &val);
1393 if (err < 0)
1394 return err;
1395
1396 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 127);
08c79950
RM		 1397
1398 mutex_lock(&data->update_lock);
1399 data->target_temp[nr] = val;
279af1a9 1400 w83627ehf_write_value(data, data->REG_TARGET[nr], val);
08c79950
RM		 1401 mutex_unlock(&data->update_lock);
1402 return count;
1403}
1404
1405static ssize_t
1406store_tolerance(struct device *dev, struct device_attribute *attr,
1407 const char *buf, size_t count)
1408{
1ea6dd38 1409 struct w83627ehf_data *data = dev_get_drvdata(dev);
ec3e5a16 1410 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08c79950
RM		 1411 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1412 int nr = sensor_attr->index;
1413 u16 reg;
bce26c58
GR		 1414 long val;
1415 int err;
1416
1417 err = strict_strtol(buf, 10, &val);
1418 if (err < 0)
1419 return err;
1420
08c79950 1421 /* Limit the temp to 0C - 15C */
bce26c58 1422 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 15);
08c79950
RM		 1423
1424 mutex_lock(&data->update_lock);
ec3e5a16
GR		 1425 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1426 /* Limit tolerance further for NCT6776F */
1427 if (sio_data->kind == nct6776 && val > 7)
1428 val = 7;
1429 reg = w83627ehf_read_value(data, NCT6775_REG_FAN_MODE[nr]);
08c79950 1430 reg = (reg & 0xf0) | val;
ec3e5a16
GR		 1431 w83627ehf_write_value(data, NCT6775_REG_FAN_MODE[nr], reg);
1432 } else {
1433 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
1434 if (nr == 1)
1435 reg = (reg & 0x0f) | (val << 4);
1436 else
1437 reg = (reg & 0xf0) | val;
1438 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
1439 }
1440 data->tolerance[nr] = val;
08c79950
RM		 1441 mutex_unlock(&data->update_lock);
1442 return count;
1443}
1444
1445static struct sensor_device_attribute sda_pwm[] = {
1446 SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0),
1447 SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1),
1448 SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2),
1449 SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3),
1450};
1451
1452static struct sensor_device_attribute sda_pwm_mode[] = {
1453 SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1454 store_pwm_mode, 0),
1455 SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1456 store_pwm_mode, 1),
1457 SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1458 store_pwm_mode, 2),
1459 SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1460 store_pwm_mode, 3),
1461};
1462
1463static struct sensor_device_attribute sda_pwm_enable[] = {
1464 SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1465 store_pwm_enable, 0),
1466 SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1467 store_pwm_enable, 1),
1468 SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1469 store_pwm_enable, 2),
1470 SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1471 store_pwm_enable, 3),
1472};
1473
1474static struct sensor_device_attribute sda_target_temp[] = {
1475 SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp,
1476 store_target_temp, 0),
1477 SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp,
1478 store_target_temp, 1),
1479 SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp,
1480 store_target_temp, 2),
1481 SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp,
1482 store_target_temp, 3),
1483};
1484
1485static struct sensor_device_attribute sda_tolerance[] = {
1486 SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1487 store_tolerance, 0),
1488 SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1489 store_tolerance, 1),
1490 SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1491 store_tolerance, 2),
1492 SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1493 store_tolerance, 3),
1494};
1495
08c79950
RM		 1496/* Smart Fan registers */
1497
1498#define fan_functions(reg, REG) \
1499static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1500 char *buf) \
1501{ \
1502 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1503 struct sensor_device_attribute *sensor_attr = \
1504 to_sensor_dev_attr(attr); \
08c79950
RM		 1505 int nr = sensor_attr->index; \
1506 return sprintf(buf, "%d\n", data->reg[nr]); \
e7e1ca6e 1507} \
08c79950
RM		 1508static ssize_t \
1509store_##reg(struct device *dev, struct device_attribute *attr, \
1510 const char *buf, size_t count) \
e7e1ca6e 1511{ \
1ea6dd38 1512 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1513 struct sensor_device_attribute *sensor_attr = \
1514 to_sensor_dev_attr(attr); \
08c79950 1515 int nr = sensor_attr->index; \
bce26c58
GR		 1516 unsigned long val; \
1517 int err; \
1518 err = strict_strtoul(buf, 10, &val); \
1519 if (err < 0) \
1520 return err; \
1521 val = SENSORS_LIMIT(val, 1, 255); \
08c79950
RM		 1522 mutex_lock(&data->update_lock); \
1523 data->reg[nr] = val; \
da2e0255 1524 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
08c79950
RM		 1525 mutex_unlock(&data->update_lock); \
1526 return count; \
1527}
1528
41e9a062
DB		 1529fan_functions(fan_start_output, FAN_START_OUTPUT)
1530fan_functions(fan_stop_output, FAN_STOP_OUTPUT)
1531fan_functions(fan_max_output, FAN_MAX_OUTPUT)
1532fan_functions(fan_step_output, FAN_STEP_OUTPUT)
08c79950
RM		 1533
1534#define fan_time_functions(reg, REG) \
1535static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1536 char *buf) \
1537{ \
1538 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1539 struct sensor_device_attribute *sensor_attr = \
1540 to_sensor_dev_attr(attr); \
08c79950
RM		 1541 int nr = sensor_attr->index; \
1542 return sprintf(buf, "%d\n", \
e7e1ca6e
GR		 1543 step_time_from_reg(data->reg[nr], \
1544 data->pwm_mode[nr])); \
08c79950
RM		 1545} \
1546\
1547static ssize_t \
1548store_##reg(struct device *dev, struct device_attribute *attr, \
1549 const char *buf, size_t count) \
1550{ \
1ea6dd38 1551 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1552 struct sensor_device_attribute *sensor_attr = \
1553 to_sensor_dev_attr(attr); \
08c79950 1554 int nr = sensor_attr->index; \
bce26c58
GR		 1555 unsigned long val; \
1556 int err; \
1557 err = strict_strtoul(buf, 10, &val); \
1558 if (err < 0) \
1559 return err; \
1560 val = step_time_to_reg(val, data->pwm_mode[nr]); \
08c79950
RM		 1561 mutex_lock(&data->update_lock); \
1562 data->reg[nr] = val; \
1ea6dd38 1563 w83627ehf_write_value(data, W83627EHF_REG_##REG[nr], val); \
08c79950
RM		 1564 mutex_unlock(&data->update_lock); \
1565 return count; \
1566} \
1567
1568fan_time_functions(fan_stop_time, FAN_STOP_TIME)
1569
1ea6dd38
DH		 1570static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1571 char *buf)
1572{
1573 struct w83627ehf_data *data = dev_get_drvdata(dev);
1574
1575 return sprintf(buf, "%s\n", data->name);
1576}
1577static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
08c79950
RM		 1578
1579static struct sensor_device_attribute sda_sf3_arrays_fan4[] = {
1580 SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1581 store_fan_stop_time, 3),
41e9a062
DB		 1582 SENSOR_ATTR(pwm4_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1583 store_fan_start_output, 3),
1584 SENSOR_ATTR(pwm4_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1585 store_fan_stop_output, 3),
1586 SENSOR_ATTR(pwm4_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1587 store_fan_max_output, 3),
1588 SENSOR_ATTR(pwm4_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1589 store_fan_step_output, 3),
08c79950
RM		 1590};
1591
1592static struct sensor_device_attribute sda_sf3_arrays[] = {
1593 SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1594 store_fan_stop_time, 0),
1595 SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1596 store_fan_stop_time, 1),
1597 SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1598 store_fan_stop_time, 2),
41e9a062
DB		 1599 SENSOR_ATTR(pwm1_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1600 store_fan_start_output, 0),
1601 SENSOR_ATTR(pwm2_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1602 store_fan_start_output, 1),
1603 SENSOR_ATTR(pwm3_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1604 store_fan_start_output, 2),
1605 SENSOR_ATTR(pwm1_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1606 store_fan_stop_output, 0),
1607 SENSOR_ATTR(pwm2_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1608 store_fan_stop_output, 1),
1609 SENSOR_ATTR(pwm3_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1610 store_fan_stop_output, 2),
da2e0255 1611};
41e9a062 1612
da2e0255
GR		 1613
1614/*
1615 * pwm1 and pwm3 don't support max and step settings on all chips.
1616 * Need to check support while generating/removing attribute files.
1617 */
1618static struct sensor_device_attribute sda_sf3_max_step_arrays[] = {
1619 SENSOR_ATTR(pwm1_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1620 store_fan_max_output, 0),
1621 SENSOR_ATTR(pwm1_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1622 store_fan_step_output, 0),
41e9a062
DB		 1623 SENSOR_ATTR(pwm2_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1624 store_fan_max_output, 1),
1625 SENSOR_ATTR(pwm2_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1626 store_fan_step_output, 1),
da2e0255
GR		 1627 SENSOR_ATTR(pwm3_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1628 store_fan_max_output, 2),
1629 SENSOR_ATTR(pwm3_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1630 store_fan_step_output, 2),
08c79950
RM		 1631};
1632
fc18d6c0
JD		 1633static ssize_t
1634show_vid(struct device *dev, struct device_attribute *attr, char *buf)
1635{
1636 struct w83627ehf_data *data = dev_get_drvdata(dev);
1637 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1638}
1639static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1640
08e7e278 1641/*
1ea6dd38 1642 * Driver and device management
08e7e278
JD		 1643 */
1644
c18beb5b
DH		 1645static void w83627ehf_device_remove_files(struct device *dev)
1646{
1647 /* some entries in the following arrays may not have been used in
1648 * device_create_file(), but device_remove_file() will ignore them */
1649 int i;
1ea6dd38 1650 struct w83627ehf_data *data = dev_get_drvdata(dev);
c18beb5b
DH		 1651
1652 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
1653 device_remove_file(dev, &sda_sf3_arrays[i].dev_attr);
da2e0255
GR		 1654 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
1655 struct sensor_device_attribute *attr =
1656 &sda_sf3_max_step_arrays[i];
ec3e5a16
GR		 1657 if (data->REG_FAN_STEP_OUTPUT &&
1658 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff)
da2e0255
GR		 1659 device_remove_file(dev, &attr->dev_attr);
1660 }
c18beb5b
DH		 1661 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++)
1662 device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr);
1ea6dd38 1663 for (i = 0; i < data->in_num; i++) {
a157d06d
GJ		 1664 if ((i == 6) && data->in6_skip)
1665 continue;
c18beb5b
DH		 1666 device_remove_file(dev, &sda_in_input[i].dev_attr);
1667 device_remove_file(dev, &sda_in_alarm[i].dev_attr);
1668 device_remove_file(dev, &sda_in_min[i].dev_attr);
1669 device_remove_file(dev, &sda_in_max[i].dev_attr);
1670 }
1671 for (i = 0; i < 5; i++) {
1672 device_remove_file(dev, &sda_fan_input[i].dev_attr);
1673 device_remove_file(dev, &sda_fan_alarm[i].dev_attr);
1674 device_remove_file(dev, &sda_fan_div[i].dev_attr);
1675 device_remove_file(dev, &sda_fan_min[i].dev_attr);
1676 }
237c8d2f 1677 for (i = 0; i < data->pwm_num; i++) {
c18beb5b
DH		 1678 device_remove_file(dev, &sda_pwm[i].dev_attr);
1679 device_remove_file(dev, &sda_pwm_mode[i].dev_attr);
1680 device_remove_file(dev, &sda_pwm_enable[i].dev_attr);
1681 device_remove_file(dev, &sda_target_temp[i].dev_attr);
1682 device_remove_file(dev, &sda_tolerance[i].dev_attr);
1683 }
d36cf32c
GR		 1684 for (i = 0; i < NUM_REG_TEMP; i++) {
1685 if (!(data->have_temp & (1 << i)))
a157d06d
GJ		 1686 continue;
1687 device_remove_file(dev, &sda_temp_input[i].dev_attr);
d36cf32c 1688 device_remove_file(dev, &sda_temp_label[i].dev_attr);
a157d06d
GJ		 1689 device_remove_file(dev, &sda_temp_max[i].dev_attr);
1690 device_remove_file(dev, &sda_temp_max_hyst[i].dev_attr);
ec3e5a16
GR		 1691 if (i > 2)
1692 continue;
a157d06d
GJ		 1693 device_remove_file(dev, &sda_temp_alarm[i].dev_attr);
1694 device_remove_file(dev, &sda_temp_type[i].dev_attr);
1695 }
c18beb5b 1696
1ea6dd38 1697 device_remove_file(dev, &dev_attr_name);
cbe311f2 1698 device_remove_file(dev, &dev_attr_cpu0_vid);
1ea6dd38 1699}
08e7e278 1700
1ea6dd38
DH		 1701/* Get the monitoring functions started */
1702static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data)
08e7e278
JD		 1703{
1704 int i;
da667365 1705 u8 tmp, diode;
08e7e278
JD		 1706
1707 /* Start monitoring is needed */
1ea6dd38 1708 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
08e7e278 1709 if (!(tmp & 0x01))
1ea6dd38 1710 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
08e7e278
JD		 1711 tmp | 0x01);
1712
d36cf32c
GR		 1713 /* Enable temperature sensors if needed */
1714 for (i = 0; i < NUM_REG_TEMP; i++) {
1715 if (!(data->have_temp & (1 << i)))
1716 continue;
ec3e5a16 1717 if (!data->reg_temp_config[i])
d36cf32c 1718 continue;
1ea6dd38 1719 tmp = w83627ehf_read_value(data,
ec3e5a16 1720 data->reg_temp_config[i]);
08e7e278 1721 if (tmp & 0x01)
1ea6dd38 1722 w83627ehf_write_value(data,
ec3e5a16 1723 data->reg_temp_config[i],
08e7e278
JD		 1724 tmp & 0xfe);
1725 }
d3130f0e
JD		 1726
1727 /* Enable VBAT monitoring if needed */
1728 tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1729 if (!(tmp & 0x01))
1730 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
da667365
JD		 1731
1732 /* Get thermal sensor types */
1733 diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
1734 for (i = 0; i < 3; i++) {
1735 if ((tmp & (0x02 << i)))
1736 data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 2;
1737 else
1738 data->temp_type[i] = 4; /* thermistor */
1739 }
08e7e278
JD		 1740}
1741
ec3e5a16
GR		 1742static void w82627ehf_swap_tempreg(struct w83627ehf_data *data,
1743 int r1, int r2)
1744{
1745 u16 tmp;
1746
1747 tmp = data->temp_src[r1];
1748 data->temp_src[r1] = data->temp_src[r2];
1749 data->temp_src[r2] = tmp;
1750
1751 tmp = data->reg_temp[r1];
1752 data->reg_temp[r1] = data->reg_temp[r2];
1753 data->reg_temp[r2] = tmp;
1754
1755 tmp = data->reg_temp_over[r1];
1756 data->reg_temp_over[r1] = data->reg_temp_over[r2];
1757 data->reg_temp_over[r2] = tmp;
1758
1759 tmp = data->reg_temp_hyst[r1];
1760 data->reg_temp_hyst[r1] = data->reg_temp_hyst[r2];
1761 data->reg_temp_hyst[r2] = tmp;
1762
1763 tmp = data->reg_temp_config[r1];
1764 data->reg_temp_config[r1] = data->reg_temp_config[r2];
1765 data->reg_temp_config[r2] = tmp;
1766}
1767
1ea6dd38 1768static int __devinit w83627ehf_probe(struct platform_device *pdev)
08e7e278 1769{
1ea6dd38
DH		 1770 struct device *dev = &pdev->dev;
1771 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08e7e278 1772 struct w83627ehf_data *data;
1ea6dd38 1773 struct resource *res;
ec3e5a16 1774 u8 fan3pin, fan4pin, fan4min, fan5pin, en_vrm10;
08e7e278
JD		 1775 int i, err = 0;
1776
1ea6dd38
DH		 1777 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1778 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
08e7e278 1779 err = -EBUSY;
1ea6dd38
DH		 1780 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
1781 (unsigned long)res->start,
1782 (unsigned long)res->start + IOREGION_LENGTH - 1);
08e7e278
JD		 1783 goto exit;
1784 }
1785
e7e1ca6e
GR		 1786 data = kzalloc(sizeof(struct w83627ehf_data), GFP_KERNEL);
1787 if (!data) {
08e7e278
JD		 1788 err = -ENOMEM;
1789 goto exit_release;
1790 }
08e7e278 1791
1ea6dd38 1792 data->addr = res->start;
9a61bf63 1793 mutex_init(&data->lock);
9a61bf63 1794 mutex_init(&data->update_lock);
1ea6dd38
DH		 1795 data->name = w83627ehf_device_names[sio_data->kind];
1796 platform_set_drvdata(pdev, data);
08e7e278 1797
237c8d2f
GJ		 1798 /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
1799 data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
ec3e5a16 1800 /* 667HG, NCT6775F, and NCT6776F have 3 pwms */
c39aedaf 1801 data->pwm_num = (sio_data->kind == w83667hg
ec3e5a16
GR		 1802 || sio_data->kind == w83667hg_b
1803 || sio_data->kind == nct6775
1804 || sio_data->kind == nct6776) ? 3 : 4;
08e7e278 1805
d36cf32c 1806 data->have_temp = 0x07;
a157d06d 1807 /* Check temp3 configuration bit for 667HG */
d36cf32c
GR		 1808 if (sio_data->kind == w83667hg) {
1809 u8 reg;
1810
1811 reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
1812 if (reg & 0x01)
1813 data->have_temp &= ~(1 << 2);
1814 else
ec3e5a16
GR		 1815 data->in6_skip = 1; /* either temp3 or in6 */
1816 }
1817
1818 /* Deal with temperature register setup first. */
1819 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1820 int mask = 0;
1821
1822 /*
1823 * Display temperature sensor output only if it monitors
1824 * a source other than one already reported. Always display
1825 * first three temperature registers, though.
1826 */
1827 for (i = 0; i < NUM_REG_TEMP; i++) {
1828 u8 src;
1829
1830 data->reg_temp[i] = NCT6775_REG_TEMP[i];
1831 data->reg_temp_over[i] = NCT6775_REG_TEMP_OVER[i];
1832 data->reg_temp_hyst[i] = NCT6775_REG_TEMP_HYST[i];
1833 data->reg_temp_config[i] = NCT6775_REG_TEMP_CONFIG[i];
1834
1835 src = w83627ehf_read_value(data,
1836 NCT6775_REG_TEMP_SOURCE[i]);
1837 src &= 0x1f;
1838 if (src && !(mask & (1 << src))) {
1839 data->have_temp |= 1 << i;
1840 mask |= 1 << src;
1841 }
1842
1843 data->temp_src[i] = src;
1844
1845 /*
1846 * Now do some register swapping if index 0..2 don't
1847 * point to SYSTIN(1), CPUIN(2), and AUXIN(3).
1848 * Idea is to have the first three attributes
1849 * report SYSTIN, CPUIN, and AUXIN if possible
1850 * without overriding the basic system configuration.
1851 */
1852 if (i > 0 && data->temp_src[0] != 1
1853 && data->temp_src[i] == 1)
1854 w82627ehf_swap_tempreg(data, 0, i);
1855 if (i > 1 && data->temp_src[1] != 2
1856 && data->temp_src[i] == 2)
1857 w82627ehf_swap_tempreg(data, 1, i);
1858 if (i > 2 && data->temp_src[2] != 3
1859 && data->temp_src[i] == 3)
1860 w82627ehf_swap_tempreg(data, 2, i);
1861 }
1862 if (sio_data->kind == nct6776) {
1863 /*
1864 * On NCT6776, AUXTIN and VIN3 pins are shared.
1865 * Only way to detect it is to check if AUXTIN is used
1866 * as a temperature source, and if that source is
1867 * enabled.
1868 *
1869 * If that is the case, disable in6, which reports VIN3.
1870 * Otherwise disable temp3.
1871 */
1872 if (data->temp_src[2] == 3) {
1873 u8 reg;
1874
1875 if (data->reg_temp_config[2])
1876 reg = w83627ehf_read_value(data,
1877 data->reg_temp_config[2]);
1878 else
1879 reg = 0; /* Assume AUXTIN is used */
1880
1881 if (reg & 0x01)
1882 data->have_temp &= ~(1 << 2);
1883 else
1884 data->in6_skip = 1;
1885 }
1886 }
1887
1888 data->temp_label = nct6776_temp_label;
d36cf32c
GR		 1889 } else if (sio_data->kind == w83667hg_b) {
1890 u8 reg;
1891
ec3e5a16
GR		 1892 /*
1893 * Temperature sources are selected with bank 0, registers 0x49
1894 * and 0x4a.
1895 */
1896 for (i = 0; i < ARRAY_SIZE(W83627EHF_REG_TEMP); i++) {
1897 data->reg_temp[i] = W83627EHF_REG_TEMP[i];
1898 data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
1899 data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
1900 data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
1901 }
d36cf32c
GR		 1902 reg = w83627ehf_read_value(data, 0x4a);
1903 data->temp_src[0] = reg >> 5;
1904 reg = w83627ehf_read_value(data, 0x49);
1905 data->temp_src[1] = reg & 0x07;
ec3e5a16 1906 data->temp_src[2] = (reg >> 4) & 0x07;
d36cf32c
GR		 1907
1908 /*
1909 * W83667HG-B has another temperature register at 0x7e.
1910 * The temperature source is selected with register 0x7d.
1911 * Support it if the source differs from already reported
1912 * sources.
1913 */
1914 reg = w83627ehf_read_value(data, 0x7d);
1915 reg &= 0x07;
1916 if (reg != data->temp_src[0] && reg != data->temp_src[1]
1917 && reg != data->temp_src[2]) {
1918 data->temp_src[3] = reg;
1919 data->have_temp |= 1 << 3;
1920 }
1921
1922 /*
1923 * Chip supports either AUXTIN or VIN3. Try to find out which
1924 * one.
1925 */
1926 reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
1927 if (data->temp_src[2] == 2 && (reg & 0x01))
1928 data->have_temp &= ~(1 << 2);
1929
1930 if ((data->temp_src[2] == 2 && (data->have_temp & (1 << 2)))
1931 || (data->temp_src[3] == 2 && (data->have_temp & (1 << 3))))
1932 data->in6_skip = 1;
1933
1934 data->temp_label = w83667hg_b_temp_label;
ec3e5a16
GR		 1935 } else {
1936 /* Temperature sources are fixed */
1937 for (i = 0; i < 3; i++) {
1938 data->reg_temp[i] = W83627EHF_REG_TEMP[i];
1939 data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
1940 data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
1941 data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
1942 }
a157d06d
GJ		 1943 }
1944
ec3e5a16
GR		 1945 if (sio_data->kind == nct6775) {
1946 data->REG_PWM = NCT6775_REG_PWM;
1947 data->REG_TARGET = NCT6775_REG_TARGET;
1948 data->REG_FAN = W83627EHF_REG_FAN;
1949 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
1950 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
1951 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
1952 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
1953 data->REG_FAN_MAX_OUTPUT = NCT6775_REG_FAN_MAX_OUTPUT;
1954 data->REG_FAN_STEP_OUTPUT = NCT6775_REG_FAN_STEP_OUTPUT;
1955 } else if (sio_data->kind == nct6776) {
1956 data->REG_PWM = NCT6775_REG_PWM;
1957 data->REG_TARGET = NCT6775_REG_TARGET;
1958 data->REG_FAN = NCT6776_REG_FAN;
1959 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
1960 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
1961 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
1962 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
1963 } else if (sio_data->kind == w83667hg_b) {
1964 data->REG_PWM = W83627EHF_REG_PWM;
1965 data->REG_TARGET = W83627EHF_REG_TARGET;
1966 data->REG_FAN = W83627EHF_REG_FAN;
1967 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
1968 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
1969 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
1970 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
c39aedaf
GR		 1971 data->REG_FAN_MAX_OUTPUT =
1972 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B;
1973 data->REG_FAN_STEP_OUTPUT =
1974 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B;
1975 } else {
ec3e5a16
GR		 1976 data->REG_PWM = W83627EHF_REG_PWM;
1977 data->REG_TARGET = W83627EHF_REG_TARGET;
1978 data->REG_FAN = W83627EHF_REG_FAN;
1979 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
1980 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
1981 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
1982 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
c39aedaf
GR		 1983 data->REG_FAN_MAX_OUTPUT =
1984 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON;
1985 data->REG_FAN_STEP_OUTPUT =
1986 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON;
1987 }
da2e0255 1988
08e7e278 1989 /* Initialize the chip */
1ea6dd38 1990 w83627ehf_init_device(data);
08e7e278 1991
fc18d6c0
JD		 1992 data->vrm = vid_which_vrm();
1993 superio_enter(sio_data->sioreg);
fc18d6c0 1994 /* Read VID value */
ec3e5a16
GR		 1995 if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b ||
1996 sio_data->kind == nct6775 || sio_data->kind == nct6776) {
237c8d2f
GJ		 1997 /* W83667HG has different pins for VID input and output, so
1998 we can get the VID input values directly at logical device D
1999 0xe3. */
2000 superio_select(sio_data->sioreg, W83667HG_LD_VID);
2001 data->vid = superio_inb(sio_data->sioreg, 0xe3);
cbe311f2
JD		 2002 err = device_create_file(dev, &dev_attr_cpu0_vid);
2003 if (err)
2004 goto exit_release;
58e6e781 2005 } else {
237c8d2f
GJ		 2006 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2007 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
2008 /* Set VID input sensibility if needed. In theory the
2009 BIOS should have set it, but in practice it's not
2010 always the case. We only do it for the W83627EHF/EHG
2011 because the W83627DHG is more complex in this
2012 respect. */
2013 if (sio_data->kind == w83627ehf) {
2014 en_vrm10 = superio_inb(sio_data->sioreg,
2015 SIO_REG_EN_VRM10);
2016 if ((en_vrm10 & 0x08) && data->vrm == 90) {
2017 dev_warn(dev, "Setting VID input "
2018 "voltage to TTL\n");
2019 superio_outb(sio_data->sioreg,
2020 SIO_REG_EN_VRM10,
2021 en_vrm10 & ~0x08);
2022 } else if (!(en_vrm10 & 0x08)
2023 && data->vrm == 100) {
2024 dev_warn(dev, "Setting VID input "
2025 "voltage to VRM10\n");
2026 superio_outb(sio_data->sioreg,
2027 SIO_REG_EN_VRM10,
2028 en_vrm10 | 0x08);
2029 }
2030 }
2031
2032 data->vid = superio_inb(sio_data->sioreg,
2033 SIO_REG_VID_DATA);
2034 if (sio_data->kind == w83627ehf) /* 6 VID pins only */
2035 data->vid &= 0x3f;
2036
2037 err = device_create_file(dev, &dev_attr_cpu0_vid);
2038 if (err)
2039 goto exit_release;
2040 } else {
2041 dev_info(dev, "VID pins in output mode, CPU VID not "
2042 "available\n");
2043 }
fc18d6c0
JD		 2044 }
2045
08c79950 2046 /* fan4 and fan5 share some pins with the GPIO and serial flash */
ec3e5a16
GR		 2047 if (sio_data->kind == nct6775) {
2048 /* On NCT6775, fan4 shares pins with the fdc interface */
2049 fan3pin = 1;
2050 fan4pin = !(superio_inb(sio_data->sioreg, 0x2A) & 0x80);
2051 fan4min = 0;
2052 fan5pin = 0;
2053 } else if (sio_data->kind == nct6776) {
2054 fan3pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x40);
2055 fan4pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x01);
2056 fan5pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x02);
2057 fan4min = fan4pin;
2058 } else if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
2059 fan3pin = 1;
237c8d2f 2060 fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
ec3e5a16
GR		 2061 fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
2062 fan4min = fan4pin;
237c8d2f 2063 } else {
ec3e5a16 2064 fan3pin = 1;
237c8d2f 2065 fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
ec3e5a16
GR		 2066 fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
2067 fan4min = fan4pin;
237c8d2f 2068 }
1ea6dd38 2069 superio_exit(sio_data->sioreg);
08c79950 2070
08e7e278 2071 /* It looks like fan4 and fan5 pins can be alternatively used
14992c7e
RM		 2072 as fan on/off switches, but fan5 control is write only :/
2073 We assume that if the serial interface is disabled, designers
2074 connected fan5 as input unless they are emitting log 1, which
2075 is not the default. */
08c79950 2076
ec3e5a16
GR		 2077 data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
2078
2079 data->has_fan |= (fan3pin << 2);
2080 data->has_fan_min |= (fan3pin << 2);
2081
2082 /*
2083 * NCT6775F and NCT6776F don't have the W83627EHF_REG_FANDIV1 register
2084 */
2085 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
2086 data->has_fan |= (fan4pin << 3) | (fan5pin << 4);
2087 data->has_fan_min |= (fan4min << 3) | (fan5pin << 4);
2088 } else {
2089 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
2090 if ((i & (1 << 2)) && fan4pin) {
2091 data->has_fan |= (1 << 3);
2092 data->has_fan_min |= (1 << 3);
2093 }
2094 if (!(i & (1 << 1)) && fan5pin) {
2095 data->has_fan |= (1 << 4);
2096 data->has_fan_min |= (1 << 4);
2097 }
2098 }
08e7e278 2099
ea7be66c 2100 /* Read fan clock dividers immediately */
ec3e5a16
GR		 2101 w83627ehf_update_fan_div_common(dev, data);
2102
2103 /* Read pwm data to save original values */
2104 w83627ehf_update_pwm_common(dev, data);
2105 for (i = 0; i < data->pwm_num; i++)
2106 data->pwm_enable_orig[i] = data->pwm_enable[i];
ea7be66c 2107
b84bb518
GR		 2108 /* Read pwm data to save original values */
2109 w83627ehf_update_pwm_common(dev, data);
2110 for (i = 0; i < data->pwm_num; i++)
2111 data->pwm_enable_orig[i] = data->pwm_enable[i];
2112
08e7e278 2113 /* Register sysfs hooks */
e7e1ca6e
GR		 2114 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++) {
2115 err = device_create_file(dev, &sda_sf3_arrays[i].dev_attr);
2116 if (err)
c18beb5b 2117 goto exit_remove;
e7e1ca6e 2118 }
08c79950 2119
da2e0255
GR		 2120 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
2121 struct sensor_device_attribute *attr =
2122 &sda_sf3_max_step_arrays[i];
ec3e5a16
GR		 2123 if (data->REG_FAN_STEP_OUTPUT &&
2124 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff) {
da2e0255
GR		 2125 err = device_create_file(dev, &attr->dev_attr);
2126 if (err)
2127 goto exit_remove;
2128 }
2129 }
08c79950 2130 /* if fan4 is enabled create the sf3 files for it */
237c8d2f 2131 if ((data->has_fan & (1 << 3)) && data->pwm_num >= 4)
c18beb5b 2132 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) {
e7e1ca6e
GR		 2133 err = device_create_file(dev,
2134 &sda_sf3_arrays_fan4[i].dev_attr);
2135 if (err)
c18beb5b
DH		 2136 goto exit_remove;
2137 }
08c79950 2138
a157d06d
GJ		 2139 for (i = 0; i < data->in_num; i++) {
2140 if ((i == 6) && data->in6_skip)
2141 continue;
c18beb5b
DH		 2142 if ((err = device_create_file(dev, &sda_in_input[i].dev_attr))
2143 || (err = device_create_file(dev,
2144 &sda_in_alarm[i].dev_attr))
2145 || (err = device_create_file(dev,
2146 &sda_in_min[i].dev_attr))
2147 || (err = device_create_file(dev,
2148 &sda_in_max[i].dev_attr)))
2149 goto exit_remove;
a157d06d 2150 }
cf0676fe 2151
412fec82 2152 for (i = 0; i < 5; i++) {
08c79950 2153 if (data->has_fan & (1 << i)) {
c18beb5b
DH		 2154 if ((err = device_create_file(dev,
2155 &sda_fan_input[i].dev_attr))
2156 || (err = device_create_file(dev,
ec3e5a16 2157 &sda_fan_alarm[i].dev_attr)))
c18beb5b 2158 goto exit_remove;
ec3e5a16
GR		 2159 if (sio_data->kind != nct6776) {
2160 err = device_create_file(dev,
2161 &sda_fan_div[i].dev_attr);
2162 if (err)
2163 goto exit_remove;
2164 }
2165 if (data->has_fan_min & (1 << i)) {
2166 err = device_create_file(dev,
2167 &sda_fan_min[i].dev_attr);
2168 if (err)
2169 goto exit_remove;
2170 }
237c8d2f 2171 if (i < data->pwm_num &&
c18beb5b
DH		 2172 ((err = device_create_file(dev,
2173 &sda_pwm[i].dev_attr))
2174 || (err = device_create_file(dev,
2175 &sda_pwm_mode[i].dev_attr))
2176 || (err = device_create_file(dev,
2177 &sda_pwm_enable[i].dev_attr))
2178 || (err = device_create_file(dev,
2179 &sda_target_temp[i].dev_attr))
2180 || (err = device_create_file(dev,
2181 &sda_tolerance[i].dev_attr))))
2182 goto exit_remove;
08c79950 2183 }
08e7e278 2184 }
08c79950 2185
d36cf32c
GR		 2186 for (i = 0; i < NUM_REG_TEMP; i++) {
2187 if (!(data->have_temp & (1 << i)))
a157d06d 2188 continue;
d36cf32c
GR		 2189 err = device_create_file(dev, &sda_temp_input[i].dev_attr);
2190 if (err)
2191 goto exit_remove;
2192 if (data->temp_label) {
2193 err = device_create_file(dev,
2194 &sda_temp_label[i].dev_attr);
2195 if (err)
2196 goto exit_remove;
2197 }
ec3e5a16
GR		 2198 if (data->reg_temp_over[i]) {
2199 err = device_create_file(dev,
2200 &sda_temp_max[i].dev_attr);
2201 if (err)
2202 goto exit_remove;
2203 }
2204 if (data->reg_temp_hyst[i]) {
2205 err = device_create_file(dev,
2206 &sda_temp_max_hyst[i].dev_attr);
2207 if (err)
2208 goto exit_remove;
2209 }
d36cf32c 2210 if (i > 2)
ec3e5a16
GR		 2211 continue;
2212 if ((err = device_create_file(dev,
a157d06d
GJ		 2213 &sda_temp_alarm[i].dev_attr))
2214 || (err = device_create_file(dev,
2215 &sda_temp_type[i].dev_attr)))
c18beb5b 2216 goto exit_remove;
a157d06d 2217 }
c18beb5b 2218
1ea6dd38
DH		 2219 err = device_create_file(dev, &dev_attr_name);
2220 if (err)
2221 goto exit_remove;
2222
1beeffe4
TJ		 2223 data->hwmon_dev = hwmon_device_register(dev);
2224 if (IS_ERR(data->hwmon_dev)) {
2225 err = PTR_ERR(data->hwmon_dev);
c18beb5b
DH		 2226 goto exit_remove;
2227 }
08e7e278
JD		 2228
2229 return 0;
2230
c18beb5b
DH		 2231exit_remove:
2232 w83627ehf_device_remove_files(dev);
08e7e278 2233 kfree(data);
1ea6dd38 2234 platform_set_drvdata(pdev, NULL);
08e7e278 2235exit_release:
1ea6dd38 2236 release_region(res->start, IOREGION_LENGTH);
08e7e278
JD		 2237exit:
2238 return err;
2239}
2240
1ea6dd38 2241static int __devexit w83627ehf_remove(struct platform_device *pdev)
08e7e278 2242{
1ea6dd38 2243 struct w83627ehf_data *data = platform_get_drvdata(pdev);
08e7e278 2244
1beeffe4 2245 hwmon_device_unregister(data->hwmon_dev);
1ea6dd38
DH		 2246 w83627ehf_device_remove_files(&pdev->dev);
2247 release_region(data->addr, IOREGION_LENGTH);
2248 platform_set_drvdata(pdev, NULL);
943b0830 2249 kfree(data);
08e7e278
JD		 2250
2251 return 0;
2252}
2253
1ea6dd38 2254static struct platform_driver w83627ehf_driver = {
cdaf7934 2255 .driver = {
87218842 2256 .owner = THIS_MODULE,
1ea6dd38 2257 .name = DRVNAME,
cdaf7934 2258 },
1ea6dd38
DH		 2259 .probe = w83627ehf_probe,
2260 .remove = __devexit_p(w83627ehf_remove),
08e7e278
JD		 2261};
2262
1ea6dd38
DH		 2263/* w83627ehf_find() looks for a '627 in the Super-I/O config space */
2264static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
2265 struct w83627ehf_sio_data *sio_data)
08e7e278 2266{
1ea6dd38
DH		 2267 static const char __initdata sio_name_W83627EHF[] = "W83627EHF";
2268 static const char __initdata sio_name_W83627EHG[] = "W83627EHG";
2269 static const char __initdata sio_name_W83627DHG[] = "W83627DHG";
c1e48dce 2270 static const char __initdata sio_name_W83627DHG_P[] = "W83627DHG-P";
237c8d2f 2271 static const char __initdata sio_name_W83667HG[] = "W83667HG";
c39aedaf 2272 static const char __initdata sio_name_W83667HG_B[] = "W83667HG-B";
ec3e5a16
GR		 2273 static const char __initdata sio_name_NCT6775[] = "NCT6775F";
2274 static const char __initdata sio_name_NCT6776[] = "NCT6776F";
1ea6dd38 2275
08e7e278 2276 u16 val;
1ea6dd38 2277 const char *sio_name;
08e7e278 2278
1ea6dd38 2279 superio_enter(sioaddr);
08e7e278 2280
67b671bc
JD		 2281 if (force_id)
2282 val = force_id;
2283 else
2284 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
2285 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
657c93b1 2286 switch (val & SIO_ID_MASK) {
657c93b1 2287 case SIO_W83627EHF_ID:
1ea6dd38
DH		 2288 sio_data->kind = w83627ehf;
2289 sio_name = sio_name_W83627EHF;
2290 break;
657c93b1 2291 case SIO_W83627EHG_ID:
1ea6dd38
DH		 2292 sio_data->kind = w83627ehf;
2293 sio_name = sio_name_W83627EHG;
2294 break;
2295 case SIO_W83627DHG_ID:
2296 sio_data->kind = w83627dhg;
2297 sio_name = sio_name_W83627DHG;
657c93b1 2298 break;
c1e48dce
JD		 2299 case SIO_W83627DHG_P_ID:
2300 sio_data->kind = w83627dhg_p;
2301 sio_name = sio_name_W83627DHG_P;
2302 break;
237c8d2f
GJ		 2303 case SIO_W83667HG_ID:
2304 sio_data->kind = w83667hg;
2305 sio_name = sio_name_W83667HG;
2306 break;
c39aedaf
GR		 2307 case SIO_W83667HG_B_ID:
2308 sio_data->kind = w83667hg_b;
2309 sio_name = sio_name_W83667HG_B;
2310 break;
ec3e5a16
GR		 2311 case SIO_NCT6775_ID:
2312 sio_data->kind = nct6775;
2313 sio_name = sio_name_NCT6775;
2314 break;
2315 case SIO_NCT6776_ID:
2316 sio_data->kind = nct6776;
2317 sio_name = sio_name_NCT6776;
2318 break;
657c93b1 2319 default:
9f66036b 2320 if (val != 0xffff)
abdc6fd1 2321 pr_debug("unsupported chip ID: 0x%04x\n", val);
1ea6dd38 2322 superio_exit(sioaddr);
08e7e278
JD		 2323 return -ENODEV;
2324 }
2325
1ea6dd38
DH		 2326 /* We have a known chip, find the HWM I/O address */
2327 superio_select(sioaddr, W83627EHF_LD_HWM);
2328 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
2329 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
1a641fce 2330 *addr = val & IOREGION_ALIGNMENT;
2d8672c5 2331 if (*addr == 0) {
abdc6fd1 2332 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
1ea6dd38 2333 superio_exit(sioaddr);
08e7e278
JD		 2334 return -ENODEV;
2335 }
2336
2337 /* Activate logical device if needed */
1ea6dd38 2338 val = superio_inb(sioaddr, SIO_REG_ENABLE);
475ef855 2339 if (!(val & 0x01)) {
e7e1ca6e
GR		 2340 pr_warn("Forcibly enabling Super-I/O. "
2341 "Sensor is probably unusable.\n");
1ea6dd38 2342 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
475ef855 2343 }
1ea6dd38
DH		 2344
2345 superio_exit(sioaddr);
abdc6fd1 2346 pr_info("Found %s chip at %#x\n", sio_name, *addr);
1ea6dd38 2347 sio_data->sioreg = sioaddr;
08e7e278 2348
08e7e278
JD		 2349 return 0;
2350}
2351
1ea6dd38
DH		 2352/* when Super-I/O functions move to a separate file, the Super-I/O
2353 * bus will manage the lifetime of the device and this module will only keep
2354 * track of the w83627ehf driver. But since we platform_device_alloc(), we
2355 * must keep track of the device */
2356static struct platform_device *pdev;
2357
08e7e278
JD		 2358static int __init sensors_w83627ehf_init(void)
2359{
1ea6dd38
DH		 2360 int err;
2361 unsigned short address;
2362 struct resource res;
2363 struct w83627ehf_sio_data sio_data;
2364
2365 /* initialize sio_data->kind and sio_data->sioreg.
2366 *
2367 * when Super-I/O functions move to a separate file, the Super-I/O
2368 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
2369 * w83627ehf hardware monitor, and call probe() */
2370 if (w83627ehf_find(0x2e, &address, &sio_data) &&
2371 w83627ehf_find(0x4e, &address, &sio_data))
08e7e278
JD		 2372 return -ENODEV;
2373
1ea6dd38
DH		 2374 err = platform_driver_register(&w83627ehf_driver);
2375 if (err)
2376 goto exit;
2377
e7e1ca6e
GR		 2378 pdev = platform_device_alloc(DRVNAME, address);
2379 if (!pdev) {
1ea6dd38 2380 err = -ENOMEM;
abdc6fd1 2381 pr_err("Device allocation failed\n");
1ea6dd38
DH		 2382 goto exit_unregister;
2383 }
2384
2385 err = platform_device_add_data(pdev, &sio_data,
2386 sizeof(struct w83627ehf_sio_data));
2387 if (err) {
abdc6fd1 2388 pr_err("Platform data allocation failed\n");
1ea6dd38
DH		 2389 goto exit_device_put;
2390 }
2391
2392 memset(&res, 0, sizeof(res));
2393 res.name = DRVNAME;
2394 res.start = address + IOREGION_OFFSET;
2395 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
2396 res.flags = IORESOURCE_IO;
b9acb64a
JD		 2397
2398 err = acpi_check_resource_conflict(&res);
2399 if (err)
18632f84 2400 goto exit_device_put;
b9acb64a 2401
1ea6dd38
DH		 2402 err = platform_device_add_resources(pdev, &res, 1);
2403 if (err) {
abdc6fd1 2404 pr_err("Device resource addition failed (%d)\n", err);
1ea6dd38
DH		 2405 goto exit_device_put;
2406 }
2407
2408 /* platform_device_add calls probe() */
2409 err = platform_device_add(pdev);
2410 if (err) {
abdc6fd1 2411 pr_err("Device addition failed (%d)\n", err);
1ea6dd38
DH		 2412 goto exit_device_put;
2413 }
2414
2415 return 0;
2416
2417exit_device_put:
2418 platform_device_put(pdev);
2419exit_unregister:
2420 platform_driver_unregister(&w83627ehf_driver);
2421exit:
2422 return err;
08e7e278
JD		 2423}
2424
2425static void __exit sensors_w83627ehf_exit(void)
2426{
1ea6dd38
DH		 2427 platform_device_unregister(pdev);
2428 platform_driver_unregister(&w83627ehf_driver);
08e7e278
JD		 2429}
2430
2431MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
2432MODULE_DESCRIPTION("W83627EHF driver");
2433MODULE_LICENSE("GPL");
2434
2435module_init(sensors_w83627ehf_init);
2436module_exit(sensors_w83627ehf_exit);
Linux kernel - Deliverables
This page took 0.830786 seconds and 5 git commands to generate.