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Merge tag 'for-v3.11' of git://git.infradead.org/battery-2.6
[deliverable/linux.git] / drivers / hwmon / w83781d.c
CommitLineData
1da177e4 1/*
aff6e00e
GR		 2 * w83781d.c - Part of lm_sensors, Linux kernel modules for hardware
3 * monitoring
4 * Copyright (c) 1998 - 2001 Frodo Looijaard <frodol@dds.nl>,
5 * Philip Edelbrock <phil@netroedge.com>,
6 * and Mark Studebaker <mdsxyz123@yahoo.com>
7 * Copyright (c) 2007 - 2008 Jean Delvare <khali@linux-fr.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
1da177e4
LT		 23
24/*
aff6e00e
GR		 25 * Supports following chips:
26 *
4101ece3 27 * Chip #vin #fanin #pwm #temp wchipid vendid i2c ISA
aff6e00e
GR		 28 * as99127f 7 3 0 3 0x31 0x12c3 yes no
29 * as99127f rev.2 (type_name = as99127f) 0x31 0x5ca3 yes no
30 * w83781d 7 3 0 3 0x10-1 0x5ca3 yes yes
31 * w83782d 9 3 2-4 3 0x30 0x5ca3 yes yes
32 * w83783s 5-6 3 2 1-2 0x40 0x5ca3 yes no
33 *
34 */
1da177e4 35
1ca28218
JP		 36#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37
1da177e4
LT		 38#include <linux/module.h>
39#include <linux/init.h>
40#include <linux/slab.h>
41#include <linux/jiffies.h>
42#include <linux/i2c.h>
943b0830 43#include <linux/hwmon.h>
303760b4 44#include <linux/hwmon-vid.h>
34875337 45#include <linux/hwmon-sysfs.h>
311ce2ef 46#include <linux/sysfs.h>
943b0830 47#include <linux/err.h>
9a61bf63 48#include <linux/mutex.h>
443850ce
WG		 49
50#ifdef CONFIG_ISA
51#include <linux/platform_device.h>
52#include <linux/ioport.h>
6055fae8 53#include <linux/io.h>
443850ce 54#endif
1da177e4 55
443850ce 56#include "lm75.h"
7666c13c 57
1da177e4 58/* Addresses to scan */
25e9c86d
MH		 59static const unsigned short normal_i2c[] = { 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d,
60 0x2e, 0x2f, I2C_CLIENT_END };
3aed198c 61
e5e9f44c
JD		 62enum chips { w83781d, w83782d, w83783s, as99127f };
63
64/* Insmod parameters */
3aed198c
JD		 65static unsigned short force_subclients[4];
66module_param_array(force_subclients, short, NULL, 0);
b55f3757
GR		 67MODULE_PARM_DESC(force_subclients,
68 "List of subclient addresses: {bus, clientaddr, subclientaddr1, subclientaddr2}");
1da177e4 69
90ab5ee9 70static bool reset;
fabddcd4
JD		 71module_param(reset, bool, 0);
72MODULE_PARM_DESC(reset, "Set to one to reset chip on load");
73
90ab5ee9 74static bool init = 1;
1da177e4
LT		 75module_param(init, bool, 0);
76MODULE_PARM_DESC(init, "Set to zero to bypass chip initialization");
77
78/* Constants specified below */
79
80/* Length of ISA address segment */
81#define W83781D_EXTENT 8
82
83/* Where are the ISA address/data registers relative to the base address */
84#define W83781D_ADDR_REG_OFFSET 5
85#define W83781D_DATA_REG_OFFSET 6
86
34875337
JD		 87/* The device registers */
88/* in nr from 0 to 8 */
1da177e4
LT		 89#define W83781D_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
90 (0x554 + (((nr) - 7) * 2)))
91#define W83781D_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
92 (0x555 + (((nr) - 7) * 2)))
93#define W83781D_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
94 (0x550 + (nr) - 7))
95
34875337
JD		 96/* fan nr from 0 to 2 */
97#define W83781D_REG_FAN_MIN(nr) (0x3b + (nr))
98#define W83781D_REG_FAN(nr) (0x28 + (nr))
1da177e4
LT		 99
100#define W83781D_REG_BANK 0x4E
101#define W83781D_REG_TEMP2_CONFIG 0x152
102#define W83781D_REG_TEMP3_CONFIG 0x252
34875337 103/* temp nr from 1 to 3 */
1da177e4
LT		 104#define W83781D_REG_TEMP(nr) ((nr == 3) ? (0x0250) : \
105 ((nr == 2) ? (0x0150) : \
106 (0x27)))
107#define W83781D_REG_TEMP_HYST(nr) ((nr == 3) ? (0x253) : \
108 ((nr == 2) ? (0x153) : \
109 (0x3A)))
110#define W83781D_REG_TEMP_OVER(nr) ((nr == 3) ? (0x255) : \
111 ((nr == 2) ? (0x155) : \
112 (0x39)))
113
114#define W83781D_REG_CONFIG 0x40
c7f5d7ed
JD		 115
116/* Interrupt status (W83781D, AS99127F) */
1da177e4
LT		 117#define W83781D_REG_ALARM1 0x41
118#define W83781D_REG_ALARM2 0x42
1da177e4 119
05663368 120/* Real-time status (W83782D, W83783S) */
c7f5d7ed
JD		 121#define W83782D_REG_ALARM1 0x459
122#define W83782D_REG_ALARM2 0x45A
123#define W83782D_REG_ALARM3 0x45B
124
1da177e4
LT		 125#define W83781D_REG_BEEP_CONFIG 0x4D
126#define W83781D_REG_BEEP_INTS1 0x56
127#define W83781D_REG_BEEP_INTS2 0x57
128#define W83781D_REG_BEEP_INTS3 0x453 /* not on W83781D */
129
130#define W83781D_REG_VID_FANDIV 0x47
131
132#define W83781D_REG_CHIPID 0x49
133#define W83781D_REG_WCHIPID 0x58
134#define W83781D_REG_CHIPMAN 0x4F
135#define W83781D_REG_PIN 0x4B
136
137/* 782D/783S only */
138#define W83781D_REG_VBAT 0x5D
139
140/* PWM 782D (1-4) and 783S (1-2) only */
34875337 141static const u8 W83781D_REG_PWM[] = { 0x5B, 0x5A, 0x5E, 0x5F };
1da177e4
LT		 142#define W83781D_REG_PWMCLK12 0x5C
143#define W83781D_REG_PWMCLK34 0x45C
1da177e4
LT		 144
145#define W83781D_REG_I2C_ADDR 0x48
146#define W83781D_REG_I2C_SUBADDR 0x4A
147
aff6e00e
GR		 148/*
149 * The following are undocumented in the data sheets however we
150 * received the information in an email from Winbond tech support
151 */
1da177e4
LT		 152/* Sensor selection - not on 781d */
153#define W83781D_REG_SCFG1 0x5D
154static const u8 BIT_SCFG1[] = { 0x02, 0x04, 0x08 };
155
156#define W83781D_REG_SCFG2 0x59
157static const u8 BIT_SCFG2[] = { 0x10, 0x20, 0x40 };
158
159#define W83781D_DEFAULT_BETA 3435
160
474d00a8 161/* Conversions */
2a844c14 162#define IN_TO_REG(val) clamp_val(((val) + 8) / 16, 0, 255)
474d00a8 163#define IN_FROM_REG(val) ((val) * 16)
1da177e4
LT		 164
165static inline u8
166FAN_TO_REG(long rpm, int div)
167{
168 if (rpm == 0)
169 return 255;
2a844c14
GR		 170 rpm = clamp_val(rpm, 1, 1000000);
171 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
1da177e4
LT		 172}
173
474d00a8
JD		 174static inline long
175FAN_FROM_REG(u8 val, int div)
176{
177 if (val == 0)
178 return -1;
179 if (val == 255)
180 return 0;
181 return 1350000 / (val * div);
182}
1da177e4 183
2a844c14 184#define TEMP_TO_REG(val) clamp_val((val) / 1000, -127, 128)
474d00a8 185#define TEMP_FROM_REG(val) ((val) * 1000)
1da177e4 186
c531eb3f 187#define BEEP_MASK_FROM_REG(val, type) ((type) == as99127f ? \
2fbbbf14 188 (~(val)) & 0x7fff : (val) & 0xff7fff)
c531eb3f 189#define BEEP_MASK_TO_REG(val, type) ((type) == as99127f ? \
2fbbbf14 190 (~(val)) & 0x7fff : (val) & 0xff7fff)
1da177e4 191
1da177e4
LT		 192#define DIV_FROM_REG(val) (1 << (val))
193
194static inline u8
195DIV_TO_REG(long val, enum chips type)
196{
197 int i;
2a844c14
GR		 198 val = clamp_val(val, 1,
199 ((type == w83781d || type == as99127f) ? 8 : 128)) >> 1;
abc01922 200 for (i = 0; i < 7; i++) {
1da177e4
LT		 201 if (val == 0)
202 break;
203 val >>= 1;
204 }
474d00a8 205 return i;
1da177e4
LT		 206}
207
1da177e4 208struct w83781d_data {
0217eae3 209 struct i2c_client *client;
1beeffe4 210 struct device *hwmon_dev;
9a61bf63 211 struct mutex lock;
1da177e4
LT		 212 enum chips type;
213
360782dd
JD		 214 /* For ISA device only */
215 const char *name;
216 int isa_addr;
217
9a61bf63 218 struct mutex update_lock;
1da177e4
LT		 219 char valid; /* !=0 if following fields are valid */
220 unsigned long last_updated; /* In jiffies */
221
222 struct i2c_client *lm75[2]; /* for secondary I2C addresses */
223 /* array of 2 pointers to subclients */
224
225 u8 in[9]; /* Register value - 8 & 9 for 782D only */
226 u8 in_max[9]; /* Register value - 8 & 9 for 782D only */
227 u8 in_min[9]; /* Register value - 8 & 9 for 782D only */
228 u8 fan[3]; /* Register value */
229 u8 fan_min[3]; /* Register value */
474d00a8
JD		 230 s8 temp; /* Register value */
231 s8 temp_max; /* Register value */
232 s8 temp_max_hyst; /* Register value */
1da177e4
LT		 233 u16 temp_add[2]; /* Register value */
234 u16 temp_max_add[2]; /* Register value */
235 u16 temp_max_hyst_add[2]; /* Register value */
236 u8 fan_div[3]; /* Register encoding, shifted right */
237 u8 vid; /* Register encoding, combined */
238 u32 alarms; /* Register encoding, combined */
239 u32 beep_mask; /* Register encoding, combined */
1da177e4 240 u8 pwm[4]; /* Register value */
34875337 241 u8 pwm2_enable; /* Boolean */
aff6e00e
GR		 242 u16 sens[3]; /*
243 * 782D/783S only.
244 * 1 = pentium diode; 2 = 3904 diode;
245 * 4 = thermistor
246 */
1da177e4
LT		 247 u8 vrm;
248};
249
443850ce
WG		 250static struct w83781d_data *w83781d_data_if_isa(void);
251static int w83781d_alias_detect(struct i2c_client *client, u8 chipid);
252
31b8dc4d
JD		 253static int w83781d_read_value(struct w83781d_data *data, u16 reg);
254static int w83781d_write_value(struct w83781d_data *data, u16 reg, u16 value);
1da177e4 255static struct w83781d_data *w83781d_update_device(struct device *dev);
7666c13c 256static void w83781d_init_device(struct device *dev);
1da177e4 257
1da177e4
LT		 258/* following are the sysfs callback functions */
259#define show_in_reg(reg) \
c531eb3f 260static ssize_t show_##reg(struct device *dev, struct device_attribute *da, \
34875337 261 char *buf) \
1da177e4 262{ \
34875337 263 struct sensor_device_attribute *attr = to_sensor_dev_attr(da); \
1da177e4 264 struct w83781d_data *data = w83781d_update_device(dev); \
34875337
JD		 265 return sprintf(buf, "%ld\n", \
266 (long)IN_FROM_REG(data->reg[attr->index])); \
1da177e4
LT		 267}
268show_in_reg(in);
269show_in_reg(in_min);
270show_in_reg(in_max);
271
272#define store_in_reg(REG, reg) \
c531eb3f 273static ssize_t store_in_##reg(struct device *dev, struct device_attribute \
34875337 274 *da, const char *buf, size_t count) \
1da177e4 275{ \
34875337 276 struct sensor_device_attribute *attr = to_sensor_dev_attr(da); \
7666c13c 277 struct w83781d_data *data = dev_get_drvdata(dev); \
34875337 278 int nr = attr->index; \
c531eb3f
GR		 279 unsigned long val; \
280 int err = kstrtoul(buf, 10, &val); \
281 if (err) \
282 return err; \
9a61bf63 283 mutex_lock(&data->update_lock); \
1da177e4 284 data->in_##reg[nr] = IN_TO_REG(val); \
c531eb3f
GR		 285 w83781d_write_value(data, W83781D_REG_IN_##REG(nr), \
286 data->in_##reg[nr]); \
287 \
9a61bf63 288 mutex_unlock(&data->update_lock); \
1da177e4
LT		 289 return count; \
290}
291store_in_reg(MIN, min);
292store_in_reg(MAX, max);
293
1da177e4 294#define sysfs_in_offsets(offset) \
34875337
JD		 295static SENSOR_DEVICE_ATTR(in##offset##_input, S_IRUGO, \
296 show_in, NULL, offset); \
297static SENSOR_DEVICE_ATTR(in##offset##_min, S_IRUGO | S_IWUSR, \
298 show_in_min, store_in_min, offset); \
299static SENSOR_DEVICE_ATTR(in##offset##_max, S_IRUGO | S_IWUSR, \
300 show_in_max, store_in_max, offset)
1da177e4
LT		 301
302sysfs_in_offsets(0);
303sysfs_in_offsets(1);
304sysfs_in_offsets(2);
305sysfs_in_offsets(3);
306sysfs_in_offsets(4);
307sysfs_in_offsets(5);
308sysfs_in_offsets(6);
309sysfs_in_offsets(7);
310sysfs_in_offsets(8);
311
1da177e4 312#define show_fan_reg(reg) \
c531eb3f 313static ssize_t show_##reg(struct device *dev, struct device_attribute *da, \
34875337 314 char *buf) \
1da177e4 315{ \
34875337 316 struct sensor_device_attribute *attr = to_sensor_dev_attr(da); \
1da177e4 317 struct w83781d_data *data = w83781d_update_device(dev); \
c531eb3f 318 return sprintf(buf, "%ld\n", \
34875337
JD		 319 FAN_FROM_REG(data->reg[attr->index], \
320 DIV_FROM_REG(data->fan_div[attr->index]))); \
1da177e4
LT		 321}
322show_fan_reg(fan);
323show_fan_reg(fan_min);
324
325static ssize_t
34875337
JD		 326store_fan_min(struct device *dev, struct device_attribute *da,
327 const char *buf, size_t count)
1da177e4 328{
34875337 329 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
7666c13c 330 struct w83781d_data *data = dev_get_drvdata(dev);
34875337 331 int nr = attr->index;
c531eb3f
GR		 332 unsigned long val;
333 int err;
1da177e4 334
c531eb3f
GR		 335 err = kstrtoul(buf, 10, &val);
336 if (err)
337 return err;
1da177e4 338
9a61bf63 339 mutex_lock(&data->update_lock);
34875337
JD		 340 data->fan_min[nr] =
341 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
31b8dc4d 342 w83781d_write_value(data, W83781D_REG_FAN_MIN(nr),
34875337 343 data->fan_min[nr]);
1da177e4 344
9a61bf63 345 mutex_unlock(&data->update_lock);
1da177e4
LT		 346 return count;
347}
348
34875337
JD		 349static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0);
350static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO | S_IWUSR,
351 show_fan_min, store_fan_min, 0);
352static SENSOR_DEVICE_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1);
353static SENSOR_DEVICE_ATTR(fan2_min, S_IRUGO | S_IWUSR,
354 show_fan_min, store_fan_min, 1);
355static SENSOR_DEVICE_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2);
356static SENSOR_DEVICE_ATTR(fan3_min, S_IRUGO | S_IWUSR,
357 show_fan_min, store_fan_min, 2);
1da177e4 358
1da177e4 359#define show_temp_reg(reg) \
c531eb3f 360static ssize_t show_##reg(struct device *dev, struct device_attribute *da, \
34875337 361 char *buf) \
1da177e4 362{ \
34875337 363 struct sensor_device_attribute *attr = to_sensor_dev_attr(da); \
1da177e4 364 struct w83781d_data *data = w83781d_update_device(dev); \
34875337 365 int nr = attr->index; \
1da177e4 366 if (nr >= 2) { /* TEMP2 and TEMP3 */ \
c531eb3f 367 return sprintf(buf, "%d\n", \
1da177e4
LT		 368 LM75_TEMP_FROM_REG(data->reg##_add[nr-2])); \
369 } else { /* TEMP1 */ \
c531eb3f 370 return sprintf(buf, "%ld\n", (long)TEMP_FROM_REG(data->reg)); \
1da177e4
LT		 371 } \
372}
373show_temp_reg(temp);
374show_temp_reg(temp_max);
375show_temp_reg(temp_max_hyst);
376
377#define store_temp_reg(REG, reg) \
c531eb3f 378static ssize_t store_temp_##reg(struct device *dev, \
34875337 379 struct device_attribute *da, const char *buf, size_t count) \
1da177e4 380{ \
34875337 381 struct sensor_device_attribute *attr = to_sensor_dev_attr(da); \
7666c13c 382 struct w83781d_data *data = dev_get_drvdata(dev); \
34875337 383 int nr = attr->index; \
5bfedac0 384 long val; \
c531eb3f
GR		 385 int err = kstrtol(buf, 10, &val); \
386 if (err) \
387 return err; \
9a61bf63 388 mutex_lock(&data->update_lock); \
1da177e4
LT		 389 \
390 if (nr >= 2) { /* TEMP2 and TEMP3 */ \
391 data->temp_##reg##_add[nr-2] = LM75_TEMP_TO_REG(val); \
31b8dc4d 392 w83781d_write_value(data, W83781D_REG_TEMP_##REG(nr), \
1da177e4
LT		 393 data->temp_##reg##_add[nr-2]); \
394 } else { /* TEMP1 */ \
395 data->temp_##reg = TEMP_TO_REG(val); \
31b8dc4d 396 w83781d_write_value(data, W83781D_REG_TEMP_##REG(nr), \
1da177e4
LT		 397 data->temp_##reg); \
398 } \
399 \
9a61bf63 400 mutex_unlock(&data->update_lock); \
1da177e4
LT		 401 return count; \
402}
403store_temp_reg(OVER, max);
404store_temp_reg(HYST, max_hyst);
405
1da177e4 406#define sysfs_temp_offsets(offset) \
34875337
JD		 407static SENSOR_DEVICE_ATTR(temp##offset##_input, S_IRUGO, \
408 show_temp, NULL, offset); \
409static SENSOR_DEVICE_ATTR(temp##offset##_max, S_IRUGO | S_IWUSR, \
410 show_temp_max, store_temp_max, offset); \
411static SENSOR_DEVICE_ATTR(temp##offset##_max_hyst, S_IRUGO | S_IWUSR, \
412 show_temp_max_hyst, store_temp_max_hyst, offset);
1da177e4
LT		 413
414sysfs_temp_offsets(1);
415sysfs_temp_offsets(2);
416sysfs_temp_offsets(3);
417
1da177e4 418static ssize_t
e404e274 419show_vid_reg(struct device *dev, struct device_attribute *attr, char *buf)
1da177e4
LT		 420{
421 struct w83781d_data *data = w83781d_update_device(dev);
422 return sprintf(buf, "%ld\n", (long) vid_from_reg(data->vid, data->vrm));
423}
424
311ce2ef
JC		 425static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
426
1da177e4 427static ssize_t
e404e274 428show_vrm_reg(struct device *dev, struct device_attribute *attr, char *buf)
1da177e4 429{
90d6619a 430 struct w83781d_data *data = dev_get_drvdata(dev);
1da177e4
LT		 431 return sprintf(buf, "%ld\n", (long) data->vrm);
432}
433
434static ssize_t
c531eb3f
GR		 435store_vrm_reg(struct device *dev, struct device_attribute *attr,
436 const char *buf, size_t count)
1da177e4 437{
7666c13c 438 struct w83781d_data *data = dev_get_drvdata(dev);
c531eb3f
GR		 439 unsigned long val;
440 int err;
1da177e4 441
c531eb3f
GR		 442 err = kstrtoul(buf, 10, &val);
443 if (err)
444 return err;
2a844c14 445 data->vrm = clamp_val(val, 0, 255);
1da177e4
LT		 446
447 return count;
448}
449
311ce2ef
JC		 450static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
451
1da177e4 452static ssize_t
e404e274 453show_alarms_reg(struct device *dev, struct device_attribute *attr, char *buf)
1da177e4
LT		 454{
455 struct w83781d_data *data = w83781d_update_device(dev);
68188ba7 456 return sprintf(buf, "%u\n", data->alarms);
1da177e4
LT		 457}
458
311ce2ef
JC		 459static DEVICE_ATTR(alarms, S_IRUGO, show_alarms_reg, NULL);
460
7d4a1374
JD		 461static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
462 char *buf)
463{
464 struct w83781d_data *data = w83781d_update_device(dev);
465 int bitnr = to_sensor_dev_attr(attr)->index;
466 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
467}
468
469/* The W83781D has a single alarm bit for temp2 and temp3 */
470static ssize_t show_temp3_alarm(struct device *dev,
471 struct device_attribute *attr, char *buf)
472{
473 struct w83781d_data *data = w83781d_update_device(dev);
474 int bitnr = (data->type == w83781d) ? 5 : 13;
475 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
476}
477
478static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0);
479static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1);
480static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2);
481static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3);
482static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8);
483static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 9);
484static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 10);
485static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16);
486static SENSOR_DEVICE_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17);
487static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6);
488static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7);
489static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11);
490static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4);
491static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5);
492static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_temp3_alarm, NULL, 0);
493
c531eb3f
GR		 494static ssize_t show_beep_mask(struct device *dev,
495 struct device_attribute *attr, char *buf)
1da177e4
LT		 496{
497 struct w83781d_data *data = w83781d_update_device(dev);
498 return sprintf(buf, "%ld\n",
499 (long)BEEP_MASK_FROM_REG(data->beep_mask, data->type));
500}
1da177e4 501
1da177e4 502static ssize_t
34875337
JD		 503store_beep_mask(struct device *dev, struct device_attribute *attr,
504 const char *buf, size_t count)
1da177e4 505{
7666c13c 506 struct w83781d_data *data = dev_get_drvdata(dev);
c531eb3f
GR		 507 unsigned long val;
508 int err;
1da177e4 509
c531eb3f
GR		 510 err = kstrtoul(buf, 10, &val);
511 if (err)
512 return err;
1da177e4 513
9a61bf63 514 mutex_lock(&data->update_lock);
2fbbbf14
JD		 515 data->beep_mask &= 0x8000; /* preserve beep enable */
516 data->beep_mask |= BEEP_MASK_TO_REG(val, data->type);
34875337
JD		 517 w83781d_write_value(data, W83781D_REG_BEEP_INTS1,
518 data->beep_mask & 0xff);
519 w83781d_write_value(data, W83781D_REG_BEEP_INTS2,
2fbbbf14 520 (data->beep_mask >> 8) & 0xff);
34875337
JD		 521 if (data->type != w83781d && data->type != as99127f) {
522 w83781d_write_value(data, W83781D_REG_BEEP_INTS3,
523 ((data->beep_mask) >> 16) & 0xff);
524 }
525 mutex_unlock(&data->update_lock);
1da177e4 526
34875337
JD		 527 return count;
528}
1da177e4 529
34875337
JD		 530static DEVICE_ATTR(beep_mask, S_IRUGO | S_IWUSR,
531 show_beep_mask, store_beep_mask);
1da177e4 532
7d4a1374
JD		 533static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
534 char *buf)
535{
536 struct w83781d_data *data = w83781d_update_device(dev);
537 int bitnr = to_sensor_dev_attr(attr)->index;
538 return sprintf(buf, "%u\n", (data->beep_mask >> bitnr) & 1);
539}
540
541static ssize_t
542store_beep(struct device *dev, struct device_attribute *attr,
543 const char *buf, size_t count)
544{
545 struct w83781d_data *data = dev_get_drvdata(dev);
546 int bitnr = to_sensor_dev_attr(attr)->index;
7d4a1374 547 u8 reg;
c531eb3f
GR		 548 unsigned long bit;
549 int err;
550
551 err = kstrtoul(buf, 10, &bit);
552 if (err)
553 return err;
7d4a1374 554
7d4a1374
JD		 555 if (bit & ~1)
556 return -EINVAL;
557
558 mutex_lock(&data->update_lock);
559 if (bit)
560 data->beep_mask |= (1 << bitnr);
561 else
562 data->beep_mask &= ~(1 << bitnr);
563
564 if (bitnr < 8) {
565 reg = w83781d_read_value(data, W83781D_REG_BEEP_INTS1);
566 if (bit)
567 reg |= (1 << bitnr);
568 else
569 reg &= ~(1 << bitnr);
570 w83781d_write_value(data, W83781D_REG_BEEP_INTS1, reg);
571 } else if (bitnr < 16) {
572 reg = w83781d_read_value(data, W83781D_REG_BEEP_INTS2);
573 if (bit)
574 reg |= (1 << (bitnr - 8));
575 else
576 reg &= ~(1 << (bitnr - 8));
577 w83781d_write_value(data, W83781D_REG_BEEP_INTS2, reg);
578 } else {
579 reg = w83781d_read_value(data, W83781D_REG_BEEP_INTS3);
580 if (bit)
581 reg |= (1 << (bitnr - 16));
582 else
583 reg &= ~(1 << (bitnr - 16));
584 w83781d_write_value(data, W83781D_REG_BEEP_INTS3, reg);
585 }
586 mutex_unlock(&data->update_lock);
587
588 return count;
589}
590
591/* The W83781D has a single beep bit for temp2 and temp3 */
592static ssize_t show_temp3_beep(struct device *dev,
593 struct device_attribute *attr, char *buf)
594{
595 struct w83781d_data *data = w83781d_update_device(dev);
596 int bitnr = (data->type == w83781d) ? 5 : 13;
597 return sprintf(buf, "%u\n", (data->beep_mask >> bitnr) & 1);
598}
599
600static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
601 show_beep, store_beep, 0);
602static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO | S_IWUSR,
603 show_beep, store_beep, 1);
604static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO | S_IWUSR,
605 show_beep, store_beep, 2);
606static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO | S_IWUSR,
607 show_beep, store_beep, 3);
608static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO | S_IWUSR,
609 show_beep, store_beep, 8);
610static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO | S_IWUSR,
611 show_beep, store_beep, 9);
612static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO | S_IWUSR,
613 show_beep, store_beep, 10);
614static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO | S_IWUSR,
615 show_beep, store_beep, 16);
616static SENSOR_DEVICE_ATTR(in8_beep, S_IRUGO | S_IWUSR,
617 show_beep, store_beep, 17);
618static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO | S_IWUSR,
619 show_beep, store_beep, 6);
620static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO | S_IWUSR,
621 show_beep, store_beep, 7);
622static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO | S_IWUSR,
623 show_beep, store_beep, 11);
624static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
625 show_beep, store_beep, 4);
626static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO | S_IWUSR,
627 show_beep, store_beep, 5);
628static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO,
629 show_temp3_beep, store_beep, 13);
2fbbbf14
JD		 630static SENSOR_DEVICE_ATTR(beep_enable, S_IRUGO | S_IWUSR,
631 show_beep, store_beep, 15);
7d4a1374 632
1da177e4 633static ssize_t
34875337 634show_fan_div(struct device *dev, struct device_attribute *da, char *buf)
1da177e4 635{
34875337 636 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
1da177e4
LT		 637 struct w83781d_data *data = w83781d_update_device(dev);
638 return sprintf(buf, "%ld\n",
34875337 639 (long) DIV_FROM_REG(data->fan_div[attr->index]));
1da177e4
LT		 640}
641
aff6e00e
GR		 642/*
643 * Note: we save and restore the fan minimum here, because its value is
644 * determined in part by the fan divisor. This follows the principle of
645 * least surprise; the user doesn't expect the fan minimum to change just
646 * because the divisor changed.
647 */
1da177e4 648static ssize_t
34875337
JD		 649store_fan_div(struct device *dev, struct device_attribute *da,
650 const char *buf, size_t count)
1da177e4 651{
34875337 652 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
7666c13c 653 struct w83781d_data *data = dev_get_drvdata(dev);
1da177e4 654 unsigned long min;
34875337 655 int nr = attr->index;
1da177e4 656 u8 reg;
c531eb3f
GR		 657 unsigned long val;
658 int err;
659
660 err = kstrtoul(buf, 10, &val);
661 if (err)
662 return err;
1da177e4 663
9a61bf63 664 mutex_lock(&data->update_lock);
293c0997 665
1da177e4
LT		 666 /* Save fan_min */
667 min = FAN_FROM_REG(data->fan_min[nr],
668 DIV_FROM_REG(data->fan_div[nr]));
669
670 data->fan_div[nr] = DIV_TO_REG(val, data->type);
671
c531eb3f
GR		 672 reg = (w83781d_read_value(data, nr == 2 ?
673 W83781D_REG_PIN : W83781D_REG_VID_FANDIV)
674 & (nr == 0 ? 0xcf : 0x3f))
675 | ((data->fan_div[nr] & 0x03) << (nr == 0 ? 4 : 6));
676 w83781d_write_value(data, nr == 2 ?
677 W83781D_REG_PIN : W83781D_REG_VID_FANDIV, reg);
1da177e4
LT		 678
679 /* w83781d and as99127f don't have extended divisor bits */
680 if (data->type != w83781d && data->type != as99127f) {
31b8dc4d 681 reg = (w83781d_read_value(data, W83781D_REG_VBAT)
1da177e4
LT		 682 & ~(1 << (5 + nr)))
683 | ((data->fan_div[nr] & 0x04) << (3 + nr));
31b8dc4d 684 w83781d_write_value(data, W83781D_REG_VBAT, reg);
1da177e4
LT		 685 }
686
687 /* Restore fan_min */
688 data->fan_min[nr] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
34875337 689 w83781d_write_value(data, W83781D_REG_FAN_MIN(nr), data->fan_min[nr]);
1da177e4 690
9a61bf63 691 mutex_unlock(&data->update_lock);
1da177e4
LT		 692 return count;
693}
694
34875337
JD		 695static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR,
696 show_fan_div, store_fan_div, 0);
697static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR,
698 show_fan_div, store_fan_div, 1);
699static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR,
700 show_fan_div, store_fan_div, 2);
1da177e4 701
1da177e4 702static ssize_t
34875337 703show_pwm(struct device *dev, struct device_attribute *da, char *buf)
1da177e4 704{
34875337 705 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
1da177e4 706 struct w83781d_data *data = w83781d_update_device(dev);
34875337 707 return sprintf(buf, "%d\n", (int)data->pwm[attr->index]);
1da177e4
LT		 708}
709
710static ssize_t
34875337 711show_pwm2_enable(struct device *dev, struct device_attribute *da, char *buf)
1da177e4
LT		 712{
713 struct w83781d_data *data = w83781d_update_device(dev);
34875337 714 return sprintf(buf, "%d\n", (int)data->pwm2_enable);
1da177e4
LT		 715}
716
717static ssize_t
34875337
JD		 718store_pwm(struct device *dev, struct device_attribute *da, const char *buf,
719 size_t count)
1da177e4 720{
34875337 721 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
7666c13c 722 struct w83781d_data *data = dev_get_drvdata(dev);
34875337 723 int nr = attr->index;
c531eb3f
GR		 724 unsigned long val;
725 int err;
1da177e4 726
c531eb3f
GR		 727 err = kstrtoul(buf, 10, &val);
728 if (err)
729 return err;
1da177e4 730
9a61bf63 731 mutex_lock(&data->update_lock);
2a844c14 732 data->pwm[nr] = clamp_val(val, 0, 255);
34875337 733 w83781d_write_value(data, W83781D_REG_PWM[nr], data->pwm[nr]);
9a61bf63 734 mutex_unlock(&data->update_lock);
1da177e4
LT		 735 return count;
736}
737
738static ssize_t
34875337
JD		 739store_pwm2_enable(struct device *dev, struct device_attribute *da,
740 const char *buf, size_t count)
1da177e4 741{
7666c13c 742 struct w83781d_data *data = dev_get_drvdata(dev);
c531eb3f
GR		 743 unsigned long val;
744 u32 reg;
745 int err;
1da177e4 746
c531eb3f
GR		 747 err = kstrtoul(buf, 10, &val);
748 if (err)
749 return err;
1da177e4 750
9a61bf63 751 mutex_lock(&data->update_lock);
1da177e4
LT		 752
753 switch (val) {
754 case 0:
755 case 1:
31b8dc4d
JD		 756 reg = w83781d_read_value(data, W83781D_REG_PWMCLK12);
757 w83781d_write_value(data, W83781D_REG_PWMCLK12,
1da177e4
LT		 758 (reg & 0xf7) | (val << 3));
759
31b8dc4d
JD		 760 reg = w83781d_read_value(data, W83781D_REG_BEEP_CONFIG);
761 w83781d_write_value(data, W83781D_REG_BEEP_CONFIG,
1da177e4
LT		 762 (reg & 0xef) | (!val << 4));
763
34875337 764 data->pwm2_enable = val;
1da177e4
LT		 765 break;
766
767 default:
9a61bf63 768 mutex_unlock(&data->update_lock);
1da177e4
LT		 769 return -EINVAL;
770 }
771
9a61bf63 772 mutex_unlock(&data->update_lock);
1da177e4
LT		 773 return count;
774}
775
34875337
JD		 776static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, store_pwm, 0);
777static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, store_pwm, 1);
778static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, store_pwm, 2);
779static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, store_pwm, 3);
780/* only PWM2 can be enabled/disabled */
781static DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
782 show_pwm2_enable, store_pwm2_enable);
1da177e4 783
1da177e4 784static ssize_t
34875337 785show_sensor(struct device *dev, struct device_attribute *da, char *buf)
1da177e4 786{
34875337 787 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
1da177e4 788 struct w83781d_data *data = w83781d_update_device(dev);
34875337 789 return sprintf(buf, "%d\n", (int)data->sens[attr->index]);
1da177e4
LT		 790}
791
792static ssize_t
34875337
JD		 793store_sensor(struct device *dev, struct device_attribute *da,
794 const char *buf, size_t count)
1da177e4 795{
34875337 796 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
7666c13c 797 struct w83781d_data *data = dev_get_drvdata(dev);
34875337 798 int nr = attr->index;
c531eb3f
GR		 799 unsigned long val;
800 u32 tmp;
801 int err;
1da177e4 802
c531eb3f
GR		 803 err = kstrtoul(buf, 10, &val);
804 if (err)
805 return err;
1da177e4 806
9a61bf63 807 mutex_lock(&data->update_lock);
1da177e4
LT		 808
809 switch (val) {
810 case 1: /* PII/Celeron diode */
31b8dc4d
JD		 811 tmp = w83781d_read_value(data, W83781D_REG_SCFG1);
812 w83781d_write_value(data, W83781D_REG_SCFG1,
34875337 813 tmp | BIT_SCFG1[nr]);
31b8dc4d
JD		 814 tmp = w83781d_read_value(data, W83781D_REG_SCFG2);
815 w83781d_write_value(data, W83781D_REG_SCFG2,
34875337
JD		 816 tmp | BIT_SCFG2[nr]);
817 data->sens[nr] = val;
1da177e4
LT		 818 break;
819 case 2: /* 3904 */
31b8dc4d
JD		 820 tmp = w83781d_read_value(data, W83781D_REG_SCFG1);
821 w83781d_write_value(data, W83781D_REG_SCFG1,
34875337 822 tmp | BIT_SCFG1[nr]);
31b8dc4d
JD		 823 tmp = w83781d_read_value(data, W83781D_REG_SCFG2);
824 w83781d_write_value(data, W83781D_REG_SCFG2,
34875337
JD		 825 tmp & ~BIT_SCFG2[nr]);
826 data->sens[nr] = val;
1da177e4 827 break;
b26f9330 828 case W83781D_DEFAULT_BETA:
b55f3757
GR		 829 dev_warn(dev,
830 "Sensor type %d is deprecated, please use 4 instead\n",
831 W83781D_DEFAULT_BETA);
b26f9330
JD		 832 /* fall through */
833 case 4: /* thermistor */
31b8dc4d
JD		 834 tmp = w83781d_read_value(data, W83781D_REG_SCFG1);
835 w83781d_write_value(data, W83781D_REG_SCFG1,
34875337
JD		 836 tmp & ~BIT_SCFG1[nr]);
837 data->sens[nr] = val;
1da177e4
LT		 838 break;
839 default:
b26f9330
JD		 840 dev_err(dev, "Invalid sensor type %ld; must be 1, 2, or 4\n",
841 (long) val);
1da177e4
LT		 842 break;
843 }
844
9a61bf63 845 mutex_unlock(&data->update_lock);
1da177e4
LT		 846 return count;
847}
848
34875337
JD		 849static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR,
850 show_sensor, store_sensor, 0);
851static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR,
393cdad6 852 show_sensor, store_sensor, 1);
34875337 853static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR,
393cdad6 854 show_sensor, store_sensor, 2);
1da177e4 855
aff6e00e
GR		 856/*
857 * Assumes that adapter is of I2C, not ISA variety.
1da177e4
LT		 858 * OTHERWISE DON'T CALL THIS
859 */
860static int
0217eae3 861w83781d_detect_subclients(struct i2c_client *new_client)
1da177e4
LT		 862{
863 int i, val1 = 0, id;
864 int err;
0217eae3
WG		 865 int address = new_client->addr;
866 unsigned short sc_addr[2];
867 struct i2c_adapter *adapter = new_client->adapter;
1da177e4 868 struct w83781d_data *data = i2c_get_clientdata(new_client);
0217eae3 869 enum chips kind = data->type;
bbc8a569 870 int num_sc = 1;
1da177e4
LT		 871
872 id = i2c_adapter_id(adapter);
873
874 if (force_subclients[0] == id && force_subclients[1] == address) {
875 for (i = 2; i <= 3; i++) {
876 if (force_subclients[i] < 0x48 ||
877 force_subclients[i] > 0x4f) {
b55f3757
GR		 878 dev_err(&new_client->dev,
879 "Invalid subclient address %d; must be 0x48-0x4f\n",
1da177e4
LT		 880 force_subclients[i]);
881 err = -EINVAL;
882 goto ERROR_SC_1;
883 }
884 }
31b8dc4d 885 w83781d_write_value(data, W83781D_REG_I2C_SUBADDR,
1da177e4
LT		 886 (force_subclients[2] & 0x07) |
887 ((force_subclients[3] & 0x07) << 4));
0217eae3 888 sc_addr[0] = force_subclients[2];
1da177e4 889 } else {
31b8dc4d 890 val1 = w83781d_read_value(data, W83781D_REG_I2C_SUBADDR);
0217eae3 891 sc_addr[0] = 0x48 + (val1 & 0x07);
1da177e4
LT		 892 }
893
894 if (kind != w83783s) {
bbc8a569 895 num_sc = 2;
1da177e4
LT		 896 if (force_subclients[0] == id &&
897 force_subclients[1] == address) {
0217eae3 898 sc_addr[1] = force_subclients[3];
1da177e4 899 } else {
0217eae3 900 sc_addr[1] = 0x48 + ((val1 >> 4) & 0x07);
1da177e4 901 }
0217eae3 902 if (sc_addr[0] == sc_addr[1]) {
1da177e4
LT		 903 dev_err(&new_client->dev,
904 "Duplicate addresses 0x%x for subclients.\n",
0217eae3 905 sc_addr[0]);
1da177e4
LT		 906 err = -EBUSY;
907 goto ERROR_SC_2;
908 }
909 }
910
bbc8a569 911 for (i = 0; i < num_sc; i++) {
0217eae3
WG		 912 data->lm75[i] = i2c_new_dummy(adapter, sc_addr[i]);
913 if (!data->lm75[i]) {
b55f3757
GR		 914 dev_err(&new_client->dev,
915 "Subclient %d registration at address 0x%x failed.\n",
916 i, sc_addr[i]);
0217eae3 917 err = -ENOMEM;
1da177e4
LT		 918 if (i == 1)
919 goto ERROR_SC_3;
920 goto ERROR_SC_2;
921 }
1da177e4
LT		 922 }
923
924 return 0;
925
926/* Undo inits in case of errors */
927ERROR_SC_3:
0217eae3 928 i2c_unregister_device(data->lm75[0]);
1da177e4 929ERROR_SC_2:
1da177e4 930ERROR_SC_1:
1da177e4
LT		 931 return err;
932}
933
34875337
JD		 934#define IN_UNIT_ATTRS(X) \
935 &sensor_dev_attr_in##X##_input.dev_attr.attr, \
936 &sensor_dev_attr_in##X##_min.dev_attr.attr, \
293c0997 937 &sensor_dev_attr_in##X##_max.dev_attr.attr, \
7d4a1374
JD		 938 &sensor_dev_attr_in##X##_alarm.dev_attr.attr, \
939 &sensor_dev_attr_in##X##_beep.dev_attr.attr
311ce2ef 940
34875337
JD		 941#define FAN_UNIT_ATTRS(X) \
942 &sensor_dev_attr_fan##X##_input.dev_attr.attr, \
943 &sensor_dev_attr_fan##X##_min.dev_attr.attr, \
7d4a1374
JD		 944 &sensor_dev_attr_fan##X##_div.dev_attr.attr, \
945 &sensor_dev_attr_fan##X##_alarm.dev_attr.attr, \
946 &sensor_dev_attr_fan##X##_beep.dev_attr.attr
311ce2ef 947
34875337
JD		 948#define TEMP_UNIT_ATTRS(X) \
949 &sensor_dev_attr_temp##X##_input.dev_attr.attr, \
950 &sensor_dev_attr_temp##X##_max.dev_attr.attr, \
7d4a1374
JD		 951 &sensor_dev_attr_temp##X##_max_hyst.dev_attr.attr, \
952 &sensor_dev_attr_temp##X##_alarm.dev_attr.attr, \
953 &sensor_dev_attr_temp##X##_beep.dev_attr.attr
311ce2ef 954
c531eb3f 955static struct attribute *w83781d_attributes[] = {
311ce2ef
JC		 956 IN_UNIT_ATTRS(0),
957 IN_UNIT_ATTRS(2),
958 IN_UNIT_ATTRS(3),
959 IN_UNIT_ATTRS(4),
960 IN_UNIT_ATTRS(5),
961 IN_UNIT_ATTRS(6),
962 FAN_UNIT_ATTRS(1),
963 FAN_UNIT_ATTRS(2),
964 FAN_UNIT_ATTRS(3),
965 TEMP_UNIT_ATTRS(1),
966 TEMP_UNIT_ATTRS(2),
967 &dev_attr_cpu0_vid.attr,
968 &dev_attr_vrm.attr,
969 &dev_attr_alarms.attr,
970 &dev_attr_beep_mask.attr,
2fbbbf14 971 &sensor_dev_attr_beep_enable.dev_attr.attr,
311ce2ef
JC		 972 NULL
973};
974static const struct attribute_group w83781d_group = {
975 .attrs = w83781d_attributes,
976};
977
79501333 978static struct attribute *w83781d_attributes_in1[] = {
311ce2ef 979 IN_UNIT_ATTRS(1),
79501333
GR		 980 NULL
981};
982static const struct attribute_group w83781d_group_in1 = {
983 .attrs = w83781d_attributes_in1,
984};
985
986static struct attribute *w83781d_attributes_in78[] = {
311ce2ef
JC		 987 IN_UNIT_ATTRS(7),
988 IN_UNIT_ATTRS(8),
79501333
GR		 989 NULL
990};
991static const struct attribute_group w83781d_group_in78 = {
992 .attrs = w83781d_attributes_in78,
993};
994
995static struct attribute *w83781d_attributes_temp3[] = {
311ce2ef 996 TEMP_UNIT_ATTRS(3),
79501333
GR		 997 NULL
998};
999static const struct attribute_group w83781d_group_temp3 = {
1000 .attrs = w83781d_attributes_temp3,
1001};
1002
1003static struct attribute *w83781d_attributes_pwm12[] = {
34875337
JD		 1004 &sensor_dev_attr_pwm1.dev_attr.attr,
1005 &sensor_dev_attr_pwm2.dev_attr.attr,
79501333
GR		 1006 &dev_attr_pwm2_enable.attr,
1007 NULL
1008};
1009static const struct attribute_group w83781d_group_pwm12 = {
1010 .attrs = w83781d_attributes_pwm12,
1011};
1012
1013static struct attribute *w83781d_attributes_pwm34[] = {
34875337
JD		 1014 &sensor_dev_attr_pwm3.dev_attr.attr,
1015 &sensor_dev_attr_pwm4.dev_attr.attr,
79501333
GR		 1016 NULL
1017};
1018static const struct attribute_group w83781d_group_pwm34 = {
1019 .attrs = w83781d_attributes_pwm34,
1020};
1021
1022static struct attribute *w83781d_attributes_other[] = {
34875337
JD		 1023 &sensor_dev_attr_temp1_type.dev_attr.attr,
1024 &sensor_dev_attr_temp2_type.dev_attr.attr,
1025 &sensor_dev_attr_temp3_type.dev_attr.attr,
311ce2ef
JC		 1026 NULL
1027};
79501333
GR		 1028static const struct attribute_group w83781d_group_other = {
1029 .attrs = w83781d_attributes_other,
311ce2ef
JC		 1030};
1031
7666c13c 1032/* No clean up is done on error, it's up to the caller */
1da177e4 1033static int
7666c13c 1034w83781d_create_files(struct device *dev, int kind, int is_isa)
1da177e4 1035{
1da177e4 1036 int err;
1da177e4 1037
c531eb3f
GR		 1038 err = sysfs_create_group(&dev->kobj, &w83781d_group);
1039 if (err)
7666c13c
JD		 1040 return err;
1041
1042 if (kind != w83783s) {
79501333
GR		 1043 err = sysfs_create_group(&dev->kobj, &w83781d_group_in1);
1044 if (err)
7666c13c
JD		 1045 return err;
1046 }
1047 if (kind != as99127f && kind != w83781d && kind != w83783s) {
79501333
GR		 1048 err = sysfs_create_group(&dev->kobj, &w83781d_group_in78);
1049 if (err)
7666c13c
JD		 1050 return err;
1051 }
1052 if (kind != w83783s) {
79501333
GR		 1053 err = sysfs_create_group(&dev->kobj, &w83781d_group_temp3);
1054 if (err)
7666c13c 1055 return err;
7d4a1374 1056
7768aa76 1057 if (kind != w83781d) {
7d4a1374
JD		 1058 err = sysfs_chmod_file(&dev->kobj,
1059 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
1060 S_IRUGO | S_IWUSR);
1061 if (err)
1062 return err;
7768aa76 1063 }
1da177e4
LT		 1064 }
1065
7666c13c 1066 if (kind != w83781d && kind != as99127f) {
79501333
GR		 1067 err = sysfs_create_group(&dev->kobj, &w83781d_group_pwm12);
1068 if (err)
7666c13c 1069 return err;
1da177e4 1070 }
7666c13c 1071 if (kind == w83782d && !is_isa) {
79501333
GR		 1072 err = sysfs_create_group(&dev->kobj, &w83781d_group_pwm34);
1073 if (err)
7666c13c
JD		 1074 return err;
1075 }
1076
1077 if (kind != as99127f && kind != w83781d) {
79501333
GR		 1078 err = device_create_file(dev,
1079 &sensor_dev_attr_temp1_type.dev_attr);
1080 if (err)
1081 return err;
1082 err = device_create_file(dev,
1083 &sensor_dev_attr_temp2_type.dev_attr);
1084 if (err)
7666c13c
JD		 1085 return err;
1086 if (kind != w83783s) {
c531eb3f 1087 err = device_create_file(dev,
79501333 1088 &sensor_dev_attr_temp3_type.dev_attr);
c531eb3f 1089 if (err)
7666c13c 1090 return err;
1da177e4 1091 }
7666c13c 1092 }
1da177e4 1093
7666c13c
JD		 1094 return 0;
1095}
1da177e4 1096
0217eae3 1097/* Return 0 if detection is successful, -ENODEV otherwise */
7666c13c 1098static int
310ec792 1099w83781d_detect(struct i2c_client *client, struct i2c_board_info *info)
7666c13c 1100{
bab2bf44 1101 int val1, val2;
0217eae3
WG		 1102 struct w83781d_data *isa = w83781d_data_if_isa();
1103 struct i2c_adapter *adapter = client->adapter;
1104 int address = client->addr;
bab2bf44 1105 const char *client_name;
7666c13c
JD		 1106 enum vendor { winbond, asus } vendid;
1107
0217eae3
WG		 1108 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1109 return -ENODEV;
1da177e4 1110
aff6e00e
GR		 1111 /*
1112 * We block updates of the ISA device to minimize the risk of
1113 * concurrent access to the same W83781D chip through different
1114 * interfaces.
1115 */
0217eae3
WG		 1116 if (isa)
1117 mutex_lock(&isa->update_lock);
1da177e4 1118
bab2bf44
JD		 1119 if (i2c_smbus_read_byte_data(client, W83781D_REG_CONFIG) & 0x80) {
1120 dev_dbg(&adapter->dev,
1121 "Detection of w83781d chip failed at step 3\n");
1122 goto err_nodev;
1123 }
1124
1125 val1 = i2c_smbus_read_byte_data(client, W83781D_REG_BANK);
1126 val2 = i2c_smbus_read_byte_data(client, W83781D_REG_CHIPMAN);
1127 /* Check for Winbond or Asus ID if in bank 0 */
1128 if (!(val1 & 0x07) &&
1129 ((!(val1 & 0x80) && val2 != 0xa3 && val2 != 0xc3) ||
c531eb3f 1130 ((val1 & 0x80) && val2 != 0x5c && val2 != 0x12))) {
bab2bf44
JD		 1131 dev_dbg(&adapter->dev,
1132 "Detection of w83781d chip failed at step 4\n");
1133 goto err_nodev;
1134 }
aff6e00e
GR		 1135 /*
1136 * If Winbond SMBus, check address at 0x48.
1137 * Asus doesn't support, except for as99127f rev.2
1138 */
bab2bf44 1139 if ((!(val1 & 0x80) && val2 == 0xa3) ||
c531eb3f 1140 ((val1 & 0x80) && val2 == 0x5c)) {
bab2bf44
JD		 1141 if (i2c_smbus_read_byte_data(client, W83781D_REG_I2C_ADDR)
1142 != address) {
1143 dev_dbg(&adapter->dev,
1144 "Detection of w83781d chip failed at step 5\n");
0217eae3 1145 goto err_nodev;
1da177e4 1146 }
1da177e4
LT		 1147 }
1148
bab2bf44 1149 /* Put it now into bank 0 and Vendor ID High Byte */
0217eae3
WG		 1150 i2c_smbus_write_byte_data(client, W83781D_REG_BANK,
1151 (i2c_smbus_read_byte_data(client, W83781D_REG_BANK)
1152 & 0x78) | 0x80);
1da177e4 1153
bab2bf44
JD		 1154 /* Get the vendor ID */
1155 val2 = i2c_smbus_read_byte_data(client, W83781D_REG_CHIPMAN);
1156 if (val2 == 0x5c)
1157 vendid = winbond;
1158 else if (val2 == 0x12)
1159 vendid = asus;
1160 else {
1161 dev_dbg(&adapter->dev,
1162 "w83781d chip vendor is neither Winbond nor Asus\n");
1163 goto err_nodev;
1da177e4
LT		 1164 }
1165
bab2bf44
JD		 1166 /* Determine the chip type. */
1167 val1 = i2c_smbus_read_byte_data(client, W83781D_REG_WCHIPID);
1168 if ((val1 == 0x10 || val1 == 0x11) && vendid == winbond)
1da177e4 1169 client_name = "w83781d";
bab2bf44 1170 else if (val1 == 0x30 && vendid == winbond)
1da177e4 1171 client_name = "w83782d";
bab2bf44 1172 else if (val1 == 0x40 && vendid == winbond && address == 0x2d)
1da177e4 1173 client_name = "w83783s";
bab2bf44 1174 else if (val1 == 0x31)
1da177e4 1175 client_name = "as99127f";
bab2bf44
JD		 1176 else
1177 goto err_nodev;
1178
1179 if (val1 <= 0x30 && w83781d_alias_detect(client, val1)) {
b55f3757
GR		 1180 dev_dbg(&adapter->dev,
1181 "Device at 0x%02x appears to be the same as ISA device\n",
1182 address);
bab2bf44 1183 goto err_nodev;
1da177e4
LT		 1184 }
1185
bab2bf44
JD		 1186 if (isa)
1187 mutex_unlock(&isa->update_lock);
1188
0217eae3
WG		 1189 strlcpy(info->type, client_name, I2C_NAME_SIZE);
1190
1191 return 0;
1192
1193 err_nodev:
1194 if (isa)
1195 mutex_unlock(&isa->update_lock);
1196 return -ENODEV;
1197}
1198
79501333
GR		 1199static void w83781d_remove_files(struct device *dev)
1200{
1201 sysfs_remove_group(&dev->kobj, &w83781d_group);
1202 sysfs_remove_group(&dev->kobj, &w83781d_group_in1);
1203 sysfs_remove_group(&dev->kobj, &w83781d_group_in78);
1204 sysfs_remove_group(&dev->kobj, &w83781d_group_temp3);
1205 sysfs_remove_group(&dev->kobj, &w83781d_group_pwm12);
1206 sysfs_remove_group(&dev->kobj, &w83781d_group_pwm34);
1207 sysfs_remove_group(&dev->kobj, &w83781d_group_other);
1208}
1209
0217eae3
WG		 1210static int
1211w83781d_probe(struct i2c_client *client, const struct i2c_device_id *id)
1212{
1213 struct device *dev = &client->dev;
1214 struct w83781d_data *data;
1215 int err;
1216
144d2b99
GR		 1217 data = devm_kzalloc(dev, sizeof(struct w83781d_data), GFP_KERNEL);
1218 if (!data)
1219 return -ENOMEM;
0217eae3
WG		 1220
1221 i2c_set_clientdata(client, data);
1222 mutex_init(&data->lock);
1223 mutex_init(&data->update_lock);
1da177e4 1224
0217eae3
WG		 1225 data->type = id->driver_data;
1226 data->client = client;
1da177e4
LT		 1227
1228 /* attach secondary i2c lm75-like clients */
0217eae3
WG		 1229 err = w83781d_detect_subclients(client);
1230 if (err)
144d2b99 1231 return err;
1da177e4
LT		 1232
1233 /* Initialize the chip */
7666c13c 1234 w83781d_init_device(dev);
1da177e4
LT		 1235
1236 /* Register sysfs hooks */
0217eae3 1237 err = w83781d_create_files(dev, data->type, 0);
7666c13c 1238 if (err)
144d2b99 1239 goto exit_remove_files;
943b0830 1240
1beeffe4
TJ		 1241 data->hwmon_dev = hwmon_device_register(dev);
1242 if (IS_ERR(data->hwmon_dev)) {
1243 err = PTR_ERR(data->hwmon_dev);
144d2b99 1244 goto exit_remove_files;
1da177e4
LT		 1245 }
1246
1247 return 0;
1248
144d2b99 1249 exit_remove_files:
79501333 1250 w83781d_remove_files(dev);
0217eae3
WG		 1251 if (data->lm75[0])
1252 i2c_unregister_device(data->lm75[0]);
1253 if (data->lm75[1])
1254 i2c_unregister_device(data->lm75[1]);
1da177e4
LT		 1255 return err;
1256}
1257
1258static int
0217eae3 1259w83781d_remove(struct i2c_client *client)
1da177e4 1260{
943b0830 1261 struct w83781d_data *data = i2c_get_clientdata(client);
0217eae3 1262 struct device *dev = &client->dev;
1da177e4 1263
0217eae3 1264 hwmon_device_unregister(data->hwmon_dev);
79501333 1265 w83781d_remove_files(dev);
1da177e4 1266
0217eae3
WG		 1267 if (data->lm75[0])
1268 i2c_unregister_device(data->lm75[0]);
1269 if (data->lm75[1])
1270 i2c_unregister_device(data->lm75[1]);
943b0830 1271
1da177e4
LT		 1272 return 0;
1273}
1274
1da177e4 1275static int
443850ce 1276w83781d_read_value_i2c(struct w83781d_data *data, u16 reg)
1da177e4 1277{
0217eae3 1278 struct i2c_client *client = data->client;
443850ce 1279 int res, bank;
1da177e4
LT		 1280 struct i2c_client *cl;
1281
443850ce
WG		 1282 bank = (reg >> 8) & 0x0f;
1283 if (bank > 2)
1284 /* switch banks */
1285 i2c_smbus_write_byte_data(client, W83781D_REG_BANK,
1286 bank);
1287 if (bank == 0 || bank > 2) {
1288 res = i2c_smbus_read_byte_data(client, reg & 0xff);
1da177e4 1289 } else {
443850ce
WG		 1290 /* switch to subclient */
1291 cl = data->lm75[bank - 1];
1292 /* convert from ISA to LM75 I2C addresses */
1293 switch (reg & 0xff) {
1294 case 0x50: /* TEMP */
90f4102c 1295 res = i2c_smbus_read_word_swapped(cl, 0);
443850ce
WG		 1296 break;
1297 case 0x52: /* CONFIG */
1298 res = i2c_smbus_read_byte_data(cl, 1);
1299 break;
1300 case 0x53: /* HYST */
90f4102c 1301 res = i2c_smbus_read_word_swapped(cl, 2);
443850ce
WG		 1302 break;
1303 case 0x55: /* OVER */
1304 default:
90f4102c 1305 res = i2c_smbus_read_word_swapped(cl, 3);
443850ce 1306 break;
1da177e4 1307 }
1da177e4 1308 }
443850ce
WG		 1309 if (bank > 2)
1310 i2c_smbus_write_byte_data(client, W83781D_REG_BANK, 0);
1311
1da177e4
LT		 1312 return res;
1313}
1314
1315static int
443850ce 1316w83781d_write_value_i2c(struct w83781d_data *data, u16 reg, u16 value)
1da177e4 1317{
0217eae3 1318 struct i2c_client *client = data->client;
443850ce 1319 int bank;
1da177e4
LT		 1320 struct i2c_client *cl;
1321
443850ce
WG		 1322 bank = (reg >> 8) & 0x0f;
1323 if (bank > 2)
1324 /* switch banks */
1325 i2c_smbus_write_byte_data(client, W83781D_REG_BANK,
1326 bank);
1327 if (bank == 0 || bank > 2) {
1328 i2c_smbus_write_byte_data(client, reg & 0xff,
1329 value & 0xff);
1da177e4 1330 } else {
443850ce
WG		 1331 /* switch to subclient */
1332 cl = data->lm75[bank - 1];
1333 /* convert from ISA to LM75 I2C addresses */
1334 switch (reg & 0xff) {
1335 case 0x52: /* CONFIG */
1336 i2c_smbus_write_byte_data(cl, 1, value & 0xff);
1337 break;
1338 case 0x53: /* HYST */
90f4102c 1339 i2c_smbus_write_word_swapped(cl, 2, value);
443850ce
WG		 1340 break;
1341 case 0x55: /* OVER */
90f4102c 1342 i2c_smbus_write_word_swapped(cl, 3, value);
443850ce 1343 break;
1da177e4 1344 }
1da177e4 1345 }
443850ce
WG		 1346 if (bank > 2)
1347 i2c_smbus_write_byte_data(client, W83781D_REG_BANK, 0);
1348
1da177e4
LT		 1349 return 0;
1350}
1351
1da177e4 1352static void
7666c13c 1353w83781d_init_device(struct device *dev)
1da177e4 1354{
7666c13c 1355 struct w83781d_data *data = dev_get_drvdata(dev);
1da177e4
LT		 1356 int i, p;
1357 int type = data->type;
1358 u8 tmp;
1359
aff6e00e
GR		 1360 if (reset && type != as99127f) { /*
1361 * this resets registers we don't have
1362 * documentation for on the as99127f
1363 */
1364 /*
1365 * Resetting the chip has been the default for a long time,
1366 * but it causes the BIOS initializations (fan clock dividers,
1367 * thermal sensor types...) to be lost, so it is now optional.
1368 * It might even go away if nobody reports it as being useful,
1369 * as I see very little reason why this would be needed at
1370 * all.
1371 */
b55f3757
GR		 1372 dev_info(dev,
1373 "If reset=1 solved a problem you were having, please report!\n");
fabddcd4 1374
1da177e4 1375 /* save these registers */
31b8dc4d
JD		 1376 i = w83781d_read_value(data, W83781D_REG_BEEP_CONFIG);
1377 p = w83781d_read_value(data, W83781D_REG_PWMCLK12);
aff6e00e
GR		 1378 /*
1379 * Reset all except Watchdog values and last conversion values
1380 * This sets fan-divs to 2, among others
1381 */
31b8dc4d 1382 w83781d_write_value(data, W83781D_REG_CONFIG, 0x80);
aff6e00e
GR		 1383 /*
1384 * Restore the registers and disable power-on abnormal beep.
1385 * This saves FAN 1/2/3 input/output values set by BIOS.
1386 */
31b8dc4d
JD		 1387 w83781d_write_value(data, W83781D_REG_BEEP_CONFIG, i | 0x80);
1388 w83781d_write_value(data, W83781D_REG_PWMCLK12, p);
c531eb3f
GR		 1389 /*
1390 * Disable master beep-enable (reset turns it on).
1391 * Individual beep_mask should be reset to off but for some
1392 * reason disabling this bit helps some people not get beeped
1393 */
31b8dc4d 1394 w83781d_write_value(data, W83781D_REG_BEEP_INTS2, 0);
1da177e4
LT		 1395 }
1396
aff6e00e
GR		 1397 /*
1398 * Disable power-on abnormal beep, as advised by the datasheet.
1399 * Already done if reset=1.
1400 */
fabddcd4 1401 if (init && !reset && type != as99127f) {
31b8dc4d
JD		 1402 i = w83781d_read_value(data, W83781D_REG_BEEP_CONFIG);
1403 w83781d_write_value(data, W83781D_REG_BEEP_CONFIG, i | 0x80);
fabddcd4
JD		 1404 }
1405
303760b4 1406 data->vrm = vid_which_vrm();
1da177e4
LT		 1407
1408 if ((type != w83781d) && (type != as99127f)) {
31b8dc4d 1409 tmp = w83781d_read_value(data, W83781D_REG_SCFG1);
1da177e4
LT		 1410 for (i = 1; i <= 3; i++) {
1411 if (!(tmp & BIT_SCFG1[i - 1])) {
b26f9330 1412 data->sens[i - 1] = 4;
1da177e4
LT		 1413 } else {
1414 if (w83781d_read_value
31b8dc4d 1415 (data,
1da177e4
LT		 1416 W83781D_REG_SCFG2) & BIT_SCFG2[i - 1])
1417 data->sens[i - 1] = 1;
1418 else
1419 data->sens[i - 1] = 2;
1420 }
7c7a5304 1421 if (type == w83783s && i == 2)
1da177e4
LT		 1422 break;
1423 }
1424 }
1425
1426 if (init && type != as99127f) {
1427 /* Enable temp2 */
31b8dc4d 1428 tmp = w83781d_read_value(data, W83781D_REG_TEMP2_CONFIG);
1da177e4 1429 if (tmp & 0x01) {
b55f3757
GR		 1430 dev_warn(dev,
1431 "Enabling temp2, readings might not make sense\n");
31b8dc4d 1432 w83781d_write_value(data, W83781D_REG_TEMP2_CONFIG,
1da177e4
LT		 1433 tmp & 0xfe);
1434 }
1435
1436 /* Enable temp3 */
7c7a5304 1437 if (type != w83783s) {
31b8dc4d 1438 tmp = w83781d_read_value(data,
1da177e4
LT		 1439 W83781D_REG_TEMP3_CONFIG);
1440 if (tmp & 0x01) {
b55f3757
GR		 1441 dev_warn(dev,
1442 "Enabling temp3, readings might not make sense\n");
31b8dc4d 1443 w83781d_write_value(data,
1da177e4
LT		 1444 W83781D_REG_TEMP3_CONFIG, tmp & 0xfe);
1445 }
1446 }
1da177e4
LT		 1447 }
1448
1449 /* Start monitoring */
31b8dc4d
JD		 1450 w83781d_write_value(data, W83781D_REG_CONFIG,
1451 (w83781d_read_value(data,
1da177e4
LT		 1452 W83781D_REG_CONFIG) & 0xf7)
1453 | 0x01);
7666c13c
JD		 1454
1455 /* A few vars need to be filled upon startup */
34875337
JD		 1456 for (i = 0; i < 3; i++) {
1457 data->fan_min[i] = w83781d_read_value(data,
7666c13c
JD		 1458 W83781D_REG_FAN_MIN(i));
1459 }
7666c13c
JD		 1460
1461 mutex_init(&data->update_lock);
1da177e4
LT		 1462}
1463
1464static struct w83781d_data *w83781d_update_device(struct device *dev)
1465{
7666c13c 1466 struct w83781d_data *data = dev_get_drvdata(dev);
0217eae3 1467 struct i2c_client *client = data->client;
1da177e4
LT		 1468 int i;
1469
9a61bf63 1470 mutex_lock(&data->update_lock);
1da177e4
LT		 1471
1472 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
1473 || !data->valid) {
1474 dev_dbg(dev, "Starting device update\n");
1475
1476 for (i = 0; i <= 8; i++) {
7c7a5304 1477 if (data->type == w83783s && i == 1)
1da177e4
LT		 1478 continue; /* 783S has no in1 */
1479 data->in[i] =
31b8dc4d 1480 w83781d_read_value(data, W83781D_REG_IN(i));
1da177e4 1481 data->in_min[i] =
31b8dc4d 1482 w83781d_read_value(data, W83781D_REG_IN_MIN(i));
1da177e4 1483 data->in_max[i] =
31b8dc4d 1484 w83781d_read_value(data, W83781D_REG_IN_MAX(i));
05663368 1485 if ((data->type != w83782d) && (i == 6))
1da177e4
LT		 1486 break;
1487 }
34875337
JD		 1488 for (i = 0; i < 3; i++) {
1489 data->fan[i] =
31b8dc4d 1490 w83781d_read_value(data, W83781D_REG_FAN(i));
34875337 1491 data->fan_min[i] =
31b8dc4d 1492 w83781d_read_value(data, W83781D_REG_FAN_MIN(i));
1da177e4
LT		 1493 }
1494 if (data->type != w83781d && data->type != as99127f) {
34875337
JD		 1495 for (i = 0; i < 4; i++) {
1496 data->pwm[i] =
31b8dc4d 1497 w83781d_read_value(data,
34875337 1498 W83781D_REG_PWM[i]);
848ddf11
JD		 1499 /* Only W83782D on SMBus has PWM3 and PWM4 */
1500 if ((data->type != w83782d || !client)
34875337 1501 && i == 1)
1da177e4
LT		 1502 break;
1503 }
1504 /* Only PWM2 can be disabled */
34875337 1505 data->pwm2_enable = (w83781d_read_value(data,
c531eb3f 1506 W83781D_REG_PWMCLK12) & 0x08) >> 3;
1da177e4
LT		 1507 }
1508
31b8dc4d 1509 data->temp = w83781d_read_value(data, W83781D_REG_TEMP(1));
1da177e4 1510 data->temp_max =
31b8dc4d 1511 w83781d_read_value(data, W83781D_REG_TEMP_OVER(1));
1da177e4 1512 data->temp_max_hyst =
31b8dc4d 1513 w83781d_read_value(data, W83781D_REG_TEMP_HYST(1));
1da177e4 1514 data->temp_add[0] =
31b8dc4d 1515 w83781d_read_value(data, W83781D_REG_TEMP(2));
1da177e4 1516 data->temp_max_add[0] =
31b8dc4d 1517 w83781d_read_value(data, W83781D_REG_TEMP_OVER(2));
1da177e4 1518 data->temp_max_hyst_add[0] =
31b8dc4d 1519 w83781d_read_value(data, W83781D_REG_TEMP_HYST(2));
7c7a5304 1520 if (data->type != w83783s) {
1da177e4 1521 data->temp_add[1] =
31b8dc4d 1522 w83781d_read_value(data, W83781D_REG_TEMP(3));
1da177e4 1523 data->temp_max_add[1] =
31b8dc4d 1524 w83781d_read_value(data,
1da177e4
LT		 1525 W83781D_REG_TEMP_OVER(3));
1526 data->temp_max_hyst_add[1] =
31b8dc4d 1527 w83781d_read_value(data,
1da177e4
LT		 1528 W83781D_REG_TEMP_HYST(3));
1529 }
31b8dc4d 1530 i = w83781d_read_value(data, W83781D_REG_VID_FANDIV);
7c7a5304 1531 data->vid = i & 0x0f;
31b8dc4d 1532 data->vid |= (w83781d_read_value(data,
7c7a5304 1533 W83781D_REG_CHIPID) & 0x01) << 4;
1da177e4
LT		 1534 data->fan_div[0] = (i >> 4) & 0x03;
1535 data->fan_div[1] = (i >> 6) & 0x03;
31b8dc4d 1536 data->fan_div[2] = (w83781d_read_value(data,
7c7a5304 1537 W83781D_REG_PIN) >> 6) & 0x03;
1da177e4 1538 if ((data->type != w83781d) && (data->type != as99127f)) {
31b8dc4d 1539 i = w83781d_read_value(data, W83781D_REG_VBAT);
1da177e4
LT		 1540 data->fan_div[0] |= (i >> 3) & 0x04;
1541 data->fan_div[1] |= (i >> 4) & 0x04;
7c7a5304 1542 data->fan_div[2] |= (i >> 5) & 0x04;
1da177e4 1543 }
05663368 1544 if (data->type == w83782d) {
31b8dc4d 1545 data->alarms = w83781d_read_value(data,
c7f5d7ed 1546 W83782D_REG_ALARM1)
31b8dc4d 1547 | (w83781d_read_value(data,
c7f5d7ed 1548 W83782D_REG_ALARM2) << 8)
31b8dc4d 1549 | (w83781d_read_value(data,
c7f5d7ed
JD		 1550 W83782D_REG_ALARM3) << 16);
1551 } else if (data->type == w83783s) {
31b8dc4d 1552 data->alarms = w83781d_read_value(data,
c7f5d7ed 1553 W83782D_REG_ALARM1)
31b8dc4d 1554 | (w83781d_read_value(data,
c7f5d7ed
JD		 1555 W83782D_REG_ALARM2) << 8);
1556 } else {
aff6e00e
GR		 1557 /*
1558 * No real-time status registers, fall back to
1559 * interrupt status registers
1560 */
31b8dc4d 1561 data->alarms = w83781d_read_value(data,
c7f5d7ed 1562 W83781D_REG_ALARM1)
31b8dc4d 1563 | (w83781d_read_value(data,
c7f5d7ed 1564 W83781D_REG_ALARM2) << 8);
1da177e4 1565 }
31b8dc4d 1566 i = w83781d_read_value(data, W83781D_REG_BEEP_INTS2);
2fbbbf14 1567 data->beep_mask = (i << 8) +
31b8dc4d 1568 w83781d_read_value(data, W83781D_REG_BEEP_INTS1);
1da177e4
LT		 1569 if ((data->type != w83781d) && (data->type != as99127f)) {
1570 data->beep_mask |=
31b8dc4d 1571 w83781d_read_value(data,
1da177e4
LT		 1572 W83781D_REG_BEEP_INTS3) << 16;
1573 }
1574 data->last_updated = jiffies;
1575 data->valid = 1;
1576 }
1577
9a61bf63 1578 mutex_unlock(&data->update_lock);
1da177e4
LT		 1579
1580 return data;
1581}
1582
0217eae3
WG		 1583static const struct i2c_device_id w83781d_ids[] = {
1584 { "w83781d", w83781d, },
1585 { "w83782d", w83782d, },
1586 { "w83783s", w83783s, },
1587 { "as99127f", as99127f },
1588 { /* LIST END */ }
1589};
1590MODULE_DEVICE_TABLE(i2c, w83781d_ids);
1591
1592static struct i2c_driver w83781d_driver = {
1593 .class = I2C_CLASS_HWMON,
1594 .driver = {
1595 .name = "w83781d",
1596 },
1597 .probe = w83781d_probe,
1598 .remove = w83781d_remove,
1599 .id_table = w83781d_ids,
1600 .detect = w83781d_detect,
c3813d6a 1601 .address_list = normal_i2c,
0217eae3
WG		 1602};
1603
1604/*
1605 * ISA related code
1606 */
443850ce
WG		 1607#ifdef CONFIG_ISA
1608
1609/* ISA device, if found */
1610static struct platform_device *pdev;
1611
1612static unsigned short isa_address = 0x290;
1613
aff6e00e
GR		 1614/*
1615 * I2C devices get this name attribute automatically, but for ISA devices
1616 * we must create it by ourselves.
1617 */
443850ce
WG		 1618static ssize_t
1619show_name(struct device *dev, struct device_attribute *devattr, char *buf)
1620{
1621 struct w83781d_data *data = dev_get_drvdata(dev);
360782dd 1622 return sprintf(buf, "%s\n", data->name);
443850ce
WG		 1623}
1624static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
1625
1626static struct w83781d_data *w83781d_data_if_isa(void)
1627{
1628 return pdev ? platform_get_drvdata(pdev) : NULL;
1629}
1630
1631/* Returns 1 if the I2C chip appears to be an alias of the ISA chip */
1632static int w83781d_alias_detect(struct i2c_client *client, u8 chipid)
1633{
0217eae3 1634 struct w83781d_data *isa;
443850ce
WG		 1635 int i;
1636
1637 if (!pdev) /* No ISA chip */
1638 return 0;
1639
443850ce
WG		 1640 isa = platform_get_drvdata(pdev);
1641
1642 if (w83781d_read_value(isa, W83781D_REG_I2C_ADDR) != client->addr)
1643 return 0; /* Address doesn't match */
1644 if (w83781d_read_value(isa, W83781D_REG_WCHIPID) != chipid)
1645 return 0; /* Chip type doesn't match */
1646
aff6e00e
GR		 1647 /*
1648 * We compare all the limit registers, the config register and the
1649 * interrupt mask registers
1650 */
443850ce 1651 for (i = 0x2b; i <= 0x3d; i++) {
0217eae3
WG		 1652 if (w83781d_read_value(isa, i) !=
1653 i2c_smbus_read_byte_data(client, i))
443850ce
WG		 1654 return 0;
1655 }
1656 if (w83781d_read_value(isa, W83781D_REG_CONFIG) !=
0217eae3 1657 i2c_smbus_read_byte_data(client, W83781D_REG_CONFIG))
443850ce
WG		 1658 return 0;
1659 for (i = 0x43; i <= 0x46; i++) {
0217eae3
WG		 1660 if (w83781d_read_value(isa, i) !=
1661 i2c_smbus_read_byte_data(client, i))
443850ce
WG		 1662 return 0;
1663 }
1664
1665 return 1;
1666}
1667
1668static int
1669w83781d_read_value_isa(struct w83781d_data *data, u16 reg)
1670{
443850ce
WG		 1671 int word_sized, res;
1672
1673 word_sized = (((reg & 0xff00) == 0x100)
1674 || ((reg & 0xff00) == 0x200))
1675 && (((reg & 0x00ff) == 0x50)
1676 || ((reg & 0x00ff) == 0x53)
1677 || ((reg & 0x00ff) == 0x55));
1678 if (reg & 0xff00) {
1679 outb_p(W83781D_REG_BANK,
360782dd 1680 data->isa_addr + W83781D_ADDR_REG_OFFSET);
443850ce 1681 outb_p(reg >> 8,
360782dd 1682 data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce 1683 }
360782dd
JD		 1684 outb_p(reg & 0xff, data->isa_addr + W83781D_ADDR_REG_OFFSET);
1685 res = inb_p(data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce
WG		 1686 if (word_sized) {
1687 outb_p((reg & 0xff) + 1,
360782dd 1688 data->isa_addr + W83781D_ADDR_REG_OFFSET);
443850ce 1689 res =
360782dd 1690 (res << 8) + inb_p(data->isa_addr +
443850ce
WG		 1691 W83781D_DATA_REG_OFFSET);
1692 }
1693 if (reg & 0xff00) {
1694 outb_p(W83781D_REG_BANK,
360782dd
JD		 1695 data->isa_addr + W83781D_ADDR_REG_OFFSET);
1696 outb_p(0, data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce
WG		 1697 }
1698 return res;
1699}
1700
1701static void
1702w83781d_write_value_isa(struct w83781d_data *data, u16 reg, u16 value)
1703{
443850ce
WG		 1704 int word_sized;
1705
1706 word_sized = (((reg & 0xff00) == 0x100)
1707 || ((reg & 0xff00) == 0x200))
1708 && (((reg & 0x00ff) == 0x53)
1709 || ((reg & 0x00ff) == 0x55));
1710 if (reg & 0xff00) {
1711 outb_p(W83781D_REG_BANK,
360782dd 1712 data->isa_addr + W83781D_ADDR_REG_OFFSET);
443850ce 1713 outb_p(reg >> 8,
360782dd 1714 data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce 1715 }
360782dd 1716 outb_p(reg & 0xff, data->isa_addr + W83781D_ADDR_REG_OFFSET);
443850ce
WG		 1717 if (word_sized) {
1718 outb_p(value >> 8,
360782dd 1719 data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce 1720 outb_p((reg & 0xff) + 1,
360782dd 1721 data->isa_addr + W83781D_ADDR_REG_OFFSET);
443850ce 1722 }
360782dd 1723 outb_p(value & 0xff, data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce
WG		 1724 if (reg & 0xff00) {
1725 outb_p(W83781D_REG_BANK,
360782dd
JD		 1726 data->isa_addr + W83781D_ADDR_REG_OFFSET);
1727 outb_p(0, data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce
WG		 1728 }
1729}
1730
aff6e00e
GR		 1731/*
1732 * The SMBus locks itself, usually, but nothing may access the Winbond between
1733 * bank switches. ISA access must always be locked explicitly!
1734 * We ignore the W83781D BUSY flag at this moment - it could lead to deadlocks,
1735 * would slow down the W83781D access and should not be necessary.
1736 * There are some ugly typecasts here, but the good news is - they should
1737 * nowhere else be necessary!
1738 */
443850ce
WG		 1739static int
1740w83781d_read_value(struct w83781d_data *data, u16 reg)
1741{
0217eae3 1742 struct i2c_client *client = data->client;
443850ce
WG		 1743 int res;
1744
1745 mutex_lock(&data->lock);
0217eae3 1746 if (client)
443850ce
WG		 1747 res = w83781d_read_value_i2c(data, reg);
1748 else
1749 res = w83781d_read_value_isa(data, reg);
1750 mutex_unlock(&data->lock);
1751 return res;
1752}
1753
1754static int
1755w83781d_write_value(struct w83781d_data *data, u16 reg, u16 value)
1756{
0217eae3 1757 struct i2c_client *client = data->client;
443850ce
WG		 1758
1759 mutex_lock(&data->lock);
0217eae3 1760 if (client)
443850ce
WG		 1761 w83781d_write_value_i2c(data, reg, value);
1762 else
1763 w83781d_write_value_isa(data, reg, value);
1764 mutex_unlock(&data->lock);
1765 return 0;
1766}
1767
6c931ae1 1768static int
443850ce
WG		 1769w83781d_isa_probe(struct platform_device *pdev)
1770{
1771 int err, reg;
1772 struct w83781d_data *data;
1773 struct resource *res;
443850ce
WG		 1774
1775 /* Reserve the ISA region */
1776 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
144d2b99
GR		 1777 if (!devm_request_region(&pdev->dev,
1778 res->start + W83781D_ADDR_REG_OFFSET, 2,
1779 "w83781d"))
1780 return -EBUSY;
1781
1782 data = devm_kzalloc(&pdev->dev, sizeof(struct w83781d_data),
1783 GFP_KERNEL);
1784 if (!data)
1785 return -ENOMEM;
443850ce 1786
443850ce 1787 mutex_init(&data->lock);
360782dd 1788 data->isa_addr = res->start;
443850ce
WG		 1789 platform_set_drvdata(pdev, data);
1790
1791 reg = w83781d_read_value(data, W83781D_REG_WCHIPID);
1792 switch (reg) {
1793 case 0x30:
1794 data->type = w83782d;
360782dd 1795 data->name = "w83782d";
443850ce
WG		 1796 break;
1797 default:
1798 data->type = w83781d;
360782dd 1799 data->name = "w83781d";
443850ce 1800 }
443850ce
WG		 1801
1802 /* Initialize the W83781D chip */
1803 w83781d_init_device(&pdev->dev);
1804
1805 /* Register sysfs hooks */
1806 err = w83781d_create_files(&pdev->dev, data->type, 1);
1807 if (err)
1808 goto exit_remove_files;
1809
1810 err = device_create_file(&pdev->dev, &dev_attr_name);
1811 if (err)
1812 goto exit_remove_files;
1813
1814 data->hwmon_dev = hwmon_device_register(&pdev->dev);
1815 if (IS_ERR(data->hwmon_dev)) {
1816 err = PTR_ERR(data->hwmon_dev);
1817 goto exit_remove_files;
1818 }
1819
1820 return 0;
1821
1822 exit_remove_files:
79501333 1823 w83781d_remove_files(&pdev->dev);
443850ce 1824 device_remove_file(&pdev->dev, &dev_attr_name);
443850ce
WG		 1825 return err;
1826}
1827
281dfd0b 1828static int
443850ce
WG		 1829w83781d_isa_remove(struct platform_device *pdev)
1830{
1831 struct w83781d_data *data = platform_get_drvdata(pdev);
1832
1833 hwmon_device_unregister(data->hwmon_dev);
79501333 1834 w83781d_remove_files(&pdev->dev);
443850ce 1835 device_remove_file(&pdev->dev, &dev_attr_name);
443850ce
WG		 1836
1837 return 0;
1838}
1839
1840static struct platform_driver w83781d_isa_driver = {
1841 .driver = {
1842 .owner = THIS_MODULE,
1843 .name = "w83781d",
1844 },
1845 .probe = w83781d_isa_probe,
9e5e9b7a 1846 .remove = w83781d_isa_remove,
443850ce
WG		 1847};
1848
7666c13c
JD		 1849/* return 1 if a supported chip is found, 0 otherwise */
1850static int __init
1851w83781d_isa_found(unsigned short address)
1852{
1853 int val, save, found = 0;
b0bcdd3c
JD		 1854 int port;
1855
aff6e00e
GR		 1856 /*
1857 * Some boards declare base+0 to base+7 as a PNP device, some base+4
b0bcdd3c 1858 * to base+7 and some base+5 to base+6. So we better request each port
aff6e00e
GR		 1859 * individually for the probing phase.
1860 */
b0bcdd3c
JD		 1861 for (port = address; port < address + W83781D_EXTENT; port++) {
1862 if (!request_region(port, 1, "w83781d")) {
1ca28218 1863 pr_debug("Failed to request port 0x%x\n", port);
b0bcdd3c
JD		 1864 goto release;
1865 }
2961cb22 1866 }
7666c13c
JD		 1867
1868#define REALLY_SLOW_IO
aff6e00e
GR		 1869 /*
1870 * We need the timeouts for at least some W83781D-like
1871 * chips. But only if we read 'undefined' registers.
1872 */
7666c13c
JD		 1873 val = inb_p(address + 1);
1874 if (inb_p(address + 2) != val
1875 || inb_p(address + 3) != val
1876 || inb_p(address + 7) != val) {
1ca28218 1877 pr_debug("Detection failed at step %d\n", 1);
7666c13c
JD		 1878 goto release;
1879 }
1880#undef REALLY_SLOW_IO
1881
aff6e00e
GR		 1882 /*
1883 * We should be able to change the 7 LSB of the address port. The
1884 * MSB (busy flag) should be clear initially, set after the write.
1885 */
7666c13c
JD		 1886 save = inb_p(address + W83781D_ADDR_REG_OFFSET);
1887 if (save & 0x80) {
1ca28218 1888 pr_debug("Detection failed at step %d\n", 2);
7666c13c
JD		 1889 goto release;
1890 }
1891 val = ~save & 0x7f;
1892 outb_p(val, address + W83781D_ADDR_REG_OFFSET);
1893 if (inb_p(address + W83781D_ADDR_REG_OFFSET) != (val | 0x80)) {
1894 outb_p(save, address + W83781D_ADDR_REG_OFFSET);
1ca28218 1895 pr_debug("Detection failed at step %d\n", 3);
7666c13c
JD		 1896 goto release;
1897 }
1898
1899 /* We found a device, now see if it could be a W83781D */
1900 outb_p(W83781D_REG_CONFIG, address + W83781D_ADDR_REG_OFFSET);
1901 val = inb_p(address + W83781D_DATA_REG_OFFSET);
1902 if (val & 0x80) {
1ca28218 1903 pr_debug("Detection failed at step %d\n", 4);
7666c13c
JD		 1904 goto release;
1905 }
1906 outb_p(W83781D_REG_BANK, address + W83781D_ADDR_REG_OFFSET);
1907 save = inb_p(address + W83781D_DATA_REG_OFFSET);
1908 outb_p(W83781D_REG_CHIPMAN, address + W83781D_ADDR_REG_OFFSET);
1909 val = inb_p(address + W83781D_DATA_REG_OFFSET);
1910 if ((!(save & 0x80) && (val != 0xa3))
1911 || ((save & 0x80) && (val != 0x5c))) {
1ca28218 1912 pr_debug("Detection failed at step %d\n", 5);
7666c13c
JD		 1913 goto release;
1914 }
1915 outb_p(W83781D_REG_I2C_ADDR, address + W83781D_ADDR_REG_OFFSET);
1916 val = inb_p(address + W83781D_DATA_REG_OFFSET);
1917 if (val < 0x03 || val > 0x77) { /* Not a valid I2C address */
1ca28218 1918 pr_debug("Detection failed at step %d\n", 6);
7666c13c
JD		 1919 goto release;
1920 }
1921
1922 /* The busy flag should be clear again */
1923 if (inb_p(address + W83781D_ADDR_REG_OFFSET) & 0x80) {
1ca28218 1924 pr_debug("Detection failed at step %d\n", 7);
7666c13c
JD		 1925 goto release;
1926 }
1927
1928 /* Determine the chip type */
1929 outb_p(W83781D_REG_BANK, address + W83781D_ADDR_REG_OFFSET);
1930 save = inb_p(address + W83781D_DATA_REG_OFFSET);
1931 outb_p(save & 0xf8, address + W83781D_DATA_REG_OFFSET);
1932 outb_p(W83781D_REG_WCHIPID, address + W83781D_ADDR_REG_OFFSET);
1933 val = inb_p(address + W83781D_DATA_REG_OFFSET);
1934 if ((val & 0xfe) == 0x10 /* W83781D */
05663368 1935 || val == 0x30) /* W83782D */
7666c13c
JD		 1936 found = 1;
1937
1938 if (found)
1ca28218 1939 pr_info("Found a %s chip at %#x\n",
7666c13c
JD		 1940 val == 0x30 ? "W83782D" : "W83781D", (int)address);
1941
1942 release:
b0bcdd3c
JD		 1943 for (port--; port >= address; port--)
1944 release_region(port, 1);
7666c13c
JD		 1945 return found;
1946}
1947
1948static int __init
1949w83781d_isa_device_add(unsigned short address)
1950{
1951 struct resource res = {
1952 .start = address,
15bde2f1 1953 .end = address + W83781D_EXTENT - 1,
7666c13c
JD		 1954 .name = "w83781d",
1955 .flags = IORESOURCE_IO,
1956 };
1957 int err;
1958
1959 pdev = platform_device_alloc("w83781d", address);
1960 if (!pdev) {
1961 err = -ENOMEM;
1ca28218 1962 pr_err("Device allocation failed\n");
7666c13c
JD		 1963 goto exit;
1964 }
1965
1966 err = platform_device_add_resources(pdev, &res, 1);
1967 if (err) {
1ca28218 1968 pr_err("Device resource addition failed (%d)\n", err);
7666c13c
JD		 1969 goto exit_device_put;
1970 }
1971
1972 err = platform_device_add(pdev);
1973 if (err) {
1ca28218 1974 pr_err("Device addition failed (%d)\n", err);
7666c13c
JD		 1975 goto exit_device_put;
1976 }
1977
1978 return 0;
1979
1980 exit_device_put:
1981 platform_device_put(pdev);
1982 exit:
1983 pdev = NULL;
1984 return err;
1985}
1986
1da177e4 1987static int __init
443850ce 1988w83781d_isa_register(void)
1da177e4 1989{
fde09509
JD		 1990 int res;
1991
7666c13c
JD		 1992 if (w83781d_isa_found(isa_address)) {
1993 res = platform_driver_register(&w83781d_isa_driver);
1994 if (res)
c6566206 1995 goto exit;
fde09509 1996
7666c13c
JD		 1997 /* Sets global pdev as a side effect */
1998 res = w83781d_isa_device_add(isa_address);
1999 if (res)
2000 goto exit_unreg_isa_driver;
2001 }
fde09509
JD		 2002
2003 return 0;
7666c13c 2004
443850ce 2005exit_unreg_isa_driver:
7666c13c 2006 platform_driver_unregister(&w83781d_isa_driver);
443850ce 2007exit:
7666c13c 2008 return res;
1da177e4
LT		 2009}
2010
dd56b638 2011static void
443850ce 2012w83781d_isa_unregister(void)
1da177e4 2013{
7666c13c
JD		 2014 if (pdev) {
2015 platform_device_unregister(pdev);
2016 platform_driver_unregister(&w83781d_isa_driver);
2017 }
443850ce
WG		 2018}
2019#else /* !CONFIG_ISA */
2020
2021static struct w83781d_data *w83781d_data_if_isa(void)
2022{
2023 return NULL;
2024}
2025
2026static int
2027w83781d_alias_detect(struct i2c_client *client, u8 chipid)
2028{
2029 return 0;
2030}
2031
2032static int
2033w83781d_read_value(struct w83781d_data *data, u16 reg)
2034{
2035 int res;
2036
2037 mutex_lock(&data->lock);
2038 res = w83781d_read_value_i2c(data, reg);
2039 mutex_unlock(&data->lock);
2040
2041 return res;
2042}
2043
2044static int
2045w83781d_write_value(struct w83781d_data *data, u16 reg, u16 value)
2046{
2047 mutex_lock(&data->lock);
2048 w83781d_write_value_i2c(data, reg, value);
2049 mutex_unlock(&data->lock);
2050
2051 return 0;
2052}
2053
2054static int __init
2055w83781d_isa_register(void)
2056{
2057 return 0;
2058}
2059
dd56b638 2060static void
443850ce
WG		 2061w83781d_isa_unregister(void)
2062{
2063}
2064#endif /* CONFIG_ISA */
2065
2066static int __init
2067sensors_w83781d_init(void)
2068{
2069 int res;
2070
aff6e00e
GR		 2071 /*
2072 * We register the ISA device first, so that we can skip the
2073 * registration of an I2C interface to the same device.
2074 */
443850ce
WG		 2075 res = w83781d_isa_register();
2076 if (res)
2077 goto exit;
2078
2079 res = i2c_add_driver(&w83781d_driver);
2080 if (res)
2081 goto exit_unreg_isa;
2082
2083 return 0;
2084
2085 exit_unreg_isa:
2086 w83781d_isa_unregister();
2087 exit:
2088 return res;
2089}
2090
2091static void __exit
2092sensors_w83781d_exit(void)
2093{
2094 w83781d_isa_unregister();
1da177e4
LT		 2095 i2c_del_driver(&w83781d_driver);
2096}
2097
2098MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>, "
2099 "Philip Edelbrock <phil@netroedge.com>, "
2100 "and Mark Studebaker <mdsxyz123@yahoo.com>");
2101MODULE_DESCRIPTION("W83781D driver");
2102MODULE_LICENSE("GPL");
2103
2104module_init(sensors_w83781d_init);
2105module_exit(sensors_w83781d_exit);
Linux kernel - Deliverables
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