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fdfc0d8a PP |
1 | /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. |
2 | * | |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License version 2 and | |
5 | * only version 2 as published by the Free Software Foundation. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/types.h> | |
17 | #include <linux/device.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/fs.h> | |
21 | #include <linux/miscdevice.h> | |
22 | #include <linux/uaccess.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/spinlock.h> | |
1b19f59d | 25 | #include <linux/pm_runtime.h> |
fdfc0d8a PP |
26 | #include <linux/seq_file.h> |
27 | #include <linux/coresight.h> | |
28 | #include <linux/amba/bus.h> | |
267b2c23 | 29 | #include <linux/clk.h> |
fdfc0d8a PP |
30 | |
31 | #include "coresight-priv.h" | |
32 | ||
33 | #define ETB_RAM_DEPTH_REG 0x004 | |
34 | #define ETB_STATUS_REG 0x00c | |
35 | #define ETB_RAM_READ_DATA_REG 0x010 | |
36 | #define ETB_RAM_READ_POINTER 0x014 | |
37 | #define ETB_RAM_WRITE_POINTER 0x018 | |
38 | #define ETB_TRG 0x01c | |
39 | #define ETB_CTL_REG 0x020 | |
40 | #define ETB_RWD_REG 0x024 | |
41 | #define ETB_FFSR 0x300 | |
42 | #define ETB_FFCR 0x304 | |
43 | #define ETB_ITMISCOP0 0xee0 | |
44 | #define ETB_ITTRFLINACK 0xee4 | |
45 | #define ETB_ITTRFLIN 0xee8 | |
46 | #define ETB_ITATBDATA0 0xeeC | |
47 | #define ETB_ITATBCTR2 0xef0 | |
48 | #define ETB_ITATBCTR1 0xef4 | |
49 | #define ETB_ITATBCTR0 0xef8 | |
50 | ||
51 | /* register description */ | |
52 | /* STS - 0x00C */ | |
53 | #define ETB_STATUS_RAM_FULL BIT(0) | |
54 | /* CTL - 0x020 */ | |
55 | #define ETB_CTL_CAPT_EN BIT(0) | |
56 | /* FFCR - 0x304 */ | |
57 | #define ETB_FFCR_EN_FTC BIT(0) | |
58 | #define ETB_FFCR_FON_MAN BIT(6) | |
59 | #define ETB_FFCR_STOP_FI BIT(12) | |
60 | #define ETB_FFCR_STOP_TRIGGER BIT(13) | |
61 | ||
62 | #define ETB_FFCR_BIT 6 | |
63 | #define ETB_FFSR_BIT 1 | |
64 | #define ETB_FRAME_SIZE_WORDS 4 | |
65 | ||
66 | /** | |
67 | * struct etb_drvdata - specifics associated to an ETB component | |
68 | * @base: memory mapped base address for this component. | |
69 | * @dev: the device entity associated to this component. | |
267b2c23 | 70 | * @atclk: optional clock for the core parts of the ETB. |
fdfc0d8a PP |
71 | * @csdev: component vitals needed by the framework. |
72 | * @miscdev: specifics to handle "/dev/xyz.etb" entry. | |
fdfc0d8a PP |
73 | * @spinlock: only one at a time pls. |
74 | * @in_use: synchronise user space access to etb buffer. | |
75 | * @buf: area of memory where ETB buffer content gets sent. | |
76 | * @buffer_depth: size of @buf. | |
77 | * @enable: this ETB is being used. | |
78 | * @trigger_cntr: amount of words to store after a trigger. | |
79 | */ | |
80 | struct etb_drvdata { | |
81 | void __iomem *base; | |
82 | struct device *dev; | |
267b2c23 | 83 | struct clk *atclk; |
fdfc0d8a PP |
84 | struct coresight_device *csdev; |
85 | struct miscdevice miscdev; | |
fdfc0d8a PP |
86 | spinlock_t spinlock; |
87 | atomic_t in_use; | |
88 | u8 *buf; | |
89 | u32 buffer_depth; | |
90 | bool enable; | |
91 | u32 trigger_cntr; | |
92 | }; | |
93 | ||
94 | static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata) | |
95 | { | |
fdfc0d8a PP |
96 | u32 depth = 0; |
97 | ||
1b19f59d | 98 | pm_runtime_get_sync(drvdata->dev); |
fdfc0d8a PP |
99 | |
100 | /* RO registers don't need locking */ | |
101 | depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG); | |
102 | ||
1b19f59d | 103 | pm_runtime_put(drvdata->dev); |
fdfc0d8a PP |
104 | return depth; |
105 | } | |
106 | ||
107 | static void etb_enable_hw(struct etb_drvdata *drvdata) | |
108 | { | |
109 | int i; | |
110 | u32 depth; | |
111 | ||
112 | CS_UNLOCK(drvdata->base); | |
113 | ||
114 | depth = drvdata->buffer_depth; | |
115 | /* reset write RAM pointer address */ | |
116 | writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); | |
117 | /* clear entire RAM buffer */ | |
118 | for (i = 0; i < depth; i++) | |
119 | writel_relaxed(0x0, drvdata->base + ETB_RWD_REG); | |
120 | ||
121 | /* reset write RAM pointer address */ | |
122 | writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); | |
123 | /* reset read RAM pointer address */ | |
124 | writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); | |
125 | ||
126 | writel_relaxed(drvdata->trigger_cntr, drvdata->base + ETB_TRG); | |
127 | writel_relaxed(ETB_FFCR_EN_FTC | ETB_FFCR_STOP_TRIGGER, | |
128 | drvdata->base + ETB_FFCR); | |
129 | /* ETB trace capture enable */ | |
130 | writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG); | |
131 | ||
132 | CS_LOCK(drvdata->base); | |
133 | } | |
134 | ||
135 | static int etb_enable(struct coresight_device *csdev) | |
136 | { | |
137 | struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); | |
fdfc0d8a PP |
138 | unsigned long flags; |
139 | ||
1b19f59d | 140 | pm_runtime_get_sync(drvdata->dev); |
fdfc0d8a PP |
141 | |
142 | spin_lock_irqsave(&drvdata->spinlock, flags); | |
143 | etb_enable_hw(drvdata); | |
144 | drvdata->enable = true; | |
145 | spin_unlock_irqrestore(&drvdata->spinlock, flags); | |
146 | ||
147 | dev_info(drvdata->dev, "ETB enabled\n"); | |
148 | return 0; | |
149 | } | |
150 | ||
151 | static void etb_disable_hw(struct etb_drvdata *drvdata) | |
152 | { | |
153 | u32 ffcr; | |
154 | ||
155 | CS_UNLOCK(drvdata->base); | |
156 | ||
157 | ffcr = readl_relaxed(drvdata->base + ETB_FFCR); | |
158 | /* stop formatter when a stop has completed */ | |
159 | ffcr |= ETB_FFCR_STOP_FI; | |
160 | writel_relaxed(ffcr, drvdata->base + ETB_FFCR); | |
161 | /* manually generate a flush of the system */ | |
162 | ffcr |= ETB_FFCR_FON_MAN; | |
163 | writel_relaxed(ffcr, drvdata->base + ETB_FFCR); | |
164 | ||
165 | if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) { | |
166 | dev_err(drvdata->dev, | |
167 | "timeout observed when probing at offset %#x\n", | |
168 | ETB_FFCR); | |
169 | } | |
170 | ||
171 | /* disable trace capture */ | |
172 | writel_relaxed(0x0, drvdata->base + ETB_CTL_REG); | |
173 | ||
174 | if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) { | |
175 | dev_err(drvdata->dev, | |
176 | "timeout observed when probing at offset %#x\n", | |
177 | ETB_FFCR); | |
178 | } | |
179 | ||
180 | CS_LOCK(drvdata->base); | |
181 | } | |
182 | ||
183 | static void etb_dump_hw(struct etb_drvdata *drvdata) | |
184 | { | |
185 | int i; | |
186 | u8 *buf_ptr; | |
187 | u32 read_data, depth; | |
188 | u32 read_ptr, write_ptr; | |
189 | u32 frame_off, frame_endoff; | |
190 | ||
191 | CS_UNLOCK(drvdata->base); | |
192 | ||
193 | read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER); | |
194 | write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER); | |
195 | ||
196 | frame_off = write_ptr % ETB_FRAME_SIZE_WORDS; | |
197 | frame_endoff = ETB_FRAME_SIZE_WORDS - frame_off; | |
198 | if (frame_off) { | |
199 | dev_err(drvdata->dev, | |
200 | "write_ptr: %lu not aligned to formatter frame size\n", | |
201 | (unsigned long)write_ptr); | |
202 | dev_err(drvdata->dev, "frameoff: %lu, frame_endoff: %lu\n", | |
203 | (unsigned long)frame_off, (unsigned long)frame_endoff); | |
204 | write_ptr += frame_endoff; | |
205 | } | |
206 | ||
207 | if ((readl_relaxed(drvdata->base + ETB_STATUS_REG) | |
208 | & ETB_STATUS_RAM_FULL) == 0) | |
209 | writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); | |
210 | else | |
211 | writel_relaxed(write_ptr, drvdata->base + ETB_RAM_READ_POINTER); | |
212 | ||
213 | depth = drvdata->buffer_depth; | |
214 | buf_ptr = drvdata->buf; | |
215 | for (i = 0; i < depth; i++) { | |
216 | read_data = readl_relaxed(drvdata->base + | |
217 | ETB_RAM_READ_DATA_REG); | |
218 | *buf_ptr++ = read_data >> 0; | |
219 | *buf_ptr++ = read_data >> 8; | |
220 | *buf_ptr++ = read_data >> 16; | |
221 | *buf_ptr++ = read_data >> 24; | |
222 | } | |
223 | ||
224 | if (frame_off) { | |
225 | buf_ptr -= (frame_endoff * 4); | |
226 | for (i = 0; i < frame_endoff; i++) { | |
227 | *buf_ptr++ = 0x0; | |
228 | *buf_ptr++ = 0x0; | |
229 | *buf_ptr++ = 0x0; | |
230 | *buf_ptr++ = 0x0; | |
231 | } | |
232 | } | |
233 | ||
234 | writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER); | |
235 | ||
236 | CS_LOCK(drvdata->base); | |
237 | } | |
238 | ||
239 | static void etb_disable(struct coresight_device *csdev) | |
240 | { | |
241 | struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); | |
242 | unsigned long flags; | |
243 | ||
244 | spin_lock_irqsave(&drvdata->spinlock, flags); | |
245 | etb_disable_hw(drvdata); | |
246 | etb_dump_hw(drvdata); | |
247 | drvdata->enable = false; | |
248 | spin_unlock_irqrestore(&drvdata->spinlock, flags); | |
249 | ||
1b19f59d | 250 | pm_runtime_put(drvdata->dev); |
fdfc0d8a PP |
251 | |
252 | dev_info(drvdata->dev, "ETB disabled\n"); | |
253 | } | |
254 | ||
255 | static const struct coresight_ops_sink etb_sink_ops = { | |
256 | .enable = etb_enable, | |
257 | .disable = etb_disable, | |
258 | }; | |
259 | ||
260 | static const struct coresight_ops etb_cs_ops = { | |
261 | .sink_ops = &etb_sink_ops, | |
262 | }; | |
263 | ||
264 | static void etb_dump(struct etb_drvdata *drvdata) | |
265 | { | |
266 | unsigned long flags; | |
267 | ||
268 | spin_lock_irqsave(&drvdata->spinlock, flags); | |
269 | if (drvdata->enable) { | |
270 | etb_disable_hw(drvdata); | |
271 | etb_dump_hw(drvdata); | |
272 | etb_enable_hw(drvdata); | |
273 | } | |
274 | spin_unlock_irqrestore(&drvdata->spinlock, flags); | |
275 | ||
276 | dev_info(drvdata->dev, "ETB dumped\n"); | |
277 | } | |
278 | ||
279 | static int etb_open(struct inode *inode, struct file *file) | |
280 | { | |
281 | struct etb_drvdata *drvdata = container_of(file->private_data, | |
282 | struct etb_drvdata, miscdev); | |
283 | ||
284 | if (atomic_cmpxchg(&drvdata->in_use, 0, 1)) | |
285 | return -EBUSY; | |
286 | ||
287 | dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__); | |
288 | return 0; | |
289 | } | |
290 | ||
291 | static ssize_t etb_read(struct file *file, char __user *data, | |
292 | size_t len, loff_t *ppos) | |
293 | { | |
294 | u32 depth; | |
295 | struct etb_drvdata *drvdata = container_of(file->private_data, | |
296 | struct etb_drvdata, miscdev); | |
297 | ||
298 | etb_dump(drvdata); | |
299 | ||
300 | depth = drvdata->buffer_depth; | |
301 | if (*ppos + len > depth * 4) | |
302 | len = depth * 4 - *ppos; | |
303 | ||
304 | if (copy_to_user(data, drvdata->buf + *ppos, len)) { | |
305 | dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__); | |
306 | return -EFAULT; | |
307 | } | |
308 | ||
309 | *ppos += len; | |
310 | ||
72f641fe MP |
311 | dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n", |
312 | __func__, len, (int)(depth * 4 - *ppos)); | |
fdfc0d8a PP |
313 | return len; |
314 | } | |
315 | ||
316 | static int etb_release(struct inode *inode, struct file *file) | |
317 | { | |
318 | struct etb_drvdata *drvdata = container_of(file->private_data, | |
319 | struct etb_drvdata, miscdev); | |
320 | atomic_set(&drvdata->in_use, 0); | |
321 | ||
322 | dev_dbg(drvdata->dev, "%s: released\n", __func__); | |
323 | return 0; | |
324 | } | |
325 | ||
326 | static const struct file_operations etb_fops = { | |
327 | .owner = THIS_MODULE, | |
328 | .open = etb_open, | |
329 | .read = etb_read, | |
330 | .release = etb_release, | |
331 | .llseek = no_llseek, | |
332 | }; | |
333 | ||
334 | static ssize_t status_show(struct device *dev, | |
335 | struct device_attribute *attr, char *buf) | |
336 | { | |
fdfc0d8a PP |
337 | unsigned long flags; |
338 | u32 etb_rdr, etb_sr, etb_rrp, etb_rwp; | |
339 | u32 etb_trg, etb_cr, etb_ffsr, etb_ffcr; | |
340 | struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent); | |
341 | ||
1b19f59d | 342 | pm_runtime_get_sync(drvdata->dev); |
fdfc0d8a PP |
343 | spin_lock_irqsave(&drvdata->spinlock, flags); |
344 | CS_UNLOCK(drvdata->base); | |
345 | ||
346 | etb_rdr = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG); | |
347 | etb_sr = readl_relaxed(drvdata->base + ETB_STATUS_REG); | |
348 | etb_rrp = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER); | |
349 | etb_rwp = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER); | |
350 | etb_trg = readl_relaxed(drvdata->base + ETB_TRG); | |
351 | etb_cr = readl_relaxed(drvdata->base + ETB_CTL_REG); | |
352 | etb_ffsr = readl_relaxed(drvdata->base + ETB_FFSR); | |
353 | etb_ffcr = readl_relaxed(drvdata->base + ETB_FFCR); | |
354 | ||
355 | CS_LOCK(drvdata->base); | |
356 | spin_unlock_irqrestore(&drvdata->spinlock, flags); | |
357 | ||
1b19f59d | 358 | pm_runtime_put(drvdata->dev); |
fdfc0d8a PP |
359 | |
360 | return sprintf(buf, | |
361 | "Depth:\t\t0x%x\n" | |
362 | "Status:\t\t0x%x\n" | |
363 | "RAM read ptr:\t0x%x\n" | |
364 | "RAM wrt ptr:\t0x%x\n" | |
365 | "Trigger cnt:\t0x%x\n" | |
366 | "Control:\t0x%x\n" | |
367 | "Flush status:\t0x%x\n" | |
368 | "Flush ctrl:\t0x%x\n", | |
369 | etb_rdr, etb_sr, etb_rrp, etb_rwp, | |
370 | etb_trg, etb_cr, etb_ffsr, etb_ffcr); | |
1b19f59d | 371 | |
fdfc0d8a PP |
372 | return -EINVAL; |
373 | } | |
374 | static DEVICE_ATTR_RO(status); | |
375 | ||
376 | static ssize_t trigger_cntr_show(struct device *dev, | |
377 | struct device_attribute *attr, char *buf) | |
378 | { | |
379 | struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent); | |
380 | unsigned long val = drvdata->trigger_cntr; | |
381 | ||
382 | return sprintf(buf, "%#lx\n", val); | |
383 | } | |
384 | ||
385 | static ssize_t trigger_cntr_store(struct device *dev, | |
386 | struct device_attribute *attr, | |
387 | const char *buf, size_t size) | |
388 | { | |
389 | int ret; | |
390 | unsigned long val; | |
391 | struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent); | |
392 | ||
393 | ret = kstrtoul(buf, 16, &val); | |
394 | if (ret) | |
395 | return ret; | |
396 | ||
397 | drvdata->trigger_cntr = val; | |
398 | return size; | |
399 | } | |
400 | static DEVICE_ATTR_RW(trigger_cntr); | |
401 | ||
402 | static struct attribute *coresight_etb_attrs[] = { | |
403 | &dev_attr_trigger_cntr.attr, | |
404 | &dev_attr_status.attr, | |
405 | NULL, | |
406 | }; | |
407 | ATTRIBUTE_GROUPS(coresight_etb); | |
408 | ||
409 | static int etb_probe(struct amba_device *adev, const struct amba_id *id) | |
410 | { | |
411 | int ret; | |
412 | void __iomem *base; | |
413 | struct device *dev = &adev->dev; | |
414 | struct coresight_platform_data *pdata = NULL; | |
415 | struct etb_drvdata *drvdata; | |
416 | struct resource *res = &adev->res; | |
417 | struct coresight_desc *desc; | |
418 | struct device_node *np = adev->dev.of_node; | |
419 | ||
420 | if (np) { | |
421 | pdata = of_get_coresight_platform_data(dev, np); | |
422 | if (IS_ERR(pdata)) | |
423 | return PTR_ERR(pdata); | |
424 | adev->dev.platform_data = pdata; | |
425 | } | |
426 | ||
427 | drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); | |
428 | if (!drvdata) | |
429 | return -ENOMEM; | |
430 | ||
431 | drvdata->dev = &adev->dev; | |
267b2c23 LW |
432 | drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ |
433 | if (!IS_ERR(drvdata->atclk)) { | |
434 | ret = clk_prepare_enable(drvdata->atclk); | |
435 | if (ret) | |
436 | return ret; | |
437 | } | |
fdfc0d8a PP |
438 | dev_set_drvdata(dev, drvdata); |
439 | ||
440 | /* validity for the resource is already checked by the AMBA core */ | |
441 | base = devm_ioremap_resource(dev, res); | |
442 | if (IS_ERR(base)) | |
443 | return PTR_ERR(base); | |
444 | ||
445 | drvdata->base = base; | |
446 | ||
447 | spin_lock_init(&drvdata->spinlock); | |
448 | ||
d786a47d | 449 | drvdata->buffer_depth = etb_get_buffer_depth(drvdata); |
1b19f59d | 450 | pm_runtime_put(&adev->dev); |
fdfc0d8a | 451 | |
f5da7cb2 | 452 | if (drvdata->buffer_depth & 0x80000000) |
fdfc0d8a PP |
453 | return -EINVAL; |
454 | ||
455 | drvdata->buf = devm_kzalloc(dev, | |
456 | drvdata->buffer_depth * 4, GFP_KERNEL); | |
cc545449 MB |
457 | if (!drvdata->buf) { |
458 | dev_err(dev, "Failed to allocate %u bytes for buffer data\n", | |
459 | drvdata->buffer_depth * 4); | |
fdfc0d8a | 460 | return -ENOMEM; |
cc545449 | 461 | } |
fdfc0d8a PP |
462 | |
463 | desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); | |
464 | if (!desc) | |
465 | return -ENOMEM; | |
466 | ||
467 | desc->type = CORESIGHT_DEV_TYPE_SINK; | |
468 | desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; | |
469 | desc->ops = &etb_cs_ops; | |
470 | desc->pdata = pdata; | |
471 | desc->dev = dev; | |
472 | desc->groups = coresight_etb_groups; | |
473 | drvdata->csdev = coresight_register(desc); | |
474 | if (IS_ERR(drvdata->csdev)) | |
475 | return PTR_ERR(drvdata->csdev); | |
476 | ||
477 | drvdata->miscdev.name = pdata->name; | |
478 | drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; | |
479 | drvdata->miscdev.fops = &etb_fops; | |
480 | ret = misc_register(&drvdata->miscdev); | |
481 | if (ret) | |
482 | goto err_misc_register; | |
483 | ||
484 | dev_info(dev, "ETB initialized\n"); | |
485 | return 0; | |
486 | ||
487 | err_misc_register: | |
488 | coresight_unregister(drvdata->csdev); | |
489 | return ret; | |
490 | } | |
491 | ||
492 | static int etb_remove(struct amba_device *adev) | |
493 | { | |
494 | struct etb_drvdata *drvdata = amba_get_drvdata(adev); | |
495 | ||
496 | misc_deregister(&drvdata->miscdev); | |
497 | coresight_unregister(drvdata->csdev); | |
498 | return 0; | |
499 | } | |
500 | ||
267b2c23 LW |
501 | #ifdef CONFIG_PM |
502 | static int etb_runtime_suspend(struct device *dev) | |
503 | { | |
504 | struct etb_drvdata *drvdata = dev_get_drvdata(dev); | |
505 | ||
506 | if (drvdata && !IS_ERR(drvdata->atclk)) | |
507 | clk_disable_unprepare(drvdata->atclk); | |
508 | ||
509 | return 0; | |
510 | } | |
511 | ||
512 | static int etb_runtime_resume(struct device *dev) | |
513 | { | |
514 | struct etb_drvdata *drvdata = dev_get_drvdata(dev); | |
515 | ||
516 | if (drvdata && !IS_ERR(drvdata->atclk)) | |
517 | clk_prepare_enable(drvdata->atclk); | |
518 | ||
519 | return 0; | |
520 | } | |
521 | #endif | |
522 | ||
523 | static const struct dev_pm_ops etb_dev_pm_ops = { | |
524 | SET_RUNTIME_PM_OPS(etb_runtime_suspend, etb_runtime_resume, NULL) | |
525 | }; | |
526 | ||
fdfc0d8a PP |
527 | static struct amba_id etb_ids[] = { |
528 | { | |
529 | .id = 0x0003b907, | |
530 | .mask = 0x0003ffff, | |
531 | }, | |
532 | { 0, 0}, | |
533 | }; | |
534 | ||
535 | static struct amba_driver etb_driver = { | |
536 | .drv = { | |
537 | .name = "coresight-etb10", | |
538 | .owner = THIS_MODULE, | |
267b2c23 LW |
539 | .pm = &etb_dev_pm_ops, |
540 | ||
fdfc0d8a PP |
541 | }, |
542 | .probe = etb_probe, | |
543 | .remove = etb_remove, | |
544 | .id_table = etb_ids, | |
545 | }; | |
546 | ||
52d6bbb9 | 547 | module_amba_driver(etb_driver); |
fdfc0d8a PP |
548 | |
549 | MODULE_LICENSE("GPL v2"); | |
550 | MODULE_DESCRIPTION("CoreSight Embedded Trace Buffer driver"); |