Commit | Line | Data |
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fac368a0 NV |
1 | /* |
2 | * i2c Support for Atmel's AT91 Two-Wire Interface (TWI) | |
3 | * | |
4 | * Copyright (C) 2011 Weinmann Medical GmbH | |
5 | * Author: Nikolaus Voss <n.voss@weinmann.de> | |
6 | * | |
7 | * Evolved from original work by: | |
8 | * Copyright (C) 2004 Rick Bronson | |
9 | * Converted to 2.6 by Andrew Victor <andrew@sanpeople.com> | |
10 | * | |
11 | * Borrowed heavily from original work by: | |
12 | * Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com> | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | */ | |
19 | ||
20 | #include <linux/clk.h> | |
21 | #include <linux/completion.h> | |
60937b2c LD |
22 | #include <linux/dma-mapping.h> |
23 | #include <linux/dmaengine.h> | |
fac368a0 NV |
24 | #include <linux/err.h> |
25 | #include <linux/i2c.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/module.h> | |
70d46a24 LD |
29 | #include <linux/of.h> |
30 | #include <linux/of_device.h> | |
fac368a0 NV |
31 | #include <linux/platform_device.h> |
32 | #include <linux/slab.h> | |
60937b2c | 33 | #include <linux/platform_data/dma-atmel.h> |
d64a8188 | 34 | #include <linux/pm_runtime.h> |
62d10c40 | 35 | #include <linux/pinctrl/consumer.h> |
fac368a0 | 36 | |
75b6c4b6 | 37 | #define DEFAULT_TWI_CLK_HZ 100000 /* max 400 Kbits/s */ |
fac368a0 | 38 | #define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */ |
60937b2c | 39 | #define AT91_I2C_DMA_THRESHOLD 8 /* enable DMA if transfer size is bigger than this threshold */ |
d64a8188 | 40 | #define AUTOSUSPEND_TIMEOUT 2000 |
fac368a0 NV |
41 | |
42 | /* AT91 TWI register definitions */ | |
43 | #define AT91_TWI_CR 0x0000 /* Control Register */ | |
44 | #define AT91_TWI_START 0x0001 /* Send a Start Condition */ | |
45 | #define AT91_TWI_STOP 0x0002 /* Send a Stop Condition */ | |
46 | #define AT91_TWI_MSEN 0x0004 /* Master Transfer Enable */ | |
47 | #define AT91_TWI_SVDIS 0x0020 /* Slave Transfer Disable */ | |
7c3fe64d | 48 | #define AT91_TWI_QUICK 0x0040 /* SMBus quick command */ |
fac368a0 NV |
49 | #define AT91_TWI_SWRST 0x0080 /* Software Reset */ |
50 | ||
51 | #define AT91_TWI_MMR 0x0004 /* Master Mode Register */ | |
52 | #define AT91_TWI_IADRSZ_1 0x0100 /* Internal Device Address Size */ | |
53 | #define AT91_TWI_MREAD 0x1000 /* Master Read Direction */ | |
54 | ||
55 | #define AT91_TWI_IADR 0x000c /* Internal Address Register */ | |
56 | ||
57 | #define AT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg */ | |
58 | ||
59 | #define AT91_TWI_SR 0x0020 /* Status Register */ | |
60 | #define AT91_TWI_TXCOMP 0x0001 /* Transmission Complete */ | |
61 | #define AT91_TWI_RXRDY 0x0002 /* Receive Holding Register Ready */ | |
62 | #define AT91_TWI_TXRDY 0x0004 /* Transmit Holding Register Ready */ | |
63 | ||
64 | #define AT91_TWI_OVRE 0x0040 /* Overrun Error */ | |
65 | #define AT91_TWI_UNRE 0x0080 /* Underrun Error */ | |
66 | #define AT91_TWI_NACK 0x0100 /* Not Acknowledged */ | |
67 | ||
68 | #define AT91_TWI_IER 0x0024 /* Interrupt Enable Register */ | |
69 | #define AT91_TWI_IDR 0x0028 /* Interrupt Disable Register */ | |
70 | #define AT91_TWI_IMR 0x002c /* Interrupt Mask Register */ | |
71 | #define AT91_TWI_RHR 0x0030 /* Receive Holding Register */ | |
72 | #define AT91_TWI_THR 0x0034 /* Transmit Holding Register */ | |
73 | ||
74 | struct at91_twi_pdata { | |
5f433819 LD |
75 | unsigned clk_max_div; |
76 | unsigned clk_offset; | |
77 | bool has_unre_flag; | |
60937b2c LD |
78 | struct at_dma_slave dma_slave; |
79 | }; | |
80 | ||
81 | struct at91_twi_dma { | |
82 | struct dma_chan *chan_rx; | |
83 | struct dma_chan *chan_tx; | |
84 | struct scatterlist sg; | |
85 | struct dma_async_tx_descriptor *data_desc; | |
86 | enum dma_data_direction direction; | |
87 | bool buf_mapped; | |
88 | bool xfer_in_progress; | |
fac368a0 NV |
89 | }; |
90 | ||
91 | struct at91_twi_dev { | |
5f433819 LD |
92 | struct device *dev; |
93 | void __iomem *base; | |
94 | struct completion cmd_complete; | |
95 | struct clk *clk; | |
96 | u8 *buf; | |
97 | size_t buf_len; | |
98 | struct i2c_msg *msg; | |
99 | int irq; | |
60937b2c | 100 | unsigned imr; |
5f433819 LD |
101 | unsigned transfer_status; |
102 | struct i2c_adapter adapter; | |
103 | unsigned twi_cwgr_reg; | |
104 | struct at91_twi_pdata *pdata; | |
60937b2c | 105 | bool use_dma; |
75b81f33 | 106 | bool recv_len_abort; |
60937b2c | 107 | struct at91_twi_dma dma; |
fac368a0 NV |
108 | }; |
109 | ||
110 | static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg) | |
111 | { | |
112 | return readl_relaxed(dev->base + reg); | |
113 | } | |
114 | ||
115 | static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val) | |
116 | { | |
117 | writel_relaxed(val, dev->base + reg); | |
118 | } | |
119 | ||
120 | static void at91_disable_twi_interrupts(struct at91_twi_dev *dev) | |
121 | { | |
122 | at91_twi_write(dev, AT91_TWI_IDR, | |
123 | AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY); | |
124 | } | |
125 | ||
60937b2c LD |
126 | static void at91_twi_irq_save(struct at91_twi_dev *dev) |
127 | { | |
128 | dev->imr = at91_twi_read(dev, AT91_TWI_IMR) & 0x7; | |
129 | at91_disable_twi_interrupts(dev); | |
130 | } | |
131 | ||
132 | static void at91_twi_irq_restore(struct at91_twi_dev *dev) | |
133 | { | |
134 | at91_twi_write(dev, AT91_TWI_IER, dev->imr); | |
135 | } | |
136 | ||
fac368a0 NV |
137 | static void at91_init_twi_bus(struct at91_twi_dev *dev) |
138 | { | |
139 | at91_disable_twi_interrupts(dev); | |
140 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST); | |
141 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN); | |
142 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS); | |
143 | at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg); | |
144 | } | |
145 | ||
146 | /* | |
147 | * Calculate symmetric clock as stated in datasheet: | |
148 | * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset)) | |
149 | */ | |
0b255e92 | 150 | static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk) |
fac368a0 NV |
151 | { |
152 | int ckdiv, cdiv, div; | |
153 | struct at91_twi_pdata *pdata = dev->pdata; | |
154 | int offset = pdata->clk_offset; | |
155 | int max_ckdiv = pdata->clk_max_div; | |
156 | ||
157 | div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk), | |
158 | 2 * twi_clk) - offset); | |
159 | ckdiv = fls(div >> 8); | |
160 | cdiv = div >> ckdiv; | |
161 | ||
162 | if (ckdiv > max_ckdiv) { | |
163 | dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n", | |
164 | ckdiv, max_ckdiv); | |
165 | ckdiv = max_ckdiv; | |
166 | cdiv = 255; | |
167 | } | |
168 | ||
169 | dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv; | |
170 | dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv); | |
171 | } | |
172 | ||
60937b2c LD |
173 | static void at91_twi_dma_cleanup(struct at91_twi_dev *dev) |
174 | { | |
175 | struct at91_twi_dma *dma = &dev->dma; | |
176 | ||
177 | at91_twi_irq_save(dev); | |
178 | ||
179 | if (dma->xfer_in_progress) { | |
180 | if (dma->direction == DMA_FROM_DEVICE) | |
181 | dmaengine_terminate_all(dma->chan_rx); | |
182 | else | |
183 | dmaengine_terminate_all(dma->chan_tx); | |
184 | dma->xfer_in_progress = false; | |
185 | } | |
186 | if (dma->buf_mapped) { | |
187 | dma_unmap_single(dev->dev, sg_dma_address(&dma->sg), | |
188 | dev->buf_len, dma->direction); | |
189 | dma->buf_mapped = false; | |
190 | } | |
191 | ||
192 | at91_twi_irq_restore(dev); | |
193 | } | |
194 | ||
fac368a0 NV |
195 | static void at91_twi_write_next_byte(struct at91_twi_dev *dev) |
196 | { | |
197 | if (dev->buf_len <= 0) | |
198 | return; | |
199 | ||
200 | at91_twi_write(dev, AT91_TWI_THR, *dev->buf); | |
201 | ||
202 | /* send stop when last byte has been written */ | |
203 | if (--dev->buf_len == 0) | |
204 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP); | |
205 | ||
206 | dev_dbg(dev->dev, "wrote 0x%x, to go %d\n", *dev->buf, dev->buf_len); | |
207 | ||
208 | ++dev->buf; | |
209 | } | |
210 | ||
60937b2c LD |
211 | static void at91_twi_write_data_dma_callback(void *data) |
212 | { | |
213 | struct at91_twi_dev *dev = (struct at91_twi_dev *)data; | |
214 | ||
215 | dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg), | |
28772ac8 | 216 | dev->buf_len, DMA_TO_DEVICE); |
60937b2c LD |
217 | |
218 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP); | |
219 | } | |
220 | ||
221 | static void at91_twi_write_data_dma(struct at91_twi_dev *dev) | |
222 | { | |
223 | dma_addr_t dma_addr; | |
224 | struct dma_async_tx_descriptor *txdesc; | |
225 | struct at91_twi_dma *dma = &dev->dma; | |
226 | struct dma_chan *chan_tx = dma->chan_tx; | |
227 | ||
228 | if (dev->buf_len <= 0) | |
229 | return; | |
230 | ||
231 | dma->direction = DMA_TO_DEVICE; | |
232 | ||
233 | at91_twi_irq_save(dev); | |
234 | dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len, | |
235 | DMA_TO_DEVICE); | |
236 | if (dma_mapping_error(dev->dev, dma_addr)) { | |
237 | dev_err(dev->dev, "dma map failed\n"); | |
238 | return; | |
239 | } | |
240 | dma->buf_mapped = true; | |
241 | at91_twi_irq_restore(dev); | |
242 | sg_dma_len(&dma->sg) = dev->buf_len; | |
243 | sg_dma_address(&dma->sg) = dma_addr; | |
244 | ||
245 | txdesc = dmaengine_prep_slave_sg(chan_tx, &dma->sg, 1, DMA_MEM_TO_DEV, | |
246 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
247 | if (!txdesc) { | |
248 | dev_err(dev->dev, "dma prep slave sg failed\n"); | |
249 | goto error; | |
250 | } | |
251 | ||
252 | txdesc->callback = at91_twi_write_data_dma_callback; | |
253 | txdesc->callback_param = dev; | |
254 | ||
255 | dma->xfer_in_progress = true; | |
256 | dmaengine_submit(txdesc); | |
257 | dma_async_issue_pending(chan_tx); | |
258 | ||
259 | return; | |
260 | ||
261 | error: | |
262 | at91_twi_dma_cleanup(dev); | |
263 | } | |
264 | ||
fac368a0 NV |
265 | static void at91_twi_read_next_byte(struct at91_twi_dev *dev) |
266 | { | |
267 | if (dev->buf_len <= 0) | |
268 | return; | |
269 | ||
270 | *dev->buf = at91_twi_read(dev, AT91_TWI_RHR) & 0xff; | |
271 | --dev->buf_len; | |
272 | ||
75b81f33 MR |
273 | /* return if aborting, we only needed to read RHR to clear RXRDY*/ |
274 | if (dev->recv_len_abort) | |
275 | return; | |
276 | ||
fac368a0 NV |
277 | /* handle I2C_SMBUS_BLOCK_DATA */ |
278 | if (unlikely(dev->msg->flags & I2C_M_RECV_LEN)) { | |
75b81f33 MR |
279 | /* ensure length byte is a valid value */ |
280 | if (*dev->buf <= I2C_SMBUS_BLOCK_MAX && *dev->buf > 0) { | |
281 | dev->msg->flags &= ~I2C_M_RECV_LEN; | |
282 | dev->buf_len += *dev->buf; | |
283 | dev->msg->len = dev->buf_len + 1; | |
284 | dev_dbg(dev->dev, "received block length %d\n", | |
285 | dev->buf_len); | |
286 | } else { | |
287 | /* abort and send the stop by reading one more byte */ | |
288 | dev->recv_len_abort = true; | |
289 | dev->buf_len = 1; | |
290 | } | |
fac368a0 NV |
291 | } |
292 | ||
293 | /* send stop if second but last byte has been read */ | |
294 | if (dev->buf_len == 1) | |
295 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP); | |
296 | ||
297 | dev_dbg(dev->dev, "read 0x%x, to go %d\n", *dev->buf, dev->buf_len); | |
298 | ||
299 | ++dev->buf; | |
300 | } | |
301 | ||
60937b2c LD |
302 | static void at91_twi_read_data_dma_callback(void *data) |
303 | { | |
304 | struct at91_twi_dev *dev = (struct at91_twi_dev *)data; | |
305 | ||
306 | dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg), | |
28772ac8 | 307 | dev->buf_len, DMA_FROM_DEVICE); |
60937b2c LD |
308 | |
309 | /* The last two bytes have to be read without using dma */ | |
310 | dev->buf += dev->buf_len - 2; | |
311 | dev->buf_len = 2; | |
312 | at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_RXRDY); | |
313 | } | |
314 | ||
315 | static void at91_twi_read_data_dma(struct at91_twi_dev *dev) | |
316 | { | |
317 | dma_addr_t dma_addr; | |
318 | struct dma_async_tx_descriptor *rxdesc; | |
319 | struct at91_twi_dma *dma = &dev->dma; | |
320 | struct dma_chan *chan_rx = dma->chan_rx; | |
321 | ||
322 | dma->direction = DMA_FROM_DEVICE; | |
323 | ||
324 | /* Keep in mind that we won't use dma to read the last two bytes */ | |
325 | at91_twi_irq_save(dev); | |
326 | dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len - 2, | |
327 | DMA_FROM_DEVICE); | |
328 | if (dma_mapping_error(dev->dev, dma_addr)) { | |
329 | dev_err(dev->dev, "dma map failed\n"); | |
330 | return; | |
331 | } | |
332 | dma->buf_mapped = true; | |
333 | at91_twi_irq_restore(dev); | |
334 | dma->sg.dma_address = dma_addr; | |
335 | sg_dma_len(&dma->sg) = dev->buf_len - 2; | |
336 | ||
337 | rxdesc = dmaengine_prep_slave_sg(chan_rx, &dma->sg, 1, DMA_DEV_TO_MEM, | |
338 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
339 | if (!rxdesc) { | |
340 | dev_err(dev->dev, "dma prep slave sg failed\n"); | |
341 | goto error; | |
342 | } | |
343 | ||
344 | rxdesc->callback = at91_twi_read_data_dma_callback; | |
345 | rxdesc->callback_param = dev; | |
346 | ||
347 | dma->xfer_in_progress = true; | |
348 | dmaengine_submit(rxdesc); | |
349 | dma_async_issue_pending(dma->chan_rx); | |
350 | ||
351 | return; | |
352 | ||
353 | error: | |
354 | at91_twi_dma_cleanup(dev); | |
355 | } | |
356 | ||
fac368a0 NV |
357 | static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id) |
358 | { | |
359 | struct at91_twi_dev *dev = dev_id; | |
360 | const unsigned status = at91_twi_read(dev, AT91_TWI_SR); | |
361 | const unsigned irqstatus = status & at91_twi_read(dev, AT91_TWI_IMR); | |
362 | ||
363 | if (!irqstatus) | |
364 | return IRQ_NONE; | |
365 | else if (irqstatus & AT91_TWI_RXRDY) | |
366 | at91_twi_read_next_byte(dev); | |
367 | else if (irqstatus & AT91_TWI_TXRDY) | |
368 | at91_twi_write_next_byte(dev); | |
369 | ||
370 | /* catch error flags */ | |
371 | dev->transfer_status |= status; | |
372 | ||
373 | if (irqstatus & AT91_TWI_TXCOMP) { | |
374 | at91_disable_twi_interrupts(dev); | |
375 | complete(&dev->cmd_complete); | |
376 | } | |
377 | ||
378 | return IRQ_HANDLED; | |
379 | } | |
380 | ||
381 | static int at91_do_twi_transfer(struct at91_twi_dev *dev) | |
382 | { | |
383 | int ret; | |
384 | bool has_unre_flag = dev->pdata->has_unre_flag; | |
385 | ||
386 | dev_dbg(dev->dev, "transfer: %s %d bytes.\n", | |
387 | (dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len); | |
388 | ||
16735d02 | 389 | reinit_completion(&dev->cmd_complete); |
fac368a0 | 390 | dev->transfer_status = 0; |
7c3fe64d LD |
391 | |
392 | if (!dev->buf_len) { | |
393 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_QUICK); | |
394 | at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP); | |
395 | } else if (dev->msg->flags & I2C_M_RD) { | |
fac368a0 NV |
396 | unsigned start_flags = AT91_TWI_START; |
397 | ||
398 | if (at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_RXRDY) { | |
399 | dev_err(dev->dev, "RXRDY still set!"); | |
400 | at91_twi_read(dev, AT91_TWI_RHR); | |
401 | } | |
402 | ||
403 | /* if only one byte is to be read, immediately stop transfer */ | |
404 | if (dev->buf_len <= 1 && !(dev->msg->flags & I2C_M_RECV_LEN)) | |
405 | start_flags |= AT91_TWI_STOP; | |
406 | at91_twi_write(dev, AT91_TWI_CR, start_flags); | |
60937b2c LD |
407 | /* |
408 | * When using dma, the last byte has to be read manually in | |
409 | * order to not send the stop command too late and then | |
410 | * to receive extra data. In practice, there are some issues | |
411 | * if you use the dma to read n-1 bytes because of latency. | |
412 | * Reading n-2 bytes with dma and the two last ones manually | |
413 | * seems to be the best solution. | |
414 | */ | |
415 | if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) { | |
416 | at91_twi_read_data_dma(dev); | |
417 | /* | |
418 | * It is important to enable TXCOMP irq here because | |
419 | * doing it only when transferring the last two bytes | |
420 | * will mask NACK errors since TXCOMP is set when a | |
421 | * NACK occurs. | |
422 | */ | |
423 | at91_twi_write(dev, AT91_TWI_IER, | |
424 | AT91_TWI_TXCOMP); | |
425 | } else | |
426 | at91_twi_write(dev, AT91_TWI_IER, | |
fac368a0 NV |
427 | AT91_TWI_TXCOMP | AT91_TWI_RXRDY); |
428 | } else { | |
60937b2c LD |
429 | if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) { |
430 | at91_twi_write_data_dma(dev); | |
431 | at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP); | |
432 | } else { | |
433 | at91_twi_write_next_byte(dev); | |
434 | at91_twi_write(dev, AT91_TWI_IER, | |
435 | AT91_TWI_TXCOMP | AT91_TWI_TXRDY); | |
436 | } | |
fac368a0 NV |
437 | } |
438 | ||
11cfbfb0 | 439 | ret = wait_for_completion_timeout(&dev->cmd_complete, |
6721f28a | 440 | dev->adapter.timeout); |
fac368a0 NV |
441 | if (ret == 0) { |
442 | dev_err(dev->dev, "controller timed out\n"); | |
443 | at91_init_twi_bus(dev); | |
60937b2c LD |
444 | ret = -ETIMEDOUT; |
445 | goto error; | |
fac368a0 NV |
446 | } |
447 | if (dev->transfer_status & AT91_TWI_NACK) { | |
448 | dev_dbg(dev->dev, "received nack\n"); | |
60937b2c LD |
449 | ret = -EREMOTEIO; |
450 | goto error; | |
fac368a0 NV |
451 | } |
452 | if (dev->transfer_status & AT91_TWI_OVRE) { | |
453 | dev_err(dev->dev, "overrun while reading\n"); | |
60937b2c LD |
454 | ret = -EIO; |
455 | goto error; | |
fac368a0 NV |
456 | } |
457 | if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) { | |
458 | dev_err(dev->dev, "underrun while writing\n"); | |
60937b2c LD |
459 | ret = -EIO; |
460 | goto error; | |
fac368a0 | 461 | } |
75b81f33 MR |
462 | if (dev->recv_len_abort) { |
463 | dev_err(dev->dev, "invalid smbus block length recvd\n"); | |
464 | ret = -EPROTO; | |
465 | goto error; | |
466 | } | |
467 | ||
fac368a0 NV |
468 | dev_dbg(dev->dev, "transfer complete\n"); |
469 | ||
470 | return 0; | |
60937b2c LD |
471 | |
472 | error: | |
473 | at91_twi_dma_cleanup(dev); | |
474 | return ret; | |
fac368a0 NV |
475 | } |
476 | ||
477 | static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num) | |
478 | { | |
479 | struct at91_twi_dev *dev = i2c_get_adapdata(adap); | |
480 | int ret; | |
481 | unsigned int_addr_flag = 0; | |
482 | struct i2c_msg *m_start = msg; | |
483 | ||
484 | dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num); | |
485 | ||
d64a8188 WY |
486 | ret = pm_runtime_get_sync(dev->dev); |
487 | if (ret < 0) | |
488 | goto out; | |
489 | ||
fac368a0 NV |
490 | /* |
491 | * The hardware can handle at most two messages concatenated by a | |
492 | * repeated start via it's internal address feature. | |
493 | */ | |
494 | if (num > 2) { | |
495 | dev_err(dev->dev, | |
496 | "cannot handle more than two concatenated messages.\n"); | |
d64a8188 WY |
497 | ret = 0; |
498 | goto out; | |
fac368a0 NV |
499 | } else if (num == 2) { |
500 | int internal_address = 0; | |
501 | int i; | |
502 | ||
503 | if (msg->flags & I2C_M_RD) { | |
504 | dev_err(dev->dev, "first transfer must be write.\n"); | |
d64a8188 WY |
505 | ret = -EINVAL; |
506 | goto out; | |
fac368a0 NV |
507 | } |
508 | if (msg->len > 3) { | |
509 | dev_err(dev->dev, "first message size must be <= 3.\n"); | |
d64a8188 WY |
510 | ret = -EINVAL; |
511 | goto out; | |
fac368a0 NV |
512 | } |
513 | ||
514 | /* 1st msg is put into the internal address, start with 2nd */ | |
515 | m_start = &msg[1]; | |
516 | for (i = 0; i < msg->len; ++i) { | |
517 | const unsigned addr = msg->buf[msg->len - 1 - i]; | |
518 | ||
519 | internal_address |= addr << (8 * i); | |
520 | int_addr_flag += AT91_TWI_IADRSZ_1; | |
521 | } | |
522 | at91_twi_write(dev, AT91_TWI_IADR, internal_address); | |
523 | } | |
524 | ||
525 | at91_twi_write(dev, AT91_TWI_MMR, (m_start->addr << 16) | int_addr_flag | |
526 | | ((m_start->flags & I2C_M_RD) ? AT91_TWI_MREAD : 0)); | |
527 | ||
528 | dev->buf_len = m_start->len; | |
529 | dev->buf = m_start->buf; | |
530 | dev->msg = m_start; | |
75b81f33 | 531 | dev->recv_len_abort = false; |
fac368a0 NV |
532 | |
533 | ret = at91_do_twi_transfer(dev); | |
534 | ||
d64a8188 WY |
535 | ret = (ret < 0) ? ret : num; |
536 | out: | |
537 | pm_runtime_mark_last_busy(dev->dev); | |
538 | pm_runtime_put_autosuspend(dev->dev); | |
539 | ||
540 | return ret; | |
fac368a0 NV |
541 | } |
542 | ||
543 | static u32 at91_twi_func(struct i2c_adapter *adapter) | |
544 | { | |
545 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | |
546 | | I2C_FUNC_SMBUS_READ_BLOCK_DATA; | |
547 | } | |
548 | ||
549 | static struct i2c_algorithm at91_twi_algorithm = { | |
550 | .master_xfer = at91_twi_xfer, | |
551 | .functionality = at91_twi_func, | |
552 | }; | |
553 | ||
554 | static struct at91_twi_pdata at91rm9200_config = { | |
555 | .clk_max_div = 5, | |
556 | .clk_offset = 3, | |
557 | .has_unre_flag = true, | |
558 | }; | |
559 | ||
560 | static struct at91_twi_pdata at91sam9261_config = { | |
561 | .clk_max_div = 5, | |
562 | .clk_offset = 4, | |
563 | .has_unre_flag = false, | |
564 | }; | |
565 | ||
566 | static struct at91_twi_pdata at91sam9260_config = { | |
567 | .clk_max_div = 7, | |
568 | .clk_offset = 4, | |
569 | .has_unre_flag = false, | |
570 | }; | |
571 | ||
572 | static struct at91_twi_pdata at91sam9g20_config = { | |
573 | .clk_max_div = 7, | |
574 | .clk_offset = 4, | |
575 | .has_unre_flag = false, | |
576 | }; | |
577 | ||
578 | static struct at91_twi_pdata at91sam9g10_config = { | |
579 | .clk_max_div = 7, | |
580 | .clk_offset = 4, | |
581 | .has_unre_flag = false, | |
582 | }; | |
583 | ||
584 | static const struct platform_device_id at91_twi_devtypes[] = { | |
585 | { | |
586 | .name = "i2c-at91rm9200", | |
587 | .driver_data = (unsigned long) &at91rm9200_config, | |
588 | }, { | |
589 | .name = "i2c-at91sam9261", | |
590 | .driver_data = (unsigned long) &at91sam9261_config, | |
591 | }, { | |
592 | .name = "i2c-at91sam9260", | |
593 | .driver_data = (unsigned long) &at91sam9260_config, | |
594 | }, { | |
595 | .name = "i2c-at91sam9g20", | |
596 | .driver_data = (unsigned long) &at91sam9g20_config, | |
597 | }, { | |
598 | .name = "i2c-at91sam9g10", | |
599 | .driver_data = (unsigned long) &at91sam9g10_config, | |
600 | }, { | |
601 | /* sentinel */ | |
602 | } | |
603 | }; | |
604 | ||
70d46a24 | 605 | #if defined(CONFIG_OF) |
4182b434 JE |
606 | static struct at91_twi_pdata at91sam9x5_config = { |
607 | .clk_max_div = 7, | |
608 | .clk_offset = 4, | |
609 | .has_unre_flag = false, | |
4182b434 JE |
610 | }; |
611 | ||
70d46a24 LD |
612 | static const struct of_device_id atmel_twi_dt_ids[] = { |
613 | { | |
631056c3 JE |
614 | .compatible = "atmel,at91rm9200-i2c", |
615 | .data = &at91rm9200_config, | |
616 | } , { | |
70d46a24 LD |
617 | .compatible = "atmel,at91sam9260-i2c", |
618 | .data = &at91sam9260_config, | |
d9a3afc2 | 619 | } , { |
620 | .compatible = "atmel,at91sam9261-i2c", | |
621 | .data = &at91sam9261_config, | |
70d46a24 LD |
622 | } , { |
623 | .compatible = "atmel,at91sam9g20-i2c", | |
624 | .data = &at91sam9g20_config, | |
625 | } , { | |
626 | .compatible = "atmel,at91sam9g10-i2c", | |
627 | .data = &at91sam9g10_config, | |
628 | }, { | |
629 | .compatible = "atmel,at91sam9x5-i2c", | |
630 | .data = &at91sam9x5_config, | |
631 | }, { | |
632 | /* sentinel */ | |
633 | } | |
634 | }; | |
635 | MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids); | |
70d46a24 LD |
636 | #endif |
637 | ||
0b255e92 | 638 | static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr) |
60937b2c LD |
639 | { |
640 | int ret = 0; | |
60937b2c LD |
641 | struct dma_slave_config slave_config; |
642 | struct at91_twi_dma *dma = &dev->dma; | |
60937b2c LD |
643 | |
644 | memset(&slave_config, 0, sizeof(slave_config)); | |
645 | slave_config.src_addr = (dma_addr_t)phy_addr + AT91_TWI_RHR; | |
646 | slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
647 | slave_config.src_maxburst = 1; | |
648 | slave_config.dst_addr = (dma_addr_t)phy_addr + AT91_TWI_THR; | |
649 | slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
650 | slave_config.dst_maxburst = 1; | |
651 | slave_config.device_fc = false; | |
652 | ||
727f9c2d LD |
653 | dma->chan_tx = dma_request_slave_channel_reason(dev->dev, "tx"); |
654 | if (IS_ERR(dma->chan_tx)) { | |
655 | ret = PTR_ERR(dma->chan_tx); | |
656 | dma->chan_tx = NULL; | |
d877a721 LD |
657 | goto error; |
658 | } | |
659 | ||
727f9c2d LD |
660 | dma->chan_rx = dma_request_slave_channel_reason(dev->dev, "rx"); |
661 | if (IS_ERR(dma->chan_rx)) { | |
662 | ret = PTR_ERR(dma->chan_rx); | |
663 | dma->chan_rx = NULL; | |
60937b2c LD |
664 | goto error; |
665 | } | |
666 | ||
667 | slave_config.direction = DMA_MEM_TO_DEV; | |
668 | if (dmaengine_slave_config(dma->chan_tx, &slave_config)) { | |
669 | dev_err(dev->dev, "failed to configure tx channel\n"); | |
670 | ret = -EINVAL; | |
671 | goto error; | |
672 | } | |
673 | ||
674 | slave_config.direction = DMA_DEV_TO_MEM; | |
675 | if (dmaengine_slave_config(dma->chan_rx, &slave_config)) { | |
676 | dev_err(dev->dev, "failed to configure rx channel\n"); | |
677 | ret = -EINVAL; | |
678 | goto error; | |
679 | } | |
680 | ||
681 | sg_init_table(&dma->sg, 1); | |
682 | dma->buf_mapped = false; | |
683 | dma->xfer_in_progress = false; | |
727f9c2d | 684 | dev->use_dma = true; |
60937b2c LD |
685 | |
686 | dev_info(dev->dev, "using %s (tx) and %s (rx) for DMA transfers\n", | |
687 | dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); | |
688 | ||
689 | return ret; | |
690 | ||
691 | error: | |
727f9c2d LD |
692 | if (ret != -EPROBE_DEFER) |
693 | dev_info(dev->dev, "can't use DMA, error %d\n", ret); | |
60937b2c LD |
694 | if (dma->chan_rx) |
695 | dma_release_channel(dma->chan_rx); | |
696 | if (dma->chan_tx) | |
697 | dma_release_channel(dma->chan_tx); | |
698 | return ret; | |
699 | } | |
700 | ||
0b255e92 | 701 | static struct at91_twi_pdata *at91_twi_get_driver_data( |
70d46a24 LD |
702 | struct platform_device *pdev) |
703 | { | |
704 | if (pdev->dev.of_node) { | |
705 | const struct of_device_id *match; | |
706 | match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node); | |
707 | if (!match) | |
708 | return NULL; | |
cd32e6cc | 709 | return (struct at91_twi_pdata *)match->data; |
70d46a24 LD |
710 | } |
711 | return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data; | |
712 | } | |
713 | ||
0b255e92 | 714 | static int at91_twi_probe(struct platform_device *pdev) |
fac368a0 NV |
715 | { |
716 | struct at91_twi_dev *dev; | |
717 | struct resource *mem; | |
718 | int rc; | |
60937b2c | 719 | u32 phy_addr; |
75b6c4b6 | 720 | u32 bus_clk_rate; |
fac368a0 NV |
721 | |
722 | dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); | |
723 | if (!dev) | |
724 | return -ENOMEM; | |
725 | init_completion(&dev->cmd_complete); | |
726 | dev->dev = &pdev->dev; | |
727 | ||
728 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
729 | if (!mem) | |
730 | return -ENODEV; | |
60937b2c | 731 | phy_addr = mem->start; |
fac368a0 NV |
732 | |
733 | dev->pdata = at91_twi_get_driver_data(pdev); | |
734 | if (!dev->pdata) | |
735 | return -ENODEV; | |
736 | ||
84dbf809 TR |
737 | dev->base = devm_ioremap_resource(&pdev->dev, mem); |
738 | if (IS_ERR(dev->base)) | |
739 | return PTR_ERR(dev->base); | |
fac368a0 NV |
740 | |
741 | dev->irq = platform_get_irq(pdev, 0); | |
742 | if (dev->irq < 0) | |
743 | return dev->irq; | |
744 | ||
745 | rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0, | |
746 | dev_name(dev->dev), dev); | |
747 | if (rc) { | |
748 | dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc); | |
749 | return rc; | |
750 | } | |
751 | ||
752 | platform_set_drvdata(pdev, dev); | |
753 | ||
754 | dev->clk = devm_clk_get(dev->dev, NULL); | |
755 | if (IS_ERR(dev->clk)) { | |
756 | dev_err(dev->dev, "no clock defined\n"); | |
757 | return -ENODEV; | |
758 | } | |
759 | clk_prepare_enable(dev->clk); | |
760 | ||
dc6df6e9 | 761 | if (dev->dev->of_node) { |
727f9c2d LD |
762 | rc = at91_twi_configure_dma(dev, phy_addr); |
763 | if (rc == -EPROBE_DEFER) | |
764 | return rc; | |
60937b2c LD |
765 | } |
766 | ||
75b6c4b6 MR |
767 | rc = of_property_read_u32(dev->dev->of_node, "clock-frequency", |
768 | &bus_clk_rate); | |
769 | if (rc) | |
770 | bus_clk_rate = DEFAULT_TWI_CLK_HZ; | |
771 | ||
772 | at91_calc_twi_clock(dev, bus_clk_rate); | |
fac368a0 NV |
773 | at91_init_twi_bus(dev); |
774 | ||
775 | snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91"); | |
776 | i2c_set_adapdata(&dev->adapter, dev); | |
777 | dev->adapter.owner = THIS_MODULE; | |
b850579a | 778 | dev->adapter.class = I2C_CLASS_DEPRECATED; |
fac368a0 NV |
779 | dev->adapter.algo = &at91_twi_algorithm; |
780 | dev->adapter.dev.parent = dev->dev; | |
781 | dev->adapter.nr = pdev->id; | |
782 | dev->adapter.timeout = AT91_I2C_TIMEOUT; | |
70d46a24 | 783 | dev->adapter.dev.of_node = pdev->dev.of_node; |
fac368a0 | 784 | |
d64a8188 WY |
785 | pm_runtime_set_autosuspend_delay(dev->dev, AUTOSUSPEND_TIMEOUT); |
786 | pm_runtime_use_autosuspend(dev->dev); | |
787 | pm_runtime_set_active(dev->dev); | |
788 | pm_runtime_enable(dev->dev); | |
789 | ||
fac368a0 NV |
790 | rc = i2c_add_numbered_adapter(&dev->adapter); |
791 | if (rc) { | |
792 | dev_err(dev->dev, "Adapter %s registration failed\n", | |
793 | dev->adapter.name); | |
794 | clk_disable_unprepare(dev->clk); | |
d64a8188 WY |
795 | |
796 | pm_runtime_disable(dev->dev); | |
797 | pm_runtime_set_suspended(dev->dev); | |
798 | ||
fac368a0 NV |
799 | return rc; |
800 | } | |
801 | ||
802 | dev_info(dev->dev, "AT91 i2c bus driver.\n"); | |
803 | return 0; | |
804 | } | |
805 | ||
0b255e92 | 806 | static int at91_twi_remove(struct platform_device *pdev) |
fac368a0 NV |
807 | { |
808 | struct at91_twi_dev *dev = platform_get_drvdata(pdev); | |
fac368a0 | 809 | |
bf51a8c5 | 810 | i2c_del_adapter(&dev->adapter); |
fac368a0 NV |
811 | clk_disable_unprepare(dev->clk); |
812 | ||
d64a8188 WY |
813 | pm_runtime_disable(dev->dev); |
814 | pm_runtime_set_suspended(dev->dev); | |
815 | ||
bf51a8c5 | 816 | return 0; |
fac368a0 NV |
817 | } |
818 | ||
819 | #ifdef CONFIG_PM | |
820 | ||
821 | static int at91_twi_runtime_suspend(struct device *dev) | |
822 | { | |
823 | struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); | |
824 | ||
d64a8188 | 825 | clk_disable_unprepare(twi_dev->clk); |
fac368a0 | 826 | |
62d10c40 WY |
827 | pinctrl_pm_select_sleep_state(dev); |
828 | ||
fac368a0 NV |
829 | return 0; |
830 | } | |
831 | ||
832 | static int at91_twi_runtime_resume(struct device *dev) | |
833 | { | |
834 | struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); | |
835 | ||
62d10c40 WY |
836 | pinctrl_pm_select_default_state(dev); |
837 | ||
d64a8188 | 838 | return clk_prepare_enable(twi_dev->clk); |
fac368a0 NV |
839 | } |
840 | ||
36765293 WY |
841 | static int at91_twi_suspend_noirq(struct device *dev) |
842 | { | |
843 | if (!pm_runtime_status_suspended(dev)) | |
844 | at91_twi_runtime_suspend(dev); | |
845 | ||
846 | return 0; | |
847 | } | |
848 | ||
849 | static int at91_twi_resume_noirq(struct device *dev) | |
850 | { | |
851 | int ret; | |
852 | ||
853 | if (!pm_runtime_status_suspended(dev)) { | |
854 | ret = at91_twi_runtime_resume(dev); | |
855 | if (ret) | |
856 | return ret; | |
857 | } | |
858 | ||
859 | pm_runtime_mark_last_busy(dev); | |
860 | pm_request_autosuspend(dev); | |
861 | ||
862 | return 0; | |
863 | } | |
864 | ||
fac368a0 | 865 | static const struct dev_pm_ops at91_twi_pm = { |
36765293 WY |
866 | .suspend_noirq = at91_twi_suspend_noirq, |
867 | .resume_noirq = at91_twi_resume_noirq, | |
fac368a0 NV |
868 | .runtime_suspend = at91_twi_runtime_suspend, |
869 | .runtime_resume = at91_twi_runtime_resume, | |
870 | }; | |
871 | ||
872 | #define at91_twi_pm_ops (&at91_twi_pm) | |
873 | #else | |
874 | #define at91_twi_pm_ops NULL | |
875 | #endif | |
876 | ||
877 | static struct platform_driver at91_twi_driver = { | |
878 | .probe = at91_twi_probe, | |
0b255e92 | 879 | .remove = at91_twi_remove, |
fac368a0 NV |
880 | .id_table = at91_twi_devtypes, |
881 | .driver = { | |
882 | .name = "at91_i2c", | |
600abead | 883 | .of_match_table = of_match_ptr(atmel_twi_dt_ids), |
fac368a0 NV |
884 | .pm = at91_twi_pm_ops, |
885 | }, | |
886 | }; | |
887 | ||
888 | static int __init at91_twi_init(void) | |
889 | { | |
890 | return platform_driver_register(&at91_twi_driver); | |
891 | } | |
892 | ||
893 | static void __exit at91_twi_exit(void) | |
894 | { | |
895 | platform_driver_unregister(&at91_twi_driver); | |
896 | } | |
897 | ||
898 | subsys_initcall(at91_twi_init); | |
899 | module_exit(at91_twi_exit); | |
900 | ||
901 | MODULE_AUTHOR("Nikolaus Voss <n.voss@weinmann.de>"); | |
902 | MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91"); | |
903 | MODULE_LICENSE("GPL"); | |
904 | MODULE_ALIAS("platform:at91_i2c"); |