Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface | |
3 | * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com> | |
4 | * | |
5 | * 2.6 port by Matt Porter <mporter@kernel.crashing.org> | |
6 | * | |
7 | * The documentation describes this as an SMBus controller, but it doesn't | |
8 | * understand any of the SMBus protocol in hardware. It's really an I2C | |
9 | * controller that could emulate most of the SMBus in software. | |
10 | * | |
11 | * This is just a skeleton adapter to use with the Au1550 PSC | |
12 | * algorithm. It was developed for the Pb1550, but will work with | |
13 | * any Au1550 board that has a similar PSC configuration. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version 2 | |
18 | * of the License, or (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
1da177e4 LT |
24 | */ |
25 | ||
1da177e4 LT |
26 | #include <linux/delay.h> |
27 | #include <linux/kernel.h> | |
28 | #include <linux/module.h> | |
8b798c4d | 29 | #include <linux/platform_device.h> |
1da177e4 LT |
30 | #include <linux/errno.h> |
31 | #include <linux/i2c.h> | |
8b798c4d | 32 | #include <linux/slab.h> |
1da177e4 | 33 | |
50d5676e | 34 | #include <asm/mach-au1x00/au1000.h> |
1da177e4 LT |
35 | #include <asm/mach-au1x00/au1xxx_psc.h> |
36 | ||
c5de6467 ML |
37 | #define PSC_SEL 0x00 |
38 | #define PSC_CTRL 0x04 | |
39 | #define PSC_SMBCFG 0x08 | |
40 | #define PSC_SMBMSK 0x0C | |
41 | #define PSC_SMBPCR 0x10 | |
42 | #define PSC_SMBSTAT 0x14 | |
43 | #define PSC_SMBEVNT 0x18 | |
44 | #define PSC_SMBTXRX 0x1C | |
45 | #define PSC_SMBTMR 0x20 | |
46 | ||
8b798c4d | 47 | struct i2c_au1550_data { |
c5de6467 | 48 | void __iomem *psc_base; |
8b798c4d | 49 | int xfer_timeout; |
8b798c4d ML |
50 | struct i2c_adapter adap; |
51 | struct resource *ioarea; | |
52 | }; | |
1da177e4 | 53 | |
c5de6467 | 54 | static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v) |
1da177e4 | 55 | { |
c5de6467 ML |
56 | __raw_writel(v, a->psc_base + r); |
57 | wmb(); | |
58 | } | |
1da177e4 | 59 | |
c5de6467 ML |
60 | static inline unsigned long RD(struct i2c_au1550_data *a, int r) |
61 | { | |
62 | return __raw_readl(a->psc_base + r); | |
63 | } | |
1da177e4 | 64 | |
c5de6467 ML |
65 | static int wait_xfer_done(struct i2c_au1550_data *adap) |
66 | { | |
67 | int i; | |
68 | ||
69 | /* Wait for Tx Buffer Empty */ | |
1da177e4 | 70 | for (i = 0; i < adap->xfer_timeout; i++) { |
c5de6467 | 71 | if (RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_TE) |
1da177e4 | 72 | return 0; |
a202707e | 73 | |
1da177e4 LT |
74 | udelay(1); |
75 | } | |
76 | ||
77 | return -ETIMEDOUT; | |
78 | } | |
79 | ||
c5de6467 | 80 | static int wait_ack(struct i2c_au1550_data *adap) |
1da177e4 | 81 | { |
c5de6467 | 82 | unsigned long stat; |
1da177e4 LT |
83 | |
84 | if (wait_xfer_done(adap)) | |
85 | return -ETIMEDOUT; | |
86 | ||
c5de6467 | 87 | stat = RD(adap, PSC_SMBEVNT); |
1da177e4 LT |
88 | if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0) |
89 | return -ETIMEDOUT; | |
90 | ||
91 | return 0; | |
92 | } | |
93 | ||
c5de6467 | 94 | static int wait_master_done(struct i2c_au1550_data *adap) |
1da177e4 | 95 | { |
c5de6467 | 96 | int i; |
1da177e4 | 97 | |
c5de6467 | 98 | /* Wait for Master Done. */ |
84785f12 | 99 | for (i = 0; i < 2 * adap->xfer_timeout; i++) { |
c5de6467 | 100 | if ((RD(adap, PSC_SMBEVNT) & PSC_SMBEVNT_MD) != 0) |
1da177e4 LT |
101 | return 0; |
102 | udelay(1); | |
103 | } | |
104 | ||
105 | return -ETIMEDOUT; | |
106 | } | |
107 | ||
108 | static int | |
91f27958 | 109 | do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q) |
1da177e4 | 110 | { |
c5de6467 | 111 | unsigned long stat; |
1da177e4 | 112 | |
c5de6467 ML |
113 | /* Reset the FIFOs, clear events. */ |
114 | stat = RD(adap, PSC_SMBSTAT); | |
115 | WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR); | |
8859942e DP |
116 | |
117 | if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) { | |
c5de6467 ML |
118 | WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC); |
119 | while ((RD(adap, PSC_SMBPCR) & PSC_SMBPCR_DC) != 0) | |
120 | cpu_relax(); | |
8859942e DP |
121 | udelay(50); |
122 | } | |
1da177e4 | 123 | |
c5de6467 | 124 | /* Write out the i2c chip address and specify operation */ |
1da177e4 LT |
125 | addr <<= 1; |
126 | if (rd) | |
127 | addr |= 1; | |
128 | ||
91f27958 ML |
129 | /* zero-byte xfers stop immediately */ |
130 | if (q) | |
131 | addr |= PSC_SMBTXRX_STP; | |
132 | ||
c5de6467 ML |
133 | /* Put byte into fifo, start up master. */ |
134 | WR(adap, PSC_SMBTXRX, addr); | |
135 | WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS); | |
1da177e4 LT |
136 | if (wait_ack(adap)) |
137 | return -EIO; | |
91f27958 | 138 | return (q) ? wait_master_done(adap) : 0; |
1da177e4 LT |
139 | } |
140 | ||
c5de6467 | 141 | static int wait_for_rx_byte(struct i2c_au1550_data *adap, unsigned char *out) |
1da177e4 | 142 | { |
c5de6467 | 143 | int j; |
1da177e4 LT |
144 | |
145 | if (wait_xfer_done(adap)) | |
146 | return -EIO; | |
147 | ||
1da177e4 LT |
148 | j = adap->xfer_timeout * 100; |
149 | do { | |
150 | j--; | |
151 | if (j <= 0) | |
152 | return -EIO; | |
153 | ||
c5de6467 | 154 | if ((RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_RE) == 0) |
1da177e4 LT |
155 | j = 0; |
156 | else | |
157 | udelay(1); | |
158 | } while (j > 0); | |
c5de6467 ML |
159 | |
160 | *out = RD(adap, PSC_SMBTXRX); | |
1da177e4 LT |
161 | |
162 | return 0; | |
163 | } | |
164 | ||
c5de6467 | 165 | static int i2c_read(struct i2c_au1550_data *adap, unsigned char *buf, |
1da177e4 LT |
166 | unsigned int len) |
167 | { | |
c5de6467 | 168 | int i; |
1da177e4 LT |
169 | |
170 | if (len == 0) | |
171 | return 0; | |
172 | ||
173 | /* A read is performed by stuffing the transmit fifo with | |
174 | * zero bytes for timing, waiting for bytes to appear in the | |
175 | * receive fifo, then reading the bytes. | |
176 | */ | |
1da177e4 | 177 | i = 0; |
c5de6467 ML |
178 | while (i < (len - 1)) { |
179 | WR(adap, PSC_SMBTXRX, 0); | |
180 | if (wait_for_rx_byte(adap, &buf[i])) | |
1da177e4 LT |
181 | return -EIO; |
182 | ||
1da177e4 LT |
183 | i++; |
184 | } | |
185 | ||
c5de6467 ML |
186 | /* The last byte has to indicate transfer done. */ |
187 | WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP); | |
1da177e4 LT |
188 | if (wait_master_done(adap)) |
189 | return -EIO; | |
190 | ||
c5de6467 | 191 | buf[i] = (unsigned char)(RD(adap, PSC_SMBTXRX) & 0xff); |
1da177e4 LT |
192 | return 0; |
193 | } | |
194 | ||
c5de6467 | 195 | static int i2c_write(struct i2c_au1550_data *adap, unsigned char *buf, |
1da177e4 LT |
196 | unsigned int len) |
197 | { | |
c5de6467 ML |
198 | int i; |
199 | unsigned long data; | |
1da177e4 LT |
200 | |
201 | if (len == 0) | |
202 | return 0; | |
203 | ||
1da177e4 LT |
204 | i = 0; |
205 | while (i < (len-1)) { | |
206 | data = buf[i]; | |
c5de6467 | 207 | WR(adap, PSC_SMBTXRX, data); |
1da177e4 LT |
208 | if (wait_ack(adap)) |
209 | return -EIO; | |
210 | i++; | |
211 | } | |
212 | ||
c5de6467 | 213 | /* The last byte has to indicate transfer done. */ |
1da177e4 LT |
214 | data = buf[i]; |
215 | data |= PSC_SMBTXRX_STP; | |
c5de6467 | 216 | WR(adap, PSC_SMBTXRX, data); |
1da177e4 LT |
217 | if (wait_master_done(adap)) |
218 | return -EIO; | |
219 | return 0; | |
220 | } | |
221 | ||
222 | static int | |
223 | au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) | |
224 | { | |
225 | struct i2c_au1550_data *adap = i2c_adap->algo_data; | |
226 | struct i2c_msg *p; | |
227 | int i, err = 0; | |
228 | ||
c5de6467 | 229 | WR(adap, PSC_CTRL, PSC_CTRL_ENABLE); |
f09f71b2 | 230 | |
1da177e4 LT |
231 | for (i = 0; !err && i < num; i++) { |
232 | p = &msgs[i]; | |
91f27958 ML |
233 | err = do_address(adap, p->addr, p->flags & I2C_M_RD, |
234 | (p->len == 0)); | |
1da177e4 LT |
235 | if (err || !p->len) |
236 | continue; | |
237 | if (p->flags & I2C_M_RD) | |
238 | err = i2c_read(adap, p->buf, p->len); | |
239 | else | |
240 | err = i2c_write(adap, p->buf, p->len); | |
241 | } | |
242 | ||
243 | /* Return the number of messages processed, or the error code. | |
244 | */ | |
245 | if (err == 0) | |
246 | err = num; | |
f09f71b2 | 247 | |
c5de6467 | 248 | WR(adap, PSC_CTRL, PSC_CTRL_SUSPEND); |
f09f71b2 | 249 | |
1da177e4 LT |
250 | return err; |
251 | } | |
252 | ||
c5de6467 | 253 | static u32 au1550_func(struct i2c_adapter *adap) |
1da177e4 | 254 | { |
6ed07134 | 255 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
1da177e4 LT |
256 | } |
257 | ||
8f9082c5 | 258 | static const struct i2c_algorithm au1550_algo = { |
1da177e4 LT |
259 | .master_xfer = au1550_xfer, |
260 | .functionality = au1550_func, | |
261 | }; | |
262 | ||
f09f71b2 ML |
263 | static void i2c_au1550_setup(struct i2c_au1550_data *priv) |
264 | { | |
c5de6467 | 265 | unsigned long cfg; |
f09f71b2 | 266 | |
c5de6467 ML |
267 | WR(priv, PSC_CTRL, PSC_CTRL_DISABLE); |
268 | WR(priv, PSC_SEL, PSC_SEL_PS_SMBUSMODE); | |
269 | WR(priv, PSC_SMBCFG, 0); | |
270 | WR(priv, PSC_CTRL, PSC_CTRL_ENABLE); | |
271 | while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0) | |
272 | cpu_relax(); | |
273 | ||
274 | cfg = PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 | PSC_SMBCFG_DD_DISABLE; | |
275 | WR(priv, PSC_SMBCFG, cfg); | |
f09f71b2 ML |
276 | |
277 | /* Divide by 8 to get a 6.25 MHz clock. The later protocol | |
278 | * timings are based on this clock. | |
279 | */ | |
c5de6467 ML |
280 | cfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8); |
281 | WR(priv, PSC_SMBCFG, cfg); | |
282 | WR(priv, PSC_SMBMSK, PSC_SMBMSK_ALLMASK); | |
f09f71b2 ML |
283 | |
284 | /* Set the protocol timer values. See Table 71 in the | |
285 | * Au1550 Data Book for standard timing values. | |
286 | */ | |
c5de6467 | 287 | WR(priv, PSC_SMBTMR, PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(15) | \ |
f09f71b2 ML |
288 | PSC_SMBTMR_SET_PU(15) | PSC_SMBTMR_SET_SH(15) | \ |
289 | PSC_SMBTMR_SET_SU(15) | PSC_SMBTMR_SET_CL(15) | \ | |
c5de6467 | 290 | PSC_SMBTMR_SET_CH(15)); |
f09f71b2 | 291 | |
c5de6467 ML |
292 | cfg |= PSC_SMBCFG_DE_ENABLE; |
293 | WR(priv, PSC_SMBCFG, cfg); | |
294 | while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0) | |
295 | cpu_relax(); | |
f09f71b2 | 296 | |
c5de6467 | 297 | WR(priv, PSC_CTRL, PSC_CTRL_SUSPEND); |
f09f71b2 ML |
298 | } |
299 | ||
300 | static void i2c_au1550_disable(struct i2c_au1550_data *priv) | |
301 | { | |
c5de6467 ML |
302 | WR(priv, PSC_SMBCFG, 0); |
303 | WR(priv, PSC_CTRL, PSC_CTRL_DISABLE); | |
f09f71b2 ML |
304 | } |
305 | ||
1da177e4 LT |
306 | /* |
307 | * registering functions to load algorithms at runtime | |
308 | * Prior to calling us, the 50MHz clock frequency and routing | |
309 | * must have been set up for the PSC indicated by the adapter. | |
310 | */ | |
0b255e92 | 311 | static int |
8b798c4d | 312 | i2c_au1550_probe(struct platform_device *pdev) |
1da177e4 | 313 | { |
8b798c4d | 314 | struct i2c_au1550_data *priv; |
8b798c4d | 315 | struct resource *r; |
8b798c4d ML |
316 | int ret; |
317 | ||
318 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
319 | if (!r) { | |
320 | ret = -ENODEV; | |
321 | goto out; | |
322 | } | |
1da177e4 | 323 | |
8b798c4d ML |
324 | priv = kzalloc(sizeof(struct i2c_au1550_data), GFP_KERNEL); |
325 | if (!priv) { | |
326 | ret = -ENOMEM; | |
327 | goto out; | |
328 | } | |
329 | ||
c6ffddea | 330 | priv->ioarea = request_mem_region(r->start, resource_size(r), |
8b798c4d ML |
331 | pdev->name); |
332 | if (!priv->ioarea) { | |
333 | ret = -EBUSY; | |
334 | goto out_mem; | |
335 | } | |
336 | ||
c5de6467 ML |
337 | priv->psc_base = ioremap(r->start, resource_size(r)); |
338 | if (!priv->psc_base) { | |
339 | ret = -EIO; | |
340 | goto out_map; | |
341 | } | |
8b798c4d | 342 | priv->xfer_timeout = 200; |
8b798c4d | 343 | |
8b798c4d ML |
344 | priv->adap.nr = pdev->id; |
345 | priv->adap.algo = &au1550_algo; | |
346 | priv->adap.algo_data = priv; | |
347 | priv->adap.dev.parent = &pdev->dev; | |
348 | strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name)); | |
1da177e4 | 349 | |
c5de6467 | 350 | /* Now, set up the PSC for SMBus PIO mode. */ |
f09f71b2 | 351 | i2c_au1550_setup(priv); |
1da177e4 | 352 | |
8b798c4d ML |
353 | ret = i2c_add_numbered_adapter(&priv->adap); |
354 | if (ret == 0) { | |
355 | platform_set_drvdata(pdev, priv); | |
356 | return 0; | |
357 | } | |
358 | ||
f09f71b2 | 359 | i2c_au1550_disable(priv); |
c5de6467 ML |
360 | iounmap(priv->psc_base); |
361 | out_map: | |
8b798c4d ML |
362 | release_resource(priv->ioarea); |
363 | kfree(priv->ioarea); | |
364 | out_mem: | |
365 | kfree(priv); | |
366 | out: | |
367 | return ret; | |
368 | } | |
1da177e4 | 369 | |
0b255e92 | 370 | static int i2c_au1550_remove(struct platform_device *pdev) |
1da177e4 | 371 | { |
8b798c4d | 372 | struct i2c_au1550_data *priv = platform_get_drvdata(pdev); |
8b798c4d | 373 | |
8b798c4d | 374 | i2c_del_adapter(&priv->adap); |
f09f71b2 | 375 | i2c_au1550_disable(priv); |
c5de6467 | 376 | iounmap(priv->psc_base); |
8b798c4d ML |
377 | release_resource(priv->ioarea); |
378 | kfree(priv->ioarea); | |
379 | kfree(priv); | |
380 | return 0; | |
1da177e4 LT |
381 | } |
382 | ||
f09f71b2 | 383 | #ifdef CONFIG_PM |
46f344e2 | 384 | static int i2c_au1550_suspend(struct device *dev) |
1da177e4 | 385 | { |
46f344e2 | 386 | struct i2c_au1550_data *priv = dev_get_drvdata(dev); |
8b798c4d | 387 | |
f09f71b2 ML |
388 | i2c_au1550_disable(priv); |
389 | ||
1da177e4 LT |
390 | return 0; |
391 | } | |
392 | ||
46f344e2 | 393 | static int i2c_au1550_resume(struct device *dev) |
1da177e4 | 394 | { |
46f344e2 | 395 | struct i2c_au1550_data *priv = dev_get_drvdata(dev); |
8b798c4d | 396 | |
f09f71b2 ML |
397 | i2c_au1550_setup(priv); |
398 | ||
1da177e4 LT |
399 | return 0; |
400 | } | |
46f344e2 ML |
401 | |
402 | static const struct dev_pm_ops i2c_au1550_pmops = { | |
403 | .suspend = i2c_au1550_suspend, | |
404 | .resume = i2c_au1550_resume, | |
405 | }; | |
406 | ||
407 | #define AU1XPSC_SMBUS_PMOPS (&i2c_au1550_pmops) | |
408 | ||
f09f71b2 | 409 | #else |
46f344e2 | 410 | #define AU1XPSC_SMBUS_PMOPS NULL |
f09f71b2 | 411 | #endif |
1da177e4 | 412 | |
8b798c4d ML |
413 | static struct platform_driver au1xpsc_smbus_driver = { |
414 | .driver = { | |
415 | .name = "au1xpsc_smbus", | |
46f344e2 | 416 | .pm = AU1XPSC_SMBUS_PMOPS, |
8b798c4d ML |
417 | }, |
418 | .probe = i2c_au1550_probe, | |
0b255e92 | 419 | .remove = i2c_au1550_remove, |
1da177e4 LT |
420 | }; |
421 | ||
a3664b51 | 422 | module_platform_driver(au1xpsc_smbus_driver); |
1da177e4 LT |
423 | |
424 | MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC."); | |
425 | MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550"); | |
426 | MODULE_LICENSE("GPL"); | |
add8eda7 | 427 | MODULE_ALIAS("platform:au1xpsc_smbus"); |