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d24ecfcc BW |
1 | /* |
2 | * drivers/i2c/busses/i2c-bfin-twi.c | |
3 | * | |
4 | * Description: Driver for Blackfin Two Wire Interface | |
5 | * | |
6 | * Author: sonicz <sonic.zhang@analog.com> | |
7 | * | |
8 | * Copyright (c) 2005-2007 Analog Devices, Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <linux/module.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/i2c.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/timer.h> | |
31 | #include <linux/spinlock.h> | |
32 | #include <linux/completion.h> | |
33 | #include <linux/interrupt.h> | |
34 | #include <linux/platform_device.h> | |
35 | ||
36 | #include <asm/blackfin.h> | |
37 | #include <asm/irq.h> | |
38 | ||
39 | #define POLL_TIMEOUT (2 * HZ) | |
40 | ||
41 | /* SMBus mode*/ | |
42 | #define TWI_I2C_MODE_STANDARD 0x01 | |
43 | #define TWI_I2C_MODE_STANDARDSUB 0x02 | |
44 | #define TWI_I2C_MODE_COMBINED 0x04 | |
45 | ||
46 | struct bfin_twi_iface { | |
d24ecfcc BW |
47 | int irq; |
48 | spinlock_t lock; | |
49 | char read_write; | |
50 | u8 command; | |
51 | u8 *transPtr; | |
52 | int readNum; | |
53 | int writeNum; | |
54 | int cur_mode; | |
55 | int manual_stop; | |
56 | int result; | |
57 | int timeout_count; | |
58 | struct timer_list timeout_timer; | |
59 | struct i2c_adapter adap; | |
60 | struct completion complete; | |
61 | }; | |
62 | ||
63 | static struct bfin_twi_iface twi_iface; | |
64 | ||
65 | static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface) | |
66 | { | |
67 | unsigned short twi_int_status = bfin_read_TWI_INT_STAT(); | |
68 | unsigned short mast_stat = bfin_read_TWI_MASTER_STAT(); | |
69 | ||
70 | if (twi_int_status & XMTSERV) { | |
71 | /* Transmit next data */ | |
72 | if (iface->writeNum > 0) { | |
73 | bfin_write_TWI_XMT_DATA8(*(iface->transPtr++)); | |
74 | iface->writeNum--; | |
75 | } | |
76 | /* start receive immediately after complete sending in | |
77 | * combine mode. | |
78 | */ | |
79 | else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { | |
80 | bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | |
81 | | MDIR | RSTART); | |
82 | } else if (iface->manual_stop) | |
83 | bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | |
84 | | STOP); | |
85 | SSYNC(); | |
86 | /* Clear status */ | |
87 | bfin_write_TWI_INT_STAT(XMTSERV); | |
88 | SSYNC(); | |
89 | } | |
90 | if (twi_int_status & RCVSERV) { | |
91 | if (iface->readNum > 0) { | |
92 | /* Receive next data */ | |
93 | *(iface->transPtr) = bfin_read_TWI_RCV_DATA8(); | |
94 | if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { | |
95 | /* Change combine mode into sub mode after | |
96 | * read first data. | |
97 | */ | |
98 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
99 | /* Get read number from first byte in block | |
100 | * combine mode. | |
101 | */ | |
102 | if (iface->readNum == 1 && iface->manual_stop) | |
103 | iface->readNum = *iface->transPtr + 1; | |
104 | } | |
105 | iface->transPtr++; | |
106 | iface->readNum--; | |
107 | } else if (iface->manual_stop) { | |
108 | bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | |
109 | | STOP); | |
110 | SSYNC(); | |
111 | } | |
112 | /* Clear interrupt source */ | |
113 | bfin_write_TWI_INT_STAT(RCVSERV); | |
114 | SSYNC(); | |
115 | } | |
116 | if (twi_int_status & MERR) { | |
117 | bfin_write_TWI_INT_STAT(MERR); | |
118 | bfin_write_TWI_INT_MASK(0); | |
119 | bfin_write_TWI_MASTER_STAT(0x3e); | |
120 | bfin_write_TWI_MASTER_CTL(0); | |
121 | SSYNC(); | |
122 | iface->result = -1; | |
123 | /* if both err and complete int stats are set, return proper | |
124 | * results. | |
125 | */ | |
126 | if (twi_int_status & MCOMP) { | |
127 | bfin_write_TWI_INT_STAT(MCOMP); | |
128 | bfin_write_TWI_INT_MASK(0); | |
129 | bfin_write_TWI_MASTER_CTL(0); | |
130 | SSYNC(); | |
131 | /* If it is a quick transfer, only address bug no data, | |
132 | * not an err, return 1. | |
133 | */ | |
134 | if (iface->writeNum == 0 && (mast_stat & BUFRDERR)) | |
135 | iface->result = 1; | |
136 | /* If address not acknowledged return -1, | |
137 | * else return 0. | |
138 | */ | |
139 | else if (!(mast_stat & ANAK)) | |
140 | iface->result = 0; | |
141 | } | |
142 | complete(&iface->complete); | |
143 | return; | |
144 | } | |
145 | if (twi_int_status & MCOMP) { | |
146 | bfin_write_TWI_INT_STAT(MCOMP); | |
147 | SSYNC(); | |
148 | if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { | |
149 | if (iface->readNum == 0) { | |
150 | /* set the read number to 1 and ask for manual | |
151 | * stop in block combine mode | |
152 | */ | |
153 | iface->readNum = 1; | |
154 | iface->manual_stop = 1; | |
155 | bfin_write_TWI_MASTER_CTL( | |
156 | bfin_read_TWI_MASTER_CTL() | |
157 | | (0xff << 6)); | |
158 | } else { | |
159 | /* set the readd number in other | |
160 | * combine mode. | |
161 | */ | |
162 | bfin_write_TWI_MASTER_CTL( | |
163 | (bfin_read_TWI_MASTER_CTL() & | |
164 | (~(0xff << 6))) | | |
165 | ( iface->readNum << 6)); | |
166 | } | |
167 | /* remove restart bit and enable master receive */ | |
168 | bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() & | |
169 | ~RSTART); | |
170 | bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | | |
171 | MEN | MDIR); | |
172 | SSYNC(); | |
173 | } else { | |
174 | iface->result = 1; | |
175 | bfin_write_TWI_INT_MASK(0); | |
176 | bfin_write_TWI_MASTER_CTL(0); | |
177 | SSYNC(); | |
178 | complete(&iface->complete); | |
179 | } | |
180 | } | |
181 | } | |
182 | ||
183 | /* Interrupt handler */ | |
184 | static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id) | |
185 | { | |
186 | struct bfin_twi_iface *iface = dev_id; | |
187 | unsigned long flags; | |
188 | ||
189 | spin_lock_irqsave(&iface->lock, flags); | |
190 | del_timer(&iface->timeout_timer); | |
191 | bfin_twi_handle_interrupt(iface); | |
192 | spin_unlock_irqrestore(&iface->lock, flags); | |
193 | return IRQ_HANDLED; | |
194 | } | |
195 | ||
196 | static void bfin_twi_timeout(unsigned long data) | |
197 | { | |
198 | struct bfin_twi_iface *iface = (struct bfin_twi_iface *)data; | |
199 | unsigned long flags; | |
200 | ||
201 | spin_lock_irqsave(&iface->lock, flags); | |
202 | bfin_twi_handle_interrupt(iface); | |
203 | if (iface->result == 0) { | |
204 | iface->timeout_count--; | |
205 | if (iface->timeout_count > 0) { | |
206 | iface->timeout_timer.expires = jiffies + POLL_TIMEOUT; | |
207 | add_timer(&iface->timeout_timer); | |
208 | } else { | |
209 | iface->result = -1; | |
210 | complete(&iface->complete); | |
211 | } | |
212 | } | |
213 | spin_unlock_irqrestore(&iface->lock, flags); | |
214 | } | |
215 | ||
216 | /* | |
217 | * Generic i2c master transfer entrypoint | |
218 | */ | |
219 | static int bfin_twi_master_xfer(struct i2c_adapter *adap, | |
220 | struct i2c_msg *msgs, int num) | |
221 | { | |
222 | struct bfin_twi_iface *iface = adap->algo_data; | |
223 | struct i2c_msg *pmsg; | |
224 | int i, ret; | |
225 | int rc = 0; | |
226 | ||
227 | if (!(bfin_read_TWI_CONTROL() & TWI_ENA)) | |
228 | return -ENXIO; | |
229 | ||
d24ecfcc | 230 | while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) { |
d24ecfcc | 231 | yield(); |
d24ecfcc BW |
232 | } |
233 | ||
234 | ret = 0; | |
235 | for (i = 0; rc >= 0 && i < num; i++) { | |
236 | pmsg = &msgs[i]; | |
237 | if (pmsg->flags & I2C_M_TEN) { | |
238 | dev_err(&(adap->dev), "i2c-bfin-twi: 10 bits addr " | |
239 | "not supported !\n"); | |
240 | rc = -EINVAL; | |
241 | break; | |
242 | } | |
243 | ||
244 | iface->cur_mode = TWI_I2C_MODE_STANDARD; | |
245 | iface->manual_stop = 0; | |
246 | iface->transPtr = pmsg->buf; | |
247 | iface->writeNum = iface->readNum = pmsg->len; | |
248 | iface->result = 0; | |
249 | iface->timeout_count = 10; | |
250 | /* Set Transmit device address */ | |
251 | bfin_write_TWI_MASTER_ADDR(pmsg->addr); | |
252 | ||
253 | /* FIFO Initiation. Data in FIFO should be | |
254 | * discarded before start a new operation. | |
255 | */ | |
256 | bfin_write_TWI_FIFO_CTL(0x3); | |
257 | SSYNC(); | |
258 | bfin_write_TWI_FIFO_CTL(0); | |
259 | SSYNC(); | |
260 | ||
261 | if (pmsg->flags & I2C_M_RD) | |
262 | iface->read_write = I2C_SMBUS_READ; | |
263 | else { | |
264 | iface->read_write = I2C_SMBUS_WRITE; | |
265 | /* Transmit first data */ | |
266 | if (iface->writeNum > 0) { | |
267 | bfin_write_TWI_XMT_DATA8(*(iface->transPtr++)); | |
268 | iface->writeNum--; | |
269 | SSYNC(); | |
270 | } | |
271 | } | |
272 | ||
273 | /* clear int stat */ | |
274 | bfin_write_TWI_INT_STAT(MERR|MCOMP|XMTSERV|RCVSERV); | |
275 | ||
276 | /* Interrupt mask . Enable XMT, RCV interrupt */ | |
277 | bfin_write_TWI_INT_MASK(MCOMP | MERR | | |
278 | ((iface->read_write == I2C_SMBUS_READ)? | |
279 | RCVSERV : XMTSERV)); | |
280 | SSYNC(); | |
281 | ||
282 | if (pmsg->len > 0 && pmsg->len <= 255) | |
283 | bfin_write_TWI_MASTER_CTL(pmsg->len << 6); | |
284 | else if (pmsg->len > 255) { | |
285 | bfin_write_TWI_MASTER_CTL(0xff << 6); | |
286 | iface->manual_stop = 1; | |
287 | } else | |
288 | break; | |
289 | ||
290 | iface->timeout_timer.expires = jiffies + POLL_TIMEOUT; | |
291 | add_timer(&iface->timeout_timer); | |
292 | ||
293 | /* Master enable */ | |
294 | bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN | | |
295 | ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | | |
296 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0)); | |
297 | SSYNC(); | |
298 | ||
299 | wait_for_completion(&iface->complete); | |
300 | ||
301 | rc = iface->result; | |
302 | if (rc == 1) | |
303 | ret++; | |
304 | else if (rc == -1) | |
305 | break; | |
306 | } | |
307 | ||
d24ecfcc BW |
308 | return ret; |
309 | } | |
310 | ||
311 | /* | |
312 | * SMBus type transfer entrypoint | |
313 | */ | |
314 | ||
315 | int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr, | |
316 | unsigned short flags, char read_write, | |
317 | u8 command, int size, union i2c_smbus_data *data) | |
318 | { | |
319 | struct bfin_twi_iface *iface = adap->algo_data; | |
320 | int rc = 0; | |
321 | ||
322 | if (!(bfin_read_TWI_CONTROL() & TWI_ENA)) | |
323 | return -ENXIO; | |
324 | ||
d24ecfcc | 325 | while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) { |
d24ecfcc | 326 | yield(); |
d24ecfcc BW |
327 | } |
328 | ||
329 | iface->writeNum = 0; | |
330 | iface->readNum = 0; | |
331 | ||
332 | /* Prepare datas & select mode */ | |
333 | switch (size) { | |
334 | case I2C_SMBUS_QUICK: | |
335 | iface->transPtr = NULL; | |
336 | iface->cur_mode = TWI_I2C_MODE_STANDARD; | |
337 | break; | |
338 | case I2C_SMBUS_BYTE: | |
339 | if (data == NULL) | |
340 | iface->transPtr = NULL; | |
341 | else { | |
342 | if (read_write == I2C_SMBUS_READ) | |
343 | iface->readNum = 1; | |
344 | else | |
345 | iface->writeNum = 1; | |
346 | iface->transPtr = &data->byte; | |
347 | } | |
348 | iface->cur_mode = TWI_I2C_MODE_STANDARD; | |
349 | break; | |
350 | case I2C_SMBUS_BYTE_DATA: | |
351 | if (read_write == I2C_SMBUS_READ) { | |
352 | iface->readNum = 1; | |
353 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
354 | } else { | |
355 | iface->writeNum = 1; | |
356 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
357 | } | |
358 | iface->transPtr = &data->byte; | |
359 | break; | |
360 | case I2C_SMBUS_WORD_DATA: | |
361 | if (read_write == I2C_SMBUS_READ) { | |
362 | iface->readNum = 2; | |
363 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
364 | } else { | |
365 | iface->writeNum = 2; | |
366 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
367 | } | |
368 | iface->transPtr = (u8 *)&data->word; | |
369 | break; | |
370 | case I2C_SMBUS_PROC_CALL: | |
371 | iface->writeNum = 2; | |
372 | iface->readNum = 2; | |
373 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
374 | iface->transPtr = (u8 *)&data->word; | |
375 | break; | |
376 | case I2C_SMBUS_BLOCK_DATA: | |
377 | if (read_write == I2C_SMBUS_READ) { | |
378 | iface->readNum = 0; | |
379 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
380 | } else { | |
381 | iface->writeNum = data->block[0] + 1; | |
382 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
383 | } | |
384 | iface->transPtr = data->block; | |
385 | break; | |
386 | default: | |
387 | return -1; | |
388 | } | |
389 | ||
390 | iface->result = 0; | |
391 | iface->manual_stop = 0; | |
392 | iface->read_write = read_write; | |
393 | iface->command = command; | |
394 | iface->timeout_count = 10; | |
395 | ||
396 | /* FIFO Initiation. Data in FIFO should be discarded before | |
397 | * start a new operation. | |
398 | */ | |
399 | bfin_write_TWI_FIFO_CTL(0x3); | |
400 | SSYNC(); | |
401 | bfin_write_TWI_FIFO_CTL(0); | |
402 | ||
403 | /* clear int stat */ | |
404 | bfin_write_TWI_INT_STAT(MERR|MCOMP|XMTSERV|RCVSERV); | |
405 | ||
406 | /* Set Transmit device address */ | |
407 | bfin_write_TWI_MASTER_ADDR(addr); | |
408 | SSYNC(); | |
409 | ||
410 | iface->timeout_timer.expires = jiffies + POLL_TIMEOUT; | |
411 | add_timer(&iface->timeout_timer); | |
412 | ||
413 | switch (iface->cur_mode) { | |
414 | case TWI_I2C_MODE_STANDARDSUB: | |
415 | bfin_write_TWI_XMT_DATA8(iface->command); | |
416 | bfin_write_TWI_INT_MASK(MCOMP | MERR | | |
417 | ((iface->read_write == I2C_SMBUS_READ) ? | |
418 | RCVSERV : XMTSERV)); | |
419 | SSYNC(); | |
420 | ||
421 | if (iface->writeNum + 1 <= 255) | |
422 | bfin_write_TWI_MASTER_CTL((iface->writeNum + 1) << 6); | |
423 | else { | |
424 | bfin_write_TWI_MASTER_CTL(0xff << 6); | |
425 | iface->manual_stop = 1; | |
426 | } | |
427 | /* Master enable */ | |
428 | bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN | | |
429 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0)); | |
430 | break; | |
431 | case TWI_I2C_MODE_COMBINED: | |
432 | bfin_write_TWI_XMT_DATA8(iface->command); | |
433 | bfin_write_TWI_INT_MASK(MCOMP | MERR | RCVSERV | XMTSERV); | |
434 | SSYNC(); | |
435 | ||
436 | if (iface->writeNum > 0) | |
437 | bfin_write_TWI_MASTER_CTL((iface->writeNum + 1) << 6); | |
438 | else | |
439 | bfin_write_TWI_MASTER_CTL(0x1 << 6); | |
440 | /* Master enable */ | |
441 | bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN | | |
442 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0)); | |
443 | break; | |
444 | default: | |
445 | bfin_write_TWI_MASTER_CTL(0); | |
446 | if (size != I2C_SMBUS_QUICK) { | |
447 | /* Don't access xmit data register when this is a | |
448 | * read operation. | |
449 | */ | |
450 | if (iface->read_write != I2C_SMBUS_READ) { | |
451 | if (iface->writeNum > 0) { | |
452 | bfin_write_TWI_XMT_DATA8(*(iface->transPtr++)); | |
453 | if (iface->writeNum <= 255) | |
454 | bfin_write_TWI_MASTER_CTL(iface->writeNum << 6); | |
455 | else { | |
456 | bfin_write_TWI_MASTER_CTL(0xff << 6); | |
457 | iface->manual_stop = 1; | |
458 | } | |
459 | iface->writeNum--; | |
460 | } else { | |
461 | bfin_write_TWI_XMT_DATA8(iface->command); | |
462 | bfin_write_TWI_MASTER_CTL(1 << 6); | |
463 | } | |
464 | } else { | |
465 | if (iface->readNum > 0 && iface->readNum <= 255) | |
466 | bfin_write_TWI_MASTER_CTL(iface->readNum << 6); | |
467 | else if (iface->readNum > 255) { | |
468 | bfin_write_TWI_MASTER_CTL(0xff << 6); | |
469 | iface->manual_stop = 1; | |
470 | } else { | |
471 | del_timer(&iface->timeout_timer); | |
472 | break; | |
473 | } | |
474 | } | |
475 | } | |
476 | bfin_write_TWI_INT_MASK(MCOMP | MERR | | |
477 | ((iface->read_write == I2C_SMBUS_READ) ? | |
478 | RCVSERV : XMTSERV)); | |
479 | SSYNC(); | |
480 | ||
481 | /* Master enable */ | |
482 | bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN | | |
483 | ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | | |
484 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0)); | |
485 | break; | |
486 | } | |
487 | SSYNC(); | |
488 | ||
489 | wait_for_completion(&iface->complete); | |
490 | ||
491 | rc = (iface->result >= 0) ? 0 : -1; | |
492 | ||
d24ecfcc BW |
493 | return rc; |
494 | } | |
495 | ||
496 | /* | |
497 | * Return what the adapter supports | |
498 | */ | |
499 | static u32 bfin_twi_functionality(struct i2c_adapter *adap) | |
500 | { | |
501 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | | |
502 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | | |
503 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL | | |
504 | I2C_FUNC_I2C; | |
505 | } | |
506 | ||
507 | ||
508 | static struct i2c_algorithm bfin_twi_algorithm = { | |
509 | .master_xfer = bfin_twi_master_xfer, | |
510 | .smbus_xfer = bfin_twi_smbus_xfer, | |
511 | .functionality = bfin_twi_functionality, | |
512 | }; | |
513 | ||
514 | ||
515 | static int i2c_bfin_twi_suspend(struct platform_device *dev, pm_message_t state) | |
516 | { | |
517 | /* struct bfin_twi_iface *iface = platform_get_drvdata(dev);*/ | |
518 | ||
519 | /* Disable TWI */ | |
520 | bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() & ~TWI_ENA); | |
521 | SSYNC(); | |
522 | ||
523 | return 0; | |
524 | } | |
525 | ||
526 | static int i2c_bfin_twi_resume(struct platform_device *dev) | |
527 | { | |
528 | /* struct bfin_twi_iface *iface = platform_get_drvdata(dev);*/ | |
529 | ||
530 | /* Enable TWI */ | |
531 | bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA); | |
532 | SSYNC(); | |
533 | ||
534 | return 0; | |
535 | } | |
536 | ||
537 | static int i2c_bfin_twi_probe(struct platform_device *dev) | |
538 | { | |
539 | struct bfin_twi_iface *iface = &twi_iface; | |
540 | struct i2c_adapter *p_adap; | |
541 | int rc; | |
542 | ||
d24ecfcc BW |
543 | spin_lock_init(&(iface->lock)); |
544 | init_completion(&(iface->complete)); | |
545 | iface->irq = IRQ_TWI; | |
546 | ||
547 | init_timer(&(iface->timeout_timer)); | |
548 | iface->timeout_timer.function = bfin_twi_timeout; | |
549 | iface->timeout_timer.data = (unsigned long)iface; | |
550 | ||
551 | p_adap = &iface->adap; | |
552 | p_adap->id = I2C_HW_BLACKFIN; | |
553 | strlcpy(p_adap->name, dev->name, sizeof(p_adap->name)); | |
554 | p_adap->algo = &bfin_twi_algorithm; | |
555 | p_adap->algo_data = iface; | |
556 | p_adap->class = I2C_CLASS_ALL; | |
557 | p_adap->dev.parent = &dev->dev; | |
558 | ||
559 | rc = request_irq(iface->irq, bfin_twi_interrupt_entry, | |
560 | IRQF_DISABLED, dev->name, iface); | |
561 | if (rc) { | |
562 | dev_err(&(p_adap->dev), "i2c-bfin-twi: can't get IRQ %d !\n", | |
563 | iface->irq); | |
564 | return -ENODEV; | |
565 | } | |
566 | ||
567 | /* Set TWI internal clock as 10MHz */ | |
568 | bfin_write_TWI_CONTROL(((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F); | |
569 | ||
570 | /* Set Twi interface clock as specified */ | |
571 | bfin_write_TWI_CLKDIV((( 5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ ) | |
572 | << 8) | (( 5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ ) | |
573 | & 0xFF)); | |
574 | ||
575 | /* Enable TWI */ | |
576 | bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA); | |
577 | SSYNC(); | |
578 | ||
579 | rc = i2c_add_adapter(p_adap); | |
580 | if (rc < 0) | |
581 | free_irq(iface->irq, iface); | |
582 | else | |
583 | platform_set_drvdata(dev, iface); | |
584 | ||
585 | return rc; | |
586 | } | |
587 | ||
588 | static int i2c_bfin_twi_remove(struct platform_device *pdev) | |
589 | { | |
590 | struct bfin_twi_iface *iface = platform_get_drvdata(pdev); | |
591 | ||
592 | platform_set_drvdata(pdev, NULL); | |
593 | ||
594 | i2c_del_adapter(&(iface->adap)); | |
595 | free_irq(iface->irq, iface); | |
596 | ||
597 | return 0; | |
598 | } | |
599 | ||
600 | static struct platform_driver i2c_bfin_twi_driver = { | |
601 | .probe = i2c_bfin_twi_probe, | |
602 | .remove = i2c_bfin_twi_remove, | |
603 | .suspend = i2c_bfin_twi_suspend, | |
604 | .resume = i2c_bfin_twi_resume, | |
605 | .driver = { | |
606 | .name = "i2c-bfin-twi", | |
607 | .owner = THIS_MODULE, | |
608 | }, | |
609 | }; | |
610 | ||
611 | static int __init i2c_bfin_twi_init(void) | |
612 | { | |
613 | pr_info("I2C: Blackfin I2C TWI driver\n"); | |
614 | ||
615 | return platform_driver_register(&i2c_bfin_twi_driver); | |
616 | } | |
617 | ||
618 | static void __exit i2c_bfin_twi_exit(void) | |
619 | { | |
620 | platform_driver_unregister(&i2c_bfin_twi_driver); | |
621 | } | |
622 | ||
623 | MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>"); | |
624 | MODULE_DESCRIPTION("I2C-Bus adapter routines for Blackfin TWI"); | |
625 | MODULE_LICENSE("GPL"); | |
626 | ||
627 | module_init(i2c_bfin_twi_init); | |
628 | module_exit(i2c_bfin_twi_exit); |