[deliverable/linux.git] / drivers / i2c / busses / i2c-cpm.c

/*
 * Freescale CPM1/CPM2 I2C interface.
 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
 *
 * moved into proper i2c interface;
 * Brad Parker (brad@heeltoe.com)
 *
 * Parts from dbox2_i2c.c (cvs.tuxbox.org)
 * (C) 2000-2001 Felix Domke (tmbinc@gmx.net), Gillem (htoa@gmx.net)
 *
 * (C) 2007 Montavista Software, Inc.
 * Vitaly Bordug <vitb@kernel.crashing.org>
 *
 * Converted to of_platform_device. Renamed to i2c-cpm.c.
 * (C) 2007,2008 Jochen Friedrich <jochen@scram.de>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/errno.h>
#include <linux/stddef.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <sysdev/fsl_soc.h>
#include <asm/cpm.h>

/* Try to define this if you have an older CPU (earlier than rev D4) */
/* However, better use a GPIO based bitbang driver in this case :/   */
#undef	I2C_CHIP_ERRATA

#define CPM_MAX_READ    513
#define CPM_MAXBD       4

#define I2C_EB			(0x10) /* Big endian mode */
#define I2C_EB_CPM2		(0x30) /* Big endian mode, memory snoop */

#define DPRAM_BASE		((u8 __iomem __force *)cpm_muram_addr(0))

/* I2C parameter RAM. */
struct i2c_ram {
	ushort  rbase;		/* Rx Buffer descriptor base address */
	ushort  tbase;		/* Tx Buffer descriptor base address */
	u_char  rfcr;		/* Rx function code */
	u_char  tfcr;		/* Tx function code */
	ushort  mrblr;		/* Max receive buffer length */
	uint    rstate;		/* Internal */
	uint    rdp;		/* Internal */
	ushort  rbptr;		/* Rx Buffer descriptor pointer */
	ushort  rbc;		/* Internal */
	uint    rxtmp;		/* Internal */
	uint    tstate;		/* Internal */
	uint    tdp;		/* Internal */
	ushort  tbptr;		/* Tx Buffer descriptor pointer */
	ushort  tbc;		/* Internal */
	uint    txtmp;		/* Internal */
	char    res1[4];	/* Reserved */
	ushort  rpbase;		/* Relocation pointer */
	char    res2[2];	/* Reserved */
};

#define I2COM_START	0x80
#define I2COM_MASTER	0x01
#define I2CER_TXE	0x10
#define I2CER_BUSY	0x04
#define I2CER_TXB	0x02
#define I2CER_RXB	0x01
#define I2MOD_EN	0x01

/* I2C Registers */
struct i2c_reg {
	u8	i2mod;
	u8	res1[3];
	u8	i2add;
	u8	res2[3];
	u8	i2brg;
	u8	res3[3];
	u8	i2com;
	u8	res4[3];
	u8	i2cer;
	u8	res5[3];
	u8	i2cmr;
};

struct cpm_i2c {
	char *base;
	struct platform_device *ofdev;
	struct i2c_adapter adap;
	uint dp_addr;
	int version; /* CPM1=1, CPM2=2 */
	int irq;
	int cp_command;
	int freq;
	struct i2c_reg __iomem *i2c_reg;
	struct i2c_ram __iomem *i2c_ram;
	u16 i2c_addr;
	wait_queue_head_t i2c_wait;
	cbd_t __iomem *tbase;
	cbd_t __iomem *rbase;
	u_char *txbuf[CPM_MAXBD];
	u_char *rxbuf[CPM_MAXBD];
	u32 txdma[CPM_MAXBD];
	u32 rxdma[CPM_MAXBD];
};

static irqreturn_t cpm_i2c_interrupt(int irq, void *dev_id)
{
	struct cpm_i2c *cpm;
	struct i2c_reg __iomem *i2c_reg;
	struct i2c_adapter *adap = dev_id;
	int i;

	cpm = i2c_get_adapdata(dev_id);
	i2c_reg = cpm->i2c_reg;

	/* Clear interrupt. */
	i = in_8(&i2c_reg->i2cer);
	out_8(&i2c_reg->i2cer, i);

	dev_dbg(&adap->dev, "Interrupt: %x\n", i);

	wake_up(&cpm->i2c_wait);

	return i ? IRQ_HANDLED : IRQ_NONE;
}

static void cpm_reset_i2c_params(struct cpm_i2c *cpm)
{
	struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;

	/* Set up the I2C parameters in the parameter ram. */
	out_be16(&i2c_ram->tbase, (u8 __iomem *)cpm->tbase - DPRAM_BASE);
	out_be16(&i2c_ram->rbase, (u8 __iomem *)cpm->rbase - DPRAM_BASE);

	if (cpm->version == 1) {
		out_8(&i2c_ram->tfcr, I2C_EB);
		out_8(&i2c_ram->rfcr, I2C_EB);
	} else {
		out_8(&i2c_ram->tfcr, I2C_EB_CPM2);
		out_8(&i2c_ram->rfcr, I2C_EB_CPM2);
	}

	out_be16(&i2c_ram->mrblr, CPM_MAX_READ);

	out_be32(&i2c_ram->rstate, 0);
	out_be32(&i2c_ram->rdp, 0);
	out_be16(&i2c_ram->rbptr, 0);
	out_be16(&i2c_ram->rbc, 0);
	out_be32(&i2c_ram->rxtmp, 0);
	out_be32(&i2c_ram->tstate, 0);
	out_be32(&i2c_ram->tdp, 0);
	out_be16(&i2c_ram->tbptr, 0);
	out_be16(&i2c_ram->tbc, 0);
	out_be32(&i2c_ram->txtmp, 0);
}

static void cpm_i2c_force_close(struct i2c_adapter *adap)
{
	struct cpm_i2c *cpm = i2c_get_adapdata(adap);
	struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;

	dev_dbg(&adap->dev, "cpm_i2c_force_close()\n");

	cpm_command(cpm->cp_command, CPM_CR_CLOSE_RX_BD);

	out_8(&i2c_reg->i2cmr, 0x00);	/* Disable all interrupts */
	out_8(&i2c_reg->i2cer, 0xff);
}

static void cpm_i2c_parse_message(struct i2c_adapter *adap,
	struct i2c_msg *pmsg, int num, int tx, int rx)
{
	cbd_t __iomem *tbdf;
	cbd_t __iomem *rbdf;
	u_char addr;
	u_char *tb;
	u_char *rb;
	struct cpm_i2c *cpm = i2c_get_adapdata(adap);

	tbdf = cpm->tbase + tx;
	rbdf = cpm->rbase + rx;

	addr = pmsg->addr << 1;
	if (pmsg->flags & I2C_M_RD)
		addr |= 1;

	tb = cpm->txbuf[tx];
	rb = cpm->rxbuf[rx];

	/* Align read buffer */
	rb = (u_char *) (((ulong) rb + 1) & ~1);

	tb[0] = addr;		/* Device address byte w/rw flag */

	out_be16(&tbdf->cbd_datlen, pmsg->len + 1);
	out_be16(&tbdf->cbd_sc, 0);

	if (!(pmsg->flags & I2C_M_NOSTART))
		setbits16(&tbdf->cbd_sc, BD_I2C_START);

	if (tx + 1 == num)
		setbits16(&tbdf->cbd_sc, BD_SC_LAST | BD_SC_WRAP);

	if (pmsg->flags & I2C_M_RD) {
		/*
		 * To read, we need an empty buffer of the proper length.
		 * All that is used is the first byte for address, the remainder
		 * is just used for timing (and doesn't really have to exist).
		 */

		dev_dbg(&adap->dev, "cpm_i2c_read(abyte=0x%x)\n", addr);

		out_be16(&rbdf->cbd_datlen, 0);
		out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);

		if (rx + 1 == CPM_MAXBD)
			setbits16(&rbdf->cbd_sc, BD_SC_WRAP);

		eieio();
		setbits16(&tbdf->cbd_sc, BD_SC_READY);
	} else {
		dev_dbg(&adap->dev, "cpm_i2c_write(abyte=0x%x)\n", addr);

		memcpy(tb+1, pmsg->buf, pmsg->len);

		eieio();
		setbits16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_INTRPT);
	}
}

static int cpm_i2c_check_message(struct i2c_adapter *adap,
	struct i2c_msg *pmsg, int tx, int rx)
{
	cbd_t __iomem *tbdf;
	cbd_t __iomem *rbdf;
	u_char *tb;
	u_char *rb;
	struct cpm_i2c *cpm = i2c_get_adapdata(adap);

	tbdf = cpm->tbase + tx;
	rbdf = cpm->rbase + rx;

	tb = cpm->txbuf[tx];
	rb = cpm->rxbuf[rx];

	/* Align read buffer */
	rb = (u_char *) (((uint) rb + 1) & ~1);

	eieio();
	if (pmsg->flags & I2C_M_RD) {
		dev_dbg(&adap->dev, "tx sc 0x%04x, rx sc 0x%04x\n",
			in_be16(&tbdf->cbd_sc), in_be16(&rbdf->cbd_sc));

		if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
			dev_dbg(&adap->dev, "I2C read; No ack\n");
			return -ENXIO;
		}
		if (in_be16(&rbdf->cbd_sc) & BD_SC_EMPTY) {
			dev_err(&adap->dev,
				"I2C read; complete but rbuf empty\n");
			return -EREMOTEIO;
		}
		if (in_be16(&rbdf->cbd_sc) & BD_SC_OV) {
			dev_err(&adap->dev, "I2C read; Overrun\n");
			return -EREMOTEIO;
		}
		memcpy(pmsg->buf, rb, pmsg->len);
	} else {
		dev_dbg(&adap->dev, "tx sc %d 0x%04x\n", tx,
			in_be16(&tbdf->cbd_sc));

		if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
			dev_dbg(&adap->dev, "I2C write; No ack\n");
			return -ENXIO;
		}
		if (in_be16(&tbdf->cbd_sc) & BD_SC_UN) {
			dev_err(&adap->dev, "I2C write; Underrun\n");
			return -EIO;
		}
		if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) {
			dev_err(&adap->dev, "I2C write; Collision\n");
			return -EIO;
		}
	}
	return 0;
}

static int cpm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
	struct cpm_i2c *cpm = i2c_get_adapdata(adap);
	struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
	struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
	struct i2c_msg *pmsg;
	int ret, i;
	int tptr;
	int rptr;
	cbd_t __iomem *tbdf;
	cbd_t __iomem *rbdf;

	if (num > CPM_MAXBD)
		return -EINVAL;

	/* Check if we have any oversized READ requests */
	for (i = 0; i < num; i++) {
		pmsg = &msgs[i];
		if (pmsg->len >= CPM_MAX_READ)
			return -EINVAL;
	}

	/* Reset to use first buffer */
	out_be16(&i2c_ram->rbptr, in_be16(&i2c_ram->rbase));
	out_be16(&i2c_ram->tbptr, in_be16(&i2c_ram->tbase));

	tbdf = cpm->tbase;
	rbdf = cpm->rbase;

	tptr = 0;
	rptr = 0;

	/*
	 * If there was a collision in the last i2c transaction,
	 * Set I2COM_MASTER as it was cleared during collision.
	 */
	if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) {
		out_8(&cpm->i2c_reg->i2com, I2COM_MASTER);
	}

	while (tptr < num) {
		pmsg = &msgs[tptr];
		dev_dbg(&adap->dev, "R: %d T: %d\n", rptr, tptr);

		cpm_i2c_parse_message(adap, pmsg, num, tptr, rptr);
		if (pmsg->flags & I2C_M_RD)
			rptr++;
		tptr++;
	}
	/* Start transfer now */
	/* Enable RX/TX/Error interupts */
	out_8(&i2c_reg->i2cmr, I2CER_TXE | I2CER_TXB | I2CER_RXB);
	out_8(&i2c_reg->i2cer, 0xff);	/* Clear interrupt status */
	/* Chip bug, set enable here */
	setbits8(&i2c_reg->i2mod, I2MOD_EN);	/* Enable */
	/* Begin transmission */
	setbits8(&i2c_reg->i2com, I2COM_START);

	tptr = 0;
	rptr = 0;

	while (tptr < num) {
		/* Check for outstanding messages */
		dev_dbg(&adap->dev, "test ready.\n");
		pmsg = &msgs[tptr];
		if (pmsg->flags & I2C_M_RD)
			ret = wait_event_timeout(cpm->i2c_wait,
				(in_be16(&tbdf[tptr].cbd_sc) & BD_SC_NAK) ||
				!(in_be16(&rbdf[rptr].cbd_sc) & BD_SC_EMPTY),
				1 * HZ);
		else
			ret = wait_event_timeout(cpm->i2c_wait,
				!(in_be16(&tbdf[tptr].cbd_sc) & BD_SC_READY),
				1 * HZ);
		if (ret == 0) {
			ret = -EREMOTEIO;
			dev_err(&adap->dev, "I2C transfer: timeout\n");
			goto out_err;
		}
		if (ret > 0) {
			dev_dbg(&adap->dev, "ready.\n");
			ret = cpm_i2c_check_message(adap, pmsg, tptr, rptr);
			tptr++;
			if (pmsg->flags & I2C_M_RD)
				rptr++;
			if (ret)
				goto out_err;
		}
	}
#ifdef I2C_CHIP_ERRATA
	/*
	 * Chip errata, clear enable. This is not needed on rev D4 CPUs.
	 * Disabling I2C too early may cause too short stop condition
	 */
	udelay(4);
	clrbits8(&i2c_reg->i2mod, I2MOD_EN);
#endif
	return (num);

out_err:
	cpm_i2c_force_close(adap);
#ifdef I2C_CHIP_ERRATA
	/*
	 * Chip errata, clear enable. This is not needed on rev D4 CPUs.
	 */
	clrbits8(&i2c_reg->i2mod, I2MOD_EN);
#endif
	return ret;
}

static u32 cpm_i2c_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
}

/* -----exported algorithm data: -------------------------------------	*/

static const struct i2c_algorithm cpm_i2c_algo = {
	.master_xfer = cpm_i2c_xfer,
	.functionality = cpm_i2c_func,
};

static const struct i2c_adapter cpm_ops = {
	.owner		= THIS_MODULE,
	.name		= "i2c-cpm",
	.algo		= &cpm_i2c_algo,
};

static int cpm_i2c_setup(struct cpm_i2c *cpm)
{
	struct platform_device *ofdev = cpm->ofdev;
	const u32 *data;
	int len, ret, i;
	void __iomem *i2c_base;
	cbd_t __iomem *tbdf;
	cbd_t __iomem *rbdf;
	unsigned char brg;

	dev_dbg(&cpm->ofdev->dev, "cpm_i2c_setup()\n");

	init_waitqueue_head(&cpm->i2c_wait);

	cpm->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
	if (!cpm->irq)
		return -EINVAL;

	/* Install interrupt handler. */
	ret = request_irq(cpm->irq, cpm_i2c_interrupt, 0, "cpm_i2c",
			  &cpm->adap);
	if (ret)
		return ret;

	/* I2C parameter RAM */
	i2c_base = of_iomap(ofdev->dev.of_node, 1);
	if (i2c_base == NULL) {
		ret = -EINVAL;
		goto out_irq;
	}

	if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm1-i2c")) {

		/* Check for and use a microcode relocation patch. */
		cpm->i2c_ram = i2c_base;
		cpm->i2c_addr = in_be16(&cpm->i2c_ram->rpbase);

		/*
		 * Maybe should use cpm_muram_alloc instead of hardcoding
		 * this in micropatch.c
		 */
		if (cpm->i2c_addr) {
			cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
			iounmap(i2c_base);
		}

		cpm->version = 1;

	} else if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm2-i2c")) {
		cpm->i2c_addr = cpm_muram_alloc(sizeof(struct i2c_ram), 64);
		cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
		out_be16(i2c_base, cpm->i2c_addr);
		iounmap(i2c_base);

		cpm->version = 2;

	} else {
		iounmap(i2c_base);
		ret = -EINVAL;
		goto out_irq;
	}

	/* I2C control/status registers */
	cpm->i2c_reg = of_iomap(ofdev->dev.of_node, 0);
	if (cpm->i2c_reg == NULL) {
		ret = -EINVAL;
		goto out_ram;
	}

	data = of_get_property(ofdev->dev.of_node, "fsl,cpm-command", &len);
	if (!data || len != 4) {
		ret = -EINVAL;
		goto out_reg;
	}
	cpm->cp_command = *data;

	data = of_get_property(ofdev->dev.of_node, "linux,i2c-class", &len);
	if (data && len == 4)
		cpm->adap.class = *data;

	data = of_get_property(ofdev->dev.of_node, "clock-frequency", &len);
	if (data && len == 4)
		cpm->freq = *data;
	else
		cpm->freq = 60000; /* use 60kHz i2c clock by default */

	/*
	 * Allocate space for CPM_MAXBD transmit and receive buffer
	 * descriptors in the DP ram.
	 */
	cpm->dp_addr = cpm_muram_alloc(sizeof(cbd_t) * 2 * CPM_MAXBD, 8);
	if (!cpm->dp_addr) {
		ret = -ENOMEM;
		goto out_reg;
	}

	cpm->tbase = cpm_muram_addr(cpm->dp_addr);
	cpm->rbase = cpm_muram_addr(cpm->dp_addr + sizeof(cbd_t) * CPM_MAXBD);

	/* Allocate TX and RX buffers */

	tbdf = cpm->tbase;
	rbdf = cpm->rbase;

	for (i = 0; i < CPM_MAXBD; i++) {
		cpm->rxbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev,
						   CPM_MAX_READ + 1,
						   &cpm->rxdma[i], GFP_KERNEL);
		if (!cpm->rxbuf[i]) {
			ret = -ENOMEM;
			goto out_muram;
		}
		out_be32(&rbdf[i].cbd_bufaddr, ((cpm->rxdma[i] + 1) & ~1));

		cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL);
		if (!cpm->txbuf[i]) {
			ret = -ENOMEM;
			goto out_muram;
		}
		out_be32(&tbdf[i].cbd_bufaddr, cpm->txdma[i]);
	}

	/* Initialize Tx/Rx parameters. */

	cpm_reset_i2c_params(cpm);

	dev_dbg(&cpm->ofdev->dev, "i2c_ram 0x%p, i2c_addr 0x%04x, freq %d\n",
		cpm->i2c_ram, cpm->i2c_addr, cpm->freq);
	dev_dbg(&cpm->ofdev->dev, "tbase 0x%04x, rbase 0x%04x\n",
		(u8 __iomem *)cpm->tbase - DPRAM_BASE,
		(u8 __iomem *)cpm->rbase - DPRAM_BASE);

	cpm_command(cpm->cp_command, CPM_CR_INIT_TRX);

	/*
	 * Select an invalid address. Just make sure we don't use loopback mode
	 */
	out_8(&cpm->i2c_reg->i2add, 0x7f << 1);

	/*
	 * PDIV is set to 00 in i2mod, so brgclk/32 is used as input to the
	 * i2c baud rate generator. This is divided by 2 x (DIV + 3) to get
	 * the actual i2c bus frequency.
	 */
	brg = get_brgfreq() / (32 * 2 * cpm->freq) - 3;
	out_8(&cpm->i2c_reg->i2brg, brg);

	out_8(&cpm->i2c_reg->i2mod, 0x00);
	out_8(&cpm->i2c_reg->i2com, I2COM_MASTER);	/* Master mode */

	/* Disable interrupts. */
	out_8(&cpm->i2c_reg->i2cmr, 0);
	out_8(&cpm->i2c_reg->i2cer, 0xff);

	return 0;

out_muram:
	for (i = 0; i < CPM_MAXBD; i++) {
		if (cpm->rxbuf[i])
			dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
				cpm->rxbuf[i], cpm->rxdma[i]);
		if (cpm->txbuf[i])
			dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
				cpm->txbuf[i], cpm->txdma[i]);
	}
	cpm_muram_free(cpm->dp_addr);
out_reg:
	iounmap(cpm->i2c_reg);
out_ram:
	if ((cpm->version == 1) && (!cpm->i2c_addr))
		iounmap(cpm->i2c_ram);
	if (cpm->version == 2)
		cpm_muram_free(cpm->i2c_addr);
out_irq:
	free_irq(cpm->irq, &cpm->adap);
	return ret;
}

static void cpm_i2c_shutdown(struct cpm_i2c *cpm)
{
	int i;

	/* Shut down I2C. */
	clrbits8(&cpm->i2c_reg->i2mod, I2MOD_EN);

	/* Disable interrupts */
	out_8(&cpm->i2c_reg->i2cmr, 0);
	out_8(&cpm->i2c_reg->i2cer, 0xff);

	free_irq(cpm->irq, &cpm->adap);

	/* Free all memory */
	for (i = 0; i < CPM_MAXBD; i++) {
		dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
			cpm->rxbuf[i], cpm->rxdma[i]);
		dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
			cpm->txbuf[i], cpm->txdma[i]);
	}

	cpm_muram_free(cpm->dp_addr);
	iounmap(cpm->i2c_reg);

	if ((cpm->version == 1) && (!cpm->i2c_addr))
		iounmap(cpm->i2c_ram);
	if (cpm->version == 2)
		cpm_muram_free(cpm->i2c_addr);
}

static int cpm_i2c_probe(struct platform_device *ofdev)
{
	int result, len;
	struct cpm_i2c *cpm;
	const u32 *data;

	cpm = kzalloc(sizeof(struct cpm_i2c), GFP_KERNEL);
	if (!cpm)
		return -ENOMEM;

	cpm->ofdev = ofdev;

	platform_set_drvdata(ofdev, cpm);

	cpm->adap = cpm_ops;
	i2c_set_adapdata(&cpm->adap, cpm);
	cpm->adap.dev.parent = &ofdev->dev;
	cpm->adap.dev.of_node = of_node_get(ofdev->dev.of_node);

	result = cpm_i2c_setup(cpm);
	if (result) {
		dev_err(&ofdev->dev, "Unable to init hardware\n");
		goto out_free;
	}

	/* register new adapter to i2c module... */

	data = of_get_property(ofdev->dev.of_node, "linux,i2c-index", &len);
	cpm->adap.nr = (data && len == 4) ? be32_to_cpup(data) : -1;
	result = i2c_add_numbered_adapter(&cpm->adap);

	if (result < 0) {
		dev_err(&ofdev->dev, "Unable to register with I2C\n");
		goto out_shut;
	}

	dev_dbg(&ofdev->dev, "hw routines for %s registered.\n",
		cpm->adap.name);

	return 0;
out_shut:
	cpm_i2c_shutdown(cpm);
out_free:
	kfree(cpm);

	return result;
}

static int cpm_i2c_remove(struct platform_device *ofdev)
{
	struct cpm_i2c *cpm = platform_get_drvdata(ofdev);

	i2c_del_adapter(&cpm->adap);

	cpm_i2c_shutdown(cpm);

	kfree(cpm);

	return 0;
}

static const struct of_device_id cpm_i2c_match[] = {
	{
		.compatible = "fsl,cpm1-i2c",
	},
	{
		.compatible = "fsl,cpm2-i2c",
	},
	{},
};

MODULE_DEVICE_TABLE(of, cpm_i2c_match);

static struct platform_driver cpm_i2c_driver = {
	.probe		= cpm_i2c_probe,
	.remove		= cpm_i2c_remove,
	.driver = {
		.name = "fsl-i2c-cpm",
		.owner = THIS_MODULE,
		.of_match_table = cpm_i2c_match,
	},
};

module_platform_driver(cpm_i2c_driver);

MODULE_AUTHOR("Jochen Friedrich <jochen@scram.de>");
MODULE_DESCRIPTION("I2C-Bus adapter routines for CPM boards");
MODULE_LICENSE("GPL");
Commit	Line	Data
61045dbe JF	1	/*
	2	* Freescale CPM1/CPM2 I2C interface.
	3	* Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
	4	*
	5	* moved into proper i2c interface;
	6	* Brad Parker (brad@heeltoe.com)
	7	*
	8	* Parts from dbox2_i2c.c (cvs.tuxbox.org)
	9	* (C) 2000-2001 Felix Domke (tmbinc@gmx.net), Gillem (htoa@gmx.net)
	10	*
	11	* (C) 2007 Montavista Software, Inc.
	12	* Vitaly Bordug <vitb@kernel.crashing.org>
	13	*
	14	* Converted to of_platform_device. Renamed to i2c-cpm.c.
	15	* (C) 2007,2008 Jochen Friedrich <jochen@scram.de>
	16	*
	17	* This program is free software; you can redistribute it and/or modify
	18	* it under the terms of the GNU General Public License as published by
	19	* the Free Software Foundation; either version 2 of the License, or
	20	* (at your option) any later version.
	21	*
	22	* This program is distributed in the hope that it will be useful,
	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	25	* GNU General Public License for more details.
	26	*
	27	* You should have received a copy of the GNU General Public License
	28	* along with this program; if not, write to the Free Software
	29	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	30	*/
	31
	32	#include <linux/kernel.h>
	33	#include <linux/module.h>
	34	#include <linux/delay.h>
	35	#include <linux/slab.h>
61045dbe JF	36	#include <linux/interrupt.h>
	37	#include <linux/errno.h>
	38	#include <linux/stddef.h>
	39	#include <linux/i2c.h>
	40	#include <linux/io.h>
	41	#include <linux/dma-mapping.h>
5f12c5ec	42	#include <linux/of_address.h>
61045dbe	43	#include <linux/of_device.h>
5f12c5ec	44	#include <linux/of_irq.h>
61045dbe	45	#include <linux/of_platform.h>
61045dbe JF	46	#include <sysdev/fsl_soc.h>
	47	#include <asm/cpm.h>
	48
	49	/* Try to define this if you have an older CPU (earlier than rev D4) */
	50	/* However, better use a GPIO based bitbang driver in this case :/ */
	51	#undef I2C_CHIP_ERRATA
	52
	53	#define CPM_MAX_READ 513
	54	#define CPM_MAXBD 4
	55
	56	#define I2C_EB (0x10) /* Big endian mode */
	57	#define I2C_EB_CPM2 (0x30) /* Big endian mode, memory snoop */
	58
	59	#define DPRAM_BASE ((u8 __iomem __force *)cpm_muram_addr(0))
	60
	61	/* I2C parameter RAM. */
	62	struct i2c_ram {
	63	ushort rbase; /* Rx Buffer descriptor base address */
	64	ushort tbase; /* Tx Buffer descriptor base address */
	65	u_char rfcr; /* Rx function code */
	66	u_char tfcr; /* Tx function code */
	67	ushort mrblr; /* Max receive buffer length */
	68	uint rstate; /* Internal */
	69	uint rdp; /* Internal */
	70	ushort rbptr; /* Rx Buffer descriptor pointer */
	71	ushort rbc; /* Internal */
	72	uint rxtmp; /* Internal */
	73	uint tstate; /* Internal */
	74	uint tdp; /* Internal */
	75	ushort tbptr; /* Tx Buffer descriptor pointer */
	76	ushort tbc; /* Internal */
	77	uint txtmp; /* Internal */
	78	char res1[4]; /* Reserved */
	79	ushort rpbase; /* Relocation pointer */
	80	char res2[2]; /* Reserved */
	81	};
	82
	83	#define I2COM_START 0x80
	84	#define I2COM_MASTER 0x01
	85	#define I2CER_TXE 0x10
	86	#define I2CER_BUSY 0x04
	87	#define I2CER_TXB 0x02
	88	#define I2CER_RXB 0x01
	89	#define I2MOD_EN 0x01
	90
	91	/* I2C Registers */
	92	struct i2c_reg {
	93	u8 i2mod;
	94	u8 res1[3];
	95	u8 i2add;
	96	u8 res2[3];
	97	u8 i2brg;
	98	u8 res3[3];
	99	u8 i2com;
	100	u8 res4[3];
	101	u8 i2cer;
	102	u8 res5[3];
	103	u8 i2cmr;
	104	};
	105
	106	struct cpm_i2c {
	107	char *base;
2dc11581	108	struct platform_device *ofdev;
61045dbe JF	109	struct i2c_adapter adap;
	110	uint dp_addr;
	111	int version; /* CPM1=1, CPM2=2 */
	112	int irq;
	113	int cp_command;
	114	int freq;
	115	struct i2c_reg __iomem *i2c_reg;
	116	struct i2c_ram __iomem *i2c_ram;
	117	u16 i2c_addr;
	118	wait_queue_head_t i2c_wait;
	119	cbd_t __iomem *tbase;
	120	cbd_t __iomem *rbase;
	121	u_char *txbuf[CPM_MAXBD];
	122	u_char *rxbuf[CPM_MAXBD];
	123	u32 txdma[CPM_MAXBD];
	124	u32 rxdma[CPM_MAXBD];
	125	};
	126
	127	static irqreturn_t cpm_i2c_interrupt(int irq, void *dev_id)
	128	{
	129	struct cpm_i2c *cpm;
	130	struct i2c_reg __iomem *i2c_reg;
	131	struct i2c_adapter *adap = dev_id;
	132	int i;
	133
	134	cpm = i2c_get_adapdata(dev_id);
	135	i2c_reg = cpm->i2c_reg;
	136
	137	/* Clear interrupt. */
	138	i = in_8(&i2c_reg->i2cer);
	139	out_8(&i2c_reg->i2cer, i);
	140
	141	dev_dbg(&adap->dev, "Interrupt: %x\n", i);
	142
dc1972d0	143	wake_up(&cpm->i2c_wait);
61045dbe JF	144
	145	return i ? IRQ_HANDLED : IRQ_NONE;
	146	}
	147
	148	static void cpm_reset_i2c_params(struct cpm_i2c *cpm)
	149	{
	150	struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
	151
	152	/* Set up the I2C parameters in the parameter ram. */
	153	out_be16(&i2c_ram->tbase, (u8 __iomem *)cpm->tbase - DPRAM_BASE);
	154	out_be16(&i2c_ram->rbase, (u8 __iomem *)cpm->rbase - DPRAM_BASE);
	155
	156	if (cpm->version == 1) {
	157	out_8(&i2c_ram->tfcr, I2C_EB);
	158	out_8(&i2c_ram->rfcr, I2C_EB);
	159	} else {
	160	out_8(&i2c_ram->tfcr, I2C_EB_CPM2);
	161	out_8(&i2c_ram->rfcr, I2C_EB_CPM2);
	162	}
	163
	164	out_be16(&i2c_ram->mrblr, CPM_MAX_READ);
	165
	166	out_be32(&i2c_ram->rstate, 0);
	167	out_be32(&i2c_ram->rdp, 0);
	168	out_be16(&i2c_ram->rbptr, 0);
	169	out_be16(&i2c_ram->rbc, 0);
	170	out_be32(&i2c_ram->rxtmp, 0);
	171	out_be32(&i2c_ram->tstate, 0);
	172	out_be32(&i2c_ram->tdp, 0);
	173	out_be16(&i2c_ram->tbptr, 0);
	174	out_be16(&i2c_ram->tbc, 0);
	175	out_be32(&i2c_ram->txtmp, 0);
	176	}
	177
	178	static void cpm_i2c_force_close(struct i2c_adapter *adap)
	179	{
	180	struct cpm_i2c *cpm = i2c_get_adapdata(adap);
	181	struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
	182
	183	dev_dbg(&adap->dev, "cpm_i2c_force_close()\n");
	184
	185	cpm_command(cpm->cp_command, CPM_CR_CLOSE_RX_BD);
	186
	187	out_8(&i2c_reg->i2cmr, 0x00); /* Disable all interrupts */
	188	out_8(&i2c_reg->i2cer, 0xff);
	189	}
	190
	191	static void cpm_i2c_parse_message(struct i2c_adapter *adap,
	192	struct i2c_msg *pmsg, int num, int tx, int rx)
	193	{
	194	cbd_t __iomem *tbdf;
	195	cbd_t __iomem *rbdf;
	196	u_char addr;
	197	u_char *tb;
	198	u_char *rb;
	199	struct cpm_i2c *cpm = i2c_get_adapdata(adap);
	200
	201	tbdf = cpm->tbase + tx;
	202	rbdf = cpm->rbase + rx;
	203
	204	addr = pmsg->addr << 1;
	205	if (pmsg->flags & I2C_M_RD)
	206	addr \|= 1;
	207
208	tb = cpm->txbuf[tx];
209	rb = cpm->rxbuf[rx];
210
211	/* Align read buffer */
212	rb = (u_char *) (((ulong) rb + 1) & ~1);
213
214	tb[0] = addr; /* Device address byte w/rw flag */
215
216	out_be16(&tbdf->cbd_datlen, pmsg->len + 1);
217	out_be16(&tbdf->cbd_sc, 0);
218
219	if (!(pmsg->flags & I2C_M_NOSTART))
220	setbits16(&tbdf->cbd_sc, BD_I2C_START);
221
222	if (tx + 1 == num)
223	setbits16(&tbdf->cbd_sc, BD_SC_LAST \| BD_SC_WRAP);
224
225	if (pmsg->flags & I2C_M_RD) {
226	/*
227	* To read, we need an empty buffer of the proper length.
228	* All that is used is the first byte for address, the remainder
229	* is just used for timing (and doesn't really have to exist).
230	*/
231
232	dev_dbg(&adap->dev, "cpm_i2c_read(abyte=0x%x)\n", addr);
233
234	out_be16(&rbdf->cbd_datlen, 0);
235	out_be16(&rbdf->cbd_sc, BD_SC_EMPTY \| BD_SC_INTRPT);
236
237	if (rx + 1 == CPM_MAXBD)
238	setbits16(&rbdf->cbd_sc, BD_SC_WRAP);
239
240	eieio();
241	setbits16(&tbdf->cbd_sc, BD_SC_READY);
242	} else {
3b270804	243	dev_dbg(&adap->dev, "cpm_i2c_write(abyte=0x%x)\n", addr);
61045dbe JF	244
	245	memcpy(tb+1, pmsg->buf, pmsg->len);
	246
	247	eieio();
	248	setbits16(&tbdf->cbd_sc, BD_SC_READY \| BD_SC_INTRPT);
	249	}
	250	}
	251
	252	static int cpm_i2c_check_message(struct i2c_adapter *adap,
	253	struct i2c_msg *pmsg, int tx, int rx)
	254	{
	255	cbd_t __iomem *tbdf;
	256	cbd_t __iomem *rbdf;
	257	u_char *tb;
	258	u_char *rb;
	259	struct cpm_i2c *cpm = i2c_get_adapdata(adap);
	260
	261	tbdf = cpm->tbase + tx;
	262	rbdf = cpm->rbase + rx;
	263
	264	tb = cpm->txbuf[tx];
	265	rb = cpm->rxbuf[rx];
	266
	267	/* Align read buffer */
	268	rb = (u_char *) (((uint) rb + 1) & ~1);
	269
	270	eieio();
	271	if (pmsg->flags & I2C_M_RD) {
	272	dev_dbg(&adap->dev, "tx sc 0x%04x, rx sc 0x%04x\n",
	273	in_be16(&tbdf->cbd_sc), in_be16(&rbdf->cbd_sc));
	274
	275	if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
	276	dev_dbg(&adap->dev, "I2C read; No ack\n");
	277	return -ENXIO;
	278	}
	279	if (in_be16(&rbdf->cbd_sc) & BD_SC_EMPTY) {
	280	dev_err(&adap->dev,
	281	"I2C read; complete but rbuf empty\n");
	282	return -EREMOTEIO;
	283	}
	284	if (in_be16(&rbdf->cbd_sc) & BD_SC_OV) {
	285	dev_err(&adap->dev, "I2C read; Overrun\n");
	286	return -EREMOTEIO;
	287	}
	288	memcpy(pmsg->buf, rb, pmsg->len);
	289	} else {
	290	dev_dbg(&adap->dev, "tx sc %d 0x%04x\n", tx,
	291	in_be16(&tbdf->cbd_sc));
	292
	293	if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
	294	dev_dbg(&adap->dev, "I2C write; No ack\n");
	295	return -ENXIO;
	296	}
	297	if (in_be16(&tbdf->cbd_sc) & BD_SC_UN) {
	298	dev_err(&adap->dev, "I2C write; Underrun\n");
	299	return -EIO;
	300	}
	301	if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) {
	302	dev_err(&adap->dev, "I2C write; Collision\n");
	303	return -EIO;
	304	}
	305	}
	306	return 0;
	307	}
308
309	static int cpm_i2c_xfer(struct i2c_adapter adap, struct i2c_msg msgs, int num)
310	{
311	struct cpm_i2c *cpm = i2c_get_adapdata(adap);
312	struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
313	struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
314	struct i2c_msg *pmsg;
315	int ret, i;
316	int tptr;
317	int rptr;
318	cbd_t __iomem *tbdf;
319	cbd_t __iomem *rbdf;
320
321	if (num > CPM_MAXBD)
322	return -EINVAL;
323
324	/* Check if we have any oversized READ requests */
325	for (i = 0; i < num; i++) {
326	pmsg = &msgs[i];
327	if (pmsg->len >= CPM_MAX_READ)
328	return -EINVAL;
329	}
330
331	/* Reset to use first buffer */
332	out_be16(&i2c_ram->rbptr, in_be16(&i2c_ram->rbase));
333	out_be16(&i2c_ram->tbptr, in_be16(&i2c_ram->tbase));
334
335	tbdf = cpm->tbase;
336	rbdf = cpm->rbase;
337
338	tptr = 0;
339	rptr = 0;
340
a16d8aa4 SS	341	/*
	342	* If there was a collision in the last i2c transaction,
	343	* Set I2COM_MASTER as it was cleared during collision.
	344	*/
	345	if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) {
	346	out_8(&cpm->i2c_reg->i2com, I2COM_MASTER);
	347	}
	348
61045dbe JF	349	while (tptr < num) {
	350	pmsg = &msgs[tptr];
	351	dev_dbg(&adap->dev, "R: %d T: %d\n", rptr, tptr);
	352
	353	cpm_i2c_parse_message(adap, pmsg, num, tptr, rptr);
	354	if (pmsg->flags & I2C_M_RD)
	355	rptr++;
	356	tptr++;
	357	}
	358	/* Start transfer now */
	359	/* Enable RX/TX/Error interupts */
3b270804	360	out_8(&i2c_reg->i2cmr, I2CER_TXE \| I2CER_TXB \| I2CER_RXB);
61045dbe JF	361	out_8(&i2c_reg->i2cer, 0xff); /* Clear interrupt status */
	362	/* Chip bug, set enable here */
	363	setbits8(&i2c_reg->i2mod, I2MOD_EN); /* Enable */
	364	/* Begin transmission */
	365	setbits8(&i2c_reg->i2com, I2COM_START);
	366
	367	tptr = 0;
	368	rptr = 0;
	369
	370	while (tptr < num) {
	371	/* Check for outstanding messages */
	372	dev_dbg(&adap->dev, "test ready.\n");
	373	pmsg = &msgs[tptr];
	374	if (pmsg->flags & I2C_M_RD)
dc1972d0	375	ret = wait_event_timeout(cpm->i2c_wait,
a804644a	376	(in_be16(&tbdf[tptr].cbd_sc) & BD_SC_NAK) \|\|
61045dbe JF	377	!(in_be16(&rbdf[rptr].cbd_sc) & BD_SC_EMPTY),
	378	1 * HZ);
	379	else
dc1972d0	380	ret = wait_event_timeout(cpm->i2c_wait,
61045dbe JF	381	!(in_be16(&tbdf[tptr].cbd_sc) & BD_SC_READY),
	382	1 * HZ);
	383	if (ret == 0) {
	384	ret = -EREMOTEIO;
	385	dev_err(&adap->dev, "I2C transfer: timeout\n");
	386	goto out_err;
	387	}
	388	if (ret > 0) {
	389	dev_dbg(&adap->dev, "ready.\n");
	390	ret = cpm_i2c_check_message(adap, pmsg, tptr, rptr);
	391	tptr++;
	392	if (pmsg->flags & I2C_M_RD)
	393	rptr++;
	394	if (ret)
	395	goto out_err;
	396	}
	397	}
	398	#ifdef I2C_CHIP_ERRATA
	399	/*
	400	* Chip errata, clear enable. This is not needed on rev D4 CPUs.
	401	* Disabling I2C too early may cause too short stop condition
	402	*/
	403	udelay(4);
	404	clrbits8(&i2c_reg->i2mod, I2MOD_EN);
	405	#endif
	406	return (num);
	407
	408	out_err:
	409	cpm_i2c_force_close(adap);
	410	#ifdef I2C_CHIP_ERRATA
	411	/*
	412	* Chip errata, clear enable. This is not needed on rev D4 CPUs.
	413	*/
	414	clrbits8(&i2c_reg->i2mod, I2MOD_EN);
	415	#endif
	416	return ret;
	417	}
	418
	419	static u32 cpm_i2c_func(struct i2c_adapter *adap)
	420	{
	421	return I2C_FUNC_I2C \| (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
	422	}
	423
	424	/* -----exported algorithm data: ------------------------------------- */
	425
	426	static const struct i2c_algorithm cpm_i2c_algo = {
	427	.master_xfer = cpm_i2c_xfer,
	428	.functionality = cpm_i2c_func,
	429	};
	430
	431	static const struct i2c_adapter cpm_ops = {
	432	.owner = THIS_MODULE,
	433	.name = "i2c-cpm",
	434	.algo = &cpm_i2c_algo,
61045dbe JF	435	};
61045dbe JF	436
0b255e92	437	static int cpm_i2c_setup(struct cpm_i2c *cpm)
61045dbe	438	{
2dc11581	439	struct platform_device *ofdev = cpm->ofdev;
61045dbe JF	440	const u32 *data;
	441	int len, ret, i;
	442	void __iomem *i2c_base;
	443	cbd_t __iomem *tbdf;
	444	cbd_t __iomem *rbdf;
	445	unsigned char brg;
	446
	447	dev_dbg(&cpm->ofdev->dev, "cpm_i2c_setup()\n");
	448
	449	init_waitqueue_head(&cpm->i2c_wait);
	450
f7578496	451	cpm->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
b865a4e7	452	if (!cpm->irq)
61045dbe JF	453	return -EINVAL;
	454
	455	/* Install interrupt handler. */
	456	ret = request_irq(cpm->irq, cpm_i2c_interrupt, 0, "cpm_i2c",
	457	&cpm->adap);
	458	if (ret)
	459	return ret;
	460
	461	/* I2C parameter RAM */
61c7a080	462	i2c_base = of_iomap(ofdev->dev.of_node, 1);
61045dbe JF	463	if (i2c_base == NULL) {
	464	ret = -EINVAL;
	465	goto out_irq;
	466	}
	467
61c7a080	468	if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm1-i2c")) {
61045dbe JF	469
	470	/* Check for and use a microcode relocation patch. */
	471	cpm->i2c_ram = i2c_base;
	472	cpm->i2c_addr = in_be16(&cpm->i2c_ram->rpbase);
	473
	474	/*
	475	* Maybe should use cpm_muram_alloc instead of hardcoding
	476	* this in micropatch.c
	477	*/
	478	if (cpm->i2c_addr) {
	479	cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
	480	iounmap(i2c_base);
	481	}
	482
	483	cpm->version = 1;
	484
61c7a080	485	} else if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm2-i2c")) {
61045dbe JF	486	cpm->i2c_addr = cpm_muram_alloc(sizeof(struct i2c_ram), 64);
	487	cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
	488	out_be16(i2c_base, cpm->i2c_addr);
	489	iounmap(i2c_base);
	490
	491	cpm->version = 2;
	492
	493	} else {
	494	iounmap(i2c_base);
	495	ret = -EINVAL;
	496	goto out_irq;
	497	}
	498
	499	/* I2C control/status registers */
61c7a080	500	cpm->i2c_reg = of_iomap(ofdev->dev.of_node, 0);
61045dbe JF	501	if (cpm->i2c_reg == NULL) {
	502	ret = -EINVAL;
	503	goto out_ram;
	504	}
	505
61c7a080	506	data = of_get_property(ofdev->dev.of_node, "fsl,cpm-command", &len);
61045dbe JF	507	if (!data \|\| len != 4) {
	508	ret = -EINVAL;
	509	goto out_reg;
	510	}
	511	cpm->cp_command = *data;
	512
61c7a080	513	data = of_get_property(ofdev->dev.of_node, "linux,i2c-class", &len);
61045dbe JF	514	if (data && len == 4)
	515	cpm->adap.class = *data;
	516
61c7a080	517	data = of_get_property(ofdev->dev.of_node, "clock-frequency", &len);
61045dbe JF	518	if (data && len == 4)
	519	cpm->freq = *data;
	520	else
	521	cpm->freq = 60000; /* use 60kHz i2c clock by default */
	522
	523	/*
	524	* Allocate space for CPM_MAXBD transmit and receive buffer
	525	* descriptors in the DP ram.
	526	*/
	527	cpm->dp_addr = cpm_muram_alloc(sizeof(cbd_t) * 2 * CPM_MAXBD, 8);
	528	if (!cpm->dp_addr) {
	529	ret = -ENOMEM;
	530	goto out_reg;
	531	}
	532
	533	cpm->tbase = cpm_muram_addr(cpm->dp_addr);
	534	cpm->rbase = cpm_muram_addr(cpm->dp_addr + sizeof(cbd_t) * CPM_MAXBD);
	535
	536	/* Allocate TX and RX buffers */
	537
	538	tbdf = cpm->tbase;
	539	rbdf = cpm->rbase;
	540
	541	for (i = 0; i < CPM_MAXBD; i++) {
36521c27 MW	542	cpm->rxbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev,
	543	CPM_MAX_READ + 1,
	544	&cpm->rxdma[i], GFP_KERNEL);
61045dbe JF	545	if (!cpm->rxbuf[i]) {
	546	ret = -ENOMEM;
	547	goto out_muram;
	548	}
	549	out_be32(&rbdf[i].cbd_bufaddr, ((cpm->rxdma[i] + 1) & ~1));
	550
36521c27	551	cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL);
61045dbe JF	552	if (!cpm->txbuf[i]) {
	553	ret = -ENOMEM;
	554	goto out_muram;
	555	}
	556	out_be32(&tbdf[i].cbd_bufaddr, cpm->txdma[i]);
	557	}
	558
	559	/* Initialize Tx/Rx parameters. */
	560
	561	cpm_reset_i2c_params(cpm);
	562
3b270804 WS	563	dev_dbg(&cpm->ofdev->dev, "i2c_ram 0x%p, i2c_addr 0x%04x, freq %d\n",
3b270804 WS	564	cpm->i2c_ram, cpm->i2c_addr, cpm->freq);
61045dbe JF	565	dev_dbg(&cpm->ofdev->dev, "tbase 0x%04x, rbase 0x%04x\n",
	566	(u8 __iomem *)cpm->tbase - DPRAM_BASE,
	567	(u8 __iomem *)cpm->rbase - DPRAM_BASE);
	568
	569	cpm_command(cpm->cp_command, CPM_CR_INIT_TRX);
	570
	571	/*
	572	* Select an invalid address. Just make sure we don't use loopback mode
	573	*/
	574	out_8(&cpm->i2c_reg->i2add, 0x7f << 1);
	575
	576	/*
	577	* PDIV is set to 00 in i2mod, so brgclk/32 is used as input to the
	578	* i2c baud rate generator. This is divided by 2 x (DIV + 3) to get
	579	* the actual i2c bus frequency.
	580	*/
	581	brg = get_brgfreq() / (32 * 2 * cpm->freq) - 3;
	582	out_8(&cpm->i2c_reg->i2brg, brg);
	583
	584	out_8(&cpm->i2c_reg->i2mod, 0x00);
	585	out_8(&cpm->i2c_reg->i2com, I2COM_MASTER); /* Master mode */
	586
	587	/* Disable interrupts. */
	588	out_8(&cpm->i2c_reg->i2cmr, 0);
	589	out_8(&cpm->i2c_reg->i2cer, 0xff);
	590
	591	return 0;
	592
	593	out_muram:
	594	for (i = 0; i < CPM_MAXBD; i++) {
	595	if (cpm->rxbuf[i])
36521c27	596	dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
61045dbe JF	597	cpm->rxbuf[i], cpm->rxdma[i]);
61045dbe JF	598	if (cpm->txbuf[i])
36521c27	599	dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
61045dbe JF	600	cpm->txbuf[i], cpm->txdma[i]);
	601	}
	602	cpm_muram_free(cpm->dp_addr);
	603	out_reg:
	604	iounmap(cpm->i2c_reg);
	605	out_ram:
	606	if ((cpm->version == 1) && (!cpm->i2c_addr))
	607	iounmap(cpm->i2c_ram);
	608	if (cpm->version == 2)
	609	cpm_muram_free(cpm->i2c_addr);
	610	out_irq:
	611	free_irq(cpm->irq, &cpm->adap);
	612	return ret;
	613	}
	614
	615	static void cpm_i2c_shutdown(struct cpm_i2c *cpm)
	616	{
	617	int i;
	618
	619	/* Shut down I2C. */
	620	clrbits8(&cpm->i2c_reg->i2mod, I2MOD_EN);
	621
	622	/* Disable interrupts */
	623	out_8(&cpm->i2c_reg->i2cmr, 0);
	624	out_8(&cpm->i2c_reg->i2cer, 0xff);
	625
	626	free_irq(cpm->irq, &cpm->adap);
	627
	628	/* Free all memory */
	629	for (i = 0; i < CPM_MAXBD; i++) {
36521c27	630	dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
61045dbe	631	cpm->rxbuf[i], cpm->rxdma[i]);
36521c27	632	dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
61045dbe JF	633	cpm->txbuf[i], cpm->txdma[i]);
	634	}
	635
	636	cpm_muram_free(cpm->dp_addr);
	637	iounmap(cpm->i2c_reg);
	638
	639	if ((cpm->version == 1) && (!cpm->i2c_addr))
	640	iounmap(cpm->i2c_ram);
	641	if (cpm->version == 2)
	642	cpm_muram_free(cpm->i2c_addr);
	643	}
	644
0b255e92	645	static int cpm_i2c_probe(struct platform_device *ofdev)
61045dbe JF	646	{
	647	int result, len;
	648	struct cpm_i2c *cpm;
	649	const u32 *data;
	650
	651	cpm = kzalloc(sizeof(struct cpm_i2c), GFP_KERNEL);
	652	if (!cpm)
	653	return -ENOMEM;
	654
	655	cpm->ofdev = ofdev;
	656
c2c64954	657	platform_set_drvdata(ofdev, cpm);
61045dbe JF	658
	659	cpm->adap = cpm_ops;
	660	i2c_set_adapdata(&cpm->adap, cpm);
	661	cpm->adap.dev.parent = &ofdev->dev;
9fd04992	662	cpm->adap.dev.of_node = of_node_get(ofdev->dev.of_node);
61045dbe JF	663
	664	result = cpm_i2c_setup(cpm);
	665	if (result) {
	666	dev_err(&ofdev->dev, "Unable to init hardware\n");
	667	goto out_free;
	668	}
	669
	670	/* register new adapter to i2c module... */
	671
61c7a080	672	data = of_get_property(ofdev->dev.of_node, "linux,i2c-index", &len);
488bf314 GL	673	cpm->adap.nr = (data && len == 4) ? be32_to_cpup(data) : -1;
488bf314 GL	674	result = i2c_add_numbered_adapter(&cpm->adap);
61045dbe JF	675
	676	if (result < 0) {
	677	dev_err(&ofdev->dev, "Unable to register with I2C\n");
	678	goto out_shut;
	679	}
	680
	681	dev_dbg(&ofdev->dev, "hw routines for %s registered.\n",
	682	cpm->adap.name);
	683
61045dbe JF	684	return 0;
	685	out_shut:
	686	cpm_i2c_shutdown(cpm);
	687	out_free:
61045dbe JF	688	kfree(cpm);
	689
	690	return result;
	691	}
	692
0b255e92	693	static int cpm_i2c_remove(struct platform_device *ofdev)
61045dbe	694	{
c2c64954	695	struct cpm_i2c *cpm = platform_get_drvdata(ofdev);
61045dbe JF	696
	697	i2c_del_adapter(&cpm->adap);
	698
	699	cpm_i2c_shutdown(cpm);
	700
61045dbe JF	701	kfree(cpm);
	702
	703	return 0;
	704	}
	705
	706	static const struct of_device_id cpm_i2c_match[] = {
	707	{
	708	.compatible = "fsl,cpm1-i2c",
	709	},
	710	{
	711	.compatible = "fsl,cpm2-i2c",
	712	},
	713	{},
	714	};
	715
	716	MODULE_DEVICE_TABLE(of, cpm_i2c_match);
	717
1c48a5c9	718	static struct platform_driver cpm_i2c_driver = {
61045dbe	719	.probe = cpm_i2c_probe,
0b255e92	720	.remove = cpm_i2c_remove,
4018294b GL	721	.driver = {
	722	.name = "fsl-i2c-cpm",
	723	.owner = THIS_MODULE,
	724	.of_match_table = cpm_i2c_match,
	725	},
61045dbe JF	726	};
61045dbe JF	727
a3664b51	728	module_platform_driver(cpm_i2c_driver);
61045dbe JF	729
	730	MODULE_AUTHOR("Jochen Friedrich <jochen@scram.de>");
	731	MODULE_DESCRIPTION("I2C-Bus adapter routines for CPM boards");
	732	MODULE_LICENSE("GPL");