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Merge tag '4.4-additional' of git://git.lwn.net/linux
[deliverable/linux.git] / drivers / i2c / busses / i2c-davinci.c
CommitLineData
95a7f10e
VB		 1/*
2 * TI DAVINCI I2C adapter driver.
3 *
4 * Copyright (C) 2006 Texas Instruments.
5 * Copyright (C) 2007 MontaVista Software Inc.
6 *
7 * Updated by Vinod & Sudhakar Feb 2005
8 *
9 * ----------------------------------------------------------------------------
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
95a7f10e
VB		 20 * ----------------------------------------------------------------------------
21 *
22 */
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/delay.h>
26#include <linux/i2c.h>
27#include <linux/clk.h>
28#include <linux/errno.h>
29#include <linux/sched.h>
30#include <linux/err.h>
31#include <linux/interrupt.h>
32#include <linux/platform_device.h>
33#include <linux/io.h>
5a0e3ad6 34#include <linux/slab.h>
82c0de11 35#include <linux/cpufreq.h>
8574faf9 36#include <linux/gpio.h>
5c3d8a46 37#include <linux/of_device.h>
ec2a0833 38#include <linux/platform_data/i2c-davinci.h>
95a7f10e
VB		 39
40/* ----- global defines ----------------------------------------------- */
41
42#define DAVINCI_I2C_TIMEOUT (1*HZ)
8574faf9 43#define DAVINCI_I2C_MAX_TRIES 2
41c8d452
AS		 44#define DAVINCI_I2C_OWN_ADDRESS 0x08
45#define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_SCD | \
95a7f10e
VB		 46 DAVINCI_I2C_IMR_ARDY | \
47 DAVINCI_I2C_IMR_NACK | \
48 DAVINCI_I2C_IMR_AL)
49
50#define DAVINCI_I2C_OAR_REG 0x00
51#define DAVINCI_I2C_IMR_REG 0x04
52#define DAVINCI_I2C_STR_REG 0x08
53#define DAVINCI_I2C_CLKL_REG 0x0c
54#define DAVINCI_I2C_CLKH_REG 0x10
55#define DAVINCI_I2C_CNT_REG 0x14
56#define DAVINCI_I2C_DRR_REG 0x18
57#define DAVINCI_I2C_SAR_REG 0x1c
58#define DAVINCI_I2C_DXR_REG 0x20
59#define DAVINCI_I2C_MDR_REG 0x24
60#define DAVINCI_I2C_IVR_REG 0x28
61#define DAVINCI_I2C_EMDR_REG 0x2c
62#define DAVINCI_I2C_PSC_REG 0x30
7ef97e9a
GS		 63#define DAVINCI_I2C_FUNC_REG 0x48
64#define DAVINCI_I2C_DIR_REG 0x4c
65#define DAVINCI_I2C_DIN_REG 0x50
66#define DAVINCI_I2C_DOUT_REG 0x54
67#define DAVINCI_I2C_DSET_REG 0x58
68#define DAVINCI_I2C_DCLR_REG 0x5c
95a7f10e
VB		 69
70#define DAVINCI_I2C_IVR_AAS 0x07
71#define DAVINCI_I2C_IVR_SCD 0x06
72#define DAVINCI_I2C_IVR_XRDY 0x05
73#define DAVINCI_I2C_IVR_RDR 0x04
74#define DAVINCI_I2C_IVR_ARDY 0x03
75#define DAVINCI_I2C_IVR_NACK 0x02
76#define DAVINCI_I2C_IVR_AL 0x01
77
c062a251
C		 78#define DAVINCI_I2C_STR_BB BIT(12)
79#define DAVINCI_I2C_STR_RSFULL BIT(11)
80#define DAVINCI_I2C_STR_SCD BIT(5)
81#define DAVINCI_I2C_STR_ARDY BIT(2)
82#define DAVINCI_I2C_STR_NACK BIT(1)
83#define DAVINCI_I2C_STR_AL BIT(0)
84
85#define DAVINCI_I2C_MDR_NACK BIT(15)
86#define DAVINCI_I2C_MDR_STT BIT(13)
87#define DAVINCI_I2C_MDR_STP BIT(11)
88#define DAVINCI_I2C_MDR_MST BIT(10)
89#define DAVINCI_I2C_MDR_TRX BIT(9)
90#define DAVINCI_I2C_MDR_XA BIT(8)
91#define DAVINCI_I2C_MDR_RM BIT(7)
92#define DAVINCI_I2C_MDR_IRS BIT(5)
93
94#define DAVINCI_I2C_IMR_AAS BIT(6)
95#define DAVINCI_I2C_IMR_SCD BIT(5)
96#define DAVINCI_I2C_IMR_XRDY BIT(4)
97#define DAVINCI_I2C_IMR_RRDY BIT(3)
98#define DAVINCI_I2C_IMR_ARDY BIT(2)
99#define DAVINCI_I2C_IMR_NACK BIT(1)
100#define DAVINCI_I2C_IMR_AL BIT(0)
95a7f10e 101
7ef97e9a
GS		 102/* set SDA and SCL as GPIO */
103#define DAVINCI_I2C_FUNC_PFUNC0 BIT(0)
104
105/* set SCL as output when used as GPIO*/
106#define DAVINCI_I2C_DIR_PDIR0 BIT(0)
107/* set SDA as output when used as GPIO*/
108#define DAVINCI_I2C_DIR_PDIR1 BIT(1)
109
110/* read SCL GPIO level */
111#define DAVINCI_I2C_DIN_PDIN0 BIT(0)
112/* read SDA GPIO level */
113#define DAVINCI_I2C_DIN_PDIN1 BIT(1)
114
115/*set the SCL GPIO high */
116#define DAVINCI_I2C_DSET_PDSET0 BIT(0)
117/*set the SDA GPIO high */
118#define DAVINCI_I2C_DSET_PDSET1 BIT(1)
119
120/* set the SCL GPIO low */
121#define DAVINCI_I2C_DCLR_PDCLR0 BIT(0)
122/* set the SDA GPIO low */
123#define DAVINCI_I2C_DCLR_PDCLR1 BIT(1)
124
95a7f10e
VB		 125struct davinci_i2c_dev {
126 struct device *dev;
127 void __iomem *base;
128 struct completion cmd_complete;
129 struct clk *clk;
130 int cmd_err;
131 u8 *buf;
132 size_t buf_len;
133 int irq;
c6c7c729 134 int stop;
5a0d5f5f 135 u8 terminate;
95a7f10e 136 struct i2c_adapter adapter;
82c0de11
C		 137#ifdef CONFIG_CPU_FREQ
138 struct completion xfr_complete;
139 struct notifier_block freq_transition;
140#endif
5c3d8a46 141 struct davinci_i2c_platform_data *pdata;
95a7f10e
VB		 142};
143
144/* default platform data to use if not supplied in the platform_device */
145static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
146 .bus_freq = 100,
147 .bus_delay = 0,
148};
149
150static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
151 int reg, u16 val)
152{
a238dcfa 153 writew_relaxed(val, i2c_dev->base + reg);
95a7f10e
VB		 154}
155
156static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
157{
a238dcfa 158 return readw_relaxed(i2c_dev->base + reg);
95a7f10e
VB		 159}
160
5ae5b113
C		 161static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
162 int val)
163{
164 u16 w;
165
166 w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
167 if (!val) /* put I2C into reset */
168 w &= ~DAVINCI_I2C_MDR_IRS;
169 else /* take I2C out of reset */
170 w |= DAVINCI_I2C_MDR_IRS;
171
172 davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
173}
174
175static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
95a7f10e 176{
5c3d8a46 177 struct davinci_i2c_platform_data *pdata = dev->pdata;
95a7f10e
VB		 178 u16 psc;
179 u32 clk;
cc99ff70 180 u32 d;
95a7f10e
VB		 181 u32 clkh;
182 u32 clkl;
183 u32 input_clock = clk_get_rate(dev->clk);
35780e86 184 struct device_node *of_node = dev->dev->of_node;
95a7f10e
VB		 185
186 /* NOTE: I2C Clock divider programming info
187 * As per I2C specs the following formulas provide prescaler
188 * and low/high divider values
189 * input clk --> PSC Div -----------> ICCL/H Div --> output clock
190 * module clk
191 *
192 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
193 *
194 * Thus,
195 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
196 *
197 * where if PSC == 0, d = 7,
198 * if PSC == 1, d = 6
199 * if PSC > 1 , d = 5
35780e86
AS		 200 *
201 * Note:
202 * d is always 6 on Keystone I2C controller
95a7f10e
VB		 203 */
204
cc99ff70
TK		 205 /* get minimum of 7 MHz clock, but max of 12 MHz */
206 psc = (input_clock / 7000000) - 1;
207 if ((input_clock / (psc + 1)) > 12000000)
208 psc++; /* better to run under spec than over */
209 d = (psc >= 2) ? 5 : 7 - psc;
95a7f10e 210
35780e86
AS		 211 if (of_node && of_device_is_compatible(of_node, "ti,keystone-i2c"))
212 d = 6;
213
955fc950
AS		 214 clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000));
215 /* Avoid driving the bus too fast because of rounding errors above */
216 if (input_clock / (psc + 1) / clk > pdata->bus_freq * 1000)
217 clk++;
218 /*
219 * According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at
220 * least 1.3uS, which is not the case with 50% duty cycle. Driving HIGH
221 * to LOW ratio as 1 to 2 is more safe.
222 */
223 if (pdata->bus_freq > 100)
224 clkl = (clk << 1) / 3;
225 else
226 clkl = (clk >> 1);
227 /*
228 * It's not always possible to have 1 to 2 ratio when d=7, so fall back
229 * to minimal possible clkh in this case.
230 */
231 if (clk >= clkl + d) {
232 clkh = clk - clkl - d;
233 clkl -= d;
234 } else {
235 clkh = 0;
236 clkl = clk - (d << 1);
237 }
95a7f10e
VB		 238
239 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
240 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
241 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
242
5ae5b113
C		 243 dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
244}
245
246/*
247 * This function configures I2C and brings I2C out of reset.
248 * This function is called during I2C init function. This function
249 * also gets called if I2C encounters any errors.
250 */
251static int i2c_davinci_init(struct davinci_i2c_dev *dev)
252{
5c3d8a46 253 struct davinci_i2c_platform_data *pdata = dev->pdata;
5ae5b113
C		 254
255 /* put I2C into reset */
256 davinci_i2c_reset_ctrl(dev, 0);
257
258 /* compute clock dividers */
259 i2c_davinci_calc_clk_dividers(dev);
260
7605fa3b
DB		 261 /* Respond at reserved "SMBus Host" slave address" (and zero);
262 * we seem to have no option to not respond...
263 */
41c8d452 264 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, DAVINCI_I2C_OWN_ADDRESS);
7605fa3b 265
95a7f10e
VB		 266 dev_dbg(dev->dev, "PSC = %d\n",
267 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
268 dev_dbg(dev->dev, "CLKL = %d\n",
269 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
270 dev_dbg(dev->dev, "CLKH = %d\n",
271 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
cc99ff70
TK		 272 dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
273 pdata->bus_freq, pdata->bus_delay);
95a7f10e 274
5c3d8a46 275
95a7f10e 276 /* Take the I2C module out of reset: */
5ae5b113 277 davinci_i2c_reset_ctrl(dev, 1);
95a7f10e
VB		 278
279 /* Enable interrupts */
280 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
281
282 return 0;
283}
284
2e65676f
GS		 285/*
286 * This routine does i2c bus recovery by using i2c_generic_gpio_recovery
287 * which is provided by I2C Bus recovery infrastructure.
288 */
289static void davinci_i2c_prepare_recovery(struct i2c_adapter *adap)
290{
291 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
292
293 /* Disable interrupts */
294 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, 0);
295
296 /* put I2C into reset */
297 davinci_i2c_reset_ctrl(dev, 0);
298}
299
300static void davinci_i2c_unprepare_recovery(struct i2c_adapter *adap)
301{
302 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
303
304 i2c_davinci_init(dev);
305}
306
307static struct i2c_bus_recovery_info davinci_i2c_gpio_recovery_info = {
308 .recover_bus = i2c_generic_gpio_recovery,
309 .prepare_recovery = davinci_i2c_prepare_recovery,
310 .unprepare_recovery = davinci_i2c_unprepare_recovery,
311};
312
7ef97e9a
GS		 313static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val)
314{
315 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
316
317 if (val)
318 davinci_i2c_write_reg(dev, DAVINCI_I2C_DSET_REG,
319 DAVINCI_I2C_DSET_PDSET0);
320 else
321 davinci_i2c_write_reg(dev, DAVINCI_I2C_DCLR_REG,
322 DAVINCI_I2C_DCLR_PDCLR0);
323}
324
325static int davinci_i2c_get_scl(struct i2c_adapter *adap)
326{
327 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
328 int val;
329
330 /* read the state of SCL */
331 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
332 return val & DAVINCI_I2C_DIN_PDIN0;
333}
334
335static int davinci_i2c_get_sda(struct i2c_adapter *adap)
336{
337 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
338 int val;
339
340 /* read the state of SDA */
341 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
342 return val & DAVINCI_I2C_DIN_PDIN1;
343}
344
345static void davinci_i2c_scl_prepare_recovery(struct i2c_adapter *adap)
346{
347 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
348
349 davinci_i2c_prepare_recovery(adap);
350
351 /* SCL output, SDA input */
352 davinci_i2c_write_reg(dev, DAVINCI_I2C_DIR_REG, DAVINCI_I2C_DIR_PDIR0);
353
354 /* change to GPIO mode */
355 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG,
356 DAVINCI_I2C_FUNC_PFUNC0);
357}
358
359static void davinci_i2c_scl_unprepare_recovery(struct i2c_adapter *adap)
360{
361 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
362
363 /* change back to I2C mode */
364 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 0);
365
366 davinci_i2c_unprepare_recovery(adap);
367}
368
369static struct i2c_bus_recovery_info davinci_i2c_scl_recovery_info = {
370 .recover_bus = i2c_generic_scl_recovery,
371 .set_scl = davinci_i2c_set_scl,
372 .get_scl = davinci_i2c_get_scl,
373 .get_sda = davinci_i2c_get_sda,
374 .prepare_recovery = davinci_i2c_scl_prepare_recovery,
375 .unprepare_recovery = davinci_i2c_scl_unprepare_recovery,
376};
377
95a7f10e
VB		 378/*
379 * Waiting for bus not busy
380 */
72a956c5 381static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev)
95a7f10e 382{
72a956c5
AS		 383 unsigned long timeout = jiffies + dev->adapter.timeout;
384
385 do {
386 if (!(davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB))
387 return 0;
388 schedule_timeout_uninterruptible(1);
389 } while (time_before_eq(jiffies, timeout));
390
391 dev_warn(dev->dev, "timeout waiting for bus ready\n");
392 i2c_recover_bus(&dev->adapter);
393
394 /*
395 * if bus is still "busy" here, it's most probably a HW problem like
396 * short-circuit
397 */
398 if (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB)
399 return -EIO;
95a7f10e
VB		 400
401 return 0;
402}
403
404/*
405 * Low level master read/write transaction. This function is called
406 * from i2c_davinci_xfer.
407 */
408static int
409i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
410{
411 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
5c3d8a46 412 struct davinci_i2c_platform_data *pdata = dev->pdata;
95a7f10e 413 u32 flag;
95a7f10e 414 u16 w;
d9e1f441 415 unsigned long time_left;
95a7f10e 416
41c8d452
AS		 417 if (msg->addr == DAVINCI_I2C_OWN_ADDRESS) {
418 dev_warn(dev->dev, "transfer to own address aborted\n");
419 return -EADDRNOTAVAIL;
420 }
421
95a7f10e
VB		 422 /* Introduce a delay, required for some boards (e.g Davinci EVM) */
423 if (pdata->bus_delay)
424 udelay(pdata->bus_delay);
425
426 /* set the slave address */
427 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
428
429 dev->buf = msg->buf;
430 dev->buf_len = msg->len;
c6c7c729 431 dev->stop = stop;
95a7f10e
VB		 432
433 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
434
16735d02 435 reinit_completion(&dev->cmd_complete);
95a7f10e
VB		 436 dev->cmd_err = 0;
437
c5b4afec
JP		 438 /* Take I2C out of reset and configure it as master */
439 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
95a7f10e
VB		 440
441 /* if the slave address is ten bit address, enable XA bit */
442 if (msg->flags & I2C_M_TEN)
443 flag |= DAVINCI_I2C_MDR_XA;
444 if (!(msg->flags & I2C_M_RD))
445 flag |= DAVINCI_I2C_MDR_TRX;
c5b4afec 446 if (msg->len == 0)
c6c7c729 447 flag |= DAVINCI_I2C_MDR_RM;
95a7f10e
VB		 448
449 /* Enable receive or transmit interrupts */
450 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
451 if (msg->flags & I2C_M_RD)
c062a251 452 w |= DAVINCI_I2C_IMR_RRDY;
95a7f10e 453 else
c062a251 454 w |= DAVINCI_I2C_IMR_XRDY;
95a7f10e
VB		 455 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
456
5a0d5f5f 457 dev->terminate = 0;
c6c7c729 458
c5b4afec
JP		 459 /*
460 * Write mode register first as needed for correct behaviour
461 * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
25985edc 462 * occurring before we have loaded DXR
c5b4afec
JP		 463 */
464 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
465
c6c7c729
DB		 466 /*
467 * First byte should be set here, not after interrupt,
468 * because transmit-data-ready interrupt can come before
469 * NACK-interrupt during sending of previous message and
470 * ICDXR may have wrong data
c5b4afec 471 * It also saves us one interrupt, slightly faster
c6c7c729
DB		 472 */
473 if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
474 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
475 dev->buf_len--;
476 }
477
c5b4afec
JP		 478 /* Set STT to begin transmit now DXR is loaded */
479 flag |= DAVINCI_I2C_MDR_STT;
480 if (stop && msg->len != 0)
481 flag |= DAVINCI_I2C_MDR_STP;
4bba0fd8
JP		 482 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
483
d9e1f441
NMG		 484 time_left = wait_for_completion_timeout(&dev->cmd_complete,
485 dev->adapter.timeout);
486 if (!time_left) {
95a7f10e 487 dev_err(dev->dev, "controller timed out\n");
2e65676f 488 i2c_recover_bus(adap);
5a0d5f5f 489 dev->buf_len = 0;
95a7f10e
VB		 490 return -ETIMEDOUT;
491 }
5a0d5f5f
TK		 492 if (dev->buf_len) {
493 /* This should be 0 if all bytes were transferred
494 * or dev->cmd_err denotes an error.
5a0d5f5f 495 */
d9e1f441
NMG		 496 dev_err(dev->dev, "abnormal termination buf_len=%i\n",
497 dev->buf_len);
5a0d5f5f
TK		 498 dev->terminate = 1;
499 wmb();
500 dev->buf_len = 0;
d9e1f441 501 return -EREMOTEIO;
5a0d5f5f 502 }
95a7f10e
VB		 503
504 /* no error */
505 if (likely(!dev->cmd_err))
506 return msg->len;
507
508 /* We have an error */
509 if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
510 i2c_davinci_init(dev);
511 return -EIO;
512 }
513
514 if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
515 if (msg->flags & I2C_M_IGNORE_NAK)
516 return msg->len;
9ea359f7
GS		 517 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
518 w |= DAVINCI_I2C_MDR_STP;
519 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
95a7f10e
VB		 520 return -EREMOTEIO;
521 }
522 return -EIO;
523}
524
525/*
526 * Prepare controller for a transaction and call i2c_davinci_xfer_msg
527 */
528static int
529i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
530{
531 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
532 int i;
533 int ret;
534
08882d20 535 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
95a7f10e 536
72a956c5 537 ret = i2c_davinci_wait_bus_not_busy(dev);
95a7f10e
VB		 538 if (ret < 0) {
539 dev_warn(dev->dev, "timeout waiting for bus ready\n");
540 return ret;
541 }
542
543 for (i = 0; i < num; i++) {
544 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
d868caa1
TK		 545 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
546 ret);
95a7f10e
VB		 547 if (ret < 0)
548 return ret;
549 }
82c0de11
C		 550
551#ifdef CONFIG_CPU_FREQ
552 complete(&dev->xfr_complete);
553#endif
554
95a7f10e
VB		 555 return num;
556}
557
558static u32 i2c_davinci_func(struct i2c_adapter *adap)
559{
c6c7c729 560 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
95a7f10e
VB		 561}
562
5a0d5f5f
TK		 563static void terminate_read(struct davinci_i2c_dev *dev)
564{
565 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
566 w |= DAVINCI_I2C_MDR_NACK;
567 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
568
569 /* Throw away data */
570 davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
571 if (!dev->terminate)
572 dev_err(dev->dev, "RDR IRQ while no data requested\n");
573}
574static void terminate_write(struct davinci_i2c_dev *dev)
575{
576 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
577 w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
578 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
579
580 if (!dev->terminate)
7605fa3b 581 dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
5a0d5f5f
TK		 582}
583
95a7f10e
VB		 584/*
585 * Interrupt service routine. This gets called whenever an I2C interrupt
586 * occurs.
587 */
588static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
589{
590 struct davinci_i2c_dev *dev = dev_id;
591 u32 stat;
592 int count = 0;
593 u16 w;
594
595 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
08882d20 596 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
95a7f10e
VB		 597 if (count++ == 100) {
598 dev_warn(dev->dev, "Too much work in one IRQ\n");
599 break;
600 }
601
602 switch (stat) {
603 case DAVINCI_I2C_IVR_AL:
5a0d5f5f 604 /* Arbitration lost, must retry */
95a7f10e 605 dev->cmd_err |= DAVINCI_I2C_STR_AL;
5a0d5f5f 606 dev->buf_len = 0;
95a7f10e
VB		 607 complete(&dev->cmd_complete);
608 break;
609
610 case DAVINCI_I2C_IVR_NACK:
611 dev->cmd_err |= DAVINCI_I2C_STR_NACK;
5a0d5f5f 612 dev->buf_len = 0;
95a7f10e
VB		 613 complete(&dev->cmd_complete);
614 break;
615
616 case DAVINCI_I2C_IVR_ARDY:
b73a9aec
TK		 617 davinci_i2c_write_reg(dev,
618 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
c6c7c729
DB		 619 if (((dev->buf_len == 0) && (dev->stop != 0)) ||
620 (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
621 w = davinci_i2c_read_reg(dev,
622 DAVINCI_I2C_MDR_REG);
623 w |= DAVINCI_I2C_MDR_STP;
624 davinci_i2c_write_reg(dev,
625 DAVINCI_I2C_MDR_REG, w);
626 }
95a7f10e
VB		 627 complete(&dev->cmd_complete);
628 break;
629
630 case DAVINCI_I2C_IVR_RDR:
631 if (dev->buf_len) {
632 *dev->buf++ =
633 davinci_i2c_read_reg(dev,
634 DAVINCI_I2C_DRR_REG);
635 dev->buf_len--;
636 if (dev->buf_len)
637 continue;
638
95a7f10e 639 davinci_i2c_write_reg(dev,
b73a9aec
TK		 640 DAVINCI_I2C_STR_REG,
641 DAVINCI_I2C_IMR_RRDY);
5a0d5f5f
TK		 642 } else {
643 /* signal can terminate transfer */
644 terminate_read(dev);
645 }
95a7f10e
VB		 646 break;
647
648 case DAVINCI_I2C_IVR_XRDY:
649 if (dev->buf_len) {
650 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
651 *dev->buf++);
652 dev->buf_len--;
653 if (dev->buf_len)
654 continue;
655
656 w = davinci_i2c_read_reg(dev,
657 DAVINCI_I2C_IMR_REG);
c062a251 658 w &= ~DAVINCI_I2C_IMR_XRDY;
95a7f10e
VB		 659 davinci_i2c_write_reg(dev,
660 DAVINCI_I2C_IMR_REG,
661 w);
5a0d5f5f
TK		 662 } else {
663 /* signal can terminate transfer */
664 terminate_write(dev);
665 }
95a7f10e
VB		 666 break;
667
668 case DAVINCI_I2C_IVR_SCD:
b73a9aec
TK		 669 davinci_i2c_write_reg(dev,
670 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
95a7f10e
VB		 671 complete(&dev->cmd_complete);
672 break;
673
674 case DAVINCI_I2C_IVR_AAS:
7605fa3b
DB		 675 dev_dbg(dev->dev, "Address as slave interrupt\n");
676 break;
677
678 default:
679 dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
680 break;
681 }
682 }
95a7f10e
VB		 683
684 return count ? IRQ_HANDLED : IRQ_NONE;
685}
686
82c0de11
C		 687#ifdef CONFIG_CPU_FREQ
688static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
689 unsigned long val, void *data)
690{
691 struct davinci_i2c_dev *dev;
692
693 dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
694 if (val == CPUFREQ_PRECHANGE) {
695 wait_for_completion(&dev->xfr_complete);
696 davinci_i2c_reset_ctrl(dev, 0);
697 } else if (val == CPUFREQ_POSTCHANGE) {
698 i2c_davinci_calc_clk_dividers(dev);
699 davinci_i2c_reset_ctrl(dev, 1);
700 }
701
702 return 0;
703}
704
705static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
706{
707 dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
708
709 return cpufreq_register_notifier(&dev->freq_transition,
710 CPUFREQ_TRANSITION_NOTIFIER);
711}
712
713static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
714{
715 cpufreq_unregister_notifier(&dev->freq_transition,
716 CPUFREQ_TRANSITION_NOTIFIER);
717}
718#else
719static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
720{
721 return 0;
722}
723
724static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
725{
726}
727#endif
728
95a7f10e
VB		 729static struct i2c_algorithm i2c_davinci_algo = {
730 .master_xfer = i2c_davinci_xfer,
731 .functionality = i2c_davinci_func,
732};
733
5c3d8a46
HS		 734static const struct of_device_id davinci_i2c_of_match[] = {
735 {.compatible = "ti,davinci-i2c", },
35780e86 736 {.compatible = "ti,keystone-i2c", },
5c3d8a46
HS		 737 {},
738};
739MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
740
95a7f10e
VB		 741static int davinci_i2c_probe(struct platform_device *pdev)
742{
743 struct davinci_i2c_dev *dev;
744 struct i2c_adapter *adap;
2c6ef04f
GS		 745 struct resource *mem;
746 int r, irq;
747
748 irq = platform_get_irq(pdev, 0);
749 if (irq <= 0) {
750 if (!irq)
751 irq = -ENXIO;
752 if (irq != -EPROBE_DEFER)
753 dev_err(&pdev->dev,
754 "can't get irq resource ret=%d\n", irq);
755 return irq;
95a7f10e
VB		 756 }
757
85796843
VBM		 758 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev),
759 GFP_KERNEL);
95a7f10e 760 if (!dev) {
85796843
VBM		 761 dev_err(&pdev->dev, "Memory allocation failed\n");
762 return -ENOMEM;
95a7f10e
VB		 763 }
764
2e743787 765 init_completion(&dev->cmd_complete);
82c0de11
C		 766#ifdef CONFIG_CPU_FREQ
767 init_completion(&dev->xfr_complete);
768#endif
c4df5000 769 dev->dev = &pdev->dev;
2c6ef04f 770 dev->irq = irq;
1e2c2390 771 dev->pdata = dev_get_platdata(&pdev->dev);
95a7f10e
VB		 772 platform_set_drvdata(pdev, dev);
773
5c3d8a46
HS		 774 if (!dev->pdata && pdev->dev.of_node) {
775 u32 prop;
776
777 dev->pdata = devm_kzalloc(&pdev->dev,
778 sizeof(struct davinci_i2c_platform_data), GFP_KERNEL);
c4df5000
WS		 779 if (!dev->pdata)
780 return -ENOMEM;
781
5c3d8a46
HS		 782 memcpy(dev->pdata, &davinci_i2c_platform_data_default,
783 sizeof(struct davinci_i2c_platform_data));
784 if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
785 &prop))
786 dev->pdata->bus_freq = prop / 1000;
7ef97e9a
GS		 787
788 dev->pdata->has_pfunc =
789 of_property_read_bool(pdev->dev.of_node,
790 "ti,has-pfunc");
5c3d8a46
HS		 791 } else if (!dev->pdata) {
792 dev->pdata = &davinci_i2c_platform_data_default;
793 }
794
85796843 795 dev->clk = devm_clk_get(&pdev->dev, NULL);
c4df5000
WS		 796 if (IS_ERR(dev->clk))
797 return -ENODEV;
2bdbfa9c 798 clk_prepare_enable(dev->clk);
95a7f10e 799
3cc2d009 800 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
85796843
VBM		 801 dev->base = devm_ioremap_resource(&pdev->dev, mem);
802 if (IS_ERR(dev->base)) {
803 r = PTR_ERR(dev->base);
804 goto err_unuse_clocks;
c062a251
C		 805 }
806
95a7f10e
VB		 807 i2c_davinci_init(dev);
808
85796843
VBM		 809 r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0,
810 pdev->name, dev);
95a7f10e
VB		 811 if (r) {
812 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
813 goto err_unuse_clocks;
814 }
815
82c0de11
C		 816 r = i2c_davinci_cpufreq_register(dev);
817 if (r) {
818 dev_err(&pdev->dev, "failed to register cpufreq\n");
85796843 819 goto err_unuse_clocks;
82c0de11
C		 820 }
821
95a7f10e
VB		 822 adap = &dev->adapter;
823 i2c_set_adapdata(adap, dev);
824 adap->owner = THIS_MODULE;
adcb82a9 825 adap->class = I2C_CLASS_DEPRECATED;
95a7f10e
VB		 826 strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
827 adap->algo = &i2c_davinci_algo;
828 adap->dev.parent = &pdev->dev;
98a679ca 829 adap->timeout = DAVINCI_I2C_TIMEOUT;
5c3d8a46 830 adap->dev.of_node = pdev->dev.of_node;
95a7f10e 831
7ef97e9a
GS		 832 if (dev->pdata->has_pfunc)
833 adap->bus_recovery_info = &davinci_i2c_scl_recovery_info;
834 else if (dev->pdata->scl_pin) {
2e65676f
GS		 835 adap->bus_recovery_info = &davinci_i2c_gpio_recovery_info;
836 adap->bus_recovery_info->scl_gpio = dev->pdata->scl_pin;
837 adap->bus_recovery_info->sda_gpio = dev->pdata->sda_pin;
838 }
839
95a7f10e
VB		 840 adap->nr = pdev->id;
841 r = i2c_add_numbered_adapter(adap);
842 if (r) {
843 dev_err(&pdev->dev, "failure adding adapter\n");
85796843 844 goto err_unuse_clocks;
95a7f10e
VB		 845 }
846
847 return 0;
848
95a7f10e 849err_unuse_clocks:
2bdbfa9c 850 clk_disable_unprepare(dev->clk);
95a7f10e 851 dev->clk = NULL;
95a7f10e
VB		 852 return r;
853}
854
855static int davinci_i2c_remove(struct platform_device *pdev)
856{
857 struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
95a7f10e 858
82c0de11
C		 859 i2c_davinci_cpufreq_deregister(dev);
860
95a7f10e 861 i2c_del_adapter(&dev->adapter);
95a7f10e 862
2bdbfa9c 863 clk_disable_unprepare(dev->clk);
95a7f10e
VB		 864 dev->clk = NULL;
865
866 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
95a7f10e 867
95a7f10e
VB		 868 return 0;
869}
870
68f15de9
C		 871#ifdef CONFIG_PM
872static int davinci_i2c_suspend(struct device *dev)
873{
874 struct platform_device *pdev = to_platform_device(dev);
875 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
876
877 /* put I2C into reset */
878 davinci_i2c_reset_ctrl(i2c_dev, 0);
2bdbfa9c 879 clk_disable_unprepare(i2c_dev->clk);
68f15de9
C		 880
881 return 0;
882}
883
884static int davinci_i2c_resume(struct device *dev)
885{
886 struct platform_device *pdev = to_platform_device(dev);
887 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
888
2bdbfa9c 889 clk_prepare_enable(i2c_dev->clk);
68f15de9
C		 890 /* take I2C out of reset */
891 davinci_i2c_reset_ctrl(i2c_dev, 1);
892
893 return 0;
894}
895
896static const struct dev_pm_ops davinci_i2c_pm = {
897 .suspend = davinci_i2c_suspend,
898 .resume = davinci_i2c_resume,
899};
900
901#define davinci_i2c_pm_ops (&davinci_i2c_pm)
902#else
903#define davinci_i2c_pm_ops NULL
904#endif
905
add8eda7
KS		 906/* work with hotplug and coldplug */
907MODULE_ALIAS("platform:i2c_davinci");
908
95a7f10e
VB		 909static struct platform_driver davinci_i2c_driver = {
910 .probe = davinci_i2c_probe,
911 .remove = davinci_i2c_remove,
912 .driver = {
913 .name = "i2c_davinci",
68f15de9 914 .pm = davinci_i2c_pm_ops,
4e905323 915 .of_match_table = davinci_i2c_of_match,
95a7f10e
VB		 916 },
917};
918
919/* I2C may be needed to bring up other drivers */
920static int __init davinci_i2c_init_driver(void)
921{
922 return platform_driver_register(&davinci_i2c_driver);
923}
924subsys_initcall(davinci_i2c_init_driver);
925
926static void __exit davinci_i2c_exit_driver(void)
927{
928 platform_driver_unregister(&davinci_i2c_driver);
929}
930module_exit(davinci_i2c_exit_driver);
931
932MODULE_AUTHOR("Texas Instruments India");
933MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
934MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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