projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
i2c: davinci: Avoid sending to own address
[deliverable/linux.git] / drivers / i2c / busses / i2c-davinci.c
CommitLineData
95a7f10e
VB		 1/*
2 * TI DAVINCI I2C adapter driver.
3 *
4 * Copyright (C) 2006 Texas Instruments.
5 * Copyright (C) 2007 MontaVista Software Inc.
6 *
7 * Updated by Vinod & Sudhakar Feb 2005
8 *
9 * ----------------------------------------------------------------------------
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
95a7f10e
VB		 20 * ----------------------------------------------------------------------------
21 *
22 */
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/delay.h>
26#include <linux/i2c.h>
27#include <linux/clk.h>
28#include <linux/errno.h>
29#include <linux/sched.h>
30#include <linux/err.h>
31#include <linux/interrupt.h>
32#include <linux/platform_device.h>
33#include <linux/io.h>
5a0e3ad6 34#include <linux/slab.h>
82c0de11 35#include <linux/cpufreq.h>
8574faf9 36#include <linux/gpio.h>
5c3d8a46 37#include <linux/of_device.h>
ec2a0833 38#include <linux/platform_data/i2c-davinci.h>
95a7f10e
VB		 39
40/* ----- global defines ----------------------------------------------- */
41
42#define DAVINCI_I2C_TIMEOUT (1*HZ)
8574faf9 43#define DAVINCI_I2C_MAX_TRIES 2
41c8d452
AS		 44#define DAVINCI_I2C_OWN_ADDRESS 0x08
45#define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_SCD | \
95a7f10e
VB		 46 DAVINCI_I2C_IMR_ARDY | \
47 DAVINCI_I2C_IMR_NACK | \
48 DAVINCI_I2C_IMR_AL)
49
50#define DAVINCI_I2C_OAR_REG 0x00
51#define DAVINCI_I2C_IMR_REG 0x04
52#define DAVINCI_I2C_STR_REG 0x08
53#define DAVINCI_I2C_CLKL_REG 0x0c
54#define DAVINCI_I2C_CLKH_REG 0x10
55#define DAVINCI_I2C_CNT_REG 0x14
56#define DAVINCI_I2C_DRR_REG 0x18
57#define DAVINCI_I2C_SAR_REG 0x1c
58#define DAVINCI_I2C_DXR_REG 0x20
59#define DAVINCI_I2C_MDR_REG 0x24
60#define DAVINCI_I2C_IVR_REG 0x28
61#define DAVINCI_I2C_EMDR_REG 0x2c
62#define DAVINCI_I2C_PSC_REG 0x30
7ef97e9a
GS		 63#define DAVINCI_I2C_FUNC_REG 0x48
64#define DAVINCI_I2C_DIR_REG 0x4c
65#define DAVINCI_I2C_DIN_REG 0x50
66#define DAVINCI_I2C_DOUT_REG 0x54
67#define DAVINCI_I2C_DSET_REG 0x58
68#define DAVINCI_I2C_DCLR_REG 0x5c
95a7f10e
VB		 69
70#define DAVINCI_I2C_IVR_AAS 0x07
71#define DAVINCI_I2C_IVR_SCD 0x06
72#define DAVINCI_I2C_IVR_XRDY 0x05
73#define DAVINCI_I2C_IVR_RDR 0x04
74#define DAVINCI_I2C_IVR_ARDY 0x03
75#define DAVINCI_I2C_IVR_NACK 0x02
76#define DAVINCI_I2C_IVR_AL 0x01
77
c062a251
C		 78#define DAVINCI_I2C_STR_BB BIT(12)
79#define DAVINCI_I2C_STR_RSFULL BIT(11)
80#define DAVINCI_I2C_STR_SCD BIT(5)
81#define DAVINCI_I2C_STR_ARDY BIT(2)
82#define DAVINCI_I2C_STR_NACK BIT(1)
83#define DAVINCI_I2C_STR_AL BIT(0)
84
85#define DAVINCI_I2C_MDR_NACK BIT(15)
86#define DAVINCI_I2C_MDR_STT BIT(13)
87#define DAVINCI_I2C_MDR_STP BIT(11)
88#define DAVINCI_I2C_MDR_MST BIT(10)
89#define DAVINCI_I2C_MDR_TRX BIT(9)
90#define DAVINCI_I2C_MDR_XA BIT(8)
91#define DAVINCI_I2C_MDR_RM BIT(7)
92#define DAVINCI_I2C_MDR_IRS BIT(5)
93
94#define DAVINCI_I2C_IMR_AAS BIT(6)
95#define DAVINCI_I2C_IMR_SCD BIT(5)
96#define DAVINCI_I2C_IMR_XRDY BIT(4)
97#define DAVINCI_I2C_IMR_RRDY BIT(3)
98#define DAVINCI_I2C_IMR_ARDY BIT(2)
99#define DAVINCI_I2C_IMR_NACK BIT(1)
100#define DAVINCI_I2C_IMR_AL BIT(0)
95a7f10e 101
7ef97e9a
GS		 102/* set SDA and SCL as GPIO */
103#define DAVINCI_I2C_FUNC_PFUNC0 BIT(0)
104
105/* set SCL as output when used as GPIO*/
106#define DAVINCI_I2C_DIR_PDIR0 BIT(0)
107/* set SDA as output when used as GPIO*/
108#define DAVINCI_I2C_DIR_PDIR1 BIT(1)
109
110/* read SCL GPIO level */
111#define DAVINCI_I2C_DIN_PDIN0 BIT(0)
112/* read SDA GPIO level */
113#define DAVINCI_I2C_DIN_PDIN1 BIT(1)
114
115/*set the SCL GPIO high */
116#define DAVINCI_I2C_DSET_PDSET0 BIT(0)
117/*set the SDA GPIO high */
118#define DAVINCI_I2C_DSET_PDSET1 BIT(1)
119
120/* set the SCL GPIO low */
121#define DAVINCI_I2C_DCLR_PDCLR0 BIT(0)
122/* set the SDA GPIO low */
123#define DAVINCI_I2C_DCLR_PDCLR1 BIT(1)
124
95a7f10e
VB		 125struct davinci_i2c_dev {
126 struct device *dev;
127 void __iomem *base;
128 struct completion cmd_complete;
129 struct clk *clk;
130 int cmd_err;
131 u8 *buf;
132 size_t buf_len;
133 int irq;
c6c7c729 134 int stop;
5a0d5f5f 135 u8 terminate;
95a7f10e 136 struct i2c_adapter adapter;
82c0de11
C		 137#ifdef CONFIG_CPU_FREQ
138 struct completion xfr_complete;
139 struct notifier_block freq_transition;
140#endif
5c3d8a46 141 struct davinci_i2c_platform_data *pdata;
95a7f10e
VB		 142};
143
144/* default platform data to use if not supplied in the platform_device */
145static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
146 .bus_freq = 100,
147 .bus_delay = 0,
148};
149
150static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
151 int reg, u16 val)
152{
a238dcfa 153 writew_relaxed(val, i2c_dev->base + reg);
95a7f10e
VB		 154}
155
156static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
157{
a238dcfa 158 return readw_relaxed(i2c_dev->base + reg);
95a7f10e
VB		 159}
160
5ae5b113
C		 161static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
162 int val)
163{
164 u16 w;
165
166 w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
167 if (!val) /* put I2C into reset */
168 w &= ~DAVINCI_I2C_MDR_IRS;
169 else /* take I2C out of reset */
170 w |= DAVINCI_I2C_MDR_IRS;
171
172 davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
173}
174
175static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
95a7f10e 176{
5c3d8a46 177 struct davinci_i2c_platform_data *pdata = dev->pdata;
95a7f10e
VB		 178 u16 psc;
179 u32 clk;
cc99ff70 180 u32 d;
95a7f10e
VB		 181 u32 clkh;
182 u32 clkl;
183 u32 input_clock = clk_get_rate(dev->clk);
95a7f10e
VB		 184
185 /* NOTE: I2C Clock divider programming info
186 * As per I2C specs the following formulas provide prescaler
187 * and low/high divider values
188 * input clk --> PSC Div -----------> ICCL/H Div --> output clock
189 * module clk
190 *
191 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
192 *
193 * Thus,
194 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
195 *
196 * where if PSC == 0, d = 7,
197 * if PSC == 1, d = 6
198 * if PSC > 1 , d = 5
199 */
200
cc99ff70
TK		 201 /* get minimum of 7 MHz clock, but max of 12 MHz */
202 psc = (input_clock / 7000000) - 1;
203 if ((input_clock / (psc + 1)) > 12000000)
204 psc++; /* better to run under spec than over */
205 d = (psc >= 2) ? 5 : 7 - psc;
95a7f10e 206
cc99ff70
TK		 207 clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1);
208 clkh = clk >> 1;
95a7f10e
VB		 209 clkl = clk - clkh;
210
211 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
212 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
213 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
214
5ae5b113
C		 215 dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
216}
217
218/*
219 * This function configures I2C and brings I2C out of reset.
220 * This function is called during I2C init function. This function
221 * also gets called if I2C encounters any errors.
222 */
223static int i2c_davinci_init(struct davinci_i2c_dev *dev)
224{
5c3d8a46 225 struct davinci_i2c_platform_data *pdata = dev->pdata;
5ae5b113
C		 226
227 /* put I2C into reset */
228 davinci_i2c_reset_ctrl(dev, 0);
229
230 /* compute clock dividers */
231 i2c_davinci_calc_clk_dividers(dev);
232
7605fa3b
DB		 233 /* Respond at reserved "SMBus Host" slave address" (and zero);
234 * we seem to have no option to not respond...
235 */
41c8d452 236 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, DAVINCI_I2C_OWN_ADDRESS);
7605fa3b 237
95a7f10e
VB		 238 dev_dbg(dev->dev, "PSC = %d\n",
239 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
240 dev_dbg(dev->dev, "CLKL = %d\n",
241 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
242 dev_dbg(dev->dev, "CLKH = %d\n",
243 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
cc99ff70
TK		 244 dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
245 pdata->bus_freq, pdata->bus_delay);
95a7f10e 246
5c3d8a46 247
95a7f10e 248 /* Take the I2C module out of reset: */
5ae5b113 249 davinci_i2c_reset_ctrl(dev, 1);
95a7f10e
VB		 250
251 /* Enable interrupts */
252 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
253
254 return 0;
255}
256
2e65676f
GS		 257/*
258 * This routine does i2c bus recovery by using i2c_generic_gpio_recovery
259 * which is provided by I2C Bus recovery infrastructure.
260 */
261static void davinci_i2c_prepare_recovery(struct i2c_adapter *adap)
262{
263 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
264
265 /* Disable interrupts */
266 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, 0);
267
268 /* put I2C into reset */
269 davinci_i2c_reset_ctrl(dev, 0);
270}
271
272static void davinci_i2c_unprepare_recovery(struct i2c_adapter *adap)
273{
274 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
275
276 i2c_davinci_init(dev);
277}
278
279static struct i2c_bus_recovery_info davinci_i2c_gpio_recovery_info = {
280 .recover_bus = i2c_generic_gpio_recovery,
281 .prepare_recovery = davinci_i2c_prepare_recovery,
282 .unprepare_recovery = davinci_i2c_unprepare_recovery,
283};
284
7ef97e9a
GS		 285static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val)
286{
287 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
288
289 if (val)
290 davinci_i2c_write_reg(dev, DAVINCI_I2C_DSET_REG,
291 DAVINCI_I2C_DSET_PDSET0);
292 else
293 davinci_i2c_write_reg(dev, DAVINCI_I2C_DCLR_REG,
294 DAVINCI_I2C_DCLR_PDCLR0);
295}
296
297static int davinci_i2c_get_scl(struct i2c_adapter *adap)
298{
299 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
300 int val;
301
302 /* read the state of SCL */
303 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
304 return val & DAVINCI_I2C_DIN_PDIN0;
305}
306
307static int davinci_i2c_get_sda(struct i2c_adapter *adap)
308{
309 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
310 int val;
311
312 /* read the state of SDA */
313 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
314 return val & DAVINCI_I2C_DIN_PDIN1;
315}
316
317static void davinci_i2c_scl_prepare_recovery(struct i2c_adapter *adap)
318{
319 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
320
321 davinci_i2c_prepare_recovery(adap);
322
323 /* SCL output, SDA input */
324 davinci_i2c_write_reg(dev, DAVINCI_I2C_DIR_REG, DAVINCI_I2C_DIR_PDIR0);
325
326 /* change to GPIO mode */
327 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG,
328 DAVINCI_I2C_FUNC_PFUNC0);
329}
330
331static void davinci_i2c_scl_unprepare_recovery(struct i2c_adapter *adap)
332{
333 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
334
335 /* change back to I2C mode */
336 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 0);
337
338 davinci_i2c_unprepare_recovery(adap);
339}
340
341static struct i2c_bus_recovery_info davinci_i2c_scl_recovery_info = {
342 .recover_bus = i2c_generic_scl_recovery,
343 .set_scl = davinci_i2c_set_scl,
344 .get_scl = davinci_i2c_get_scl,
345 .get_sda = davinci_i2c_get_sda,
346 .prepare_recovery = davinci_i2c_scl_prepare_recovery,
347 .unprepare_recovery = davinci_i2c_scl_unprepare_recovery,
348};
349
95a7f10e
VB		 350/*
351 * Waiting for bus not busy
352 */
72a956c5 353static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev)
95a7f10e 354{
72a956c5
AS		 355 unsigned long timeout = jiffies + dev->adapter.timeout;
356
357 do {
358 if (!(davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB))
359 return 0;
360 schedule_timeout_uninterruptible(1);
361 } while (time_before_eq(jiffies, timeout));
362
363 dev_warn(dev->dev, "timeout waiting for bus ready\n");
364 i2c_recover_bus(&dev->adapter);
365
366 /*
367 * if bus is still "busy" here, it's most probably a HW problem like
368 * short-circuit
369 */
370 if (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB)
371 return -EIO;
95a7f10e
VB		 372
373 return 0;
374}
375
376/*
377 * Low level master read/write transaction. This function is called
378 * from i2c_davinci_xfer.
379 */
380static int
381i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
382{
383 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
5c3d8a46 384 struct davinci_i2c_platform_data *pdata = dev->pdata;
95a7f10e 385 u32 flag;
95a7f10e 386 u16 w;
d9e1f441 387 unsigned long time_left;
95a7f10e 388
41c8d452
AS		 389 if (msg->addr == DAVINCI_I2C_OWN_ADDRESS) {
390 dev_warn(dev->dev, "transfer to own address aborted\n");
391 return -EADDRNOTAVAIL;
392 }
393
95a7f10e
VB		 394 /* Introduce a delay, required for some boards (e.g Davinci EVM) */
395 if (pdata->bus_delay)
396 udelay(pdata->bus_delay);
397
398 /* set the slave address */
399 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
400
401 dev->buf = msg->buf;
402 dev->buf_len = msg->len;
c6c7c729 403 dev->stop = stop;
95a7f10e
VB		 404
405 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
406
16735d02 407 reinit_completion(&dev->cmd_complete);
95a7f10e
VB		 408 dev->cmd_err = 0;
409
c5b4afec
JP		 410 /* Take I2C out of reset and configure it as master */
411 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
95a7f10e
VB		 412
413 /* if the slave address is ten bit address, enable XA bit */
414 if (msg->flags & I2C_M_TEN)
415 flag |= DAVINCI_I2C_MDR_XA;
416 if (!(msg->flags & I2C_M_RD))
417 flag |= DAVINCI_I2C_MDR_TRX;
c5b4afec 418 if (msg->len == 0)
c6c7c729 419 flag |= DAVINCI_I2C_MDR_RM;
95a7f10e
VB		 420
421 /* Enable receive or transmit interrupts */
422 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
423 if (msg->flags & I2C_M_RD)
c062a251 424 w |= DAVINCI_I2C_IMR_RRDY;
95a7f10e 425 else
c062a251 426 w |= DAVINCI_I2C_IMR_XRDY;
95a7f10e
VB		 427 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
428
5a0d5f5f 429 dev->terminate = 0;
c6c7c729 430
c5b4afec
JP		 431 /*
432 * Write mode register first as needed for correct behaviour
433 * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
25985edc 434 * occurring before we have loaded DXR
c5b4afec
JP		 435 */
436 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
437
c6c7c729
DB		 438 /*
439 * First byte should be set here, not after interrupt,
440 * because transmit-data-ready interrupt can come before
441 * NACK-interrupt during sending of previous message and
442 * ICDXR may have wrong data
c5b4afec 443 * It also saves us one interrupt, slightly faster
c6c7c729
DB		 444 */
445 if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
446 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
447 dev->buf_len--;
448 }
449
c5b4afec
JP		 450 /* Set STT to begin transmit now DXR is loaded */
451 flag |= DAVINCI_I2C_MDR_STT;
452 if (stop && msg->len != 0)
453 flag |= DAVINCI_I2C_MDR_STP;
4bba0fd8
JP		 454 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
455
d9e1f441
NMG		 456 time_left = wait_for_completion_timeout(&dev->cmd_complete,
457 dev->adapter.timeout);
458 if (!time_left) {
95a7f10e 459 dev_err(dev->dev, "controller timed out\n");
2e65676f 460 i2c_recover_bus(adap);
5a0d5f5f 461 dev->buf_len = 0;
95a7f10e
VB		 462 return -ETIMEDOUT;
463 }
5a0d5f5f
TK		 464 if (dev->buf_len) {
465 /* This should be 0 if all bytes were transferred
466 * or dev->cmd_err denotes an error.
5a0d5f5f 467 */
d9e1f441
NMG		 468 dev_err(dev->dev, "abnormal termination buf_len=%i\n",
469 dev->buf_len);
5a0d5f5f
TK		 470 dev->terminate = 1;
471 wmb();
472 dev->buf_len = 0;
d9e1f441 473 return -EREMOTEIO;
5a0d5f5f 474 }
95a7f10e
VB		 475
476 /* no error */
477 if (likely(!dev->cmd_err))
478 return msg->len;
479
480 /* We have an error */
481 if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
482 i2c_davinci_init(dev);
483 return -EIO;
484 }
485
486 if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
487 if (msg->flags & I2C_M_IGNORE_NAK)
488 return msg->len;
9ea359f7
GS		 489 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
490 w |= DAVINCI_I2C_MDR_STP;
491 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
95a7f10e
VB		 492 return -EREMOTEIO;
493 }
494 return -EIO;
495}
496
497/*
498 * Prepare controller for a transaction and call i2c_davinci_xfer_msg
499 */
500static int
501i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
502{
503 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
504 int i;
505 int ret;
506
08882d20 507 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
95a7f10e 508
72a956c5 509 ret = i2c_davinci_wait_bus_not_busy(dev);
95a7f10e
VB		 510 if (ret < 0) {
511 dev_warn(dev->dev, "timeout waiting for bus ready\n");
512 return ret;
513 }
514
515 for (i = 0; i < num; i++) {
516 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
d868caa1
TK		 517 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
518 ret);
95a7f10e
VB		 519 if (ret < 0)
520 return ret;
521 }
82c0de11
C		 522
523#ifdef CONFIG_CPU_FREQ
524 complete(&dev->xfr_complete);
525#endif
526
95a7f10e
VB		 527 return num;
528}
529
530static u32 i2c_davinci_func(struct i2c_adapter *adap)
531{
c6c7c729 532 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
95a7f10e
VB		 533}
534
5a0d5f5f
TK		 535static void terminate_read(struct davinci_i2c_dev *dev)
536{
537 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
538 w |= DAVINCI_I2C_MDR_NACK;
539 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
540
541 /* Throw away data */
542 davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
543 if (!dev->terminate)
544 dev_err(dev->dev, "RDR IRQ while no data requested\n");
545}
546static void terminate_write(struct davinci_i2c_dev *dev)
547{
548 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
549 w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
550 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
551
552 if (!dev->terminate)
7605fa3b 553 dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
5a0d5f5f
TK		 554}
555
95a7f10e
VB		 556/*
557 * Interrupt service routine. This gets called whenever an I2C interrupt
558 * occurs.
559 */
560static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
561{
562 struct davinci_i2c_dev *dev = dev_id;
563 u32 stat;
564 int count = 0;
565 u16 w;
566
567 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
08882d20 568 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
95a7f10e
VB		 569 if (count++ == 100) {
570 dev_warn(dev->dev, "Too much work in one IRQ\n");
571 break;
572 }
573
574 switch (stat) {
575 case DAVINCI_I2C_IVR_AL:
5a0d5f5f 576 /* Arbitration lost, must retry */
95a7f10e 577 dev->cmd_err |= DAVINCI_I2C_STR_AL;
5a0d5f5f 578 dev->buf_len = 0;
95a7f10e
VB		 579 complete(&dev->cmd_complete);
580 break;
581
582 case DAVINCI_I2C_IVR_NACK:
583 dev->cmd_err |= DAVINCI_I2C_STR_NACK;
5a0d5f5f 584 dev->buf_len = 0;
95a7f10e
VB		 585 complete(&dev->cmd_complete);
586 break;
587
588 case DAVINCI_I2C_IVR_ARDY:
b73a9aec
TK		 589 davinci_i2c_write_reg(dev,
590 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
c6c7c729
DB		 591 if (((dev->buf_len == 0) && (dev->stop != 0)) ||
592 (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
593 w = davinci_i2c_read_reg(dev,
594 DAVINCI_I2C_MDR_REG);
595 w |= DAVINCI_I2C_MDR_STP;
596 davinci_i2c_write_reg(dev,
597 DAVINCI_I2C_MDR_REG, w);
598 }
95a7f10e
VB		 599 complete(&dev->cmd_complete);
600 break;
601
602 case DAVINCI_I2C_IVR_RDR:
603 if (dev->buf_len) {
604 *dev->buf++ =
605 davinci_i2c_read_reg(dev,
606 DAVINCI_I2C_DRR_REG);
607 dev->buf_len--;
608 if (dev->buf_len)
609 continue;
610
95a7f10e 611 davinci_i2c_write_reg(dev,
b73a9aec
TK		 612 DAVINCI_I2C_STR_REG,
613 DAVINCI_I2C_IMR_RRDY);
5a0d5f5f
TK		 614 } else {
615 /* signal can terminate transfer */
616 terminate_read(dev);
617 }
95a7f10e
VB		 618 break;
619
620 case DAVINCI_I2C_IVR_XRDY:
621 if (dev->buf_len) {
622 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
623 *dev->buf++);
624 dev->buf_len--;
625 if (dev->buf_len)
626 continue;
627
628 w = davinci_i2c_read_reg(dev,
629 DAVINCI_I2C_IMR_REG);
c062a251 630 w &= ~DAVINCI_I2C_IMR_XRDY;
95a7f10e
VB		 631 davinci_i2c_write_reg(dev,
632 DAVINCI_I2C_IMR_REG,
633 w);
5a0d5f5f
TK		 634 } else {
635 /* signal can terminate transfer */
636 terminate_write(dev);
637 }
95a7f10e
VB		 638 break;
639
640 case DAVINCI_I2C_IVR_SCD:
b73a9aec
TK		 641 davinci_i2c_write_reg(dev,
642 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
95a7f10e
VB		 643 complete(&dev->cmd_complete);
644 break;
645
646 case DAVINCI_I2C_IVR_AAS:
7605fa3b
DB		 647 dev_dbg(dev->dev, "Address as slave interrupt\n");
648 break;
649
650 default:
651 dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
652 break;
653 }
654 }
95a7f10e
VB		 655
656 return count ? IRQ_HANDLED : IRQ_NONE;
657}
658
82c0de11
C		 659#ifdef CONFIG_CPU_FREQ
660static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
661 unsigned long val, void *data)
662{
663 struct davinci_i2c_dev *dev;
664
665 dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
666 if (val == CPUFREQ_PRECHANGE) {
667 wait_for_completion(&dev->xfr_complete);
668 davinci_i2c_reset_ctrl(dev, 0);
669 } else if (val == CPUFREQ_POSTCHANGE) {
670 i2c_davinci_calc_clk_dividers(dev);
671 davinci_i2c_reset_ctrl(dev, 1);
672 }
673
674 return 0;
675}
676
677static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
678{
679 dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
680
681 return cpufreq_register_notifier(&dev->freq_transition,
682 CPUFREQ_TRANSITION_NOTIFIER);
683}
684
685static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
686{
687 cpufreq_unregister_notifier(&dev->freq_transition,
688 CPUFREQ_TRANSITION_NOTIFIER);
689}
690#else
691static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
692{
693 return 0;
694}
695
696static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
697{
698}
699#endif
700
95a7f10e
VB		 701static struct i2c_algorithm i2c_davinci_algo = {
702 .master_xfer = i2c_davinci_xfer,
703 .functionality = i2c_davinci_func,
704};
705
5c3d8a46
HS		 706static const struct of_device_id davinci_i2c_of_match[] = {
707 {.compatible = "ti,davinci-i2c", },
708 {},
709};
710MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
711
95a7f10e
VB		 712static int davinci_i2c_probe(struct platform_device *pdev)
713{
714 struct davinci_i2c_dev *dev;
715 struct i2c_adapter *adap;
2c6ef04f
GS		 716 struct resource *mem;
717 int r, irq;
718
719 irq = platform_get_irq(pdev, 0);
720 if (irq <= 0) {
721 if (!irq)
722 irq = -ENXIO;
723 if (irq != -EPROBE_DEFER)
724 dev_err(&pdev->dev,
725 "can't get irq resource ret=%d\n", irq);
726 return irq;
95a7f10e
VB		 727 }
728
85796843
VBM		 729 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev),
730 GFP_KERNEL);
95a7f10e 731 if (!dev) {
85796843
VBM		 732 dev_err(&pdev->dev, "Memory allocation failed\n");
733 return -ENOMEM;
95a7f10e
VB		 734 }
735
2e743787 736 init_completion(&dev->cmd_complete);
82c0de11
C		 737#ifdef CONFIG_CPU_FREQ
738 init_completion(&dev->xfr_complete);
739#endif
c4df5000 740 dev->dev = &pdev->dev;
2c6ef04f 741 dev->irq = irq;
1e2c2390 742 dev->pdata = dev_get_platdata(&pdev->dev);
95a7f10e
VB		 743 platform_set_drvdata(pdev, dev);
744
5c3d8a46
HS		 745 if (!dev->pdata && pdev->dev.of_node) {
746 u32 prop;
747
748 dev->pdata = devm_kzalloc(&pdev->dev,
749 sizeof(struct davinci_i2c_platform_data), GFP_KERNEL);
c4df5000
WS		 750 if (!dev->pdata)
751 return -ENOMEM;
752
5c3d8a46
HS		 753 memcpy(dev->pdata, &davinci_i2c_platform_data_default,
754 sizeof(struct davinci_i2c_platform_data));
755 if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
756 &prop))
757 dev->pdata->bus_freq = prop / 1000;
7ef97e9a
GS		 758
759 dev->pdata->has_pfunc =
760 of_property_read_bool(pdev->dev.of_node,
761 "ti,has-pfunc");
5c3d8a46
HS		 762 } else if (!dev->pdata) {
763 dev->pdata = &davinci_i2c_platform_data_default;
764 }
765
85796843 766 dev->clk = devm_clk_get(&pdev->dev, NULL);
c4df5000
WS		 767 if (IS_ERR(dev->clk))
768 return -ENODEV;
2bdbfa9c 769 clk_prepare_enable(dev->clk);
95a7f10e 770
3cc2d009 771 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
85796843
VBM		 772 dev->base = devm_ioremap_resource(&pdev->dev, mem);
773 if (IS_ERR(dev->base)) {
774 r = PTR_ERR(dev->base);
775 goto err_unuse_clocks;
c062a251
C		 776 }
777
95a7f10e
VB		 778 i2c_davinci_init(dev);
779
85796843
VBM		 780 r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0,
781 pdev->name, dev);
95a7f10e
VB		 782 if (r) {
783 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
784 goto err_unuse_clocks;
785 }
786
82c0de11
C		 787 r = i2c_davinci_cpufreq_register(dev);
788 if (r) {
789 dev_err(&pdev->dev, "failed to register cpufreq\n");
85796843 790 goto err_unuse_clocks;
82c0de11
C		 791 }
792
95a7f10e
VB		 793 adap = &dev->adapter;
794 i2c_set_adapdata(adap, dev);
795 adap->owner = THIS_MODULE;
adcb82a9 796 adap->class = I2C_CLASS_DEPRECATED;
95a7f10e
VB		 797 strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
798 adap->algo = &i2c_davinci_algo;
799 adap->dev.parent = &pdev->dev;
98a679ca 800 adap->timeout = DAVINCI_I2C_TIMEOUT;
5c3d8a46 801 adap->dev.of_node = pdev->dev.of_node;
95a7f10e 802
7ef97e9a
GS		 803 if (dev->pdata->has_pfunc)
804 adap->bus_recovery_info = &davinci_i2c_scl_recovery_info;
805 else if (dev->pdata->scl_pin) {
2e65676f
GS		 806 adap->bus_recovery_info = &davinci_i2c_gpio_recovery_info;
807 adap->bus_recovery_info->scl_gpio = dev->pdata->scl_pin;
808 adap->bus_recovery_info->sda_gpio = dev->pdata->sda_pin;
809 }
810
95a7f10e
VB		 811 adap->nr = pdev->id;
812 r = i2c_add_numbered_adapter(adap);
813 if (r) {
814 dev_err(&pdev->dev, "failure adding adapter\n");
85796843 815 goto err_unuse_clocks;
95a7f10e
VB		 816 }
817
818 return 0;
819
95a7f10e 820err_unuse_clocks:
2bdbfa9c 821 clk_disable_unprepare(dev->clk);
95a7f10e 822 dev->clk = NULL;
95a7f10e
VB		 823 return r;
824}
825
826static int davinci_i2c_remove(struct platform_device *pdev)
827{
828 struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
95a7f10e 829
82c0de11
C		 830 i2c_davinci_cpufreq_deregister(dev);
831
95a7f10e 832 i2c_del_adapter(&dev->adapter);
95a7f10e 833
2bdbfa9c 834 clk_disable_unprepare(dev->clk);
95a7f10e
VB		 835 dev->clk = NULL;
836
837 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
95a7f10e 838
95a7f10e
VB		 839 return 0;
840}
841
68f15de9
C		 842#ifdef CONFIG_PM
843static int davinci_i2c_suspend(struct device *dev)
844{
845 struct platform_device *pdev = to_platform_device(dev);
846 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
847
848 /* put I2C into reset */
849 davinci_i2c_reset_ctrl(i2c_dev, 0);
2bdbfa9c 850 clk_disable_unprepare(i2c_dev->clk);
68f15de9
C		 851
852 return 0;
853}
854
855static int davinci_i2c_resume(struct device *dev)
856{
857 struct platform_device *pdev = to_platform_device(dev);
858 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
859
2bdbfa9c 860 clk_prepare_enable(i2c_dev->clk);
68f15de9
C		 861 /* take I2C out of reset */
862 davinci_i2c_reset_ctrl(i2c_dev, 1);
863
864 return 0;
865}
866
867static const struct dev_pm_ops davinci_i2c_pm = {
868 .suspend = davinci_i2c_suspend,
869 .resume = davinci_i2c_resume,
870};
871
872#define davinci_i2c_pm_ops (&davinci_i2c_pm)
873#else
874#define davinci_i2c_pm_ops NULL
875#endif
876
add8eda7
KS		 877/* work with hotplug and coldplug */
878MODULE_ALIAS("platform:i2c_davinci");
879
95a7f10e
VB		 880static struct platform_driver davinci_i2c_driver = {
881 .probe = davinci_i2c_probe,
882 .remove = davinci_i2c_remove,
883 .driver = {
884 .name = "i2c_davinci",
68f15de9 885 .pm = davinci_i2c_pm_ops,
4e905323 886 .of_match_table = davinci_i2c_of_match,
95a7f10e
VB		 887 },
888};
889
890/* I2C may be needed to bring up other drivers */
891static int __init davinci_i2c_init_driver(void)
892{
893 return platform_driver_register(&davinci_i2c_driver);
894}
895subsys_initcall(davinci_i2c_init_driver);
896
897static void __exit davinci_i2c_exit_driver(void)
898{
899 platform_driver_unregister(&davinci_i2c_driver);
900}
901module_exit(davinci_i2c_exit_driver);
902
903MODULE_AUTHOR("Texas Instruments India");
904MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
905MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.573391 seconds and 5 git commands to generate.