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i2c: davinci: Add cpufreq support
[deliverable/linux.git] / drivers / i2c / busses / i2c-davinci.c
CommitLineData
95a7f10e
VB		 1/*
2 * TI DAVINCI I2C adapter driver.
3 *
4 * Copyright (C) 2006 Texas Instruments.
5 * Copyright (C) 2007 MontaVista Software Inc.
6 *
7 * Updated by Vinod & Sudhakar Feb 2005
8 *
9 * ----------------------------------------------------------------------------
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * ----------------------------------------------------------------------------
25 *
26 */
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/delay.h>
30#include <linux/i2c.h>
31#include <linux/clk.h>
32#include <linux/errno.h>
33#include <linux/sched.h>
34#include <linux/err.h>
35#include <linux/interrupt.h>
36#include <linux/platform_device.h>
37#include <linux/io.h>
5a0e3ad6 38#include <linux/slab.h>
82c0de11 39#include <linux/cpufreq.h>
95a7f10e 40
a09e64fb 41#include <mach/hardware.h>
a09e64fb 42#include <mach/i2c.h>
95a7f10e
VB		 43
44/* ----- global defines ----------------------------------------------- */
45
46#define DAVINCI_I2C_TIMEOUT (1*HZ)
47#define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \
48 DAVINCI_I2C_IMR_SCD | \
49 DAVINCI_I2C_IMR_ARDY | \
50 DAVINCI_I2C_IMR_NACK | \
51 DAVINCI_I2C_IMR_AL)
52
53#define DAVINCI_I2C_OAR_REG 0x00
54#define DAVINCI_I2C_IMR_REG 0x04
55#define DAVINCI_I2C_STR_REG 0x08
56#define DAVINCI_I2C_CLKL_REG 0x0c
57#define DAVINCI_I2C_CLKH_REG 0x10
58#define DAVINCI_I2C_CNT_REG 0x14
59#define DAVINCI_I2C_DRR_REG 0x18
60#define DAVINCI_I2C_SAR_REG 0x1c
61#define DAVINCI_I2C_DXR_REG 0x20
62#define DAVINCI_I2C_MDR_REG 0x24
63#define DAVINCI_I2C_IVR_REG 0x28
64#define DAVINCI_I2C_EMDR_REG 0x2c
65#define DAVINCI_I2C_PSC_REG 0x30
66
67#define DAVINCI_I2C_IVR_AAS 0x07
68#define DAVINCI_I2C_IVR_SCD 0x06
69#define DAVINCI_I2C_IVR_XRDY 0x05
70#define DAVINCI_I2C_IVR_RDR 0x04
71#define DAVINCI_I2C_IVR_ARDY 0x03
72#define DAVINCI_I2C_IVR_NACK 0x02
73#define DAVINCI_I2C_IVR_AL 0x01
74
c062a251
C		 75#define DAVINCI_I2C_STR_BB BIT(12)
76#define DAVINCI_I2C_STR_RSFULL BIT(11)
77#define DAVINCI_I2C_STR_SCD BIT(5)
78#define DAVINCI_I2C_STR_ARDY BIT(2)
79#define DAVINCI_I2C_STR_NACK BIT(1)
80#define DAVINCI_I2C_STR_AL BIT(0)
81
82#define DAVINCI_I2C_MDR_NACK BIT(15)
83#define DAVINCI_I2C_MDR_STT BIT(13)
84#define DAVINCI_I2C_MDR_STP BIT(11)
85#define DAVINCI_I2C_MDR_MST BIT(10)
86#define DAVINCI_I2C_MDR_TRX BIT(9)
87#define DAVINCI_I2C_MDR_XA BIT(8)
88#define DAVINCI_I2C_MDR_RM BIT(7)
89#define DAVINCI_I2C_MDR_IRS BIT(5)
90
91#define DAVINCI_I2C_IMR_AAS BIT(6)
92#define DAVINCI_I2C_IMR_SCD BIT(5)
93#define DAVINCI_I2C_IMR_XRDY BIT(4)
94#define DAVINCI_I2C_IMR_RRDY BIT(3)
95#define DAVINCI_I2C_IMR_ARDY BIT(2)
96#define DAVINCI_I2C_IMR_NACK BIT(1)
97#define DAVINCI_I2C_IMR_AL BIT(0)
95a7f10e
VB		 98
99struct davinci_i2c_dev {
100 struct device *dev;
101 void __iomem *base;
102 struct completion cmd_complete;
103 struct clk *clk;
104 int cmd_err;
105 u8 *buf;
106 size_t buf_len;
107 int irq;
c6c7c729 108 int stop;
5a0d5f5f 109 u8 terminate;
95a7f10e 110 struct i2c_adapter adapter;
82c0de11
C		 111#ifdef CONFIG_CPU_FREQ
112 struct completion xfr_complete;
113 struct notifier_block freq_transition;
114#endif
95a7f10e
VB		 115};
116
117/* default platform data to use if not supplied in the platform_device */
118static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
119 .bus_freq = 100,
120 .bus_delay = 0,
121};
122
123static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
124 int reg, u16 val)
125{
126 __raw_writew(val, i2c_dev->base + reg);
127}
128
129static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
130{
131 return __raw_readw(i2c_dev->base + reg);
132}
133
5ae5b113
C		 134static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
135 int val)
136{
137 u16 w;
138
139 w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
140 if (!val) /* put I2C into reset */
141 w &= ~DAVINCI_I2C_MDR_IRS;
142 else /* take I2C out of reset */
143 w |= DAVINCI_I2C_MDR_IRS;
144
145 davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
146}
147
148static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
95a7f10e
VB		 149{
150 struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
151 u16 psc;
152 u32 clk;
cc99ff70 153 u32 d;
95a7f10e
VB		 154 u32 clkh;
155 u32 clkl;
156 u32 input_clock = clk_get_rate(dev->clk);
95a7f10e
VB		 157
158 /* NOTE: I2C Clock divider programming info
159 * As per I2C specs the following formulas provide prescaler
160 * and low/high divider values
161 * input clk --> PSC Div -----------> ICCL/H Div --> output clock
162 * module clk
163 *
164 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
165 *
166 * Thus,
167 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
168 *
169 * where if PSC == 0, d = 7,
170 * if PSC == 1, d = 6
171 * if PSC > 1 , d = 5
172 */
173
cc99ff70
TK		 174 /* get minimum of 7 MHz clock, but max of 12 MHz */
175 psc = (input_clock / 7000000) - 1;
176 if ((input_clock / (psc + 1)) > 12000000)
177 psc++; /* better to run under spec than over */
178 d = (psc >= 2) ? 5 : 7 - psc;
95a7f10e 179
cc99ff70
TK		 180 clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1);
181 clkh = clk >> 1;
95a7f10e
VB		 182 clkl = clk - clkh;
183
184 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
185 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
186 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
187
5ae5b113
C		 188 dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
189}
190
191/*
192 * This function configures I2C and brings I2C out of reset.
193 * This function is called during I2C init function. This function
194 * also gets called if I2C encounters any errors.
195 */
196static int i2c_davinci_init(struct davinci_i2c_dev *dev)
197{
198 struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
199
200 if (!pdata)
201 pdata = &davinci_i2c_platform_data_default;
202
203 /* put I2C into reset */
204 davinci_i2c_reset_ctrl(dev, 0);
205
206 /* compute clock dividers */
207 i2c_davinci_calc_clk_dividers(dev);
208
7605fa3b
DB		 209 /* Respond at reserved "SMBus Host" slave address" (and zero);
210 * we seem to have no option to not respond...
211 */
212 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08);
213
95a7f10e
VB		 214 dev_dbg(dev->dev, "PSC = %d\n",
215 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
216 dev_dbg(dev->dev, "CLKL = %d\n",
217 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
218 dev_dbg(dev->dev, "CLKH = %d\n",
219 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
cc99ff70
TK		 220 dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
221 pdata->bus_freq, pdata->bus_delay);
95a7f10e
VB		 222
223 /* Take the I2C module out of reset: */
5ae5b113 224 davinci_i2c_reset_ctrl(dev, 1);
95a7f10e
VB		 225
226 /* Enable interrupts */
227 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
228
229 return 0;
230}
231
232/*
233 * Waiting for bus not busy
234 */
235static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
236 char allow_sleep)
237{
238 unsigned long timeout;
239
98a679ca 240 timeout = jiffies + dev->adapter.timeout;
95a7f10e
VB		 241 while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
242 & DAVINCI_I2C_STR_BB) {
243 if (time_after(jiffies, timeout)) {
244 dev_warn(dev->dev,
245 "timeout waiting for bus ready\n");
246 return -ETIMEDOUT;
247 }
248 if (allow_sleep)
249 schedule_timeout(1);
250 }
251
252 return 0;
253}
254
255/*
256 * Low level master read/write transaction. This function is called
257 * from i2c_davinci_xfer.
258 */
259static int
260i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
261{
262 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
263 struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
264 u32 flag;
95a7f10e
VB		 265 u16 w;
266 int r;
267
95a7f10e
VB		 268 if (!pdata)
269 pdata = &davinci_i2c_platform_data_default;
270 /* Introduce a delay, required for some boards (e.g Davinci EVM) */
271 if (pdata->bus_delay)
272 udelay(pdata->bus_delay);
273
274 /* set the slave address */
275 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
276
277 dev->buf = msg->buf;
278 dev->buf_len = msg->len;
c6c7c729 279 dev->stop = stop;
95a7f10e
VB		 280
281 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
282
2e743787 283 INIT_COMPLETION(dev->cmd_complete);
95a7f10e
VB		 284 dev->cmd_err = 0;
285
95a7f10e
VB		 286 /* Take I2C out of reset, configure it as master and set the
287 * start bit */
288 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST | DAVINCI_I2C_MDR_STT;
289
290 /* if the slave address is ten bit address, enable XA bit */
291 if (msg->flags & I2C_M_TEN)
292 flag |= DAVINCI_I2C_MDR_XA;
293 if (!(msg->flags & I2C_M_RD))
294 flag |= DAVINCI_I2C_MDR_TRX;
295 if (stop)
296 flag |= DAVINCI_I2C_MDR_STP;
c6c7c729
DB		 297 if (msg->len == 0) {
298 flag |= DAVINCI_I2C_MDR_RM;
299 flag &= ~DAVINCI_I2C_MDR_STP;
300 }
95a7f10e
VB		 301
302 /* Enable receive or transmit interrupts */
303 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
304 if (msg->flags & I2C_M_RD)
c062a251 305 w |= DAVINCI_I2C_IMR_RRDY;
95a7f10e 306 else
c062a251 307 w |= DAVINCI_I2C_IMR_XRDY;
95a7f10e
VB		 308 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
309
5a0d5f5f 310 dev->terminate = 0;
c6c7c729 311
95a7f10e
VB		 312 /* write the data into mode register */
313 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
314
c6c7c729
DB		 315 /*
316 * First byte should be set here, not after interrupt,
317 * because transmit-data-ready interrupt can come before
318 * NACK-interrupt during sending of previous message and
319 * ICDXR may have wrong data
320 */
321 if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
322 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
323 dev->buf_len--;
324 }
325
95a7f10e 326 r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
98a679ca 327 dev->adapter.timeout);
95a7f10e
VB		 328 if (r == 0) {
329 dev_err(dev->dev, "controller timed out\n");
330 i2c_davinci_init(dev);
5a0d5f5f 331 dev->buf_len = 0;
95a7f10e
VB		 332 return -ETIMEDOUT;
333 }
5a0d5f5f
TK		 334 if (dev->buf_len) {
335 /* This should be 0 if all bytes were transferred
336 * or dev->cmd_err denotes an error.
337 * A signal may have aborted the transfer.
338 */
339 if (r >= 0) {
340 dev_err(dev->dev, "abnormal termination buf_len=%i\n",
341 dev->buf_len);
342 r = -EREMOTEIO;
343 }
344 dev->terminate = 1;
345 wmb();
346 dev->buf_len = 0;
347 }
348 if (r < 0)
349 return r;
95a7f10e
VB		 350
351 /* no error */
352 if (likely(!dev->cmd_err))
353 return msg->len;
354
355 /* We have an error */
356 if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
357 i2c_davinci_init(dev);
358 return -EIO;
359 }
360
361 if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
362 if (msg->flags & I2C_M_IGNORE_NAK)
363 return msg->len;
364 if (stop) {
365 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
c062a251 366 w |= DAVINCI_I2C_MDR_STP;
95a7f10e
VB		 367 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
368 }
369 return -EREMOTEIO;
370 }
371 return -EIO;
372}
373
374/*
375 * Prepare controller for a transaction and call i2c_davinci_xfer_msg
376 */
377static int
378i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
379{
380 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
381 int i;
382 int ret;
383
08882d20 384 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
95a7f10e
VB		 385
386 ret = i2c_davinci_wait_bus_not_busy(dev, 1);
387 if (ret < 0) {
388 dev_warn(dev->dev, "timeout waiting for bus ready\n");
389 return ret;
390 }
391
392 for (i = 0; i < num; i++) {
393 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
d868caa1
TK		 394 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
395 ret);
95a7f10e
VB		 396 if (ret < 0)
397 return ret;
398 }
82c0de11
C		 399
400#ifdef CONFIG_CPU_FREQ
401 complete(&dev->xfr_complete);
402#endif
403
95a7f10e
VB		 404 return num;
405}
406
407static u32 i2c_davinci_func(struct i2c_adapter *adap)
408{
c6c7c729 409 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
95a7f10e
VB		 410}
411
5a0d5f5f
TK		 412static void terminate_read(struct davinci_i2c_dev *dev)
413{
414 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
415 w |= DAVINCI_I2C_MDR_NACK;
416 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
417
418 /* Throw away data */
419 davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
420 if (!dev->terminate)
421 dev_err(dev->dev, "RDR IRQ while no data requested\n");
422}
423static void terminate_write(struct davinci_i2c_dev *dev)
424{
425 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
426 w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
427 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
428
429 if (!dev->terminate)
7605fa3b 430 dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
5a0d5f5f
TK		 431}
432
95a7f10e
VB		 433/*
434 * Interrupt service routine. This gets called whenever an I2C interrupt
435 * occurs.
436 */
437static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
438{
439 struct davinci_i2c_dev *dev = dev_id;
440 u32 stat;
441 int count = 0;
442 u16 w;
443
444 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
08882d20 445 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
95a7f10e
VB		 446 if (count++ == 100) {
447 dev_warn(dev->dev, "Too much work in one IRQ\n");
448 break;
449 }
450
451 switch (stat) {
452 case DAVINCI_I2C_IVR_AL:
5a0d5f5f 453 /* Arbitration lost, must retry */
95a7f10e 454 dev->cmd_err |= DAVINCI_I2C_STR_AL;
5a0d5f5f 455 dev->buf_len = 0;
95a7f10e
VB		 456 complete(&dev->cmd_complete);
457 break;
458
459 case DAVINCI_I2C_IVR_NACK:
460 dev->cmd_err |= DAVINCI_I2C_STR_NACK;
5a0d5f5f 461 dev->buf_len = 0;
95a7f10e
VB		 462 complete(&dev->cmd_complete);
463 break;
464
465 case DAVINCI_I2C_IVR_ARDY:
b73a9aec
TK		 466 davinci_i2c_write_reg(dev,
467 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
c6c7c729
DB		 468 if (((dev->buf_len == 0) && (dev->stop != 0)) ||
469 (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
470 w = davinci_i2c_read_reg(dev,
471 DAVINCI_I2C_MDR_REG);
472 w |= DAVINCI_I2C_MDR_STP;
473 davinci_i2c_write_reg(dev,
474 DAVINCI_I2C_MDR_REG, w);
475 }
95a7f10e
VB		 476 complete(&dev->cmd_complete);
477 break;
478
479 case DAVINCI_I2C_IVR_RDR:
480 if (dev->buf_len) {
481 *dev->buf++ =
482 davinci_i2c_read_reg(dev,
483 DAVINCI_I2C_DRR_REG);
484 dev->buf_len--;
485 if (dev->buf_len)
486 continue;
487
95a7f10e 488 davinci_i2c_write_reg(dev,
b73a9aec
TK		 489 DAVINCI_I2C_STR_REG,
490 DAVINCI_I2C_IMR_RRDY);
5a0d5f5f
TK		 491 } else {
492 /* signal can terminate transfer */
493 terminate_read(dev);
494 }
95a7f10e
VB		 495 break;
496
497 case DAVINCI_I2C_IVR_XRDY:
498 if (dev->buf_len) {
499 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
500 *dev->buf++);
501 dev->buf_len--;
502 if (dev->buf_len)
503 continue;
504
505 w = davinci_i2c_read_reg(dev,
506 DAVINCI_I2C_IMR_REG);
c062a251 507 w &= ~DAVINCI_I2C_IMR_XRDY;
95a7f10e
VB		 508 davinci_i2c_write_reg(dev,
509 DAVINCI_I2C_IMR_REG,
510 w);
5a0d5f5f
TK		 511 } else {
512 /* signal can terminate transfer */
513 terminate_write(dev);
514 }
95a7f10e
VB		 515 break;
516
517 case DAVINCI_I2C_IVR_SCD:
b73a9aec
TK		 518 davinci_i2c_write_reg(dev,
519 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
95a7f10e
VB		 520 complete(&dev->cmd_complete);
521 break;
522
523 case DAVINCI_I2C_IVR_AAS:
7605fa3b
DB		 524 dev_dbg(dev->dev, "Address as slave interrupt\n");
525 break;
526
527 default:
528 dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
529 break;
530 }
531 }
95a7f10e
VB		 532
533 return count ? IRQ_HANDLED : IRQ_NONE;
534}
535
82c0de11
C		 536#ifdef CONFIG_CPU_FREQ
537static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
538 unsigned long val, void *data)
539{
540 struct davinci_i2c_dev *dev;
541
542 dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
543 if (val == CPUFREQ_PRECHANGE) {
544 wait_for_completion(&dev->xfr_complete);
545 davinci_i2c_reset_ctrl(dev, 0);
546 } else if (val == CPUFREQ_POSTCHANGE) {
547 i2c_davinci_calc_clk_dividers(dev);
548 davinci_i2c_reset_ctrl(dev, 1);
549 }
550
551 return 0;
552}
553
554static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
555{
556 dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
557
558 return cpufreq_register_notifier(&dev->freq_transition,
559 CPUFREQ_TRANSITION_NOTIFIER);
560}
561
562static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
563{
564 cpufreq_unregister_notifier(&dev->freq_transition,
565 CPUFREQ_TRANSITION_NOTIFIER);
566}
567#else
568static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
569{
570 return 0;
571}
572
573static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
574{
575}
576#endif
577
95a7f10e
VB		 578static struct i2c_algorithm i2c_davinci_algo = {
579 .master_xfer = i2c_davinci_xfer,
580 .functionality = i2c_davinci_func,
581};
582
583static int davinci_i2c_probe(struct platform_device *pdev)
584{
585 struct davinci_i2c_dev *dev;
586 struct i2c_adapter *adap;
587 struct resource *mem, *irq, *ioarea;
588 int r;
589
590 /* NOTE: driver uses the static register mapping */
591 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
592 if (!mem) {
593 dev_err(&pdev->dev, "no mem resource?\n");
594 return -ENODEV;
595 }
596
597 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
598 if (!irq) {
599 dev_err(&pdev->dev, "no irq resource?\n");
600 return -ENODEV;
601 }
602
59330825 603 ioarea = request_mem_region(mem->start, resource_size(mem),
95a7f10e
VB		 604 pdev->name);
605 if (!ioarea) {
606 dev_err(&pdev->dev, "I2C region already claimed\n");
607 return -EBUSY;
608 }
609
610 dev = kzalloc(sizeof(struct davinci_i2c_dev), GFP_KERNEL);
611 if (!dev) {
612 r = -ENOMEM;
613 goto err_release_region;
614 }
615
2e743787 616 init_completion(&dev->cmd_complete);
82c0de11
C		 617#ifdef CONFIG_CPU_FREQ
618 init_completion(&dev->xfr_complete);
619#endif
95a7f10e
VB		 620 dev->dev = get_device(&pdev->dev);
621 dev->irq = irq->start;
622 platform_set_drvdata(pdev, dev);
623
e164ddee 624 dev->clk = clk_get(&pdev->dev, NULL);
95a7f10e
VB		 625 if (IS_ERR(dev->clk)) {
626 r = -ENODEV;
627 goto err_free_mem;
628 }
629 clk_enable(dev->clk);
630
c062a251
C		 631 dev->base = ioremap(mem->start, resource_size(mem));
632 if (!dev->base) {
633 r = -EBUSY;
634 goto err_mem_ioremap;
635 }
636
95a7f10e
VB		 637 i2c_davinci_init(dev);
638
639 r = request_irq(dev->irq, i2c_davinci_isr, 0, pdev->name, dev);
640 if (r) {
641 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
642 goto err_unuse_clocks;
643 }
644
82c0de11
C		 645 r = i2c_davinci_cpufreq_register(dev);
646 if (r) {
647 dev_err(&pdev->dev, "failed to register cpufreq\n");
648 goto err_free_irq;
649 }
650
95a7f10e
VB		 651 adap = &dev->adapter;
652 i2c_set_adapdata(adap, dev);
653 adap->owner = THIS_MODULE;
654 adap->class = I2C_CLASS_HWMON;
655 strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
656 adap->algo = &i2c_davinci_algo;
657 adap->dev.parent = &pdev->dev;
98a679ca 658 adap->timeout = DAVINCI_I2C_TIMEOUT;
95a7f10e
VB		 659
660 adap->nr = pdev->id;
661 r = i2c_add_numbered_adapter(adap);
662 if (r) {
663 dev_err(&pdev->dev, "failure adding adapter\n");
664 goto err_free_irq;
665 }
666
667 return 0;
668
669err_free_irq:
670 free_irq(dev->irq, dev);
671err_unuse_clocks:
c062a251
C		 672 iounmap(dev->base);
673err_mem_ioremap:
95a7f10e
VB		 674 clk_disable(dev->clk);
675 clk_put(dev->clk);
676 dev->clk = NULL;
677err_free_mem:
678 platform_set_drvdata(pdev, NULL);
679 put_device(&pdev->dev);
680 kfree(dev);
681err_release_region:
59330825 682 release_mem_region(mem->start, resource_size(mem));
95a7f10e
VB		 683
684 return r;
685}
686
687static int davinci_i2c_remove(struct platform_device *pdev)
688{
689 struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
690 struct resource *mem;
691
82c0de11
C		 692 i2c_davinci_cpufreq_deregister(dev);
693
95a7f10e
VB		 694 platform_set_drvdata(pdev, NULL);
695 i2c_del_adapter(&dev->adapter);
696 put_device(&pdev->dev);
697
698 clk_disable(dev->clk);
699 clk_put(dev->clk);
700 dev->clk = NULL;
701
702 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
703 free_irq(IRQ_I2C, dev);
c062a251 704 iounmap(dev->base);
95a7f10e
VB		 705 kfree(dev);
706
707 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
59330825 708 release_mem_region(mem->start, resource_size(mem));
95a7f10e
VB		 709 return 0;
710}
711
68f15de9
C		 712#ifdef CONFIG_PM
713static int davinci_i2c_suspend(struct device *dev)
714{
715 struct platform_device *pdev = to_platform_device(dev);
716 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
717
718 /* put I2C into reset */
719 davinci_i2c_reset_ctrl(i2c_dev, 0);
720 clk_disable(i2c_dev->clk);
721
722 return 0;
723}
724
725static int davinci_i2c_resume(struct device *dev)
726{
727 struct platform_device *pdev = to_platform_device(dev);
728 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
729
730 clk_enable(i2c_dev->clk);
731 /* take I2C out of reset */
732 davinci_i2c_reset_ctrl(i2c_dev, 1);
733
734 return 0;
735}
736
737static const struct dev_pm_ops davinci_i2c_pm = {
738 .suspend = davinci_i2c_suspend,
739 .resume = davinci_i2c_resume,
740};
741
742#define davinci_i2c_pm_ops (&davinci_i2c_pm)
743#else
744#define davinci_i2c_pm_ops NULL
745#endif
746
add8eda7
KS		 747/* work with hotplug and coldplug */
748MODULE_ALIAS("platform:i2c_davinci");
749
95a7f10e
VB		 750static struct platform_driver davinci_i2c_driver = {
751 .probe = davinci_i2c_probe,
752 .remove = davinci_i2c_remove,
753 .driver = {
754 .name = "i2c_davinci",
755 .owner = THIS_MODULE,
68f15de9 756 .pm = davinci_i2c_pm_ops,
95a7f10e
VB		 757 },
758};
759
760/* I2C may be needed to bring up other drivers */
761static int __init davinci_i2c_init_driver(void)
762{
763 return platform_driver_register(&davinci_i2c_driver);
764}
765subsys_initcall(davinci_i2c_init_driver);
766
767static void __exit davinci_i2c_exit_driver(void)
768{
769 platform_driver_unregister(&davinci_i2c_driver);
770}
771module_exit(davinci_i2c_exit_driver);
772
773MODULE_AUTHOR("Texas Instruments India");
774MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
775MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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