Commit | Line | Data |
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1ab52cf9 | 1 | /* |
a0e06ea6 | 2 | * Synopsys DesignWare I2C adapter driver (master only). |
1ab52cf9 BS |
3 | * |
4 | * Based on the TI DAVINCI I2C adapter driver. | |
5 | * | |
6 | * Copyright (C) 2006 Texas Instruments. | |
7 | * Copyright (C) 2007 MontaVista Software Inc. | |
8 | * Copyright (C) 2009 Provigent Ltd. | |
9 | * | |
10 | * ---------------------------------------------------------------------------- | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * ---------------------------------------------------------------------------- | |
26 | * | |
27 | */ | |
e68bb91b | 28 | #include <linux/export.h> |
1ab52cf9 BS |
29 | #include <linux/clk.h> |
30 | #include <linux/errno.h> | |
1ab52cf9 | 31 | #include <linux/err.h> |
2373f6b9 | 32 | #include <linux/i2c.h> |
1ab52cf9 | 33 | #include <linux/interrupt.h> |
1ab52cf9 | 34 | #include <linux/io.h> |
18dbdda8 | 35 | #include <linux/pm_runtime.h> |
2373f6b9 | 36 | #include <linux/delay.h> |
9dd3162d | 37 | #include <linux/module.h> |
2373f6b9 | 38 | #include "i2c-designware-core.h" |
ce6eb574 | 39 | |
f3fa9f3d DB |
40 | /* |
41 | * Registers offset | |
42 | */ | |
43 | #define DW_IC_CON 0x0 | |
44 | #define DW_IC_TAR 0x4 | |
45 | #define DW_IC_DATA_CMD 0x10 | |
46 | #define DW_IC_SS_SCL_HCNT 0x14 | |
47 | #define DW_IC_SS_SCL_LCNT 0x18 | |
48 | #define DW_IC_FS_SCL_HCNT 0x1c | |
49 | #define DW_IC_FS_SCL_LCNT 0x20 | |
50 | #define DW_IC_INTR_STAT 0x2c | |
51 | #define DW_IC_INTR_MASK 0x30 | |
52 | #define DW_IC_RAW_INTR_STAT 0x34 | |
53 | #define DW_IC_RX_TL 0x38 | |
54 | #define DW_IC_TX_TL 0x3c | |
55 | #define DW_IC_CLR_INTR 0x40 | |
56 | #define DW_IC_CLR_RX_UNDER 0x44 | |
57 | #define DW_IC_CLR_RX_OVER 0x48 | |
58 | #define DW_IC_CLR_TX_OVER 0x4c | |
59 | #define DW_IC_CLR_RD_REQ 0x50 | |
60 | #define DW_IC_CLR_TX_ABRT 0x54 | |
61 | #define DW_IC_CLR_RX_DONE 0x58 | |
62 | #define DW_IC_CLR_ACTIVITY 0x5c | |
63 | #define DW_IC_CLR_STOP_DET 0x60 | |
64 | #define DW_IC_CLR_START_DET 0x64 | |
65 | #define DW_IC_CLR_GEN_CALL 0x68 | |
66 | #define DW_IC_ENABLE 0x6c | |
67 | #define DW_IC_STATUS 0x70 | |
68 | #define DW_IC_TXFLR 0x74 | |
69 | #define DW_IC_RXFLR 0x78 | |
9803f868 | 70 | #define DW_IC_SDA_HOLD 0x7c |
f3fa9f3d | 71 | #define DW_IC_TX_ABRT_SOURCE 0x80 |
3ca4ed87 | 72 | #define DW_IC_ENABLE_STATUS 0x9c |
f3fa9f3d | 73 | #define DW_IC_COMP_PARAM_1 0xf4 |
9803f868 CR |
74 | #define DW_IC_COMP_VERSION 0xf8 |
75 | #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A | |
f3fa9f3d DB |
76 | #define DW_IC_COMP_TYPE 0xfc |
77 | #define DW_IC_COMP_TYPE_VALUE 0x44570140 | |
78 | ||
79 | #define DW_IC_INTR_RX_UNDER 0x001 | |
80 | #define DW_IC_INTR_RX_OVER 0x002 | |
81 | #define DW_IC_INTR_RX_FULL 0x004 | |
82 | #define DW_IC_INTR_TX_OVER 0x008 | |
83 | #define DW_IC_INTR_TX_EMPTY 0x010 | |
84 | #define DW_IC_INTR_RD_REQ 0x020 | |
85 | #define DW_IC_INTR_TX_ABRT 0x040 | |
86 | #define DW_IC_INTR_RX_DONE 0x080 | |
87 | #define DW_IC_INTR_ACTIVITY 0x100 | |
88 | #define DW_IC_INTR_STOP_DET 0x200 | |
89 | #define DW_IC_INTR_START_DET 0x400 | |
90 | #define DW_IC_INTR_GEN_CALL 0x800 | |
91 | ||
92 | #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ | |
93 | DW_IC_INTR_TX_EMPTY | \ | |
94 | DW_IC_INTR_TX_ABRT | \ | |
95 | DW_IC_INTR_STOP_DET) | |
96 | ||
97 | #define DW_IC_STATUS_ACTIVITY 0x1 | |
98 | ||
99 | #define DW_IC_ERR_TX_ABRT 0x1 | |
100 | ||
bd63ace4 CCE |
101 | #define DW_IC_TAR_10BITADDR_MASTER BIT(12) |
102 | ||
f3fa9f3d DB |
103 | /* |
104 | * status codes | |
105 | */ | |
106 | #define STATUS_IDLE 0x0 | |
107 | #define STATUS_WRITE_IN_PROGRESS 0x1 | |
108 | #define STATUS_READ_IN_PROGRESS 0x2 | |
109 | ||
110 | #define TIMEOUT 20 /* ms */ | |
111 | ||
112 | /* | |
113 | * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register | |
114 | * | |
115 | * only expected abort codes are listed here | |
116 | * refer to the datasheet for the full list | |
117 | */ | |
118 | #define ABRT_7B_ADDR_NOACK 0 | |
119 | #define ABRT_10ADDR1_NOACK 1 | |
120 | #define ABRT_10ADDR2_NOACK 2 | |
121 | #define ABRT_TXDATA_NOACK 3 | |
122 | #define ABRT_GCALL_NOACK 4 | |
123 | #define ABRT_GCALL_READ 5 | |
124 | #define ABRT_SBYTE_ACKDET 7 | |
125 | #define ABRT_SBYTE_NORSTRT 9 | |
126 | #define ABRT_10B_RD_NORSTRT 10 | |
127 | #define ABRT_MASTER_DIS 11 | |
128 | #define ARB_LOST 12 | |
129 | ||
130 | #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK) | |
131 | #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK) | |
132 | #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK) | |
133 | #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK) | |
134 | #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK) | |
135 | #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ) | |
136 | #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET) | |
137 | #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT) | |
138 | #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT) | |
139 | #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS) | |
140 | #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST) | |
141 | ||
142 | #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ | |
143 | DW_IC_TX_ABRT_10ADDR1_NOACK | \ | |
144 | DW_IC_TX_ABRT_10ADDR2_NOACK | \ | |
145 | DW_IC_TX_ABRT_TXDATA_NOACK | \ | |
146 | DW_IC_TX_ABRT_GCALL_NOACK) | |
147 | ||
1ab52cf9 | 148 | static char *abort_sources[] = { |
a0e06ea6 | 149 | [ABRT_7B_ADDR_NOACK] = |
1ab52cf9 | 150 | "slave address not acknowledged (7bit mode)", |
a0e06ea6 | 151 | [ABRT_10ADDR1_NOACK] = |
1ab52cf9 | 152 | "first address byte not acknowledged (10bit mode)", |
a0e06ea6 | 153 | [ABRT_10ADDR2_NOACK] = |
1ab52cf9 | 154 | "second address byte not acknowledged (10bit mode)", |
a0e06ea6 | 155 | [ABRT_TXDATA_NOACK] = |
1ab52cf9 | 156 | "data not acknowledged", |
a0e06ea6 | 157 | [ABRT_GCALL_NOACK] = |
1ab52cf9 | 158 | "no acknowledgement for a general call", |
a0e06ea6 | 159 | [ABRT_GCALL_READ] = |
1ab52cf9 | 160 | "read after general call", |
a0e06ea6 | 161 | [ABRT_SBYTE_ACKDET] = |
1ab52cf9 | 162 | "start byte acknowledged", |
a0e06ea6 | 163 | [ABRT_SBYTE_NORSTRT] = |
1ab52cf9 | 164 | "trying to send start byte when restart is disabled", |
a0e06ea6 | 165 | [ABRT_10B_RD_NORSTRT] = |
1ab52cf9 | 166 | "trying to read when restart is disabled (10bit mode)", |
a0e06ea6 | 167 | [ABRT_MASTER_DIS] = |
1ab52cf9 | 168 | "trying to use disabled adapter", |
a0e06ea6 | 169 | [ARB_LOST] = |
1ab52cf9 BS |
170 | "lost arbitration", |
171 | }; | |
172 | ||
2373f6b9 | 173 | u32 dw_readl(struct dw_i2c_dev *dev, int offset) |
7f279601 | 174 | { |
a8a9f3fe | 175 | u32 value; |
18c4089e | 176 | |
a8a9f3fe SR |
177 | if (dev->accessor_flags & ACCESS_16BIT) |
178 | value = readw(dev->base + offset) | | |
179 | (readw(dev->base + offset + 2) << 16); | |
180 | else | |
181 | value = readl(dev->base + offset); | |
182 | ||
183 | if (dev->accessor_flags & ACCESS_SWAP) | |
18c4089e JHD |
184 | return swab32(value); |
185 | else | |
186 | return value; | |
7f279601 JHD |
187 | } |
188 | ||
2373f6b9 | 189 | void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset) |
7f279601 | 190 | { |
a8a9f3fe | 191 | if (dev->accessor_flags & ACCESS_SWAP) |
18c4089e JHD |
192 | b = swab32(b); |
193 | ||
a8a9f3fe SR |
194 | if (dev->accessor_flags & ACCESS_16BIT) { |
195 | writew((u16)b, dev->base + offset); | |
196 | writew((u16)(b >> 16), dev->base + offset + 2); | |
197 | } else { | |
198 | writel(b, dev->base + offset); | |
199 | } | |
7f279601 JHD |
200 | } |
201 | ||
d60c7e81 SK |
202 | static u32 |
203 | i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) | |
204 | { | |
205 | /* | |
206 | * DesignWare I2C core doesn't seem to have solid strategy to meet | |
207 | * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec | |
208 | * will result in violation of the tHD;STA spec. | |
209 | */ | |
210 | if (cond) | |
211 | /* | |
212 | * Conditional expression: | |
213 | * | |
214 | * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH | |
215 | * | |
216 | * This is based on the DW manuals, and represents an ideal | |
217 | * configuration. The resulting I2C bus speed will be | |
218 | * faster than any of the others. | |
219 | * | |
220 | * If your hardware is free from tHD;STA issue, try this one. | |
221 | */ | |
222 | return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset; | |
223 | else | |
224 | /* | |
225 | * Conditional expression: | |
226 | * | |
227 | * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) | |
228 | * | |
229 | * This is just experimental rule; the tHD;STA period turned | |
230 | * out to be proportinal to (_HCNT + 3). With this setting, | |
231 | * we could meet both tHIGH and tHD;STA timing specs. | |
232 | * | |
233 | * If unsure, you'd better to take this alternative. | |
234 | * | |
235 | * The reason why we need to take into account "tf" here, | |
236 | * is the same as described in i2c_dw_scl_lcnt(). | |
237 | */ | |
238 | return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset; | |
239 | } | |
240 | ||
241 | static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) | |
242 | { | |
243 | /* | |
244 | * Conditional expression: | |
245 | * | |
246 | * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) | |
247 | * | |
248 | * DW I2C core starts counting the SCL CNTs for the LOW period | |
249 | * of the SCL clock (tLOW) as soon as it pulls the SCL line. | |
250 | * In order to meet the tLOW timing spec, we need to take into | |
251 | * account the fall time of SCL signal (tf). Default tf value | |
252 | * should be 0.3 us, for safety. | |
253 | */ | |
254 | return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset; | |
255 | } | |
256 | ||
3ca4ed87 MW |
257 | static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable) |
258 | { | |
259 | int timeout = 100; | |
260 | ||
261 | do { | |
262 | dw_writel(dev, enable, DW_IC_ENABLE); | |
263 | if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable) | |
264 | return; | |
265 | ||
266 | /* | |
267 | * Wait 10 times the signaling period of the highest I2C | |
268 | * transfer supported by the driver (for 400KHz this is | |
269 | * 25us) as described in the DesignWare I2C databook. | |
270 | */ | |
271 | usleep_range(25, 250); | |
272 | } while (timeout--); | |
273 | ||
274 | dev_warn(dev->dev, "timeout in %sabling adapter\n", | |
275 | enable ? "en" : "dis"); | |
276 | } | |
277 | ||
1ab52cf9 BS |
278 | /** |
279 | * i2c_dw_init() - initialize the designware i2c master hardware | |
280 | * @dev: device private data | |
281 | * | |
282 | * This functions configures and enables the I2C master. | |
283 | * This function is called during I2C init function, and in case of timeout at | |
284 | * run time. | |
285 | */ | |
2373f6b9 | 286 | int i2c_dw_init(struct dw_i2c_dev *dev) |
1ab52cf9 | 287 | { |
1d31b58f | 288 | u32 input_clock_khz; |
e18563fc | 289 | u32 hcnt, lcnt; |
4a423a8c DB |
290 | u32 reg; |
291 | ||
1d31b58f DB |
292 | input_clock_khz = dev->get_clk_rate_khz(dev); |
293 | ||
4a423a8c DB |
294 | reg = dw_readl(dev, DW_IC_COMP_TYPE); |
295 | if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) { | |
a8a9f3fe SR |
296 | /* Configure register endianess access */ |
297 | dev->accessor_flags |= ACCESS_SWAP; | |
298 | } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) { | |
299 | /* Configure register access mode 16bit */ | |
300 | dev->accessor_flags |= ACCESS_16BIT; | |
301 | } else if (reg != DW_IC_COMP_TYPE_VALUE) { | |
4a423a8c DB |
302 | dev_err(dev->dev, "Unknown Synopsys component type: " |
303 | "0x%08x\n", reg); | |
304 | return -ENODEV; | |
305 | } | |
1ab52cf9 BS |
306 | |
307 | /* Disable the adapter */ | |
3ca4ed87 | 308 | __i2c_dw_enable(dev, false); |
1ab52cf9 BS |
309 | |
310 | /* set standard and fast speed deviders for high/low periods */ | |
d60c7e81 SK |
311 | |
312 | /* Standard-mode */ | |
313 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, | |
314 | 40, /* tHD;STA = tHIGH = 4.0 us */ | |
315 | 3, /* tf = 0.3 us */ | |
316 | 0, /* 0: DW default, 1: Ideal */ | |
317 | 0); /* No offset */ | |
318 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, | |
319 | 47, /* tLOW = 4.7 us */ | |
320 | 3, /* tf = 0.3 us */ | |
321 | 0); /* No offset */ | |
defc0b2f MW |
322 | |
323 | /* Allow platforms to specify the ideal HCNT and LCNT values */ | |
324 | if (dev->ss_hcnt && dev->ss_lcnt) { | |
325 | hcnt = dev->ss_hcnt; | |
326 | lcnt = dev->ss_lcnt; | |
327 | } | |
7f279601 JHD |
328 | dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT); |
329 | dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT); | |
d60c7e81 SK |
330 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
331 | ||
332 | /* Fast-mode */ | |
333 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, | |
334 | 6, /* tHD;STA = tHIGH = 0.6 us */ | |
335 | 3, /* tf = 0.3 us */ | |
336 | 0, /* 0: DW default, 1: Ideal */ | |
337 | 0); /* No offset */ | |
338 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, | |
339 | 13, /* tLOW = 1.3 us */ | |
340 | 3, /* tf = 0.3 us */ | |
341 | 0); /* No offset */ | |
defc0b2f MW |
342 | |
343 | if (dev->fs_hcnt && dev->fs_lcnt) { | |
344 | hcnt = dev->fs_hcnt; | |
345 | lcnt = dev->fs_lcnt; | |
346 | } | |
7f279601 JHD |
347 | dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT); |
348 | dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); | |
d60c7e81 | 349 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
1ab52cf9 | 350 | |
9803f868 CR |
351 | /* Configure SDA Hold Time if required */ |
352 | if (dev->sda_hold_time) { | |
353 | reg = dw_readl(dev, DW_IC_COMP_VERSION); | |
354 | if (reg >= DW_IC_SDA_HOLD_MIN_VERS) | |
355 | dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD); | |
356 | else | |
357 | dev_warn(dev->dev, | |
358 | "Hardware too old to adjust SDA hold time."); | |
359 | } | |
360 | ||
4cb6d1d6 | 361 | /* Configure Tx/Rx FIFO threshold levels */ |
7f279601 JHD |
362 | dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL); |
363 | dw_writel(dev, 0, DW_IC_RX_TL); | |
4cb6d1d6 | 364 | |
1ab52cf9 | 365 | /* configure the i2c master */ |
e18563fc | 366 | dw_writel(dev, dev->master_cfg , DW_IC_CON); |
4a423a8c | 367 | return 0; |
1ab52cf9 | 368 | } |
e68bb91b | 369 | EXPORT_SYMBOL_GPL(i2c_dw_init); |
1ab52cf9 BS |
370 | |
371 | /* | |
372 | * Waiting for bus not busy | |
373 | */ | |
374 | static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) | |
375 | { | |
376 | int timeout = TIMEOUT; | |
377 | ||
7f279601 | 378 | while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { |
1ab52cf9 BS |
379 | if (timeout <= 0) { |
380 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
381 | return -ETIMEDOUT; | |
382 | } | |
383 | timeout--; | |
1451b91f | 384 | usleep_range(1000, 1100); |
1ab52cf9 BS |
385 | } |
386 | ||
387 | return 0; | |
388 | } | |
389 | ||
81e798b7 SK |
390 | static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) |
391 | { | |
392 | struct i2c_msg *msgs = dev->msgs; | |
bd63ace4 | 393 | u32 ic_con, ic_tar = 0; |
81e798b7 SK |
394 | |
395 | /* Disable the adapter */ | |
3ca4ed87 | 396 | __i2c_dw_enable(dev, false); |
81e798b7 | 397 | |
81e798b7 | 398 | /* if the slave address is ten bit address, enable 10BITADDR */ |
7f279601 | 399 | ic_con = dw_readl(dev, DW_IC_CON); |
bd63ace4 | 400 | if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) { |
81e798b7 | 401 | ic_con |= DW_IC_CON_10BITADDR_MASTER; |
bd63ace4 CCE |
402 | /* |
403 | * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing | |
404 | * mode has to be enabled via bit 12 of IC_TAR register. | |
405 | * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be | |
406 | * detected from registers. | |
407 | */ | |
408 | ic_tar = DW_IC_TAR_10BITADDR_MASTER; | |
409 | } else { | |
81e798b7 | 410 | ic_con &= ~DW_IC_CON_10BITADDR_MASTER; |
bd63ace4 CCE |
411 | } |
412 | ||
7f279601 | 413 | dw_writel(dev, ic_con, DW_IC_CON); |
81e798b7 | 414 | |
bd63ace4 CCE |
415 | /* |
416 | * Set the slave (target) address and enable 10-bit addressing mode | |
417 | * if applicable. | |
418 | */ | |
419 | dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR); | |
420 | ||
81e798b7 | 421 | /* Enable the adapter */ |
3ca4ed87 | 422 | __i2c_dw_enable(dev, true); |
201d6a70 | 423 | |
2a2d95e9 MW |
424 | /* Clear and enable interrupts */ |
425 | i2c_dw_clear_int(dev); | |
7f279601 | 426 | dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK); |
81e798b7 SK |
427 | } |
428 | ||
1ab52cf9 | 429 | /* |
201d6a70 SK |
430 | * Initiate (and continue) low level master read/write transaction. |
431 | * This function is only called from i2c_dw_isr, and pumping i2c_msg | |
432 | * messages into the tx buffer. Even if the size of i2c_msg data is | |
433 | * longer than the size of the tx buffer, it handles everything. | |
1ab52cf9 | 434 | */ |
bccd780f | 435 | static void |
e77cf232 | 436 | i2c_dw_xfer_msg(struct dw_i2c_dev *dev) |
1ab52cf9 | 437 | { |
1ab52cf9 | 438 | struct i2c_msg *msgs = dev->msgs; |
81e798b7 | 439 | u32 intr_mask; |
ae72222d | 440 | int tx_limit, rx_limit; |
ed5e1dd5 SK |
441 | u32 addr = msgs[dev->msg_write_idx].addr; |
442 | u32 buf_len = dev->tx_buf_len; | |
69932487 | 443 | u8 *buf = dev->tx_buf; |
82564245 | 444 | bool need_restart = false; |
1ab52cf9 | 445 | |
201d6a70 | 446 | intr_mask = DW_IC_INTR_DEFAULT_MASK; |
c70c5cd3 | 447 | |
6d2ea487 | 448 | for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { |
a0e06ea6 SK |
449 | /* |
450 | * if target address has changed, we need to | |
1ab52cf9 BS |
451 | * reprogram the target address in the i2c |
452 | * adapter when we are done with this transfer | |
453 | */ | |
8f588e40 SK |
454 | if (msgs[dev->msg_write_idx].addr != addr) { |
455 | dev_err(dev->dev, | |
456 | "%s: invalid target address\n", __func__); | |
457 | dev->msg_err = -EINVAL; | |
458 | break; | |
459 | } | |
1ab52cf9 BS |
460 | |
461 | if (msgs[dev->msg_write_idx].len == 0) { | |
462 | dev_err(dev->dev, | |
463 | "%s: invalid message length\n", __func__); | |
464 | dev->msg_err = -EINVAL; | |
8f588e40 | 465 | break; |
1ab52cf9 BS |
466 | } |
467 | ||
468 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { | |
469 | /* new i2c_msg */ | |
26ea15b1 | 470 | buf = msgs[dev->msg_write_idx].buf; |
1ab52cf9 | 471 | buf_len = msgs[dev->msg_write_idx].len; |
82564245 CCE |
472 | |
473 | /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and | |
474 | * IC_RESTART_EN are set, we must manually | |
475 | * set restart bit between messages. | |
476 | */ | |
477 | if ((dev->master_cfg & DW_IC_CON_RESTART_EN) && | |
478 | (dev->msg_write_idx > 0)) | |
479 | need_restart = true; | |
1ab52cf9 BS |
480 | } |
481 | ||
7f279601 JHD |
482 | tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR); |
483 | rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR); | |
ae72222d | 484 | |
1ab52cf9 | 485 | while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { |
17a76b4b MW |
486 | u32 cmd = 0; |
487 | ||
488 | /* | |
489 | * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must | |
490 | * manually set the stop bit. However, it cannot be | |
491 | * detected from the registers so we set it always | |
492 | * when writing/reading the last byte. | |
493 | */ | |
494 | if (dev->msg_write_idx == dev->msgs_num - 1 && | |
495 | buf_len == 1) | |
496 | cmd |= BIT(9); | |
497 | ||
82564245 CCE |
498 | if (need_restart) { |
499 | cmd |= BIT(10); | |
500 | need_restart = false; | |
501 | } | |
502 | ||
1ab52cf9 | 503 | if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { |
e6f34cea JA |
504 | |
505 | /* avoid rx buffer overrun */ | |
506 | if (rx_limit - dev->rx_outstanding <= 0) | |
507 | break; | |
508 | ||
17a76b4b | 509 | dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD); |
1ab52cf9 | 510 | rx_limit--; |
e6f34cea | 511 | dev->rx_outstanding++; |
1ab52cf9 | 512 | } else |
17a76b4b | 513 | dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD); |
1ab52cf9 BS |
514 | tx_limit--; buf_len--; |
515 | } | |
c70c5cd3 | 516 | |
26ea15b1 | 517 | dev->tx_buf = buf; |
c70c5cd3 SK |
518 | dev->tx_buf_len = buf_len; |
519 | ||
520 | if (buf_len > 0) { | |
521 | /* more bytes to be written */ | |
c70c5cd3 SK |
522 | dev->status |= STATUS_WRITE_IN_PROGRESS; |
523 | break; | |
69151e53 | 524 | } else |
c70c5cd3 | 525 | dev->status &= ~STATUS_WRITE_IN_PROGRESS; |
1ab52cf9 BS |
526 | } |
527 | ||
69151e53 SK |
528 | /* |
529 | * If i2c_msg index search is completed, we don't need TX_EMPTY | |
530 | * interrupt any more. | |
531 | */ | |
532 | if (dev->msg_write_idx == dev->msgs_num) | |
533 | intr_mask &= ~DW_IC_INTR_TX_EMPTY; | |
534 | ||
8f588e40 SK |
535 | if (dev->msg_err) |
536 | intr_mask = 0; | |
537 | ||
2373f6b9 | 538 | dw_writel(dev, intr_mask, DW_IC_INTR_MASK); |
1ab52cf9 BS |
539 | } |
540 | ||
541 | static void | |
78839bd0 | 542 | i2c_dw_read(struct dw_i2c_dev *dev) |
1ab52cf9 | 543 | { |
1ab52cf9 | 544 | struct i2c_msg *msgs = dev->msgs; |
ae72222d | 545 | int rx_valid; |
1ab52cf9 | 546 | |
6d2ea487 | 547 | for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { |
ed5e1dd5 | 548 | u32 len; |
1ab52cf9 BS |
549 | u8 *buf; |
550 | ||
551 | if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) | |
552 | continue; | |
553 | ||
1ab52cf9 BS |
554 | if (!(dev->status & STATUS_READ_IN_PROGRESS)) { |
555 | len = msgs[dev->msg_read_idx].len; | |
556 | buf = msgs[dev->msg_read_idx].buf; | |
557 | } else { | |
558 | len = dev->rx_buf_len; | |
559 | buf = dev->rx_buf; | |
560 | } | |
561 | ||
7f279601 | 562 | rx_valid = dw_readl(dev, DW_IC_RXFLR); |
ae72222d | 563 | |
e6f34cea | 564 | for (; len > 0 && rx_valid > 0; len--, rx_valid--) { |
7f279601 | 565 | *buf++ = dw_readl(dev, DW_IC_DATA_CMD); |
e6f34cea JA |
566 | dev->rx_outstanding--; |
567 | } | |
1ab52cf9 BS |
568 | |
569 | if (len > 0) { | |
570 | dev->status |= STATUS_READ_IN_PROGRESS; | |
571 | dev->rx_buf_len = len; | |
572 | dev->rx_buf = buf; | |
573 | return; | |
574 | } else | |
575 | dev->status &= ~STATUS_READ_IN_PROGRESS; | |
576 | } | |
577 | } | |
578 | ||
ce6eb574 SK |
579 | static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) |
580 | { | |
581 | unsigned long abort_source = dev->abort_source; | |
582 | int i; | |
583 | ||
6d1ea0f6 | 584 | if (abort_source & DW_IC_TX_ABRT_NOACK) { |
984b3f57 | 585 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
6d1ea0f6 SK |
586 | dev_dbg(dev->dev, |
587 | "%s: %s\n", __func__, abort_sources[i]); | |
588 | return -EREMOTEIO; | |
589 | } | |
590 | ||
984b3f57 | 591 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
ce6eb574 SK |
592 | dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); |
593 | ||
594 | if (abort_source & DW_IC_TX_ARB_LOST) | |
595 | return -EAGAIN; | |
ce6eb574 SK |
596 | else if (abort_source & DW_IC_TX_ABRT_GCALL_READ) |
597 | return -EINVAL; /* wrong msgs[] data */ | |
598 | else | |
599 | return -EIO; | |
600 | } | |
601 | ||
1ab52cf9 BS |
602 | /* |
603 | * Prepare controller for a transaction and call i2c_dw_xfer_msg | |
604 | */ | |
2373f6b9 | 605 | int |
1ab52cf9 BS |
606 | i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) |
607 | { | |
608 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); | |
609 | int ret; | |
610 | ||
611 | dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); | |
612 | ||
613 | mutex_lock(&dev->lock); | |
18dbdda8 | 614 | pm_runtime_get_sync(dev->dev); |
1ab52cf9 BS |
615 | |
616 | INIT_COMPLETION(dev->cmd_complete); | |
617 | dev->msgs = msgs; | |
618 | dev->msgs_num = num; | |
619 | dev->cmd_err = 0; | |
620 | dev->msg_write_idx = 0; | |
621 | dev->msg_read_idx = 0; | |
622 | dev->msg_err = 0; | |
623 | dev->status = STATUS_IDLE; | |
ce6eb574 | 624 | dev->abort_source = 0; |
e6f34cea | 625 | dev->rx_outstanding = 0; |
1ab52cf9 BS |
626 | |
627 | ret = i2c_dw_wait_bus_not_busy(dev); | |
628 | if (ret < 0) | |
629 | goto done; | |
630 | ||
631 | /* start the transfers */ | |
81e798b7 | 632 | i2c_dw_xfer_init(dev); |
1ab52cf9 BS |
633 | |
634 | /* wait for tx to complete */ | |
e42dba56 | 635 | ret = wait_for_completion_timeout(&dev->cmd_complete, HZ); |
1ab52cf9 BS |
636 | if (ret == 0) { |
637 | dev_err(dev->dev, "controller timed out\n"); | |
38d7fade | 638 | /* i2c_dw_init implicitly disables the adapter */ |
1ab52cf9 BS |
639 | i2c_dw_init(dev); |
640 | ret = -ETIMEDOUT; | |
641 | goto done; | |
e42dba56 | 642 | } |
1ab52cf9 | 643 | |
38d7fade CR |
644 | /* |
645 | * We must disable the adapter before unlocking the &dev->lock mutex | |
646 | * below. Otherwise the hardware might continue generating interrupts | |
647 | * which in turn causes a race condition with the following transfer. | |
648 | * Needs some more investigation if the additional interrupts are | |
649 | * a hardware bug or this driver doesn't handle them correctly yet. | |
650 | */ | |
651 | __i2c_dw_enable(dev, false); | |
652 | ||
1ab52cf9 BS |
653 | if (dev->msg_err) { |
654 | ret = dev->msg_err; | |
655 | goto done; | |
656 | } | |
657 | ||
658 | /* no error */ | |
659 | if (likely(!dev->cmd_err)) { | |
1ab52cf9 BS |
660 | ret = num; |
661 | goto done; | |
662 | } | |
663 | ||
664 | /* We have an error */ | |
665 | if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { | |
ce6eb574 SK |
666 | ret = i2c_dw_handle_tx_abort(dev); |
667 | goto done; | |
1ab52cf9 BS |
668 | } |
669 | ret = -EIO; | |
670 | ||
671 | done: | |
43452335 MW |
672 | pm_runtime_mark_last_busy(dev->dev); |
673 | pm_runtime_put_autosuspend(dev->dev); | |
1ab52cf9 BS |
674 | mutex_unlock(&dev->lock); |
675 | ||
676 | return ret; | |
677 | } | |
e68bb91b | 678 | EXPORT_SYMBOL_GPL(i2c_dw_xfer); |
1ab52cf9 | 679 | |
2373f6b9 | 680 | u32 i2c_dw_func(struct i2c_adapter *adap) |
1ab52cf9 | 681 | { |
2fa8326b DB |
682 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); |
683 | return dev->functionality; | |
1ab52cf9 | 684 | } |
e68bb91b | 685 | EXPORT_SYMBOL_GPL(i2c_dw_func); |
1ab52cf9 | 686 | |
e28000a3 SK |
687 | static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) |
688 | { | |
689 | u32 stat; | |
690 | ||
691 | /* | |
692 | * The IC_INTR_STAT register just indicates "enabled" interrupts. | |
693 | * Ths unmasked raw version of interrupt status bits are available | |
694 | * in the IC_RAW_INTR_STAT register. | |
695 | * | |
696 | * That is, | |
2373f6b9 | 697 | * stat = dw_readl(IC_INTR_STAT); |
e28000a3 | 698 | * equals to, |
2373f6b9 | 699 | * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK); |
e28000a3 SK |
700 | * |
701 | * The raw version might be useful for debugging purposes. | |
702 | */ | |
7f279601 | 703 | stat = dw_readl(dev, DW_IC_INTR_STAT); |
e28000a3 SK |
704 | |
705 | /* | |
706 | * Do not use the IC_CLR_INTR register to clear interrupts, or | |
707 | * you'll miss some interrupts, triggered during the period from | |
2373f6b9 | 708 | * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR). |
e28000a3 SK |
709 | * |
710 | * Instead, use the separately-prepared IC_CLR_* registers. | |
711 | */ | |
712 | if (stat & DW_IC_INTR_RX_UNDER) | |
7f279601 | 713 | dw_readl(dev, DW_IC_CLR_RX_UNDER); |
e28000a3 | 714 | if (stat & DW_IC_INTR_RX_OVER) |
7f279601 | 715 | dw_readl(dev, DW_IC_CLR_RX_OVER); |
e28000a3 | 716 | if (stat & DW_IC_INTR_TX_OVER) |
7f279601 | 717 | dw_readl(dev, DW_IC_CLR_TX_OVER); |
e28000a3 | 718 | if (stat & DW_IC_INTR_RD_REQ) |
7f279601 | 719 | dw_readl(dev, DW_IC_CLR_RD_REQ); |
e28000a3 SK |
720 | if (stat & DW_IC_INTR_TX_ABRT) { |
721 | /* | |
722 | * The IC_TX_ABRT_SOURCE register is cleared whenever | |
723 | * the IC_CLR_TX_ABRT is read. Preserve it beforehand. | |
724 | */ | |
7f279601 JHD |
725 | dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE); |
726 | dw_readl(dev, DW_IC_CLR_TX_ABRT); | |
e28000a3 SK |
727 | } |
728 | if (stat & DW_IC_INTR_RX_DONE) | |
7f279601 | 729 | dw_readl(dev, DW_IC_CLR_RX_DONE); |
e28000a3 | 730 | if (stat & DW_IC_INTR_ACTIVITY) |
7f279601 | 731 | dw_readl(dev, DW_IC_CLR_ACTIVITY); |
e28000a3 | 732 | if (stat & DW_IC_INTR_STOP_DET) |
7f279601 | 733 | dw_readl(dev, DW_IC_CLR_STOP_DET); |
e28000a3 | 734 | if (stat & DW_IC_INTR_START_DET) |
7f279601 | 735 | dw_readl(dev, DW_IC_CLR_START_DET); |
e28000a3 | 736 | if (stat & DW_IC_INTR_GEN_CALL) |
7f279601 | 737 | dw_readl(dev, DW_IC_CLR_GEN_CALL); |
e28000a3 SK |
738 | |
739 | return stat; | |
740 | } | |
741 | ||
1ab52cf9 BS |
742 | /* |
743 | * Interrupt service routine. This gets called whenever an I2C interrupt | |
744 | * occurs. | |
745 | */ | |
2373f6b9 | 746 | irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) |
1ab52cf9 BS |
747 | { |
748 | struct dw_i2c_dev *dev = dev_id; | |
af06cf6c DB |
749 | u32 stat, enabled; |
750 | ||
751 | enabled = dw_readl(dev, DW_IC_ENABLE); | |
752 | stat = dw_readl(dev, DW_IC_RAW_INTR_STAT); | |
753 | dev_dbg(dev->dev, "%s: %s enabled= 0x%x stat=0x%x\n", __func__, | |
754 | dev->adapter.name, enabled, stat); | |
755 | if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY)) | |
756 | return IRQ_NONE; | |
1ab52cf9 | 757 | |
e28000a3 | 758 | stat = i2c_dw_read_clear_intrbits(dev); |
e28000a3 | 759 | |
1ab52cf9 | 760 | if (stat & DW_IC_INTR_TX_ABRT) { |
1ab52cf9 BS |
761 | dev->cmd_err |= DW_IC_ERR_TX_ABRT; |
762 | dev->status = STATUS_IDLE; | |
597fe310 SK |
763 | |
764 | /* | |
765 | * Anytime TX_ABRT is set, the contents of the tx/rx | |
766 | * buffers are flushed. Make sure to skip them. | |
767 | */ | |
7f279601 | 768 | dw_writel(dev, 0, DW_IC_INTR_MASK); |
597fe310 | 769 | goto tx_aborted; |
07745399 SK |
770 | } |
771 | ||
21a89d41 | 772 | if (stat & DW_IC_INTR_RX_FULL) |
07745399 | 773 | i2c_dw_read(dev); |
21a89d41 SK |
774 | |
775 | if (stat & DW_IC_INTR_TX_EMPTY) | |
07745399 | 776 | i2c_dw_xfer_msg(dev); |
07745399 SK |
777 | |
778 | /* | |
779 | * No need to modify or disable the interrupt mask here. | |
780 | * i2c_dw_xfer_msg() will take care of it according to | |
781 | * the current transmit status. | |
782 | */ | |
1ab52cf9 | 783 | |
597fe310 | 784 | tx_aborted: |
8f588e40 | 785 | if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) |
1ab52cf9 BS |
786 | complete(&dev->cmd_complete); |
787 | ||
788 | return IRQ_HANDLED; | |
789 | } | |
e68bb91b | 790 | EXPORT_SYMBOL_GPL(i2c_dw_isr); |
f3fa9f3d DB |
791 | |
792 | void i2c_dw_enable(struct dw_i2c_dev *dev) | |
793 | { | |
794 | /* Enable the adapter */ | |
3ca4ed87 | 795 | __i2c_dw_enable(dev, true); |
f3fa9f3d | 796 | } |
e68bb91b | 797 | EXPORT_SYMBOL_GPL(i2c_dw_enable); |
f3fa9f3d | 798 | |
18dbdda8 | 799 | u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev) |
f3fa9f3d | 800 | { |
18dbdda8 DB |
801 | return dw_readl(dev, DW_IC_ENABLE); |
802 | } | |
e68bb91b | 803 | EXPORT_SYMBOL_GPL(i2c_dw_is_enabled); |
f3fa9f3d | 804 | |
18dbdda8 DB |
805 | void i2c_dw_disable(struct dw_i2c_dev *dev) |
806 | { | |
f3fa9f3d | 807 | /* Disable controller */ |
3ca4ed87 | 808 | __i2c_dw_enable(dev, false); |
f3fa9f3d DB |
809 | |
810 | /* Disable all interupts */ | |
811 | dw_writel(dev, 0, DW_IC_INTR_MASK); | |
812 | dw_readl(dev, DW_IC_CLR_INTR); | |
813 | } | |
e68bb91b | 814 | EXPORT_SYMBOL_GPL(i2c_dw_disable); |
f3fa9f3d DB |
815 | |
816 | void i2c_dw_clear_int(struct dw_i2c_dev *dev) | |
817 | { | |
818 | dw_readl(dev, DW_IC_CLR_INTR); | |
819 | } | |
e68bb91b | 820 | EXPORT_SYMBOL_GPL(i2c_dw_clear_int); |
f3fa9f3d DB |
821 | |
822 | void i2c_dw_disable_int(struct dw_i2c_dev *dev) | |
823 | { | |
824 | dw_writel(dev, 0, DW_IC_INTR_MASK); | |
825 | } | |
e68bb91b | 826 | EXPORT_SYMBOL_GPL(i2c_dw_disable_int); |
f3fa9f3d DB |
827 | |
828 | u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev) | |
829 | { | |
830 | return dw_readl(dev, DW_IC_COMP_PARAM_1); | |
831 | } | |
e68bb91b | 832 | EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param); |
9dd3162d MW |
833 | |
834 | MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core"); | |
835 | MODULE_LICENSE("GPL"); |