Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, |
3 | Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker | |
4 | <mdsxyz123@yahoo.com> | |
b3b8df97 | 5 | Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> |
0cd96eb0 DW |
6 | Copyright (C) 2010 Intel Corporation, |
7 | David Woodhouse <dwmw2@infradead.org> | |
1da177e4 LT |
8 | |
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
1da177e4 LT |
18 | */ |
19 | ||
20 | /* | |
ce316110 JD |
21 | * Supports the following Intel I/O Controller Hubs (ICH): |
22 | * | |
23 | * I/O Block I2C | |
24 | * region SMBus Block proc. block | |
25 | * Chip name PCI ID size PEC buffer call read | |
26 | * --------------------------------------------------------------------------- | |
27 | * 82801AA (ICH) 0x2413 16 no no no no | |
28 | * 82801AB (ICH0) 0x2423 16 no no no no | |
29 | * 82801BA (ICH2) 0x2443 16 no no no no | |
30 | * 82801CA (ICH3) 0x2483 32 soft no no no | |
31 | * 82801DB (ICH4) 0x24c3 32 hard yes no no | |
32 | * 82801E (ICH5) 0x24d3 32 hard yes yes yes | |
33 | * 6300ESB 0x25a4 32 hard yes yes yes | |
34 | * 82801F (ICH6) 0x266a 32 hard yes yes yes | |
35 | * 6310ESB/6320ESB 0x269b 32 hard yes yes yes | |
36 | * 82801G (ICH7) 0x27da 32 hard yes yes yes | |
37 | * 82801H (ICH8) 0x283e 32 hard yes yes yes | |
38 | * 82801I (ICH9) 0x2930 32 hard yes yes yes | |
39 | * EP80579 (Tolapai) 0x5032 32 hard yes yes yes | |
40 | * ICH10 0x3a30 32 hard yes yes yes | |
41 | * ICH10 0x3a60 32 hard yes yes yes | |
42 | * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes | |
43 | * 6 Series (PCH) 0x1c22 32 hard yes yes yes | |
44 | * Patsburg (PCH) 0x1d22 32 hard yes yes yes | |
45 | * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes | |
46 | * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes | |
47 | * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes | |
48 | * DH89xxCC (PCH) 0x2330 32 hard yes yes yes | |
49 | * Panther Point (PCH) 0x1e22 32 hard yes yes yes | |
50 | * Lynx Point (PCH) 0x8c22 32 hard yes yes yes | |
51 | * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes | |
52 | * Avoton (SOC) 0x1f3c 32 hard yes yes yes | |
53 | * Wellsburg (PCH) 0x8d22 32 hard yes yes yes | |
54 | * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes | |
55 | * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes | |
56 | * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes | |
57 | * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes | |
b299de83 | 58 | * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes |
ce316110 JD |
59 | * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes |
60 | * BayTrail (SOC) 0x0f12 32 hard yes yes yes | |
3e27a844 | 61 | * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes |
3eee1799 | 62 | * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes |
ce316110 JD |
63 | * |
64 | * Features supported by this driver: | |
65 | * Software PEC no | |
66 | * Hardware PEC yes | |
67 | * Block buffer yes | |
68 | * Block process call transaction no | |
69 | * I2C block read transaction yes (doesn't use the block buffer) | |
70 | * Slave mode no | |
71 | * Interrupt processing yes | |
72 | * | |
73 | * See the file Documentation/i2c/busses/i2c-i801 for details. | |
74 | */ | |
1da177e4 | 75 | |
636752bc | 76 | #include <linux/interrupt.h> |
1da177e4 LT |
77 | #include <linux/module.h> |
78 | #include <linux/pci.h> | |
79 | #include <linux/kernel.h> | |
80 | #include <linux/stddef.h> | |
81 | #include <linux/delay.h> | |
1da177e4 LT |
82 | #include <linux/ioport.h> |
83 | #include <linux/init.h> | |
84 | #include <linux/i2c.h> | |
54fb4a05 | 85 | #include <linux/acpi.h> |
1561bfe5 | 86 | #include <linux/io.h> |
fa5bfab7 | 87 | #include <linux/dmi.h> |
665a96b7 | 88 | #include <linux/slab.h> |
636752bc | 89 | #include <linux/wait.h> |
3ad7ea18 JD |
90 | #include <linux/err.h> |
91 | ||
79e3e5b8 JD |
92 | #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ |
93 | defined CONFIG_DMI | |
3ad7ea18 JD |
94 | #include <linux/gpio.h> |
95 | #include <linux/i2c-mux-gpio.h> | |
96 | #include <linux/platform_device.h> | |
97 | #endif | |
1da177e4 | 98 | |
1da177e4 | 99 | /* I801 SMBus address offsets */ |
0cd96eb0 DW |
100 | #define SMBHSTSTS(p) (0 + (p)->smba) |
101 | #define SMBHSTCNT(p) (2 + (p)->smba) | |
102 | #define SMBHSTCMD(p) (3 + (p)->smba) | |
103 | #define SMBHSTADD(p) (4 + (p)->smba) | |
104 | #define SMBHSTDAT0(p) (5 + (p)->smba) | |
105 | #define SMBHSTDAT1(p) (6 + (p)->smba) | |
106 | #define SMBBLKDAT(p) (7 + (p)->smba) | |
107 | #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ | |
108 | #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ | |
109 | #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ | |
1da177e4 LT |
110 | |
111 | /* PCI Address Constants */ | |
6dcc19df | 112 | #define SMBBAR 4 |
aeb8a3d1 | 113 | #define SMBPCICTL 0x004 |
636752bc | 114 | #define SMBPCISTS 0x006 |
1da177e4 | 115 | #define SMBHSTCFG 0x040 |
1da177e4 | 116 | |
636752bc DK |
117 | /* Host status bits for SMBPCISTS */ |
118 | #define SMBPCISTS_INTS 0x08 | |
119 | ||
aeb8a3d1 JD |
120 | /* Control bits for SMBPCICTL */ |
121 | #define SMBPCICTL_INTDIS 0x0400 | |
122 | ||
1da177e4 LT |
123 | /* Host configuration bits for SMBHSTCFG */ |
124 | #define SMBHSTCFG_HST_EN 1 | |
125 | #define SMBHSTCFG_SMB_SMI_EN 2 | |
126 | #define SMBHSTCFG_I2C_EN 4 | |
127 | ||
25985edc | 128 | /* Auxiliary control register bits, ICH4+ only */ |
ca8b9e32 OR |
129 | #define SMBAUXCTL_CRC 1 |
130 | #define SMBAUXCTL_E32B 2 | |
131 | ||
1da177e4 | 132 | /* Other settings */ |
84c1af4c | 133 | #define MAX_RETRIES 400 |
1da177e4 LT |
134 | |
135 | /* I801 command constants */ | |
136 | #define I801_QUICK 0x00 | |
137 | #define I801_BYTE 0x04 | |
138 | #define I801_BYTE_DATA 0x08 | |
139 | #define I801_WORD_DATA 0x0C | |
ae7b0497 | 140 | #define I801_PROC_CALL 0x10 /* unimplemented */ |
1da177e4 | 141 | #define I801_BLOCK_DATA 0x14 |
6342064c | 142 | #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ |
edbeea63 DK |
143 | |
144 | /* I801 Host Control register bits */ | |
145 | #define SMBHSTCNT_INTREN 0x01 | |
146 | #define SMBHSTCNT_KILL 0x02 | |
147 | #define SMBHSTCNT_LAST_BYTE 0x20 | |
148 | #define SMBHSTCNT_START 0x40 | |
149 | #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */ | |
1da177e4 | 150 | |
ca8b9e32 OR |
151 | /* I801 Hosts Status register bits */ |
152 | #define SMBHSTSTS_BYTE_DONE 0x80 | |
153 | #define SMBHSTSTS_INUSE_STS 0x40 | |
154 | #define SMBHSTSTS_SMBALERT_STS 0x20 | |
155 | #define SMBHSTSTS_FAILED 0x10 | |
156 | #define SMBHSTSTS_BUS_ERR 0x08 | |
157 | #define SMBHSTSTS_DEV_ERR 0x04 | |
158 | #define SMBHSTSTS_INTR 0x02 | |
159 | #define SMBHSTSTS_HOST_BUSY 0x01 | |
1da177e4 | 160 | |
70a1cc19 DK |
161 | #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ |
162 | SMBHSTSTS_DEV_ERR) | |
163 | ||
164 | #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ | |
165 | STATUS_ERROR_FLAGS) | |
cf898dc5 | 166 | |
a6e5e2be | 167 | /* Older devices have their ID defined in <linux/pci_ids.h> */ |
ce316110 | 168 | #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 |
39e8e30e | 169 | #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 |
ce316110 JD |
170 | #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 |
171 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 | |
55fee8d7 | 172 | /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ |
ce316110 JD |
173 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 |
174 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 | |
175 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 | |
176 | #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 | |
177 | #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c | |
178 | #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 | |
179 | #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 | |
180 | #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 | |
181 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 | |
b299de83 | 182 | #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 |
ce316110 JD |
183 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 |
184 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d | |
185 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e | |
186 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f | |
187 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 | |
afc65924 | 188 | #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 |
3e27a844 | 189 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 |
3eee1799 | 190 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 |
55fee8d7 | 191 | |
3ad7ea18 JD |
192 | struct i801_mux_config { |
193 | char *gpio_chip; | |
194 | unsigned values[3]; | |
195 | int n_values; | |
196 | unsigned classes[3]; | |
197 | unsigned gpios[2]; /* Relative to gpio_chip->base */ | |
198 | int n_gpios; | |
199 | }; | |
200 | ||
0cd96eb0 DW |
201 | struct i801_priv { |
202 | struct i2c_adapter adapter; | |
203 | unsigned long smba; | |
204 | unsigned char original_hstcfg; | |
205 | struct pci_dev *pci_dev; | |
206 | unsigned int features; | |
636752bc DK |
207 | |
208 | /* isr processing */ | |
209 | wait_queue_head_t waitq; | |
210 | u8 status; | |
d3ff6ce4 DK |
211 | |
212 | /* Command state used by isr for byte-by-byte block transactions */ | |
213 | u8 cmd; | |
214 | bool is_read; | |
215 | int count; | |
216 | int len; | |
217 | u8 *data; | |
3ad7ea18 | 218 | |
79e3e5b8 JD |
219 | #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ |
220 | defined CONFIG_DMI | |
3ad7ea18 | 221 | const struct i801_mux_config *mux_drvdata; |
3ad7ea18 JD |
222 | struct platform_device *mux_pdev; |
223 | #endif | |
0cd96eb0 DW |
224 | }; |
225 | ||
369f6f4a JD |
226 | #define FEATURE_SMBUS_PEC (1 << 0) |
227 | #define FEATURE_BLOCK_BUFFER (1 << 1) | |
228 | #define FEATURE_BLOCK_PROC (1 << 2) | |
229 | #define FEATURE_I2C_BLOCK_READ (1 << 3) | |
636752bc | 230 | #define FEATURE_IRQ (1 << 4) |
e7198fbf JD |
231 | /* Not really a feature, but it's convenient to handle it as such */ |
232 | #define FEATURE_IDF (1 << 15) | |
1da177e4 | 233 | |
adff687d JD |
234 | static const char *i801_feature_names[] = { |
235 | "SMBus PEC", | |
236 | "Block buffer", | |
237 | "Block process call", | |
238 | "I2C block read", | |
636752bc | 239 | "Interrupt", |
adff687d JD |
240 | }; |
241 | ||
242 | static unsigned int disable_features; | |
243 | module_param(disable_features, uint, S_IRUGO | S_IWUSR); | |
53229345 JD |
244 | MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" |
245 | "\t\t 0x01 disable SMBus PEC\n" | |
246 | "\t\t 0x02 disable the block buffer\n" | |
247 | "\t\t 0x08 disable the I2C block read functionality\n" | |
248 | "\t\t 0x10 don't use interrupts "); | |
adff687d | 249 | |
cf898dc5 JD |
250 | /* Make sure the SMBus host is ready to start transmitting. |
251 | Return 0 if it is, -EBUSY if it is not. */ | |
0cd96eb0 | 252 | static int i801_check_pre(struct i801_priv *priv) |
1da177e4 | 253 | { |
2b73809d | 254 | int status; |
1da177e4 | 255 | |
0cd96eb0 | 256 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 | 257 | if (status & SMBHSTSTS_HOST_BUSY) { |
0cd96eb0 | 258 | dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); |
cf898dc5 JD |
259 | return -EBUSY; |
260 | } | |
261 | ||
262 | status &= STATUS_FLAGS; | |
263 | if (status) { | |
0cd96eb0 | 264 | dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", |
2b73809d | 265 | status); |
0cd96eb0 DW |
266 | outb_p(status, SMBHSTSTS(priv)); |
267 | status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; | |
cf898dc5 | 268 | if (status) { |
0cd96eb0 | 269 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
270 | "Failed clearing status flags (%02x)\n", |
271 | status); | |
97140342 | 272 | return -EBUSY; |
1da177e4 LT |
273 | } |
274 | } | |
275 | ||
cf898dc5 JD |
276 | return 0; |
277 | } | |
1da177e4 | 278 | |
6cad93c4 JD |
279 | /* |
280 | * Convert the status register to an error code, and clear it. | |
281 | * Note that status only contains the bits we want to clear, not the | |
282 | * actual register value. | |
283 | */ | |
284 | static int i801_check_post(struct i801_priv *priv, int status) | |
cf898dc5 JD |
285 | { |
286 | int result = 0; | |
1da177e4 | 287 | |
636752bc DK |
288 | /* |
289 | * If the SMBus is still busy, we give up | |
290 | * Note: This timeout condition only happens when using polling | |
291 | * transactions. For interrupt operation, NAK/timeout is indicated by | |
292 | * DEV_ERR. | |
293 | */ | |
6cad93c4 | 294 | if (unlikely(status < 0)) { |
0cd96eb0 | 295 | dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); |
ca8b9e32 | 296 | /* try to stop the current command */ |
0cd96eb0 DW |
297 | dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); |
298 | outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, | |
299 | SMBHSTCNT(priv)); | |
84c1af4c | 300 | usleep_range(1000, 2000); |
0cd96eb0 DW |
301 | outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), |
302 | SMBHSTCNT(priv)); | |
cf898dc5 JD |
303 | |
304 | /* Check if it worked */ | |
0cd96eb0 | 305 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 JD |
306 | if ((status & SMBHSTSTS_HOST_BUSY) || |
307 | !(status & SMBHSTSTS_FAILED)) | |
0cd96eb0 | 308 | dev_err(&priv->pci_dev->dev, |
cf898dc5 | 309 | "Failed terminating the transaction\n"); |
0cd96eb0 | 310 | outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); |
cf898dc5 | 311 | return -ETIMEDOUT; |
1da177e4 LT |
312 | } |
313 | ||
2b73809d | 314 | if (status & SMBHSTSTS_FAILED) { |
97140342 | 315 | result = -EIO; |
0cd96eb0 | 316 | dev_err(&priv->pci_dev->dev, "Transaction failed\n"); |
cf898dc5 JD |
317 | } |
318 | if (status & SMBHSTSTS_DEV_ERR) { | |
319 | result = -ENXIO; | |
0cd96eb0 | 320 | dev_dbg(&priv->pci_dev->dev, "No response\n"); |
1da177e4 | 321 | } |
2b73809d | 322 | if (status & SMBHSTSTS_BUS_ERR) { |
dcb5c923 | 323 | result = -EAGAIN; |
0cd96eb0 | 324 | dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); |
1da177e4 LT |
325 | } |
326 | ||
6cad93c4 JD |
327 | /* Clear status flags except BYTE_DONE, to be cleared by caller */ |
328 | outb_p(status, SMBHSTSTS(priv)); | |
1da177e4 | 329 | |
1da177e4 LT |
330 | return result; |
331 | } | |
332 | ||
6cad93c4 JD |
333 | /* Wait for BUSY being cleared and either INTR or an error flag being set */ |
334 | static int i801_wait_intr(struct i801_priv *priv) | |
cf898dc5 | 335 | { |
cf898dc5 | 336 | int timeout = 0; |
6cad93c4 | 337 | int status; |
cf898dc5 JD |
338 | |
339 | /* We will always wait for a fraction of a second! */ | |
340 | do { | |
84c1af4c | 341 | usleep_range(250, 500); |
0cd96eb0 | 342 | status = inb_p(SMBHSTSTS(priv)); |
6cad93c4 JD |
343 | } while (((status & SMBHSTSTS_HOST_BUSY) || |
344 | !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && | |
345 | (timeout++ < MAX_RETRIES)); | |
cf898dc5 | 346 | |
6cad93c4 JD |
347 | if (timeout > MAX_RETRIES) { |
348 | dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); | |
349 | return -ETIMEDOUT; | |
350 | } | |
351 | return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); | |
cf898dc5 JD |
352 | } |
353 | ||
6cad93c4 JD |
354 | /* Wait for either BYTE_DONE or an error flag being set */ |
355 | static int i801_wait_byte_done(struct i801_priv *priv) | |
ca8b9e32 OR |
356 | { |
357 | int timeout = 0; | |
2b73809d | 358 | int status; |
ca8b9e32 | 359 | |
6cad93c4 | 360 | /* We will always wait for a fraction of a second! */ |
ca8b9e32 | 361 | do { |
84c1af4c | 362 | usleep_range(250, 500); |
0cd96eb0 | 363 | status = inb_p(SMBHSTSTS(priv)); |
6cad93c4 JD |
364 | } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && |
365 | (timeout++ < MAX_RETRIES)); | |
366 | ||
367 | if (timeout > MAX_RETRIES) { | |
368 | dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); | |
369 | return -ETIMEDOUT; | |
370 | } | |
371 | return status & STATUS_ERROR_FLAGS; | |
372 | } | |
373 | ||
374 | static int i801_transaction(struct i801_priv *priv, int xact) | |
375 | { | |
376 | int status; | |
377 | int result; | |
b3b8df97 | 378 | const struct i2c_adapter *adap = &priv->adapter; |
ca8b9e32 | 379 | |
6cad93c4 JD |
380 | result = i801_check_pre(priv); |
381 | if (result < 0) | |
382 | return result; | |
4ccc28f7 | 383 | |
636752bc DK |
384 | if (priv->features & FEATURE_IRQ) { |
385 | outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, | |
386 | SMBHSTCNT(priv)); | |
b3b8df97 JD |
387 | result = wait_event_timeout(priv->waitq, |
388 | (status = priv->status), | |
389 | adap->timeout); | |
390 | if (!result) { | |
391 | status = -ETIMEDOUT; | |
392 | dev_warn(&priv->pci_dev->dev, | |
393 | "Timeout waiting for interrupt!\n"); | |
394 | } | |
636752bc DK |
395 | priv->status = 0; |
396 | return i801_check_post(priv, status); | |
397 | } | |
398 | ||
6cad93c4 JD |
399 | /* the current contents of SMBHSTCNT can be overwritten, since PEC, |
400 | * SMBSCMD are passed in xact */ | |
401 | outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); | |
402 | ||
403 | status = i801_wait_intr(priv); | |
404 | return i801_check_post(priv, status); | |
ca8b9e32 OR |
405 | } |
406 | ||
0cd96eb0 DW |
407 | static int i801_block_transaction_by_block(struct i801_priv *priv, |
408 | union i2c_smbus_data *data, | |
7edcb9ab OR |
409 | char read_write, int hwpec) |
410 | { | |
411 | int i, len; | |
97140342 | 412 | int status; |
7edcb9ab | 413 | |
0cd96eb0 | 414 | inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ |
7edcb9ab OR |
415 | |
416 | /* Use 32-byte buffer to process this transaction */ | |
417 | if (read_write == I2C_SMBUS_WRITE) { | |
418 | len = data->block[0]; | |
0cd96eb0 | 419 | outb_p(len, SMBHSTDAT0(priv)); |
7edcb9ab | 420 | for (i = 0; i < len; i++) |
0cd96eb0 | 421 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
7edcb9ab OR |
422 | } |
423 | ||
37af8711 | 424 | status = i801_transaction(priv, I801_BLOCK_DATA | |
edbeea63 | 425 | (hwpec ? SMBHSTCNT_PEC_EN : 0)); |
97140342 DB |
426 | if (status) |
427 | return status; | |
7edcb9ab OR |
428 | |
429 | if (read_write == I2C_SMBUS_READ) { | |
0cd96eb0 | 430 | len = inb_p(SMBHSTDAT0(priv)); |
7edcb9ab | 431 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) |
97140342 | 432 | return -EPROTO; |
7edcb9ab OR |
433 | |
434 | data->block[0] = len; | |
435 | for (i = 0; i < len; i++) | |
0cd96eb0 | 436 | data->block[i + 1] = inb_p(SMBBLKDAT(priv)); |
7edcb9ab OR |
437 | } |
438 | return 0; | |
439 | } | |
440 | ||
d3ff6ce4 DK |
441 | static void i801_isr_byte_done(struct i801_priv *priv) |
442 | { | |
443 | if (priv->is_read) { | |
444 | /* For SMBus block reads, length is received with first byte */ | |
445 | if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && | |
446 | (priv->count == 0)) { | |
447 | priv->len = inb_p(SMBHSTDAT0(priv)); | |
448 | if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { | |
449 | dev_err(&priv->pci_dev->dev, | |
450 | "Illegal SMBus block read size %d\n", | |
451 | priv->len); | |
452 | /* FIXME: Recover */ | |
453 | priv->len = I2C_SMBUS_BLOCK_MAX; | |
454 | } else { | |
455 | dev_dbg(&priv->pci_dev->dev, | |
456 | "SMBus block read size is %d\n", | |
457 | priv->len); | |
458 | } | |
459 | priv->data[-1] = priv->len; | |
460 | } | |
461 | ||
462 | /* Read next byte */ | |
463 | if (priv->count < priv->len) | |
464 | priv->data[priv->count++] = inb(SMBBLKDAT(priv)); | |
465 | else | |
466 | dev_dbg(&priv->pci_dev->dev, | |
467 | "Discarding extra byte on block read\n"); | |
468 | ||
469 | /* Set LAST_BYTE for last byte of read transaction */ | |
470 | if (priv->count == priv->len - 1) | |
471 | outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, | |
472 | SMBHSTCNT(priv)); | |
473 | } else if (priv->count < priv->len - 1) { | |
474 | /* Write next byte, except for IRQ after last byte */ | |
475 | outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); | |
476 | } | |
477 | ||
478 | /* Clear BYTE_DONE to continue with next byte */ | |
479 | outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); | |
480 | } | |
481 | ||
636752bc | 482 | /* |
d3ff6ce4 DK |
483 | * There are two kinds of interrupts: |
484 | * | |
485 | * 1) i801 signals transaction completion with one of these interrupts: | |
486 | * INTR - Success | |
487 | * DEV_ERR - Invalid command, NAK or communication timeout | |
488 | * BUS_ERR - SMI# transaction collision | |
489 | * FAILED - transaction was canceled due to a KILL request | |
490 | * When any of these occur, update ->status and wake up the waitq. | |
491 | * ->status must be cleared before kicking off the next transaction. | |
492 | * | |
493 | * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt | |
494 | * occurs for each byte of a byte-by-byte to prepare the next byte. | |
636752bc DK |
495 | */ |
496 | static irqreturn_t i801_isr(int irq, void *dev_id) | |
497 | { | |
498 | struct i801_priv *priv = dev_id; | |
499 | u16 pcists; | |
500 | u8 status; | |
501 | ||
502 | /* Confirm this is our interrupt */ | |
503 | pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); | |
504 | if (!(pcists & SMBPCISTS_INTS)) | |
505 | return IRQ_NONE; | |
506 | ||
507 | status = inb_p(SMBHSTSTS(priv)); | |
d3ff6ce4 DK |
508 | if (status & SMBHSTSTS_BYTE_DONE) |
509 | i801_isr_byte_done(priv); | |
510 | ||
636752bc DK |
511 | /* |
512 | * Clear irq sources and report transaction result. | |
513 | * ->status must be cleared before the next transaction is started. | |
514 | */ | |
515 | status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; | |
516 | if (status) { | |
517 | outb_p(status, SMBHSTSTS(priv)); | |
518 | priv->status |= status; | |
519 | wake_up(&priv->waitq); | |
520 | } | |
521 | ||
522 | return IRQ_HANDLED; | |
523 | } | |
524 | ||
efa3cb15 DK |
525 | /* |
526 | * For "byte-by-byte" block transactions: | |
527 | * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 | |
528 | * I2C read uses cmd=I801_I2C_BLOCK_DATA | |
529 | */ | |
0cd96eb0 DW |
530 | static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, |
531 | union i2c_smbus_data *data, | |
6342064c JD |
532 | char read_write, int command, |
533 | int hwpec) | |
1da177e4 LT |
534 | { |
535 | int i, len; | |
536 | int smbcmd; | |
2b73809d | 537 | int status; |
cf898dc5 | 538 | int result; |
b3b8df97 | 539 | const struct i2c_adapter *adap = &priv->adapter; |
cf898dc5 | 540 | |
0cd96eb0 | 541 | result = i801_check_pre(priv); |
cf898dc5 JD |
542 | if (result < 0) |
543 | return result; | |
1da177e4 | 544 | |
7edcb9ab | 545 | len = data->block[0]; |
1da177e4 LT |
546 | |
547 | if (read_write == I2C_SMBUS_WRITE) { | |
0cd96eb0 DW |
548 | outb_p(len, SMBHSTDAT0(priv)); |
549 | outb_p(data->block[1], SMBBLKDAT(priv)); | |
1da177e4 LT |
550 | } |
551 | ||
efa3cb15 DK |
552 | if (command == I2C_SMBUS_I2C_BLOCK_DATA && |
553 | read_write == I2C_SMBUS_READ) | |
554 | smbcmd = I801_I2C_BLOCK_DATA; | |
555 | else | |
556 | smbcmd = I801_BLOCK_DATA; | |
557 | ||
d3ff6ce4 DK |
558 | if (priv->features & FEATURE_IRQ) { |
559 | priv->is_read = (read_write == I2C_SMBUS_READ); | |
560 | if (len == 1 && priv->is_read) | |
561 | smbcmd |= SMBHSTCNT_LAST_BYTE; | |
562 | priv->cmd = smbcmd | SMBHSTCNT_INTREN; | |
563 | priv->len = len; | |
564 | priv->count = 0; | |
565 | priv->data = &data->block[1]; | |
566 | ||
567 | outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); | |
b3b8df97 JD |
568 | result = wait_event_timeout(priv->waitq, |
569 | (status = priv->status), | |
570 | adap->timeout); | |
571 | if (!result) { | |
572 | status = -ETIMEDOUT; | |
573 | dev_warn(&priv->pci_dev->dev, | |
574 | "Timeout waiting for interrupt!\n"); | |
575 | } | |
d3ff6ce4 DK |
576 | priv->status = 0; |
577 | return i801_check_post(priv, status); | |
578 | } | |
579 | ||
1da177e4 | 580 | for (i = 1; i <= len; i++) { |
efa3cb15 | 581 | if (i == len && read_write == I2C_SMBUS_READ) |
edbeea63 | 582 | smbcmd |= SMBHSTCNT_LAST_BYTE; |
37af8711 | 583 | outb_p(smbcmd, SMBHSTCNT(priv)); |
1da177e4 | 584 | |
1da177e4 | 585 | if (i == 1) |
edbeea63 | 586 | outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, |
0cd96eb0 | 587 | SMBHSTCNT(priv)); |
1da177e4 | 588 | |
6cad93c4 JD |
589 | status = i801_wait_byte_done(priv); |
590 | if (status) | |
591 | goto exit; | |
1da177e4 | 592 | |
6342064c JD |
593 | if (i == 1 && read_write == I2C_SMBUS_READ |
594 | && command != I2C_SMBUS_I2C_BLOCK_DATA) { | |
0cd96eb0 | 595 | len = inb_p(SMBHSTDAT0(priv)); |
cf898dc5 | 596 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { |
0cd96eb0 | 597 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
598 | "Illegal SMBus block read size %d\n", |
599 | len); | |
600 | /* Recover */ | |
0cd96eb0 DW |
601 | while (inb_p(SMBHSTSTS(priv)) & |
602 | SMBHSTSTS_HOST_BUSY) | |
603 | outb_p(SMBHSTSTS_BYTE_DONE, | |
604 | SMBHSTSTS(priv)); | |
605 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); | |
97140342 | 606 | return -EPROTO; |
cf898dc5 | 607 | } |
1da177e4 LT |
608 | data->block[0] = len; |
609 | } | |
610 | ||
611 | /* Retrieve/store value in SMBBLKDAT */ | |
612 | if (read_write == I2C_SMBUS_READ) | |
0cd96eb0 | 613 | data->block[i] = inb_p(SMBBLKDAT(priv)); |
1da177e4 | 614 | if (read_write == I2C_SMBUS_WRITE && i+1 <= len) |
0cd96eb0 | 615 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
1da177e4 | 616 | |
cf898dc5 | 617 | /* signals SMBBLKDAT ready */ |
6cad93c4 | 618 | outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); |
1da177e4 | 619 | } |
cf898dc5 | 620 | |
6cad93c4 JD |
621 | status = i801_wait_intr(priv); |
622 | exit: | |
623 | return i801_check_post(priv, status); | |
7edcb9ab | 624 | } |
1da177e4 | 625 | |
0cd96eb0 | 626 | static int i801_set_block_buffer_mode(struct i801_priv *priv) |
7edcb9ab | 627 | { |
0cd96eb0 DW |
628 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); |
629 | if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) | |
97140342 | 630 | return -EIO; |
7edcb9ab OR |
631 | return 0; |
632 | } | |
633 | ||
634 | /* Block transaction function */ | |
0cd96eb0 DW |
635 | static int i801_block_transaction(struct i801_priv *priv, |
636 | union i2c_smbus_data *data, char read_write, | |
7edcb9ab OR |
637 | int command, int hwpec) |
638 | { | |
639 | int result = 0; | |
640 | unsigned char hostc; | |
641 | ||
642 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
643 | if (read_write == I2C_SMBUS_WRITE) { | |
644 | /* set I2C_EN bit in configuration register */ | |
0cd96eb0 DW |
645 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); |
646 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, | |
7edcb9ab | 647 | hostc | SMBHSTCFG_I2C_EN); |
0cd96eb0 DW |
648 | } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { |
649 | dev_err(&priv->pci_dev->dev, | |
6342064c | 650 | "I2C block read is unsupported!\n"); |
97140342 | 651 | return -EOPNOTSUPP; |
7edcb9ab OR |
652 | } |
653 | } | |
654 | ||
6342064c JD |
655 | if (read_write == I2C_SMBUS_WRITE |
656 | || command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
7edcb9ab OR |
657 | if (data->block[0] < 1) |
658 | data->block[0] = 1; | |
659 | if (data->block[0] > I2C_SMBUS_BLOCK_MAX) | |
660 | data->block[0] = I2C_SMBUS_BLOCK_MAX; | |
661 | } else { | |
6342064c | 662 | data->block[0] = 32; /* max for SMBus block reads */ |
7edcb9ab OR |
663 | } |
664 | ||
c074c39d JD |
665 | /* Experience has shown that the block buffer can only be used for |
666 | SMBus (not I2C) block transactions, even though the datasheet | |
667 | doesn't mention this limitation. */ | |
0cd96eb0 | 668 | if ((priv->features & FEATURE_BLOCK_BUFFER) |
c074c39d | 669 | && command != I2C_SMBUS_I2C_BLOCK_DATA |
0cd96eb0 DW |
670 | && i801_set_block_buffer_mode(priv) == 0) |
671 | result = i801_block_transaction_by_block(priv, data, | |
672 | read_write, hwpec); | |
7edcb9ab | 673 | else |
0cd96eb0 DW |
674 | result = i801_block_transaction_byte_by_byte(priv, data, |
675 | read_write, | |
6342064c | 676 | command, hwpec); |
7edcb9ab | 677 | |
6342064c JD |
678 | if (command == I2C_SMBUS_I2C_BLOCK_DATA |
679 | && read_write == I2C_SMBUS_WRITE) { | |
1da177e4 | 680 | /* restore saved configuration register value */ |
0cd96eb0 | 681 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); |
1da177e4 LT |
682 | } |
683 | return result; | |
684 | } | |
685 | ||
97140342 | 686 | /* Return negative errno on error. */ |
3fb21c64 | 687 | static s32 i801_access(struct i2c_adapter *adap, u16 addr, |
1da177e4 | 688 | unsigned short flags, char read_write, u8 command, |
3fb21c64 | 689 | int size, union i2c_smbus_data *data) |
1da177e4 | 690 | { |
e8aac4a9 | 691 | int hwpec; |
1da177e4 LT |
692 | int block = 0; |
693 | int ret, xact = 0; | |
0cd96eb0 | 694 | struct i801_priv *priv = i2c_get_adapdata(adap); |
1da177e4 | 695 | |
0cd96eb0 | 696 | hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) |
e8aac4a9 JD |
697 | && size != I2C_SMBUS_QUICK |
698 | && size != I2C_SMBUS_I2C_BLOCK_DATA; | |
1da177e4 LT |
699 | |
700 | switch (size) { | |
701 | case I2C_SMBUS_QUICK: | |
702 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 703 | SMBHSTADD(priv)); |
1da177e4 LT |
704 | xact = I801_QUICK; |
705 | break; | |
706 | case I2C_SMBUS_BYTE: | |
707 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 708 | SMBHSTADD(priv)); |
1da177e4 | 709 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 710 | outb_p(command, SMBHSTCMD(priv)); |
1da177e4 LT |
711 | xact = I801_BYTE; |
712 | break; | |
713 | case I2C_SMBUS_BYTE_DATA: | |
714 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
715 | SMBHSTADD(priv)); |
716 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 717 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 718 | outb_p(data->byte, SMBHSTDAT0(priv)); |
1da177e4 LT |
719 | xact = I801_BYTE_DATA; |
720 | break; | |
721 | case I2C_SMBUS_WORD_DATA: | |
722 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
723 | SMBHSTADD(priv)); |
724 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 725 | if (read_write == I2C_SMBUS_WRITE) { |
0cd96eb0 DW |
726 | outb_p(data->word & 0xff, SMBHSTDAT0(priv)); |
727 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); | |
1da177e4 LT |
728 | } |
729 | xact = I801_WORD_DATA; | |
730 | break; | |
731 | case I2C_SMBUS_BLOCK_DATA: | |
1da177e4 | 732 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), |
0cd96eb0 DW |
733 | SMBHSTADD(priv)); |
734 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 LT |
735 | block = 1; |
736 | break; | |
6342064c JD |
737 | case I2C_SMBUS_I2C_BLOCK_DATA: |
738 | /* NB: page 240 of ICH5 datasheet shows that the R/#W | |
739 | * bit should be cleared here, even when reading */ | |
0cd96eb0 | 740 | outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); |
6342064c JD |
741 | if (read_write == I2C_SMBUS_READ) { |
742 | /* NB: page 240 of ICH5 datasheet also shows | |
743 | * that DATA1 is the cmd field when reading */ | |
0cd96eb0 | 744 | outb_p(command, SMBHSTDAT1(priv)); |
6342064c | 745 | } else |
0cd96eb0 | 746 | outb_p(command, SMBHSTCMD(priv)); |
6342064c JD |
747 | block = 1; |
748 | break; | |
1da177e4 | 749 | default: |
0cd96eb0 DW |
750 | dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", |
751 | size); | |
97140342 | 752 | return -EOPNOTSUPP; |
1da177e4 LT |
753 | } |
754 | ||
ca8b9e32 | 755 | if (hwpec) /* enable/disable hardware PEC */ |
0cd96eb0 | 756 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); |
ca8b9e32 | 757 | else |
0cd96eb0 DW |
758 | outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), |
759 | SMBAUXCTL(priv)); | |
e8aac4a9 | 760 | |
3fb21c64 | 761 | if (block) |
0cd96eb0 DW |
762 | ret = i801_block_transaction(priv, data, read_write, size, |
763 | hwpec); | |
7edcb9ab | 764 | else |
37af8711 | 765 | ret = i801_transaction(priv, xact); |
1da177e4 | 766 | |
c79cfbac | 767 | /* Some BIOSes don't like it when PEC is enabled at reboot or resume |
7edcb9ab OR |
768 | time, so we forcibly disable it after every transaction. Turn off |
769 | E32B for the same reason. */ | |
a0921b6c | 770 | if (hwpec || block) |
0cd96eb0 DW |
771 | outb_p(inb_p(SMBAUXCTL(priv)) & |
772 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
c79cfbac | 773 | |
3fb21c64 | 774 | if (block) |
1da177e4 | 775 | return ret; |
3fb21c64 | 776 | if (ret) |
97140342 | 777 | return ret; |
1da177e4 LT |
778 | if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) |
779 | return 0; | |
780 | ||
781 | switch (xact & 0x7f) { | |
782 | case I801_BYTE: /* Result put in SMBHSTDAT0 */ | |
783 | case I801_BYTE_DATA: | |
0cd96eb0 | 784 | data->byte = inb_p(SMBHSTDAT0(priv)); |
1da177e4 LT |
785 | break; |
786 | case I801_WORD_DATA: | |
0cd96eb0 DW |
787 | data->word = inb_p(SMBHSTDAT0(priv)) + |
788 | (inb_p(SMBHSTDAT1(priv)) << 8); | |
1da177e4 LT |
789 | break; |
790 | } | |
791 | return 0; | |
792 | } | |
793 | ||
794 | ||
795 | static u32 i801_func(struct i2c_adapter *adapter) | |
796 | { | |
0cd96eb0 DW |
797 | struct i801_priv *priv = i2c_get_adapdata(adapter); |
798 | ||
1da177e4 | 799 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | |
369f6f4a JD |
800 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | |
801 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | | |
0cd96eb0 DW |
802 | ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | |
803 | ((priv->features & FEATURE_I2C_BLOCK_READ) ? | |
6342064c | 804 | I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0); |
1da177e4 LT |
805 | } |
806 | ||
8f9082c5 | 807 | static const struct i2c_algorithm smbus_algorithm = { |
1da177e4 LT |
808 | .smbus_xfer = i801_access, |
809 | .functionality = i801_func, | |
810 | }; | |
811 | ||
392debf1 | 812 | static const struct pci_device_id i801_ids[] = { |
1da177e4 LT |
813 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, |
814 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, | |
815 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, | |
816 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, | |
817 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, | |
818 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, | |
819 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, | |
820 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, | |
821 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, | |
b0a70b57 | 822 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, |
8254fc4a | 823 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, |
adbc2a10 | 824 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, |
cb04e95b | 825 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, |
d28dc711 GJ |
826 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, |
827 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, | |
cb04e95b SH |
828 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, |
829 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, | |
e30d9859 | 830 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, |
55fee8d7 DW |
831 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, |
832 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, | |
833 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, | |
662cda8a | 834 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, |
6e2a851e | 835 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, |
062737fb | 836 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, |
4a8f1ddd | 837 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, |
c2db409c | 838 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, |
a3fc0ff0 JR |
839 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, |
840 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, | |
841 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, | |
842 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, | |
f39901c1 | 843 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, |
b299de83 | 844 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, |
afc65924 | 845 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, |
1b31e9b7 | 846 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, |
39e8e30e | 847 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, |
3e27a844 | 848 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, |
3eee1799 | 849 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) }, |
1da177e4 LT |
850 | { 0, } |
851 | }; | |
852 | ||
3fb21c64 | 853 | MODULE_DEVICE_TABLE(pci, i801_ids); |
1da177e4 | 854 | |
8eacfceb | 855 | #if defined CONFIG_X86 && defined CONFIG_DMI |
1561bfe5 JD |
856 | static unsigned char apanel_addr; |
857 | ||
858 | /* Scan the system ROM for the signature "FJKEYINF" */ | |
859 | static __init const void __iomem *bios_signature(const void __iomem *bios) | |
860 | { | |
861 | ssize_t offset; | |
862 | const unsigned char signature[] = "FJKEYINF"; | |
863 | ||
864 | for (offset = 0; offset < 0x10000; offset += 0x10) { | |
865 | if (check_signature(bios + offset, signature, | |
866 | sizeof(signature)-1)) | |
867 | return bios + offset; | |
868 | } | |
869 | return NULL; | |
870 | } | |
871 | ||
872 | static void __init input_apanel_init(void) | |
873 | { | |
874 | void __iomem *bios; | |
875 | const void __iomem *p; | |
876 | ||
877 | bios = ioremap(0xF0000, 0x10000); /* Can't fail */ | |
878 | p = bios_signature(bios); | |
879 | if (p) { | |
880 | /* just use the first address */ | |
881 | apanel_addr = readb(p + 8 + 3) >> 1; | |
882 | } | |
883 | iounmap(bios); | |
884 | } | |
1561bfe5 | 885 | |
fa5bfab7 HG |
886 | struct dmi_onboard_device_info { |
887 | const char *name; | |
888 | u8 type; | |
889 | unsigned short i2c_addr; | |
890 | const char *i2c_type; | |
891 | }; | |
892 | ||
0b255e92 | 893 | static const struct dmi_onboard_device_info dmi_devices[] = { |
fa5bfab7 HG |
894 | { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, |
895 | { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, | |
896 | { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, | |
897 | }; | |
898 | ||
0b255e92 BP |
899 | static void dmi_check_onboard_device(u8 type, const char *name, |
900 | struct i2c_adapter *adap) | |
fa5bfab7 HG |
901 | { |
902 | int i; | |
903 | struct i2c_board_info info; | |
904 | ||
905 | for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { | |
906 | /* & ~0x80, ignore enabled/disabled bit */ | |
907 | if ((type & ~0x80) != dmi_devices[i].type) | |
908 | continue; | |
faabd47f | 909 | if (strcasecmp(name, dmi_devices[i].name)) |
fa5bfab7 HG |
910 | continue; |
911 | ||
912 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
913 | info.addr = dmi_devices[i].i2c_addr; | |
914 | strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); | |
915 | i2c_new_device(adap, &info); | |
916 | break; | |
917 | } | |
918 | } | |
919 | ||
920 | /* We use our own function to check for onboard devices instead of | |
921 | dmi_find_device() as some buggy BIOS's have the devices we are interested | |
922 | in marked as disabled */ | |
0b255e92 | 923 | static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) |
fa5bfab7 HG |
924 | { |
925 | int i, count; | |
926 | ||
927 | if (dm->type != 10) | |
928 | return; | |
929 | ||
930 | count = (dm->length - sizeof(struct dmi_header)) / 2; | |
931 | for (i = 0; i < count; i++) { | |
932 | const u8 *d = (char *)(dm + 1) + (i * 2); | |
933 | const char *name = ((char *) dm) + dm->length; | |
934 | u8 type = d[0]; | |
935 | u8 s = d[1]; | |
936 | ||
937 | if (!s) | |
938 | continue; | |
939 | s--; | |
940 | while (s > 0 && name[0]) { | |
941 | name += strlen(name) + 1; | |
942 | s--; | |
943 | } | |
944 | if (name[0] == 0) /* Bogus string reference */ | |
945 | continue; | |
946 | ||
947 | dmi_check_onboard_device(type, name, adap); | |
948 | } | |
949 | } | |
fa5bfab7 | 950 | |
e7198fbf | 951 | /* Register optional slaves */ |
0b255e92 | 952 | static void i801_probe_optional_slaves(struct i801_priv *priv) |
e7198fbf JD |
953 | { |
954 | /* Only register slaves on main SMBus channel */ | |
955 | if (priv->features & FEATURE_IDF) | |
956 | return; | |
957 | ||
e7198fbf JD |
958 | if (apanel_addr) { |
959 | struct i2c_board_info info; | |
960 | ||
961 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
962 | info.addr = apanel_addr; | |
963 | strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); | |
964 | i2c_new_device(&priv->adapter, &info); | |
965 | } | |
8eacfceb | 966 | |
e7198fbf JD |
967 | if (dmi_name_in_vendors("FUJITSU")) |
968 | dmi_walk(dmi_check_onboard_devices, &priv->adapter); | |
e7198fbf | 969 | } |
8eacfceb JD |
970 | #else |
971 | static void __init input_apanel_init(void) {} | |
0b255e92 | 972 | static void i801_probe_optional_slaves(struct i801_priv *priv) {} |
8eacfceb | 973 | #endif /* CONFIG_X86 && CONFIG_DMI */ |
e7198fbf | 974 | |
79e3e5b8 JD |
975 | #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ |
976 | defined CONFIG_DMI | |
3ad7ea18 JD |
977 | static struct i801_mux_config i801_mux_config_asus_z8_d12 = { |
978 | .gpio_chip = "gpio_ich", | |
979 | .values = { 0x02, 0x03 }, | |
980 | .n_values = 2, | |
981 | .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, | |
982 | .gpios = { 52, 53 }, | |
983 | .n_gpios = 2, | |
984 | }; | |
985 | ||
986 | static struct i801_mux_config i801_mux_config_asus_z8_d18 = { | |
987 | .gpio_chip = "gpio_ich", | |
988 | .values = { 0x02, 0x03, 0x01 }, | |
989 | .n_values = 3, | |
990 | .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, | |
991 | .gpios = { 52, 53 }, | |
992 | .n_gpios = 2, | |
993 | }; | |
994 | ||
0b255e92 | 995 | static const struct dmi_system_id mux_dmi_table[] = { |
3ad7ea18 JD |
996 | { |
997 | .matches = { | |
998 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
999 | DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), | |
1000 | }, | |
1001 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1002 | }, | |
1003 | { | |
1004 | .matches = { | |
1005 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1006 | DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), | |
1007 | }, | |
1008 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1009 | }, | |
1010 | { | |
1011 | .matches = { | |
1012 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1013 | DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), | |
1014 | }, | |
1015 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1016 | }, | |
1017 | { | |
1018 | .matches = { | |
1019 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1020 | DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), | |
1021 | }, | |
1022 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1023 | }, | |
1024 | { | |
1025 | .matches = { | |
1026 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1027 | DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), | |
1028 | }, | |
1029 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1030 | }, | |
1031 | { | |
1032 | .matches = { | |
1033 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1034 | DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), | |
1035 | }, | |
1036 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1037 | }, | |
1038 | { | |
1039 | .matches = { | |
1040 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1041 | DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), | |
1042 | }, | |
1043 | .driver_data = &i801_mux_config_asus_z8_d18, | |
1044 | }, | |
1045 | { | |
1046 | .matches = { | |
1047 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1048 | DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), | |
1049 | }, | |
1050 | .driver_data = &i801_mux_config_asus_z8_d18, | |
1051 | }, | |
1052 | { | |
1053 | .matches = { | |
1054 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1055 | DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), | |
1056 | }, | |
1057 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1058 | }, | |
1059 | { } | |
1060 | }; | |
1061 | ||
3ad7ea18 | 1062 | /* Setup multiplexing if needed */ |
0b255e92 | 1063 | static int i801_add_mux(struct i801_priv *priv) |
3ad7ea18 JD |
1064 | { |
1065 | struct device *dev = &priv->adapter.dev; | |
1066 | const struct i801_mux_config *mux_config; | |
3ad7ea18 | 1067 | struct i2c_mux_gpio_platform_data gpio_data; |
f82b8626 | 1068 | int err; |
3ad7ea18 JD |
1069 | |
1070 | if (!priv->mux_drvdata) | |
1071 | return 0; | |
1072 | mux_config = priv->mux_drvdata; | |
1073 | ||
3ad7ea18 JD |
1074 | /* Prepare the platform data */ |
1075 | memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); | |
1076 | gpio_data.parent = priv->adapter.nr; | |
1077 | gpio_data.values = mux_config->values; | |
1078 | gpio_data.n_values = mux_config->n_values; | |
1079 | gpio_data.classes = mux_config->classes; | |
f82b8626 JD |
1080 | gpio_data.gpio_chip = mux_config->gpio_chip; |
1081 | gpio_data.gpios = mux_config->gpios; | |
3ad7ea18 JD |
1082 | gpio_data.n_gpios = mux_config->n_gpios; |
1083 | gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; | |
1084 | ||
1085 | /* Register the mux device */ | |
1086 | priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", | |
f82b8626 | 1087 | PLATFORM_DEVID_AUTO, &gpio_data, |
3ad7ea18 JD |
1088 | sizeof(struct i2c_mux_gpio_platform_data)); |
1089 | if (IS_ERR(priv->mux_pdev)) { | |
1090 | err = PTR_ERR(priv->mux_pdev); | |
1091 | priv->mux_pdev = NULL; | |
1092 | dev_err(dev, "Failed to register i2c-mux-gpio device\n"); | |
1093 | return err; | |
1094 | } | |
1095 | ||
1096 | return 0; | |
1097 | } | |
1098 | ||
0b255e92 | 1099 | static void i801_del_mux(struct i801_priv *priv) |
3ad7ea18 JD |
1100 | { |
1101 | if (priv->mux_pdev) | |
1102 | platform_device_unregister(priv->mux_pdev); | |
1103 | } | |
1104 | ||
0b255e92 | 1105 | static unsigned int i801_get_adapter_class(struct i801_priv *priv) |
3ad7ea18 JD |
1106 | { |
1107 | const struct dmi_system_id *id; | |
1108 | const struct i801_mux_config *mux_config; | |
1109 | unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
1110 | int i; | |
1111 | ||
1112 | id = dmi_first_match(mux_dmi_table); | |
1113 | if (id) { | |
28901f57 | 1114 | /* Remove branch classes from trunk */ |
3ad7ea18 JD |
1115 | mux_config = id->driver_data; |
1116 | for (i = 0; i < mux_config->n_values; i++) | |
1117 | class &= ~mux_config->classes[i]; | |
1118 | ||
1119 | /* Remember for later */ | |
1120 | priv->mux_drvdata = mux_config; | |
1121 | } | |
1122 | ||
1123 | return class; | |
1124 | } | |
1125 | #else | |
1126 | static inline int i801_add_mux(struct i801_priv *priv) { return 0; } | |
1127 | static inline void i801_del_mux(struct i801_priv *priv) { } | |
1128 | ||
1129 | static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) | |
1130 | { | |
1131 | return I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
1132 | } | |
1133 | #endif | |
1134 | ||
0b255e92 | 1135 | static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) |
1da177e4 | 1136 | { |
02dd7ae2 | 1137 | unsigned char temp; |
adff687d | 1138 | int err, i; |
0cd96eb0 DW |
1139 | struct i801_priv *priv; |
1140 | ||
1621c59d | 1141 | priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); |
0cd96eb0 DW |
1142 | if (!priv) |
1143 | return -ENOMEM; | |
1144 | ||
1145 | i2c_set_adapdata(&priv->adapter, priv); | |
1146 | priv->adapter.owner = THIS_MODULE; | |
3ad7ea18 | 1147 | priv->adapter.class = i801_get_adapter_class(priv); |
0cd96eb0 | 1148 | priv->adapter.algo = &smbus_algorithm; |
1da177e4 | 1149 | |
0cd96eb0 | 1150 | priv->pci_dev = dev; |
250d1bd3 | 1151 | switch (dev->device) { |
e7198fbf JD |
1152 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: |
1153 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: | |
1154 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: | |
a3fc0ff0 JR |
1155 | case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: |
1156 | case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: | |
1157 | case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: | |
e7198fbf JD |
1158 | priv->features |= FEATURE_IDF; |
1159 | /* fall through */ | |
e0e8398c | 1160 | default: |
0cd96eb0 | 1161 | priv->features |= FEATURE_I2C_BLOCK_READ; |
6676a847 | 1162 | priv->features |= FEATURE_IRQ; |
6342064c JD |
1163 | /* fall through */ |
1164 | case PCI_DEVICE_ID_INTEL_82801DB_3: | |
0cd96eb0 DW |
1165 | priv->features |= FEATURE_SMBUS_PEC; |
1166 | priv->features |= FEATURE_BLOCK_BUFFER; | |
e0e8398c JD |
1167 | /* fall through */ |
1168 | case PCI_DEVICE_ID_INTEL_82801CA_3: | |
1169 | case PCI_DEVICE_ID_INTEL_82801BA_2: | |
1170 | case PCI_DEVICE_ID_INTEL_82801AB_3: | |
1171 | case PCI_DEVICE_ID_INTEL_82801AA_3: | |
250d1bd3 | 1172 | break; |
250d1bd3 | 1173 | } |
02dd7ae2 | 1174 | |
adff687d JD |
1175 | /* Disable features on user request */ |
1176 | for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { | |
0cd96eb0 | 1177 | if (priv->features & disable_features & (1 << i)) |
adff687d JD |
1178 | dev_notice(&dev->dev, "%s disabled by user\n", |
1179 | i801_feature_names[i]); | |
1180 | } | |
0cd96eb0 | 1181 | priv->features &= ~disable_features; |
adff687d | 1182 | |
fef220da | 1183 | err = pcim_enable_device(dev); |
02dd7ae2 JD |
1184 | if (err) { |
1185 | dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", | |
1186 | err); | |
fef220da | 1187 | return err; |
02dd7ae2 | 1188 | } |
fef220da | 1189 | pcim_pin_device(dev); |
02dd7ae2 JD |
1190 | |
1191 | /* Determine the address of the SMBus area */ | |
0cd96eb0 DW |
1192 | priv->smba = pci_resource_start(dev, SMBBAR); |
1193 | if (!priv->smba) { | |
9cbbf3dc JN |
1194 | dev_err(&dev->dev, |
1195 | "SMBus base address uninitialized, upgrade BIOS\n"); | |
fef220da | 1196 | return -ENODEV; |
02dd7ae2 JD |
1197 | } |
1198 | ||
54fb4a05 | 1199 | err = acpi_check_resource_conflict(&dev->resource[SMBBAR]); |
18669eab | 1200 | if (err) { |
fef220da | 1201 | return -ENODEV; |
18669eab | 1202 | } |
54fb4a05 | 1203 | |
fef220da JN |
1204 | err = pcim_iomap_regions(dev, 1 << SMBBAR, |
1205 | dev_driver_string(&dev->dev)); | |
02dd7ae2 | 1206 | if (err) { |
9cbbf3dc JN |
1207 | dev_err(&dev->dev, |
1208 | "Failed to request SMBus region 0x%lx-0x%Lx\n", | |
1209 | priv->smba, | |
598736c5 | 1210 | (unsigned long long)pci_resource_end(dev, SMBBAR)); |
fef220da | 1211 | return err; |
02dd7ae2 JD |
1212 | } |
1213 | ||
0cd96eb0 DW |
1214 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); |
1215 | priv->original_hstcfg = temp; | |
02dd7ae2 JD |
1216 | temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ |
1217 | if (!(temp & SMBHSTCFG_HST_EN)) { | |
1218 | dev_info(&dev->dev, "Enabling SMBus device\n"); | |
1219 | temp |= SMBHSTCFG_HST_EN; | |
1220 | } | |
0cd96eb0 | 1221 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); |
02dd7ae2 | 1222 | |
636752bc | 1223 | if (temp & SMBHSTCFG_SMB_SMI_EN) { |
02dd7ae2 | 1224 | dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); |
636752bc DK |
1225 | /* Disable SMBus interrupt feature if SMBus using SMI# */ |
1226 | priv->features &= ~FEATURE_IRQ; | |
636752bc | 1227 | } |
1da177e4 | 1228 | |
a0921b6c | 1229 | /* Clear special mode bits */ |
0cd96eb0 DW |
1230 | if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) |
1231 | outb_p(inb_p(SMBAUXCTL(priv)) & | |
1232 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
a0921b6c | 1233 | |
b3b8df97 JD |
1234 | /* Default timeout in interrupt mode: 200 ms */ |
1235 | priv->adapter.timeout = HZ / 5; | |
1236 | ||
aeb8a3d1 JD |
1237 | if (priv->features & FEATURE_IRQ) { |
1238 | u16 pcictl, pcists; | |
1239 | ||
1240 | /* Complain if an interrupt is already pending */ | |
1241 | pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); | |
1242 | if (pcists & SMBPCISTS_INTS) | |
1243 | dev_warn(&dev->dev, "An interrupt is pending!\n"); | |
1244 | ||
1245 | /* Check if interrupts have been disabled */ | |
1246 | pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl); | |
1247 | if (pcictl & SMBPCICTL_INTDIS) { | |
1248 | dev_info(&dev->dev, "Interrupts are disabled\n"); | |
1249 | priv->features &= ~FEATURE_IRQ; | |
1250 | } | |
1251 | } | |
1252 | ||
636752bc DK |
1253 | if (priv->features & FEATURE_IRQ) { |
1254 | init_waitqueue_head(&priv->waitq); | |
1255 | ||
1621c59d JN |
1256 | err = devm_request_irq(&dev->dev, dev->irq, i801_isr, |
1257 | IRQF_SHARED, | |
1258 | dev_driver_string(&dev->dev), priv); | |
636752bc DK |
1259 | if (err) { |
1260 | dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", | |
1261 | dev->irq, err); | |
ae944717 | 1262 | priv->features &= ~FEATURE_IRQ; |
636752bc DK |
1263 | } |
1264 | } | |
ae944717 JD |
1265 | dev_info(&dev->dev, "SMBus using %s\n", |
1266 | priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); | |
636752bc | 1267 | |
405ae7d3 | 1268 | /* set up the sysfs linkage to our parent device */ |
0cd96eb0 | 1269 | priv->adapter.dev.parent = &dev->dev; |
1da177e4 | 1270 | |
7e2193a8 | 1271 | /* Retry up to 3 times on lost arbitration */ |
0cd96eb0 | 1272 | priv->adapter.retries = 3; |
7e2193a8 | 1273 | |
0cd96eb0 DW |
1274 | snprintf(priv->adapter.name, sizeof(priv->adapter.name), |
1275 | "SMBus I801 adapter at %04lx", priv->smba); | |
1276 | err = i2c_add_adapter(&priv->adapter); | |
02dd7ae2 JD |
1277 | if (err) { |
1278 | dev_err(&dev->dev, "Failed to add SMBus adapter\n"); | |
fef220da | 1279 | return err; |
02dd7ae2 | 1280 | } |
1561bfe5 | 1281 | |
e7198fbf | 1282 | i801_probe_optional_slaves(priv); |
3ad7ea18 JD |
1283 | /* We ignore errors - multiplexing is optional */ |
1284 | i801_add_mux(priv); | |
1561bfe5 | 1285 | |
0cd96eb0 | 1286 | pci_set_drvdata(dev, priv); |
636752bc | 1287 | |
d6fcb3b9 | 1288 | return 0; |
1da177e4 LT |
1289 | } |
1290 | ||
0b255e92 | 1291 | static void i801_remove(struct pci_dev *dev) |
1da177e4 | 1292 | { |
0cd96eb0 DW |
1293 | struct i801_priv *priv = pci_get_drvdata(dev); |
1294 | ||
3ad7ea18 | 1295 | i801_del_mux(priv); |
0cd96eb0 DW |
1296 | i2c_del_adapter(&priv->adapter); |
1297 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); | |
636752bc | 1298 | |
d6fcb3b9 DR |
1299 | /* |
1300 | * do not call pci_disable_device(dev) since it can cause hard hangs on | |
1301 | * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) | |
1302 | */ | |
1da177e4 LT |
1303 | } |
1304 | ||
a5aaea37 JD |
1305 | #ifdef CONFIG_PM |
1306 | static int i801_suspend(struct pci_dev *dev, pm_message_t mesg) | |
1307 | { | |
0cd96eb0 DW |
1308 | struct i801_priv *priv = pci_get_drvdata(dev); |
1309 | ||
a5aaea37 | 1310 | pci_save_state(dev); |
0cd96eb0 | 1311 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); |
a5aaea37 JD |
1312 | pci_set_power_state(dev, pci_choose_state(dev, mesg)); |
1313 | return 0; | |
1314 | } | |
1315 | ||
1316 | static int i801_resume(struct pci_dev *dev) | |
1317 | { | |
1318 | pci_set_power_state(dev, PCI_D0); | |
1319 | pci_restore_state(dev); | |
f85da3f5 | 1320 | return 0; |
a5aaea37 JD |
1321 | } |
1322 | #else | |
1323 | #define i801_suspend NULL | |
1324 | #define i801_resume NULL | |
1325 | #endif | |
1326 | ||
1da177e4 LT |
1327 | static struct pci_driver i801_driver = { |
1328 | .name = "i801_smbus", | |
1329 | .id_table = i801_ids, | |
1330 | .probe = i801_probe, | |
0b255e92 | 1331 | .remove = i801_remove, |
a5aaea37 JD |
1332 | .suspend = i801_suspend, |
1333 | .resume = i801_resume, | |
1da177e4 LT |
1334 | }; |
1335 | ||
1336 | static int __init i2c_i801_init(void) | |
1337 | { | |
6aa1464d JD |
1338 | if (dmi_name_in_vendors("FUJITSU")) |
1339 | input_apanel_init(); | |
1da177e4 LT |
1340 | return pci_register_driver(&i801_driver); |
1341 | } | |
1342 | ||
1343 | static void __exit i2c_i801_exit(void) | |
1344 | { | |
1345 | pci_unregister_driver(&i801_driver); | |
1346 | } | |
1347 | ||
7c81c60f | 1348 | MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>"); |
1da177e4 LT |
1349 | MODULE_DESCRIPTION("I801 SMBus driver"); |
1350 | MODULE_LICENSE("GPL"); | |
1351 | ||
1352 | module_init(i2c_i801_init); | |
1353 | module_exit(i2c_i801_exit); |