Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, |
3 | Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker | |
4 | <mdsxyz123@yahoo.com> | |
cf898dc5 | 5 | Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org> |
1da177e4 LT |
6 | |
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | */ | |
21 | ||
22 | /* | |
ae7b0497 JD |
23 | Supports the following Intel I/O Controller Hubs (ICH): |
24 | ||
25 | I/O Block I2C | |
26 | region SMBus Block proc. block | |
27 | Chip name PCI ID size PEC buffer call read | |
28 | ---------------------------------------------------------------------- | |
29 | 82801AA (ICH) 0x2413 16 no no no no | |
30 | 82801AB (ICH0) 0x2423 16 no no no no | |
31 | 82801BA (ICH2) 0x2443 16 no no no no | |
32 | 82801CA (ICH3) 0x2483 32 soft no no no | |
33 | 82801DB (ICH4) 0x24c3 32 hard yes no no | |
34 | 82801E (ICH5) 0x24d3 32 hard yes yes yes | |
35 | 6300ESB 0x25a4 32 hard yes yes yes | |
36 | 82801F (ICH6) 0x266a 32 hard yes yes yes | |
37 | 6310ESB/6320ESB 0x269b 32 hard yes yes yes | |
38 | 82801G (ICH7) 0x27da 32 hard yes yes yes | |
39 | 82801H (ICH8) 0x283e 32 hard yes yes yes | |
40 | 82801I (ICH9) 0x2930 32 hard yes yes yes | |
d28dc711 GJ |
41 | Tolapai 0x5032 32 hard yes yes yes |
42 | ICH10 0x3a30 32 hard yes yes yes | |
43 | ICH10 0x3a60 32 hard yes yes yes | |
ae7b0497 JD |
44 | |
45 | Features supported by this driver: | |
46 | Software PEC no | |
47 | Hardware PEC yes | |
48 | Block buffer yes | |
49 | Block process call transaction no | |
6342064c | 50 | I2C block read transaction yes (doesn't use the block buffer) |
ae7b0497 JD |
51 | |
52 | See the file Documentation/i2c/busses/i2c-i801 for details. | |
1da177e4 LT |
53 | */ |
54 | ||
55 | /* Note: we assume there can only be one I801, with one SMBus interface */ | |
56 | ||
1da177e4 LT |
57 | #include <linux/module.h> |
58 | #include <linux/pci.h> | |
59 | #include <linux/kernel.h> | |
60 | #include <linux/stddef.h> | |
61 | #include <linux/delay.h> | |
1da177e4 LT |
62 | #include <linux/ioport.h> |
63 | #include <linux/init.h> | |
64 | #include <linux/i2c.h> | |
54fb4a05 | 65 | #include <linux/acpi.h> |
1da177e4 LT |
66 | #include <asm/io.h> |
67 | ||
1da177e4 LT |
68 | /* I801 SMBus address offsets */ |
69 | #define SMBHSTSTS (0 + i801_smba) | |
70 | #define SMBHSTCNT (2 + i801_smba) | |
71 | #define SMBHSTCMD (3 + i801_smba) | |
72 | #define SMBHSTADD (4 + i801_smba) | |
73 | #define SMBHSTDAT0 (5 + i801_smba) | |
74 | #define SMBHSTDAT1 (6 + i801_smba) | |
75 | #define SMBBLKDAT (7 + i801_smba) | |
ae7b0497 JD |
76 | #define SMBPEC (8 + i801_smba) /* ICH3 and later */ |
77 | #define SMBAUXSTS (12 + i801_smba) /* ICH4 and later */ | |
78 | #define SMBAUXCTL (13 + i801_smba) /* ICH4 and later */ | |
1da177e4 LT |
79 | |
80 | /* PCI Address Constants */ | |
6dcc19df | 81 | #define SMBBAR 4 |
1da177e4 | 82 | #define SMBHSTCFG 0x040 |
1da177e4 LT |
83 | |
84 | /* Host configuration bits for SMBHSTCFG */ | |
85 | #define SMBHSTCFG_HST_EN 1 | |
86 | #define SMBHSTCFG_SMB_SMI_EN 2 | |
87 | #define SMBHSTCFG_I2C_EN 4 | |
88 | ||
ca8b9e32 OR |
89 | /* Auxillary control register bits, ICH4+ only */ |
90 | #define SMBAUXCTL_CRC 1 | |
91 | #define SMBAUXCTL_E32B 2 | |
92 | ||
93 | /* kill bit for SMBHSTCNT */ | |
94 | #define SMBHSTCNT_KILL 2 | |
95 | ||
1da177e4 LT |
96 | /* Other settings */ |
97 | #define MAX_TIMEOUT 100 | |
98 | #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */ | |
99 | ||
100 | /* I801 command constants */ | |
101 | #define I801_QUICK 0x00 | |
102 | #define I801_BYTE 0x04 | |
103 | #define I801_BYTE_DATA 0x08 | |
104 | #define I801_WORD_DATA 0x0C | |
ae7b0497 | 105 | #define I801_PROC_CALL 0x10 /* unimplemented */ |
1da177e4 | 106 | #define I801_BLOCK_DATA 0x14 |
6342064c | 107 | #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ |
1da177e4 | 108 | #define I801_BLOCK_LAST 0x34 |
6342064c | 109 | #define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */ |
1da177e4 | 110 | #define I801_START 0x40 |
ae7b0497 | 111 | #define I801_PEC_EN 0x80 /* ICH3 and later */ |
1da177e4 | 112 | |
ca8b9e32 OR |
113 | /* I801 Hosts Status register bits */ |
114 | #define SMBHSTSTS_BYTE_DONE 0x80 | |
115 | #define SMBHSTSTS_INUSE_STS 0x40 | |
116 | #define SMBHSTSTS_SMBALERT_STS 0x20 | |
117 | #define SMBHSTSTS_FAILED 0x10 | |
118 | #define SMBHSTSTS_BUS_ERR 0x08 | |
119 | #define SMBHSTSTS_DEV_ERR 0x04 | |
120 | #define SMBHSTSTS_INTR 0x02 | |
121 | #define SMBHSTSTS_HOST_BUSY 0x01 | |
1da177e4 | 122 | |
cf898dc5 JD |
123 | #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \ |
124 | SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \ | |
125 | SMBHSTSTS_INTR) | |
126 | ||
6dcc19df | 127 | static unsigned long i801_smba; |
a5aaea37 | 128 | static unsigned char i801_original_hstcfg; |
d6072f84 | 129 | static struct pci_driver i801_driver; |
1da177e4 | 130 | static struct pci_dev *I801_dev; |
369f6f4a JD |
131 | |
132 | #define FEATURE_SMBUS_PEC (1 << 0) | |
133 | #define FEATURE_BLOCK_BUFFER (1 << 1) | |
134 | #define FEATURE_BLOCK_PROC (1 << 2) | |
135 | #define FEATURE_I2C_BLOCK_READ (1 << 3) | |
136 | static unsigned int i801_features; | |
1da177e4 | 137 | |
cf898dc5 JD |
138 | /* Make sure the SMBus host is ready to start transmitting. |
139 | Return 0 if it is, -EBUSY if it is not. */ | |
140 | static int i801_check_pre(void) | |
1da177e4 | 141 | { |
2b73809d | 142 | int status; |
1da177e4 | 143 | |
cf898dc5 JD |
144 | status = inb_p(SMBHSTSTS); |
145 | if (status & SMBHSTSTS_HOST_BUSY) { | |
146 | dev_err(&I801_dev->dev, "SMBus is busy, can't use it!\n"); | |
147 | return -EBUSY; | |
148 | } | |
149 | ||
150 | status &= STATUS_FLAGS; | |
151 | if (status) { | |
152 | dev_dbg(&I801_dev->dev, "Clearing status flags (%02x)\n", | |
2b73809d JD |
153 | status); |
154 | outb_p(status, SMBHSTSTS); | |
cf898dc5 JD |
155 | status = inb_p(SMBHSTSTS) & STATUS_FLAGS; |
156 | if (status) { | |
157 | dev_err(&I801_dev->dev, | |
158 | "Failed clearing status flags (%02x)\n", | |
159 | status); | |
97140342 | 160 | return -EBUSY; |
1da177e4 LT |
161 | } |
162 | } | |
163 | ||
cf898dc5 JD |
164 | return 0; |
165 | } | |
1da177e4 | 166 | |
cf898dc5 JD |
167 | /* Convert the status register to an error code, and clear it. */ |
168 | static int i801_check_post(int status, int timeout) | |
169 | { | |
170 | int result = 0; | |
1da177e4 LT |
171 | |
172 | /* If the SMBus is still busy, we give up */ | |
cf898dc5 JD |
173 | if (timeout) { |
174 | dev_err(&I801_dev->dev, "Transaction timeout\n"); | |
ca8b9e32 OR |
175 | /* try to stop the current command */ |
176 | dev_dbg(&I801_dev->dev, "Terminating the current operation\n"); | |
177 | outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT); | |
178 | msleep(1); | |
179 | outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT); | |
cf898dc5 JD |
180 | |
181 | /* Check if it worked */ | |
182 | status = inb_p(SMBHSTSTS); | |
183 | if ((status & SMBHSTSTS_HOST_BUSY) || | |
184 | !(status & SMBHSTSTS_FAILED)) | |
185 | dev_err(&I801_dev->dev, | |
186 | "Failed terminating the transaction\n"); | |
187 | outb_p(STATUS_FLAGS, SMBHSTSTS); | |
188 | return -ETIMEDOUT; | |
1da177e4 LT |
189 | } |
190 | ||
2b73809d | 191 | if (status & SMBHSTSTS_FAILED) { |
97140342 | 192 | result = -EIO; |
cf898dc5 JD |
193 | dev_err(&I801_dev->dev, "Transaction failed\n"); |
194 | } | |
195 | if (status & SMBHSTSTS_DEV_ERR) { | |
196 | result = -ENXIO; | |
197 | dev_dbg(&I801_dev->dev, "No response\n"); | |
1da177e4 | 198 | } |
2b73809d | 199 | if (status & SMBHSTSTS_BUS_ERR) { |
dcb5c923 JD |
200 | result = -EAGAIN; |
201 | dev_dbg(&I801_dev->dev, "Lost arbitration\n"); | |
1da177e4 LT |
202 | } |
203 | ||
cf898dc5 JD |
204 | if (result) { |
205 | /* Clear error flags */ | |
206 | outb_p(status & STATUS_FLAGS, SMBHSTSTS); | |
207 | status = inb_p(SMBHSTSTS) & STATUS_FLAGS; | |
208 | if (status) { | |
209 | dev_warn(&I801_dev->dev, "Failed clearing status " | |
210 | "flags at end of transaction (%02x)\n", | |
211 | status); | |
212 | } | |
1da177e4 LT |
213 | } |
214 | ||
1da177e4 LT |
215 | return result; |
216 | } | |
217 | ||
cf898dc5 JD |
218 | static int i801_transaction(int xact) |
219 | { | |
220 | int status; | |
221 | int result; | |
222 | int timeout = 0; | |
223 | ||
224 | result = i801_check_pre(); | |
225 | if (result < 0) | |
226 | return result; | |
227 | ||
228 | /* the current contents of SMBHSTCNT can be overwritten, since PEC, | |
229 | * INTREN, SMBSCMD are passed in xact */ | |
230 | outb_p(xact | I801_START, SMBHSTCNT); | |
231 | ||
232 | /* We will always wait for a fraction of a second! */ | |
233 | do { | |
234 | msleep(1); | |
235 | status = inb_p(SMBHSTSTS); | |
236 | } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT)); | |
237 | ||
238 | result = i801_check_post(status, timeout >= MAX_TIMEOUT); | |
239 | if (result < 0) | |
240 | return result; | |
241 | ||
242 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS); | |
243 | return 0; | |
244 | } | |
245 | ||
ca8b9e32 OR |
246 | /* wait for INTR bit as advised by Intel */ |
247 | static void i801_wait_hwpec(void) | |
248 | { | |
249 | int timeout = 0; | |
2b73809d | 250 | int status; |
ca8b9e32 OR |
251 | |
252 | do { | |
253 | msleep(1); | |
2b73809d JD |
254 | status = inb_p(SMBHSTSTS); |
255 | } while ((!(status & SMBHSTSTS_INTR)) | |
ca8b9e32 OR |
256 | && (timeout++ < MAX_TIMEOUT)); |
257 | ||
258 | if (timeout >= MAX_TIMEOUT) { | |
259 | dev_dbg(&I801_dev->dev, "PEC Timeout!\n"); | |
260 | } | |
2b73809d | 261 | outb_p(status, SMBHSTSTS); |
ca8b9e32 OR |
262 | } |
263 | ||
7edcb9ab OR |
264 | static int i801_block_transaction_by_block(union i2c_smbus_data *data, |
265 | char read_write, int hwpec) | |
266 | { | |
267 | int i, len; | |
97140342 | 268 | int status; |
7edcb9ab OR |
269 | |
270 | inb_p(SMBHSTCNT); /* reset the data buffer index */ | |
271 | ||
272 | /* Use 32-byte buffer to process this transaction */ | |
273 | if (read_write == I2C_SMBUS_WRITE) { | |
274 | len = data->block[0]; | |
275 | outb_p(len, SMBHSTDAT0); | |
276 | for (i = 0; i < len; i++) | |
277 | outb_p(data->block[i+1], SMBBLKDAT); | |
278 | } | |
279 | ||
97140342 DB |
280 | status = i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 | |
281 | I801_PEC_EN * hwpec); | |
282 | if (status) | |
283 | return status; | |
7edcb9ab OR |
284 | |
285 | if (read_write == I2C_SMBUS_READ) { | |
286 | len = inb_p(SMBHSTDAT0); | |
287 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) | |
97140342 | 288 | return -EPROTO; |
7edcb9ab OR |
289 | |
290 | data->block[0] = len; | |
291 | for (i = 0; i < len; i++) | |
292 | data->block[i + 1] = inb_p(SMBBLKDAT); | |
293 | } | |
294 | return 0; | |
295 | } | |
296 | ||
297 | static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data, | |
6342064c JD |
298 | char read_write, int command, |
299 | int hwpec) | |
1da177e4 LT |
300 | { |
301 | int i, len; | |
302 | int smbcmd; | |
2b73809d | 303 | int status; |
cf898dc5 | 304 | int result; |
1da177e4 | 305 | int timeout; |
cf898dc5 JD |
306 | |
307 | result = i801_check_pre(); | |
308 | if (result < 0) | |
309 | return result; | |
1da177e4 | 310 | |
7edcb9ab | 311 | len = data->block[0]; |
1da177e4 LT |
312 | |
313 | if (read_write == I2C_SMBUS_WRITE) { | |
1da177e4 LT |
314 | outb_p(len, SMBHSTDAT0); |
315 | outb_p(data->block[1], SMBBLKDAT); | |
1da177e4 LT |
316 | } |
317 | ||
318 | for (i = 1; i <= len; i++) { | |
6342064c JD |
319 | if (i == len && read_write == I2C_SMBUS_READ) { |
320 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) | |
321 | smbcmd = I801_I2C_BLOCK_LAST; | |
322 | else | |
323 | smbcmd = I801_BLOCK_LAST; | |
324 | } else { | |
325 | if (command == I2C_SMBUS_I2C_BLOCK_DATA | |
326 | && read_write == I2C_SMBUS_READ) | |
327 | smbcmd = I801_I2C_BLOCK_DATA; | |
328 | else | |
329 | smbcmd = I801_BLOCK_DATA; | |
330 | } | |
1da177e4 LT |
331 | outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT); |
332 | ||
1da177e4 LT |
333 | if (i == 1) |
334 | outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT); | |
335 | ||
336 | /* We will always wait for a fraction of a second! */ | |
337 | timeout = 0; | |
338 | do { | |
1da177e4 | 339 | msleep(1); |
2b73809d | 340 | status = inb_p(SMBHSTSTS); |
1da177e4 | 341 | } |
2b73809d | 342 | while ((!(status & SMBHSTSTS_BYTE_DONE)) |
ca8b9e32 | 343 | && (timeout++ < MAX_TIMEOUT)); |
1da177e4 | 344 | |
cf898dc5 JD |
345 | result = i801_check_post(status, timeout >= MAX_TIMEOUT); |
346 | if (result < 0) | |
347 | return result; | |
1da177e4 | 348 | |
6342064c JD |
349 | if (i == 1 && read_write == I2C_SMBUS_READ |
350 | && command != I2C_SMBUS_I2C_BLOCK_DATA) { | |
1da177e4 | 351 | len = inb_p(SMBHSTDAT0); |
cf898dc5 JD |
352 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { |
353 | dev_err(&I801_dev->dev, | |
354 | "Illegal SMBus block read size %d\n", | |
355 | len); | |
356 | /* Recover */ | |
357 | while (inb_p(SMBHSTSTS) & SMBHSTSTS_HOST_BUSY) | |
358 | outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS); | |
359 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS); | |
97140342 | 360 | return -EPROTO; |
cf898dc5 | 361 | } |
1da177e4 LT |
362 | data->block[0] = len; |
363 | } | |
364 | ||
365 | /* Retrieve/store value in SMBBLKDAT */ | |
366 | if (read_write == I2C_SMBUS_READ) | |
367 | data->block[i] = inb_p(SMBBLKDAT); | |
368 | if (read_write == I2C_SMBUS_WRITE && i+1 <= len) | |
369 | outb_p(data->block[i+1], SMBBLKDAT); | |
1da177e4 | 370 | |
cf898dc5 JD |
371 | /* signals SMBBLKDAT ready */ |
372 | outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS); | |
1da177e4 | 373 | } |
cf898dc5 JD |
374 | |
375 | return 0; | |
7edcb9ab | 376 | } |
1da177e4 | 377 | |
7edcb9ab OR |
378 | static int i801_set_block_buffer_mode(void) |
379 | { | |
380 | outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL); | |
381 | if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0) | |
97140342 | 382 | return -EIO; |
7edcb9ab OR |
383 | return 0; |
384 | } | |
385 | ||
386 | /* Block transaction function */ | |
387 | static int i801_block_transaction(union i2c_smbus_data *data, char read_write, | |
388 | int command, int hwpec) | |
389 | { | |
390 | int result = 0; | |
391 | unsigned char hostc; | |
392 | ||
393 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
394 | if (read_write == I2C_SMBUS_WRITE) { | |
395 | /* set I2C_EN bit in configuration register */ | |
396 | pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc); | |
397 | pci_write_config_byte(I801_dev, SMBHSTCFG, | |
398 | hostc | SMBHSTCFG_I2C_EN); | |
6342064c | 399 | } else if (!(i801_features & FEATURE_I2C_BLOCK_READ)) { |
7edcb9ab | 400 | dev_err(&I801_dev->dev, |
6342064c | 401 | "I2C block read is unsupported!\n"); |
97140342 | 402 | return -EOPNOTSUPP; |
7edcb9ab OR |
403 | } |
404 | } | |
405 | ||
6342064c JD |
406 | if (read_write == I2C_SMBUS_WRITE |
407 | || command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
7edcb9ab OR |
408 | if (data->block[0] < 1) |
409 | data->block[0] = 1; | |
410 | if (data->block[0] > I2C_SMBUS_BLOCK_MAX) | |
411 | data->block[0] = I2C_SMBUS_BLOCK_MAX; | |
412 | } else { | |
6342064c | 413 | data->block[0] = 32; /* max for SMBus block reads */ |
7edcb9ab OR |
414 | } |
415 | ||
369f6f4a | 416 | if ((i801_features & FEATURE_BLOCK_BUFFER) |
6342064c JD |
417 | && !(command == I2C_SMBUS_I2C_BLOCK_DATA |
418 | && read_write == I2C_SMBUS_READ) | |
369f6f4a | 419 | && i801_set_block_buffer_mode() == 0) |
7edcb9ab OR |
420 | result = i801_block_transaction_by_block(data, read_write, |
421 | hwpec); | |
422 | else | |
423 | result = i801_block_transaction_byte_by_byte(data, read_write, | |
6342064c | 424 | command, hwpec); |
7edcb9ab OR |
425 | |
426 | if (result == 0 && hwpec) | |
ca8b9e32 | 427 | i801_wait_hwpec(); |
1da177e4 | 428 | |
6342064c JD |
429 | if (command == I2C_SMBUS_I2C_BLOCK_DATA |
430 | && read_write == I2C_SMBUS_WRITE) { | |
1da177e4 LT |
431 | /* restore saved configuration register value */ |
432 | pci_write_config_byte(I801_dev, SMBHSTCFG, hostc); | |
433 | } | |
434 | return result; | |
435 | } | |
436 | ||
97140342 | 437 | /* Return negative errno on error. */ |
1da177e4 LT |
438 | static s32 i801_access(struct i2c_adapter * adap, u16 addr, |
439 | unsigned short flags, char read_write, u8 command, | |
440 | int size, union i2c_smbus_data * data) | |
441 | { | |
e8aac4a9 | 442 | int hwpec; |
1da177e4 LT |
443 | int block = 0; |
444 | int ret, xact = 0; | |
445 | ||
369f6f4a | 446 | hwpec = (i801_features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) |
e8aac4a9 JD |
447 | && size != I2C_SMBUS_QUICK |
448 | && size != I2C_SMBUS_I2C_BLOCK_DATA; | |
1da177e4 LT |
449 | |
450 | switch (size) { | |
451 | case I2C_SMBUS_QUICK: | |
452 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
453 | SMBHSTADD); | |
454 | xact = I801_QUICK; | |
455 | break; | |
456 | case I2C_SMBUS_BYTE: | |
457 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
458 | SMBHSTADD); | |
459 | if (read_write == I2C_SMBUS_WRITE) | |
460 | outb_p(command, SMBHSTCMD); | |
461 | xact = I801_BYTE; | |
462 | break; | |
463 | case I2C_SMBUS_BYTE_DATA: | |
464 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
465 | SMBHSTADD); | |
466 | outb_p(command, SMBHSTCMD); | |
467 | if (read_write == I2C_SMBUS_WRITE) | |
468 | outb_p(data->byte, SMBHSTDAT0); | |
469 | xact = I801_BYTE_DATA; | |
470 | break; | |
471 | case I2C_SMBUS_WORD_DATA: | |
472 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
473 | SMBHSTADD); | |
474 | outb_p(command, SMBHSTCMD); | |
475 | if (read_write == I2C_SMBUS_WRITE) { | |
476 | outb_p(data->word & 0xff, SMBHSTDAT0); | |
477 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1); | |
478 | } | |
479 | xact = I801_WORD_DATA; | |
480 | break; | |
481 | case I2C_SMBUS_BLOCK_DATA: | |
1da177e4 LT |
482 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), |
483 | SMBHSTADD); | |
484 | outb_p(command, SMBHSTCMD); | |
485 | block = 1; | |
486 | break; | |
6342064c JD |
487 | case I2C_SMBUS_I2C_BLOCK_DATA: |
488 | /* NB: page 240 of ICH5 datasheet shows that the R/#W | |
489 | * bit should be cleared here, even when reading */ | |
490 | outb_p((addr & 0x7f) << 1, SMBHSTADD); | |
491 | if (read_write == I2C_SMBUS_READ) { | |
492 | /* NB: page 240 of ICH5 datasheet also shows | |
493 | * that DATA1 is the cmd field when reading */ | |
494 | outb_p(command, SMBHSTDAT1); | |
495 | } else | |
496 | outb_p(command, SMBHSTCMD); | |
497 | block = 1; | |
498 | break; | |
1da177e4 LT |
499 | default: |
500 | dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size); | |
97140342 | 501 | return -EOPNOTSUPP; |
1da177e4 LT |
502 | } |
503 | ||
ca8b9e32 OR |
504 | if (hwpec) /* enable/disable hardware PEC */ |
505 | outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL); | |
506 | else | |
507 | outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL); | |
e8aac4a9 | 508 | |
1da177e4 | 509 | if(block) |
585b3160 | 510 | ret = i801_block_transaction(data, read_write, size, hwpec); |
7edcb9ab OR |
511 | else |
512 | ret = i801_transaction(xact | ENABLE_INT9); | |
1da177e4 | 513 | |
c79cfbac | 514 | /* Some BIOSes don't like it when PEC is enabled at reboot or resume |
7edcb9ab OR |
515 | time, so we forcibly disable it after every transaction. Turn off |
516 | E32B for the same reason. */ | |
a0921b6c | 517 | if (hwpec || block) |
7edcb9ab OR |
518 | outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), |
519 | SMBAUXCTL); | |
c79cfbac | 520 | |
1da177e4 LT |
521 | if(block) |
522 | return ret; | |
523 | if(ret) | |
97140342 | 524 | return ret; |
1da177e4 LT |
525 | if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) |
526 | return 0; | |
527 | ||
528 | switch (xact & 0x7f) { | |
529 | case I801_BYTE: /* Result put in SMBHSTDAT0 */ | |
530 | case I801_BYTE_DATA: | |
531 | data->byte = inb_p(SMBHSTDAT0); | |
532 | break; | |
533 | case I801_WORD_DATA: | |
534 | data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8); | |
535 | break; | |
536 | } | |
537 | return 0; | |
538 | } | |
539 | ||
540 | ||
541 | static u32 i801_func(struct i2c_adapter *adapter) | |
542 | { | |
543 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | | |
369f6f4a JD |
544 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | |
545 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | | |
6342064c JD |
546 | ((i801_features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | |
547 | ((i801_features & FEATURE_I2C_BLOCK_READ) ? | |
548 | I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0); | |
1da177e4 LT |
549 | } |
550 | ||
8f9082c5 | 551 | static const struct i2c_algorithm smbus_algorithm = { |
1da177e4 LT |
552 | .smbus_xfer = i801_access, |
553 | .functionality = i801_func, | |
554 | }; | |
555 | ||
556 | static struct i2c_adapter i801_adapter = { | |
557 | .owner = THIS_MODULE, | |
9ace555d | 558 | .id = I2C_HW_SMBUS_I801, |
3401b2ff | 559 | .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, |
1da177e4 | 560 | .algo = &smbus_algorithm, |
1da177e4 LT |
561 | }; |
562 | ||
563 | static struct pci_device_id i801_ids[] = { | |
564 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, | |
565 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, | |
566 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, | |
567 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, | |
568 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, | |
569 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, | |
570 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, | |
571 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, | |
572 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, | |
b0a70b57 | 573 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, |
8254fc4a | 574 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, |
adbc2a10 | 575 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, |
e07bc679 | 576 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TOLAPAI_1) }, |
d28dc711 GJ |
577 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, |
578 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, | |
1da177e4 LT |
579 | { 0, } |
580 | }; | |
581 | ||
582 | MODULE_DEVICE_TABLE (pci, i801_ids); | |
583 | ||
584 | static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
585 | { | |
02dd7ae2 | 586 | unsigned char temp; |
455f3323 | 587 | int err; |
1da177e4 | 588 | |
02dd7ae2 | 589 | I801_dev = dev; |
369f6f4a | 590 | i801_features = 0; |
250d1bd3 | 591 | switch (dev->device) { |
250d1bd3 JD |
592 | case PCI_DEVICE_ID_INTEL_82801EB_3: |
593 | case PCI_DEVICE_ID_INTEL_ESB_4: | |
594 | case PCI_DEVICE_ID_INTEL_ICH6_16: | |
595 | case PCI_DEVICE_ID_INTEL_ICH7_17: | |
596 | case PCI_DEVICE_ID_INTEL_ESB2_17: | |
597 | case PCI_DEVICE_ID_INTEL_ICH8_5: | |
598 | case PCI_DEVICE_ID_INTEL_ICH9_6: | |
d28dc711 GJ |
599 | case PCI_DEVICE_ID_INTEL_TOLAPAI_1: |
600 | case PCI_DEVICE_ID_INTEL_ICH10_4: | |
601 | case PCI_DEVICE_ID_INTEL_ICH10_5: | |
6342064c JD |
602 | i801_features |= FEATURE_I2C_BLOCK_READ; |
603 | /* fall through */ | |
604 | case PCI_DEVICE_ID_INTEL_82801DB_3: | |
369f6f4a JD |
605 | i801_features |= FEATURE_SMBUS_PEC; |
606 | i801_features |= FEATURE_BLOCK_BUFFER; | |
250d1bd3 | 607 | break; |
250d1bd3 | 608 | } |
02dd7ae2 JD |
609 | |
610 | err = pci_enable_device(dev); | |
611 | if (err) { | |
612 | dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", | |
613 | err); | |
614 | goto exit; | |
615 | } | |
616 | ||
617 | /* Determine the address of the SMBus area */ | |
618 | i801_smba = pci_resource_start(dev, SMBBAR); | |
619 | if (!i801_smba) { | |
620 | dev_err(&dev->dev, "SMBus base address uninitialized, " | |
621 | "upgrade BIOS\n"); | |
622 | err = -ENODEV; | |
d6fcb3b9 | 623 | goto exit; |
02dd7ae2 JD |
624 | } |
625 | ||
54fb4a05 JD |
626 | err = acpi_check_resource_conflict(&dev->resource[SMBBAR]); |
627 | if (err) | |
628 | goto exit; | |
629 | ||
02dd7ae2 JD |
630 | err = pci_request_region(dev, SMBBAR, i801_driver.name); |
631 | if (err) { | |
632 | dev_err(&dev->dev, "Failed to request SMBus region " | |
598736c5 AM |
633 | "0x%lx-0x%Lx\n", i801_smba, |
634 | (unsigned long long)pci_resource_end(dev, SMBBAR)); | |
d6fcb3b9 | 635 | goto exit; |
02dd7ae2 JD |
636 | } |
637 | ||
638 | pci_read_config_byte(I801_dev, SMBHSTCFG, &temp); | |
a5aaea37 | 639 | i801_original_hstcfg = temp; |
02dd7ae2 JD |
640 | temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ |
641 | if (!(temp & SMBHSTCFG_HST_EN)) { | |
642 | dev_info(&dev->dev, "Enabling SMBus device\n"); | |
643 | temp |= SMBHSTCFG_HST_EN; | |
644 | } | |
645 | pci_write_config_byte(I801_dev, SMBHSTCFG, temp); | |
646 | ||
647 | if (temp & SMBHSTCFG_SMB_SMI_EN) | |
648 | dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); | |
649 | else | |
650 | dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n"); | |
1da177e4 | 651 | |
a0921b6c JD |
652 | /* Clear special mode bits */ |
653 | if (i801_features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) | |
654 | outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), | |
655 | SMBAUXCTL); | |
656 | ||
405ae7d3 | 657 | /* set up the sysfs linkage to our parent device */ |
1da177e4 LT |
658 | i801_adapter.dev.parent = &dev->dev; |
659 | ||
2096b956 | 660 | snprintf(i801_adapter.name, sizeof(i801_adapter.name), |
6dcc19df | 661 | "SMBus I801 adapter at %04lx", i801_smba); |
02dd7ae2 JD |
662 | err = i2c_add_adapter(&i801_adapter); |
663 | if (err) { | |
664 | dev_err(&dev->dev, "Failed to add SMBus adapter\n"); | |
d6fcb3b9 | 665 | goto exit_release; |
02dd7ae2 | 666 | } |
d6fcb3b9 | 667 | return 0; |
02dd7ae2 | 668 | |
d6fcb3b9 DR |
669 | exit_release: |
670 | pci_release_region(dev, SMBBAR); | |
02dd7ae2 JD |
671 | exit: |
672 | return err; | |
1da177e4 LT |
673 | } |
674 | ||
675 | static void __devexit i801_remove(struct pci_dev *dev) | |
676 | { | |
677 | i2c_del_adapter(&i801_adapter); | |
a5aaea37 | 678 | pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg); |
6dcc19df | 679 | pci_release_region(dev, SMBBAR); |
d6fcb3b9 DR |
680 | /* |
681 | * do not call pci_disable_device(dev) since it can cause hard hangs on | |
682 | * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) | |
683 | */ | |
1da177e4 LT |
684 | } |
685 | ||
a5aaea37 JD |
686 | #ifdef CONFIG_PM |
687 | static int i801_suspend(struct pci_dev *dev, pm_message_t mesg) | |
688 | { | |
689 | pci_save_state(dev); | |
690 | pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg); | |
691 | pci_set_power_state(dev, pci_choose_state(dev, mesg)); | |
692 | return 0; | |
693 | } | |
694 | ||
695 | static int i801_resume(struct pci_dev *dev) | |
696 | { | |
697 | pci_set_power_state(dev, PCI_D0); | |
698 | pci_restore_state(dev); | |
699 | return pci_enable_device(dev); | |
700 | } | |
701 | #else | |
702 | #define i801_suspend NULL | |
703 | #define i801_resume NULL | |
704 | #endif | |
705 | ||
1da177e4 LT |
706 | static struct pci_driver i801_driver = { |
707 | .name = "i801_smbus", | |
708 | .id_table = i801_ids, | |
709 | .probe = i801_probe, | |
710 | .remove = __devexit_p(i801_remove), | |
a5aaea37 JD |
711 | .suspend = i801_suspend, |
712 | .resume = i801_resume, | |
1da177e4 LT |
713 | }; |
714 | ||
715 | static int __init i2c_i801_init(void) | |
716 | { | |
717 | return pci_register_driver(&i801_driver); | |
718 | } | |
719 | ||
720 | static void __exit i2c_i801_exit(void) | |
721 | { | |
722 | pci_unregister_driver(&i801_driver); | |
723 | } | |
724 | ||
6342064c JD |
725 | MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, " |
726 | "Jean Delvare <khali@linux-fr.org>"); | |
1da177e4 LT |
727 | MODULE_DESCRIPTION("I801 SMBus driver"); |
728 | MODULE_LICENSE("GPL"); | |
729 | ||
730 | module_init(i2c_i801_init); | |
731 | module_exit(i2c_i801_exit); |