Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, |
3 | Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker | |
4 | <mdsxyz123@yahoo.com> | |
84c1af4c | 5 | Copyright (C) 2007 - 2012 Jean Delvare <khali@linux-fr.org> |
0cd96eb0 DW |
6 | Copyright (C) 2010 Intel Corporation, |
7 | David Woodhouse <dwmw2@infradead.org> | |
1da177e4 LT |
8 | |
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | */ | |
23 | ||
24 | /* | |
ae7b0497 JD |
25 | Supports the following Intel I/O Controller Hubs (ICH): |
26 | ||
27 | I/O Block I2C | |
28 | region SMBus Block proc. block | |
29 | Chip name PCI ID size PEC buffer call read | |
30 | ---------------------------------------------------------------------- | |
31 | 82801AA (ICH) 0x2413 16 no no no no | |
32 | 82801AB (ICH0) 0x2423 16 no no no no | |
33 | 82801BA (ICH2) 0x2443 16 no no no no | |
34 | 82801CA (ICH3) 0x2483 32 soft no no no | |
35 | 82801DB (ICH4) 0x24c3 32 hard yes no no | |
36 | 82801E (ICH5) 0x24d3 32 hard yes yes yes | |
37 | 6300ESB 0x25a4 32 hard yes yes yes | |
38 | 82801F (ICH6) 0x266a 32 hard yes yes yes | |
39 | 6310ESB/6320ESB 0x269b 32 hard yes yes yes | |
40 | 82801G (ICH7) 0x27da 32 hard yes yes yes | |
41 | 82801H (ICH8) 0x283e 32 hard yes yes yes | |
42 | 82801I (ICH9) 0x2930 32 hard yes yes yes | |
cb04e95b | 43 | EP80579 (Tolapai) 0x5032 32 hard yes yes yes |
d28dc711 GJ |
44 | ICH10 0x3a30 32 hard yes yes yes |
45 | ICH10 0x3a60 32 hard yes yes yes | |
cb04e95b | 46 | 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes |
662cda8a | 47 | 6 Series (PCH) 0x1c22 32 hard yes yes yes |
e30d9859 | 48 | Patsburg (PCH) 0x1d22 32 hard yes yes yes |
55fee8d7 DW |
49 | Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes |
50 | Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes | |
51 | Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes | |
662cda8a | 52 | DH89xxCC (PCH) 0x2330 32 hard yes yes yes |
6e2a851e | 53 | Panther Point (PCH) 0x1e22 32 hard yes yes yes |
062737fb | 54 | Lynx Point (PCH) 0x8c22 32 hard yes yes yes |
4a8f1ddd | 55 | Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes |
ae7b0497 JD |
56 | |
57 | Features supported by this driver: | |
58 | Software PEC no | |
59 | Hardware PEC yes | |
60 | Block buffer yes | |
61 | Block process call transaction no | |
6342064c | 62 | I2C block read transaction yes (doesn't use the block buffer) |
55fee8d7 | 63 | Slave mode no |
636752bc | 64 | Interrupt processing yes |
ae7b0497 JD |
65 | |
66 | See the file Documentation/i2c/busses/i2c-i801 for details. | |
1da177e4 LT |
67 | */ |
68 | ||
636752bc | 69 | #include <linux/interrupt.h> |
1da177e4 LT |
70 | #include <linux/module.h> |
71 | #include <linux/pci.h> | |
72 | #include <linux/kernel.h> | |
73 | #include <linux/stddef.h> | |
74 | #include <linux/delay.h> | |
1da177e4 LT |
75 | #include <linux/ioport.h> |
76 | #include <linux/init.h> | |
77 | #include <linux/i2c.h> | |
54fb4a05 | 78 | #include <linux/acpi.h> |
1561bfe5 | 79 | #include <linux/io.h> |
fa5bfab7 | 80 | #include <linux/dmi.h> |
665a96b7 | 81 | #include <linux/slab.h> |
636752bc | 82 | #include <linux/wait.h> |
1da177e4 | 83 | |
1da177e4 | 84 | /* I801 SMBus address offsets */ |
0cd96eb0 DW |
85 | #define SMBHSTSTS(p) (0 + (p)->smba) |
86 | #define SMBHSTCNT(p) (2 + (p)->smba) | |
87 | #define SMBHSTCMD(p) (3 + (p)->smba) | |
88 | #define SMBHSTADD(p) (4 + (p)->smba) | |
89 | #define SMBHSTDAT0(p) (5 + (p)->smba) | |
90 | #define SMBHSTDAT1(p) (6 + (p)->smba) | |
91 | #define SMBBLKDAT(p) (7 + (p)->smba) | |
92 | #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ | |
93 | #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ | |
94 | #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ | |
1da177e4 LT |
95 | |
96 | /* PCI Address Constants */ | |
6dcc19df | 97 | #define SMBBAR 4 |
636752bc | 98 | #define SMBPCISTS 0x006 |
1da177e4 | 99 | #define SMBHSTCFG 0x040 |
1da177e4 | 100 | |
636752bc DK |
101 | /* Host status bits for SMBPCISTS */ |
102 | #define SMBPCISTS_INTS 0x08 | |
103 | ||
1da177e4 LT |
104 | /* Host configuration bits for SMBHSTCFG */ |
105 | #define SMBHSTCFG_HST_EN 1 | |
106 | #define SMBHSTCFG_SMB_SMI_EN 2 | |
107 | #define SMBHSTCFG_I2C_EN 4 | |
108 | ||
25985edc | 109 | /* Auxiliary control register bits, ICH4+ only */ |
ca8b9e32 OR |
110 | #define SMBAUXCTL_CRC 1 |
111 | #define SMBAUXCTL_E32B 2 | |
112 | ||
1da177e4 | 113 | /* Other settings */ |
84c1af4c | 114 | #define MAX_RETRIES 400 |
1da177e4 LT |
115 | |
116 | /* I801 command constants */ | |
117 | #define I801_QUICK 0x00 | |
118 | #define I801_BYTE 0x04 | |
119 | #define I801_BYTE_DATA 0x08 | |
120 | #define I801_WORD_DATA 0x0C | |
ae7b0497 | 121 | #define I801_PROC_CALL 0x10 /* unimplemented */ |
1da177e4 | 122 | #define I801_BLOCK_DATA 0x14 |
6342064c | 123 | #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ |
edbeea63 DK |
124 | |
125 | /* I801 Host Control register bits */ | |
126 | #define SMBHSTCNT_INTREN 0x01 | |
127 | #define SMBHSTCNT_KILL 0x02 | |
128 | #define SMBHSTCNT_LAST_BYTE 0x20 | |
129 | #define SMBHSTCNT_START 0x40 | |
130 | #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */ | |
1da177e4 | 131 | |
ca8b9e32 OR |
132 | /* I801 Hosts Status register bits */ |
133 | #define SMBHSTSTS_BYTE_DONE 0x80 | |
134 | #define SMBHSTSTS_INUSE_STS 0x40 | |
135 | #define SMBHSTSTS_SMBALERT_STS 0x20 | |
136 | #define SMBHSTSTS_FAILED 0x10 | |
137 | #define SMBHSTSTS_BUS_ERR 0x08 | |
138 | #define SMBHSTSTS_DEV_ERR 0x04 | |
139 | #define SMBHSTSTS_INTR 0x02 | |
140 | #define SMBHSTSTS_HOST_BUSY 0x01 | |
1da177e4 | 141 | |
70a1cc19 DK |
142 | #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ |
143 | SMBHSTSTS_DEV_ERR) | |
144 | ||
145 | #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ | |
146 | STATUS_ERROR_FLAGS) | |
cf898dc5 | 147 | |
a6e5e2be JD |
148 | /* Older devices have their ID defined in <linux/pci_ids.h> */ |
149 | #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 | |
150 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 | |
55fee8d7 DW |
151 | /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ |
152 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 | |
153 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 | |
154 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 | |
6e2a851e | 155 | #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 |
a6e5e2be JD |
156 | #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 |
157 | #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 | |
062737fb | 158 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 |
4a8f1ddd | 159 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 |
55fee8d7 | 160 | |
0cd96eb0 DW |
161 | struct i801_priv { |
162 | struct i2c_adapter adapter; | |
163 | unsigned long smba; | |
164 | unsigned char original_hstcfg; | |
165 | struct pci_dev *pci_dev; | |
166 | unsigned int features; | |
636752bc DK |
167 | |
168 | /* isr processing */ | |
169 | wait_queue_head_t waitq; | |
170 | u8 status; | |
d3ff6ce4 DK |
171 | |
172 | /* Command state used by isr for byte-by-byte block transactions */ | |
173 | u8 cmd; | |
174 | bool is_read; | |
175 | int count; | |
176 | int len; | |
177 | u8 *data; | |
0cd96eb0 DW |
178 | }; |
179 | ||
d6072f84 | 180 | static struct pci_driver i801_driver; |
369f6f4a JD |
181 | |
182 | #define FEATURE_SMBUS_PEC (1 << 0) | |
183 | #define FEATURE_BLOCK_BUFFER (1 << 1) | |
184 | #define FEATURE_BLOCK_PROC (1 << 2) | |
185 | #define FEATURE_I2C_BLOCK_READ (1 << 3) | |
636752bc | 186 | #define FEATURE_IRQ (1 << 4) |
e7198fbf JD |
187 | /* Not really a feature, but it's convenient to handle it as such */ |
188 | #define FEATURE_IDF (1 << 15) | |
1da177e4 | 189 | |
adff687d JD |
190 | static const char *i801_feature_names[] = { |
191 | "SMBus PEC", | |
192 | "Block buffer", | |
193 | "Block process call", | |
194 | "I2C block read", | |
636752bc | 195 | "Interrupt", |
adff687d JD |
196 | }; |
197 | ||
198 | static unsigned int disable_features; | |
199 | module_param(disable_features, uint, S_IRUGO | S_IWUSR); | |
200 | MODULE_PARM_DESC(disable_features, "Disable selected driver features"); | |
201 | ||
cf898dc5 JD |
202 | /* Make sure the SMBus host is ready to start transmitting. |
203 | Return 0 if it is, -EBUSY if it is not. */ | |
0cd96eb0 | 204 | static int i801_check_pre(struct i801_priv *priv) |
1da177e4 | 205 | { |
2b73809d | 206 | int status; |
1da177e4 | 207 | |
0cd96eb0 | 208 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 | 209 | if (status & SMBHSTSTS_HOST_BUSY) { |
0cd96eb0 | 210 | dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); |
cf898dc5 JD |
211 | return -EBUSY; |
212 | } | |
213 | ||
214 | status &= STATUS_FLAGS; | |
215 | if (status) { | |
0cd96eb0 | 216 | dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", |
2b73809d | 217 | status); |
0cd96eb0 DW |
218 | outb_p(status, SMBHSTSTS(priv)); |
219 | status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; | |
cf898dc5 | 220 | if (status) { |
0cd96eb0 | 221 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
222 | "Failed clearing status flags (%02x)\n", |
223 | status); | |
97140342 | 224 | return -EBUSY; |
1da177e4 LT |
225 | } |
226 | } | |
227 | ||
cf898dc5 JD |
228 | return 0; |
229 | } | |
1da177e4 | 230 | |
6cad93c4 JD |
231 | /* |
232 | * Convert the status register to an error code, and clear it. | |
233 | * Note that status only contains the bits we want to clear, not the | |
234 | * actual register value. | |
235 | */ | |
236 | static int i801_check_post(struct i801_priv *priv, int status) | |
cf898dc5 JD |
237 | { |
238 | int result = 0; | |
1da177e4 | 239 | |
636752bc DK |
240 | /* |
241 | * If the SMBus is still busy, we give up | |
242 | * Note: This timeout condition only happens when using polling | |
243 | * transactions. For interrupt operation, NAK/timeout is indicated by | |
244 | * DEV_ERR. | |
245 | */ | |
6cad93c4 | 246 | if (unlikely(status < 0)) { |
0cd96eb0 | 247 | dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); |
ca8b9e32 | 248 | /* try to stop the current command */ |
0cd96eb0 DW |
249 | dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); |
250 | outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, | |
251 | SMBHSTCNT(priv)); | |
84c1af4c | 252 | usleep_range(1000, 2000); |
0cd96eb0 DW |
253 | outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), |
254 | SMBHSTCNT(priv)); | |
cf898dc5 JD |
255 | |
256 | /* Check if it worked */ | |
0cd96eb0 | 257 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 JD |
258 | if ((status & SMBHSTSTS_HOST_BUSY) || |
259 | !(status & SMBHSTSTS_FAILED)) | |
0cd96eb0 | 260 | dev_err(&priv->pci_dev->dev, |
cf898dc5 | 261 | "Failed terminating the transaction\n"); |
0cd96eb0 | 262 | outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); |
cf898dc5 | 263 | return -ETIMEDOUT; |
1da177e4 LT |
264 | } |
265 | ||
2b73809d | 266 | if (status & SMBHSTSTS_FAILED) { |
97140342 | 267 | result = -EIO; |
0cd96eb0 | 268 | dev_err(&priv->pci_dev->dev, "Transaction failed\n"); |
cf898dc5 JD |
269 | } |
270 | if (status & SMBHSTSTS_DEV_ERR) { | |
271 | result = -ENXIO; | |
0cd96eb0 | 272 | dev_dbg(&priv->pci_dev->dev, "No response\n"); |
1da177e4 | 273 | } |
2b73809d | 274 | if (status & SMBHSTSTS_BUS_ERR) { |
dcb5c923 | 275 | result = -EAGAIN; |
0cd96eb0 | 276 | dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); |
1da177e4 LT |
277 | } |
278 | ||
6cad93c4 JD |
279 | /* Clear status flags except BYTE_DONE, to be cleared by caller */ |
280 | outb_p(status, SMBHSTSTS(priv)); | |
1da177e4 | 281 | |
1da177e4 LT |
282 | return result; |
283 | } | |
284 | ||
6cad93c4 JD |
285 | /* Wait for BUSY being cleared and either INTR or an error flag being set */ |
286 | static int i801_wait_intr(struct i801_priv *priv) | |
cf898dc5 | 287 | { |
cf898dc5 | 288 | int timeout = 0; |
6cad93c4 | 289 | int status; |
cf898dc5 JD |
290 | |
291 | /* We will always wait for a fraction of a second! */ | |
292 | do { | |
84c1af4c | 293 | usleep_range(250, 500); |
0cd96eb0 | 294 | status = inb_p(SMBHSTSTS(priv)); |
6cad93c4 JD |
295 | } while (((status & SMBHSTSTS_HOST_BUSY) || |
296 | !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && | |
297 | (timeout++ < MAX_RETRIES)); | |
cf898dc5 | 298 | |
6cad93c4 JD |
299 | if (timeout > MAX_RETRIES) { |
300 | dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); | |
301 | return -ETIMEDOUT; | |
302 | } | |
303 | return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); | |
cf898dc5 JD |
304 | } |
305 | ||
6cad93c4 JD |
306 | /* Wait for either BYTE_DONE or an error flag being set */ |
307 | static int i801_wait_byte_done(struct i801_priv *priv) | |
ca8b9e32 OR |
308 | { |
309 | int timeout = 0; | |
2b73809d | 310 | int status; |
ca8b9e32 | 311 | |
6cad93c4 | 312 | /* We will always wait for a fraction of a second! */ |
ca8b9e32 | 313 | do { |
84c1af4c | 314 | usleep_range(250, 500); |
0cd96eb0 | 315 | status = inb_p(SMBHSTSTS(priv)); |
6cad93c4 JD |
316 | } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && |
317 | (timeout++ < MAX_RETRIES)); | |
318 | ||
319 | if (timeout > MAX_RETRIES) { | |
320 | dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); | |
321 | return -ETIMEDOUT; | |
322 | } | |
323 | return status & STATUS_ERROR_FLAGS; | |
324 | } | |
325 | ||
326 | static int i801_transaction(struct i801_priv *priv, int xact) | |
327 | { | |
328 | int status; | |
329 | int result; | |
ca8b9e32 | 330 | |
6cad93c4 JD |
331 | result = i801_check_pre(priv); |
332 | if (result < 0) | |
333 | return result; | |
4ccc28f7 | 334 | |
636752bc DK |
335 | if (priv->features & FEATURE_IRQ) { |
336 | outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, | |
337 | SMBHSTCNT(priv)); | |
338 | wait_event(priv->waitq, (status = priv->status)); | |
339 | priv->status = 0; | |
340 | return i801_check_post(priv, status); | |
341 | } | |
342 | ||
6cad93c4 JD |
343 | /* the current contents of SMBHSTCNT can be overwritten, since PEC, |
344 | * SMBSCMD are passed in xact */ | |
345 | outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); | |
346 | ||
347 | status = i801_wait_intr(priv); | |
348 | return i801_check_post(priv, status); | |
ca8b9e32 OR |
349 | } |
350 | ||
0cd96eb0 DW |
351 | static int i801_block_transaction_by_block(struct i801_priv *priv, |
352 | union i2c_smbus_data *data, | |
7edcb9ab OR |
353 | char read_write, int hwpec) |
354 | { | |
355 | int i, len; | |
97140342 | 356 | int status; |
7edcb9ab | 357 | |
0cd96eb0 | 358 | inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ |
7edcb9ab OR |
359 | |
360 | /* Use 32-byte buffer to process this transaction */ | |
361 | if (read_write == I2C_SMBUS_WRITE) { | |
362 | len = data->block[0]; | |
0cd96eb0 | 363 | outb_p(len, SMBHSTDAT0(priv)); |
7edcb9ab | 364 | for (i = 0; i < len; i++) |
0cd96eb0 | 365 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
7edcb9ab OR |
366 | } |
367 | ||
37af8711 | 368 | status = i801_transaction(priv, I801_BLOCK_DATA | |
edbeea63 | 369 | (hwpec ? SMBHSTCNT_PEC_EN : 0)); |
97140342 DB |
370 | if (status) |
371 | return status; | |
7edcb9ab OR |
372 | |
373 | if (read_write == I2C_SMBUS_READ) { | |
0cd96eb0 | 374 | len = inb_p(SMBHSTDAT0(priv)); |
7edcb9ab | 375 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) |
97140342 | 376 | return -EPROTO; |
7edcb9ab OR |
377 | |
378 | data->block[0] = len; | |
379 | for (i = 0; i < len; i++) | |
0cd96eb0 | 380 | data->block[i + 1] = inb_p(SMBBLKDAT(priv)); |
7edcb9ab OR |
381 | } |
382 | return 0; | |
383 | } | |
384 | ||
d3ff6ce4 DK |
385 | static void i801_isr_byte_done(struct i801_priv *priv) |
386 | { | |
387 | if (priv->is_read) { | |
388 | /* For SMBus block reads, length is received with first byte */ | |
389 | if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && | |
390 | (priv->count == 0)) { | |
391 | priv->len = inb_p(SMBHSTDAT0(priv)); | |
392 | if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { | |
393 | dev_err(&priv->pci_dev->dev, | |
394 | "Illegal SMBus block read size %d\n", | |
395 | priv->len); | |
396 | /* FIXME: Recover */ | |
397 | priv->len = I2C_SMBUS_BLOCK_MAX; | |
398 | } else { | |
399 | dev_dbg(&priv->pci_dev->dev, | |
400 | "SMBus block read size is %d\n", | |
401 | priv->len); | |
402 | } | |
403 | priv->data[-1] = priv->len; | |
404 | } | |
405 | ||
406 | /* Read next byte */ | |
407 | if (priv->count < priv->len) | |
408 | priv->data[priv->count++] = inb(SMBBLKDAT(priv)); | |
409 | else | |
410 | dev_dbg(&priv->pci_dev->dev, | |
411 | "Discarding extra byte on block read\n"); | |
412 | ||
413 | /* Set LAST_BYTE for last byte of read transaction */ | |
414 | if (priv->count == priv->len - 1) | |
415 | outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, | |
416 | SMBHSTCNT(priv)); | |
417 | } else if (priv->count < priv->len - 1) { | |
418 | /* Write next byte, except for IRQ after last byte */ | |
419 | outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); | |
420 | } | |
421 | ||
422 | /* Clear BYTE_DONE to continue with next byte */ | |
423 | outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); | |
424 | } | |
425 | ||
636752bc | 426 | /* |
d3ff6ce4 DK |
427 | * There are two kinds of interrupts: |
428 | * | |
429 | * 1) i801 signals transaction completion with one of these interrupts: | |
430 | * INTR - Success | |
431 | * DEV_ERR - Invalid command, NAK or communication timeout | |
432 | * BUS_ERR - SMI# transaction collision | |
433 | * FAILED - transaction was canceled due to a KILL request | |
434 | * When any of these occur, update ->status and wake up the waitq. | |
435 | * ->status must be cleared before kicking off the next transaction. | |
436 | * | |
437 | * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt | |
438 | * occurs for each byte of a byte-by-byte to prepare the next byte. | |
636752bc DK |
439 | */ |
440 | static irqreturn_t i801_isr(int irq, void *dev_id) | |
441 | { | |
442 | struct i801_priv *priv = dev_id; | |
443 | u16 pcists; | |
444 | u8 status; | |
445 | ||
446 | /* Confirm this is our interrupt */ | |
447 | pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); | |
448 | if (!(pcists & SMBPCISTS_INTS)) | |
449 | return IRQ_NONE; | |
450 | ||
451 | status = inb_p(SMBHSTSTS(priv)); | |
452 | if (status != 0x42) | |
453 | dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status); | |
454 | ||
d3ff6ce4 DK |
455 | if (status & SMBHSTSTS_BYTE_DONE) |
456 | i801_isr_byte_done(priv); | |
457 | ||
636752bc DK |
458 | /* |
459 | * Clear irq sources and report transaction result. | |
460 | * ->status must be cleared before the next transaction is started. | |
461 | */ | |
462 | status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; | |
463 | if (status) { | |
464 | outb_p(status, SMBHSTSTS(priv)); | |
465 | priv->status |= status; | |
466 | wake_up(&priv->waitq); | |
467 | } | |
468 | ||
469 | return IRQ_HANDLED; | |
470 | } | |
471 | ||
efa3cb15 DK |
472 | /* |
473 | * For "byte-by-byte" block transactions: | |
474 | * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 | |
475 | * I2C read uses cmd=I801_I2C_BLOCK_DATA | |
476 | */ | |
0cd96eb0 DW |
477 | static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, |
478 | union i2c_smbus_data *data, | |
6342064c JD |
479 | char read_write, int command, |
480 | int hwpec) | |
1da177e4 LT |
481 | { |
482 | int i, len; | |
483 | int smbcmd; | |
2b73809d | 484 | int status; |
cf898dc5 | 485 | int result; |
cf898dc5 | 486 | |
0cd96eb0 | 487 | result = i801_check_pre(priv); |
cf898dc5 JD |
488 | if (result < 0) |
489 | return result; | |
1da177e4 | 490 | |
7edcb9ab | 491 | len = data->block[0]; |
1da177e4 LT |
492 | |
493 | if (read_write == I2C_SMBUS_WRITE) { | |
0cd96eb0 DW |
494 | outb_p(len, SMBHSTDAT0(priv)); |
495 | outb_p(data->block[1], SMBBLKDAT(priv)); | |
1da177e4 LT |
496 | } |
497 | ||
efa3cb15 DK |
498 | if (command == I2C_SMBUS_I2C_BLOCK_DATA && |
499 | read_write == I2C_SMBUS_READ) | |
500 | smbcmd = I801_I2C_BLOCK_DATA; | |
501 | else | |
502 | smbcmd = I801_BLOCK_DATA; | |
503 | ||
d3ff6ce4 DK |
504 | if (priv->features & FEATURE_IRQ) { |
505 | priv->is_read = (read_write == I2C_SMBUS_READ); | |
506 | if (len == 1 && priv->is_read) | |
507 | smbcmd |= SMBHSTCNT_LAST_BYTE; | |
508 | priv->cmd = smbcmd | SMBHSTCNT_INTREN; | |
509 | priv->len = len; | |
510 | priv->count = 0; | |
511 | priv->data = &data->block[1]; | |
512 | ||
513 | outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); | |
514 | wait_event(priv->waitq, (status = priv->status)); | |
515 | priv->status = 0; | |
516 | return i801_check_post(priv, status); | |
517 | } | |
518 | ||
1da177e4 | 519 | for (i = 1; i <= len; i++) { |
efa3cb15 | 520 | if (i == len && read_write == I2C_SMBUS_READ) |
edbeea63 | 521 | smbcmd |= SMBHSTCNT_LAST_BYTE; |
37af8711 | 522 | outb_p(smbcmd, SMBHSTCNT(priv)); |
1da177e4 | 523 | |
1da177e4 | 524 | if (i == 1) |
edbeea63 | 525 | outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, |
0cd96eb0 | 526 | SMBHSTCNT(priv)); |
1da177e4 | 527 | |
6cad93c4 JD |
528 | status = i801_wait_byte_done(priv); |
529 | if (status) | |
530 | goto exit; | |
1da177e4 | 531 | |
6342064c JD |
532 | if (i == 1 && read_write == I2C_SMBUS_READ |
533 | && command != I2C_SMBUS_I2C_BLOCK_DATA) { | |
0cd96eb0 | 534 | len = inb_p(SMBHSTDAT0(priv)); |
cf898dc5 | 535 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { |
0cd96eb0 | 536 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
537 | "Illegal SMBus block read size %d\n", |
538 | len); | |
539 | /* Recover */ | |
0cd96eb0 DW |
540 | while (inb_p(SMBHSTSTS(priv)) & |
541 | SMBHSTSTS_HOST_BUSY) | |
542 | outb_p(SMBHSTSTS_BYTE_DONE, | |
543 | SMBHSTSTS(priv)); | |
544 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); | |
97140342 | 545 | return -EPROTO; |
cf898dc5 | 546 | } |
1da177e4 LT |
547 | data->block[0] = len; |
548 | } | |
549 | ||
550 | /* Retrieve/store value in SMBBLKDAT */ | |
551 | if (read_write == I2C_SMBUS_READ) | |
0cd96eb0 | 552 | data->block[i] = inb_p(SMBBLKDAT(priv)); |
1da177e4 | 553 | if (read_write == I2C_SMBUS_WRITE && i+1 <= len) |
0cd96eb0 | 554 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
1da177e4 | 555 | |
cf898dc5 | 556 | /* signals SMBBLKDAT ready */ |
6cad93c4 | 557 | outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); |
1da177e4 | 558 | } |
cf898dc5 | 559 | |
6cad93c4 JD |
560 | status = i801_wait_intr(priv); |
561 | exit: | |
562 | return i801_check_post(priv, status); | |
7edcb9ab | 563 | } |
1da177e4 | 564 | |
0cd96eb0 | 565 | static int i801_set_block_buffer_mode(struct i801_priv *priv) |
7edcb9ab | 566 | { |
0cd96eb0 DW |
567 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); |
568 | if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) | |
97140342 | 569 | return -EIO; |
7edcb9ab OR |
570 | return 0; |
571 | } | |
572 | ||
573 | /* Block transaction function */ | |
0cd96eb0 DW |
574 | static int i801_block_transaction(struct i801_priv *priv, |
575 | union i2c_smbus_data *data, char read_write, | |
7edcb9ab OR |
576 | int command, int hwpec) |
577 | { | |
578 | int result = 0; | |
579 | unsigned char hostc; | |
580 | ||
581 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
582 | if (read_write == I2C_SMBUS_WRITE) { | |
583 | /* set I2C_EN bit in configuration register */ | |
0cd96eb0 DW |
584 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); |
585 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, | |
7edcb9ab | 586 | hostc | SMBHSTCFG_I2C_EN); |
0cd96eb0 DW |
587 | } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { |
588 | dev_err(&priv->pci_dev->dev, | |
6342064c | 589 | "I2C block read is unsupported!\n"); |
97140342 | 590 | return -EOPNOTSUPP; |
7edcb9ab OR |
591 | } |
592 | } | |
593 | ||
6342064c JD |
594 | if (read_write == I2C_SMBUS_WRITE |
595 | || command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
7edcb9ab OR |
596 | if (data->block[0] < 1) |
597 | data->block[0] = 1; | |
598 | if (data->block[0] > I2C_SMBUS_BLOCK_MAX) | |
599 | data->block[0] = I2C_SMBUS_BLOCK_MAX; | |
600 | } else { | |
6342064c | 601 | data->block[0] = 32; /* max for SMBus block reads */ |
7edcb9ab OR |
602 | } |
603 | ||
c074c39d JD |
604 | /* Experience has shown that the block buffer can only be used for |
605 | SMBus (not I2C) block transactions, even though the datasheet | |
606 | doesn't mention this limitation. */ | |
0cd96eb0 | 607 | if ((priv->features & FEATURE_BLOCK_BUFFER) |
c074c39d | 608 | && command != I2C_SMBUS_I2C_BLOCK_DATA |
0cd96eb0 DW |
609 | && i801_set_block_buffer_mode(priv) == 0) |
610 | result = i801_block_transaction_by_block(priv, data, | |
611 | read_write, hwpec); | |
7edcb9ab | 612 | else |
0cd96eb0 DW |
613 | result = i801_block_transaction_byte_by_byte(priv, data, |
614 | read_write, | |
6342064c | 615 | command, hwpec); |
7edcb9ab | 616 | |
6342064c JD |
617 | if (command == I2C_SMBUS_I2C_BLOCK_DATA |
618 | && read_write == I2C_SMBUS_WRITE) { | |
1da177e4 | 619 | /* restore saved configuration register value */ |
0cd96eb0 | 620 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); |
1da177e4 LT |
621 | } |
622 | return result; | |
623 | } | |
624 | ||
97140342 | 625 | /* Return negative errno on error. */ |
3fb21c64 | 626 | static s32 i801_access(struct i2c_adapter *adap, u16 addr, |
1da177e4 | 627 | unsigned short flags, char read_write, u8 command, |
3fb21c64 | 628 | int size, union i2c_smbus_data *data) |
1da177e4 | 629 | { |
e8aac4a9 | 630 | int hwpec; |
1da177e4 LT |
631 | int block = 0; |
632 | int ret, xact = 0; | |
0cd96eb0 | 633 | struct i801_priv *priv = i2c_get_adapdata(adap); |
1da177e4 | 634 | |
0cd96eb0 | 635 | hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) |
e8aac4a9 JD |
636 | && size != I2C_SMBUS_QUICK |
637 | && size != I2C_SMBUS_I2C_BLOCK_DATA; | |
1da177e4 LT |
638 | |
639 | switch (size) { | |
640 | case I2C_SMBUS_QUICK: | |
641 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 642 | SMBHSTADD(priv)); |
1da177e4 LT |
643 | xact = I801_QUICK; |
644 | break; | |
645 | case I2C_SMBUS_BYTE: | |
646 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 647 | SMBHSTADD(priv)); |
1da177e4 | 648 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 649 | outb_p(command, SMBHSTCMD(priv)); |
1da177e4 LT |
650 | xact = I801_BYTE; |
651 | break; | |
652 | case I2C_SMBUS_BYTE_DATA: | |
653 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
654 | SMBHSTADD(priv)); |
655 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 656 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 657 | outb_p(data->byte, SMBHSTDAT0(priv)); |
1da177e4 LT |
658 | xact = I801_BYTE_DATA; |
659 | break; | |
660 | case I2C_SMBUS_WORD_DATA: | |
661 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
662 | SMBHSTADD(priv)); |
663 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 664 | if (read_write == I2C_SMBUS_WRITE) { |
0cd96eb0 DW |
665 | outb_p(data->word & 0xff, SMBHSTDAT0(priv)); |
666 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); | |
1da177e4 LT |
667 | } |
668 | xact = I801_WORD_DATA; | |
669 | break; | |
670 | case I2C_SMBUS_BLOCK_DATA: | |
1da177e4 | 671 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), |
0cd96eb0 DW |
672 | SMBHSTADD(priv)); |
673 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 LT |
674 | block = 1; |
675 | break; | |
6342064c JD |
676 | case I2C_SMBUS_I2C_BLOCK_DATA: |
677 | /* NB: page 240 of ICH5 datasheet shows that the R/#W | |
678 | * bit should be cleared here, even when reading */ | |
0cd96eb0 | 679 | outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); |
6342064c JD |
680 | if (read_write == I2C_SMBUS_READ) { |
681 | /* NB: page 240 of ICH5 datasheet also shows | |
682 | * that DATA1 is the cmd field when reading */ | |
0cd96eb0 | 683 | outb_p(command, SMBHSTDAT1(priv)); |
6342064c | 684 | } else |
0cd96eb0 | 685 | outb_p(command, SMBHSTCMD(priv)); |
6342064c JD |
686 | block = 1; |
687 | break; | |
1da177e4 | 688 | default: |
0cd96eb0 DW |
689 | dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", |
690 | size); | |
97140342 | 691 | return -EOPNOTSUPP; |
1da177e4 LT |
692 | } |
693 | ||
ca8b9e32 | 694 | if (hwpec) /* enable/disable hardware PEC */ |
0cd96eb0 | 695 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); |
ca8b9e32 | 696 | else |
0cd96eb0 DW |
697 | outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), |
698 | SMBAUXCTL(priv)); | |
e8aac4a9 | 699 | |
3fb21c64 | 700 | if (block) |
0cd96eb0 DW |
701 | ret = i801_block_transaction(priv, data, read_write, size, |
702 | hwpec); | |
7edcb9ab | 703 | else |
37af8711 | 704 | ret = i801_transaction(priv, xact); |
1da177e4 | 705 | |
c79cfbac | 706 | /* Some BIOSes don't like it when PEC is enabled at reboot or resume |
7edcb9ab OR |
707 | time, so we forcibly disable it after every transaction. Turn off |
708 | E32B for the same reason. */ | |
a0921b6c | 709 | if (hwpec || block) |
0cd96eb0 DW |
710 | outb_p(inb_p(SMBAUXCTL(priv)) & |
711 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
c79cfbac | 712 | |
3fb21c64 | 713 | if (block) |
1da177e4 | 714 | return ret; |
3fb21c64 | 715 | if (ret) |
97140342 | 716 | return ret; |
1da177e4 LT |
717 | if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) |
718 | return 0; | |
719 | ||
720 | switch (xact & 0x7f) { | |
721 | case I801_BYTE: /* Result put in SMBHSTDAT0 */ | |
722 | case I801_BYTE_DATA: | |
0cd96eb0 | 723 | data->byte = inb_p(SMBHSTDAT0(priv)); |
1da177e4 LT |
724 | break; |
725 | case I801_WORD_DATA: | |
0cd96eb0 DW |
726 | data->word = inb_p(SMBHSTDAT0(priv)) + |
727 | (inb_p(SMBHSTDAT1(priv)) << 8); | |
1da177e4 LT |
728 | break; |
729 | } | |
730 | return 0; | |
731 | } | |
732 | ||
733 | ||
734 | static u32 i801_func(struct i2c_adapter *adapter) | |
735 | { | |
0cd96eb0 DW |
736 | struct i801_priv *priv = i2c_get_adapdata(adapter); |
737 | ||
1da177e4 | 738 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | |
369f6f4a JD |
739 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | |
740 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | | |
0cd96eb0 DW |
741 | ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | |
742 | ((priv->features & FEATURE_I2C_BLOCK_READ) ? | |
6342064c | 743 | I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0); |
1da177e4 LT |
744 | } |
745 | ||
8f9082c5 | 746 | static const struct i2c_algorithm smbus_algorithm = { |
1da177e4 LT |
747 | .smbus_xfer = i801_access, |
748 | .functionality = i801_func, | |
749 | }; | |
750 | ||
3527bd50 | 751 | static DEFINE_PCI_DEVICE_TABLE(i801_ids) = { |
1da177e4 LT |
752 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, |
753 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, | |
754 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, | |
755 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, | |
756 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, | |
757 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, | |
758 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, | |
759 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, | |
760 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, | |
b0a70b57 | 761 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, |
8254fc4a | 762 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, |
adbc2a10 | 763 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, |
cb04e95b | 764 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, |
d28dc711 GJ |
765 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, |
766 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, | |
cb04e95b SH |
767 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, |
768 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, | |
e30d9859 | 769 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, |
55fee8d7 DW |
770 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, |
771 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, | |
772 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, | |
662cda8a | 773 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, |
6e2a851e | 774 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, |
062737fb | 775 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, |
4a8f1ddd | 776 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, |
1da177e4 LT |
777 | { 0, } |
778 | }; | |
779 | ||
3fb21c64 | 780 | MODULE_DEVICE_TABLE(pci, i801_ids); |
1da177e4 | 781 | |
8eacfceb | 782 | #if defined CONFIG_X86 && defined CONFIG_DMI |
1561bfe5 JD |
783 | static unsigned char apanel_addr; |
784 | ||
785 | /* Scan the system ROM for the signature "FJKEYINF" */ | |
786 | static __init const void __iomem *bios_signature(const void __iomem *bios) | |
787 | { | |
788 | ssize_t offset; | |
789 | const unsigned char signature[] = "FJKEYINF"; | |
790 | ||
791 | for (offset = 0; offset < 0x10000; offset += 0x10) { | |
792 | if (check_signature(bios + offset, signature, | |
793 | sizeof(signature)-1)) | |
794 | return bios + offset; | |
795 | } | |
796 | return NULL; | |
797 | } | |
798 | ||
799 | static void __init input_apanel_init(void) | |
800 | { | |
801 | void __iomem *bios; | |
802 | const void __iomem *p; | |
803 | ||
804 | bios = ioremap(0xF0000, 0x10000); /* Can't fail */ | |
805 | p = bios_signature(bios); | |
806 | if (p) { | |
807 | /* just use the first address */ | |
808 | apanel_addr = readb(p + 8 + 3) >> 1; | |
809 | } | |
810 | iounmap(bios); | |
811 | } | |
1561bfe5 | 812 | |
fa5bfab7 HG |
813 | struct dmi_onboard_device_info { |
814 | const char *name; | |
815 | u8 type; | |
816 | unsigned short i2c_addr; | |
817 | const char *i2c_type; | |
818 | }; | |
819 | ||
820 | static struct dmi_onboard_device_info __devinitdata dmi_devices[] = { | |
821 | { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, | |
822 | { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, | |
823 | { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, | |
824 | }; | |
825 | ||
826 | static void __devinit dmi_check_onboard_device(u8 type, const char *name, | |
827 | struct i2c_adapter *adap) | |
828 | { | |
829 | int i; | |
830 | struct i2c_board_info info; | |
831 | ||
832 | for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { | |
833 | /* & ~0x80, ignore enabled/disabled bit */ | |
834 | if ((type & ~0x80) != dmi_devices[i].type) | |
835 | continue; | |
faabd47f | 836 | if (strcasecmp(name, dmi_devices[i].name)) |
fa5bfab7 HG |
837 | continue; |
838 | ||
839 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
840 | info.addr = dmi_devices[i].i2c_addr; | |
841 | strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); | |
842 | i2c_new_device(adap, &info); | |
843 | break; | |
844 | } | |
845 | } | |
846 | ||
847 | /* We use our own function to check for onboard devices instead of | |
848 | dmi_find_device() as some buggy BIOS's have the devices we are interested | |
849 | in marked as disabled */ | |
850 | static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm, | |
851 | void *adap) | |
852 | { | |
853 | int i, count; | |
854 | ||
855 | if (dm->type != 10) | |
856 | return; | |
857 | ||
858 | count = (dm->length - sizeof(struct dmi_header)) / 2; | |
859 | for (i = 0; i < count; i++) { | |
860 | const u8 *d = (char *)(dm + 1) + (i * 2); | |
861 | const char *name = ((char *) dm) + dm->length; | |
862 | u8 type = d[0]; | |
863 | u8 s = d[1]; | |
864 | ||
865 | if (!s) | |
866 | continue; | |
867 | s--; | |
868 | while (s > 0 && name[0]) { | |
869 | name += strlen(name) + 1; | |
870 | s--; | |
871 | } | |
872 | if (name[0] == 0) /* Bogus string reference */ | |
873 | continue; | |
874 | ||
875 | dmi_check_onboard_device(type, name, adap); | |
876 | } | |
877 | } | |
fa5bfab7 | 878 | |
e7198fbf JD |
879 | /* Register optional slaves */ |
880 | static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) | |
881 | { | |
882 | /* Only register slaves on main SMBus channel */ | |
883 | if (priv->features & FEATURE_IDF) | |
884 | return; | |
885 | ||
e7198fbf JD |
886 | if (apanel_addr) { |
887 | struct i2c_board_info info; | |
888 | ||
889 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
890 | info.addr = apanel_addr; | |
891 | strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); | |
892 | i2c_new_device(&priv->adapter, &info); | |
893 | } | |
8eacfceb | 894 | |
e7198fbf JD |
895 | if (dmi_name_in_vendors("FUJITSU")) |
896 | dmi_walk(dmi_check_onboard_devices, &priv->adapter); | |
e7198fbf | 897 | } |
8eacfceb JD |
898 | #else |
899 | static void __init input_apanel_init(void) {} | |
900 | static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {} | |
901 | #endif /* CONFIG_X86 && CONFIG_DMI */ | |
e7198fbf | 902 | |
3fb21c64 IM |
903 | static int __devinit i801_probe(struct pci_dev *dev, |
904 | const struct pci_device_id *id) | |
1da177e4 | 905 | { |
02dd7ae2 | 906 | unsigned char temp; |
adff687d | 907 | int err, i; |
0cd96eb0 DW |
908 | struct i801_priv *priv; |
909 | ||
910 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
911 | if (!priv) | |
912 | return -ENOMEM; | |
913 | ||
914 | i2c_set_adapdata(&priv->adapter, priv); | |
915 | priv->adapter.owner = THIS_MODULE; | |
916 | priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
917 | priv->adapter.algo = &smbus_algorithm; | |
1da177e4 | 918 | |
0cd96eb0 | 919 | priv->pci_dev = dev; |
250d1bd3 | 920 | switch (dev->device) { |
e7198fbf JD |
921 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: |
922 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: | |
923 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: | |
924 | priv->features |= FEATURE_IDF; | |
925 | /* fall through */ | |
e0e8398c | 926 | default: |
0cd96eb0 | 927 | priv->features |= FEATURE_I2C_BLOCK_READ; |
6342064c JD |
928 | /* fall through */ |
929 | case PCI_DEVICE_ID_INTEL_82801DB_3: | |
0cd96eb0 DW |
930 | priv->features |= FEATURE_SMBUS_PEC; |
931 | priv->features |= FEATURE_BLOCK_BUFFER; | |
e0e8398c JD |
932 | /* fall through */ |
933 | case PCI_DEVICE_ID_INTEL_82801CA_3: | |
934 | case PCI_DEVICE_ID_INTEL_82801BA_2: | |
935 | case PCI_DEVICE_ID_INTEL_82801AB_3: | |
936 | case PCI_DEVICE_ID_INTEL_82801AA_3: | |
250d1bd3 | 937 | break; |
250d1bd3 | 938 | } |
02dd7ae2 | 939 | |
29b60854 JD |
940 | /* IRQ processing tested on CougarPoint PCH, ICH5, ICH7-M and ICH10 */ |
941 | if (dev->device == PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS || | |
942 | dev->device == PCI_DEVICE_ID_INTEL_82801EB_3 || | |
943 | dev->device == PCI_DEVICE_ID_INTEL_ICH7_17 || | |
944 | dev->device == PCI_DEVICE_ID_INTEL_ICH8_5 || | |
945 | dev->device == PCI_DEVICE_ID_INTEL_ICH9_6 || | |
946 | dev->device == PCI_DEVICE_ID_INTEL_ICH10_4 || | |
947 | dev->device == PCI_DEVICE_ID_INTEL_ICH10_5) | |
636752bc DK |
948 | priv->features |= FEATURE_IRQ; |
949 | ||
adff687d JD |
950 | /* Disable features on user request */ |
951 | for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { | |
0cd96eb0 | 952 | if (priv->features & disable_features & (1 << i)) |
adff687d JD |
953 | dev_notice(&dev->dev, "%s disabled by user\n", |
954 | i801_feature_names[i]); | |
955 | } | |
0cd96eb0 | 956 | priv->features &= ~disable_features; |
adff687d | 957 | |
02dd7ae2 JD |
958 | err = pci_enable_device(dev); |
959 | if (err) { | |
960 | dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", | |
961 | err); | |
962 | goto exit; | |
963 | } | |
964 | ||
965 | /* Determine the address of the SMBus area */ | |
0cd96eb0 DW |
966 | priv->smba = pci_resource_start(dev, SMBBAR); |
967 | if (!priv->smba) { | |
02dd7ae2 JD |
968 | dev_err(&dev->dev, "SMBus base address uninitialized, " |
969 | "upgrade BIOS\n"); | |
970 | err = -ENODEV; | |
d6fcb3b9 | 971 | goto exit; |
02dd7ae2 JD |
972 | } |
973 | ||
54fb4a05 | 974 | err = acpi_check_resource_conflict(&dev->resource[SMBBAR]); |
18669eab JD |
975 | if (err) { |
976 | err = -ENODEV; | |
54fb4a05 | 977 | goto exit; |
18669eab | 978 | } |
54fb4a05 | 979 | |
02dd7ae2 JD |
980 | err = pci_request_region(dev, SMBBAR, i801_driver.name); |
981 | if (err) { | |
982 | dev_err(&dev->dev, "Failed to request SMBus region " | |
0cd96eb0 | 983 | "0x%lx-0x%Lx\n", priv->smba, |
598736c5 | 984 | (unsigned long long)pci_resource_end(dev, SMBBAR)); |
d6fcb3b9 | 985 | goto exit; |
02dd7ae2 JD |
986 | } |
987 | ||
0cd96eb0 DW |
988 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); |
989 | priv->original_hstcfg = temp; | |
02dd7ae2 JD |
990 | temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ |
991 | if (!(temp & SMBHSTCFG_HST_EN)) { | |
992 | dev_info(&dev->dev, "Enabling SMBus device\n"); | |
993 | temp |= SMBHSTCFG_HST_EN; | |
994 | } | |
0cd96eb0 | 995 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); |
02dd7ae2 | 996 | |
636752bc | 997 | if (temp & SMBHSTCFG_SMB_SMI_EN) { |
02dd7ae2 | 998 | dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); |
636752bc DK |
999 | /* Disable SMBus interrupt feature if SMBus using SMI# */ |
1000 | priv->features &= ~FEATURE_IRQ; | |
636752bc | 1001 | } |
1da177e4 | 1002 | |
a0921b6c | 1003 | /* Clear special mode bits */ |
0cd96eb0 DW |
1004 | if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) |
1005 | outb_p(inb_p(SMBAUXCTL(priv)) & | |
1006 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
a0921b6c | 1007 | |
636752bc DK |
1008 | if (priv->features & FEATURE_IRQ) { |
1009 | init_waitqueue_head(&priv->waitq); | |
1010 | ||
1011 | err = request_irq(dev->irq, i801_isr, IRQF_SHARED, | |
1012 | i801_driver.name, priv); | |
1013 | if (err) { | |
1014 | dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", | |
1015 | dev->irq, err); | |
1016 | goto exit_release; | |
1017 | } | |
29b60854 | 1018 | dev_info(&dev->dev, "SMBus using PCI Interrupt\n"); |
636752bc DK |
1019 | } |
1020 | ||
405ae7d3 | 1021 | /* set up the sysfs linkage to our parent device */ |
0cd96eb0 | 1022 | priv->adapter.dev.parent = &dev->dev; |
1da177e4 | 1023 | |
7e2193a8 | 1024 | /* Retry up to 3 times on lost arbitration */ |
0cd96eb0 | 1025 | priv->adapter.retries = 3; |
7e2193a8 | 1026 | |
0cd96eb0 DW |
1027 | snprintf(priv->adapter.name, sizeof(priv->adapter.name), |
1028 | "SMBus I801 adapter at %04lx", priv->smba); | |
1029 | err = i2c_add_adapter(&priv->adapter); | |
02dd7ae2 JD |
1030 | if (err) { |
1031 | dev_err(&dev->dev, "Failed to add SMBus adapter\n"); | |
636752bc | 1032 | goto exit_free_irq; |
02dd7ae2 | 1033 | } |
1561bfe5 | 1034 | |
e7198fbf | 1035 | i801_probe_optional_slaves(priv); |
1561bfe5 | 1036 | |
0cd96eb0 | 1037 | pci_set_drvdata(dev, priv); |
636752bc | 1038 | |
d6fcb3b9 | 1039 | return 0; |
02dd7ae2 | 1040 | |
636752bc DK |
1041 | exit_free_irq: |
1042 | if (priv->features & FEATURE_IRQ) | |
1043 | free_irq(dev->irq, priv); | |
d6fcb3b9 DR |
1044 | exit_release: |
1045 | pci_release_region(dev, SMBBAR); | |
02dd7ae2 | 1046 | exit: |
0cd96eb0 | 1047 | kfree(priv); |
02dd7ae2 | 1048 | return err; |
1da177e4 LT |
1049 | } |
1050 | ||
1051 | static void __devexit i801_remove(struct pci_dev *dev) | |
1052 | { | |
0cd96eb0 DW |
1053 | struct i801_priv *priv = pci_get_drvdata(dev); |
1054 | ||
1055 | i2c_del_adapter(&priv->adapter); | |
1056 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); | |
636752bc DK |
1057 | |
1058 | if (priv->features & FEATURE_IRQ) | |
1059 | free_irq(dev->irq, priv); | |
6dcc19df | 1060 | pci_release_region(dev, SMBBAR); |
636752bc | 1061 | |
0cd96eb0 DW |
1062 | pci_set_drvdata(dev, NULL); |
1063 | kfree(priv); | |
d6fcb3b9 DR |
1064 | /* |
1065 | * do not call pci_disable_device(dev) since it can cause hard hangs on | |
1066 | * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) | |
1067 | */ | |
1da177e4 LT |
1068 | } |
1069 | ||
a5aaea37 JD |
1070 | #ifdef CONFIG_PM |
1071 | static int i801_suspend(struct pci_dev *dev, pm_message_t mesg) | |
1072 | { | |
0cd96eb0 DW |
1073 | struct i801_priv *priv = pci_get_drvdata(dev); |
1074 | ||
a5aaea37 | 1075 | pci_save_state(dev); |
0cd96eb0 | 1076 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); |
a5aaea37 JD |
1077 | pci_set_power_state(dev, pci_choose_state(dev, mesg)); |
1078 | return 0; | |
1079 | } | |
1080 | ||
1081 | static int i801_resume(struct pci_dev *dev) | |
1082 | { | |
1083 | pci_set_power_state(dev, PCI_D0); | |
1084 | pci_restore_state(dev); | |
1085 | return pci_enable_device(dev); | |
1086 | } | |
1087 | #else | |
1088 | #define i801_suspend NULL | |
1089 | #define i801_resume NULL | |
1090 | #endif | |
1091 | ||
1da177e4 LT |
1092 | static struct pci_driver i801_driver = { |
1093 | .name = "i801_smbus", | |
1094 | .id_table = i801_ids, | |
1095 | .probe = i801_probe, | |
1096 | .remove = __devexit_p(i801_remove), | |
a5aaea37 JD |
1097 | .suspend = i801_suspend, |
1098 | .resume = i801_resume, | |
1da177e4 LT |
1099 | }; |
1100 | ||
1101 | static int __init i2c_i801_init(void) | |
1102 | { | |
6aa1464d JD |
1103 | if (dmi_name_in_vendors("FUJITSU")) |
1104 | input_apanel_init(); | |
1da177e4 LT |
1105 | return pci_register_driver(&i801_driver); |
1106 | } | |
1107 | ||
1108 | static void __exit i2c_i801_exit(void) | |
1109 | { | |
1110 | pci_unregister_driver(&i801_driver); | |
1111 | } | |
1112 | ||
6342064c JD |
1113 | MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, " |
1114 | "Jean Delvare <khali@linux-fr.org>"); | |
1da177e4 LT |
1115 | MODULE_DESCRIPTION("I801 SMBus driver"); |
1116 | MODULE_LICENSE("GPL"); | |
1117 | ||
1118 | module_init(i2c_i801_init); | |
1119 | module_exit(i2c_i801_exit); |