Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, |
3 | Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker | |
4 | <mdsxyz123@yahoo.com> | |
84c1af4c | 5 | Copyright (C) 2007 - 2012 Jean Delvare <khali@linux-fr.org> |
0cd96eb0 DW |
6 | Copyright (C) 2010 Intel Corporation, |
7 | David Woodhouse <dwmw2@infradead.org> | |
1da177e4 LT |
8 | |
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | */ | |
23 | ||
24 | /* | |
ae7b0497 JD |
25 | Supports the following Intel I/O Controller Hubs (ICH): |
26 | ||
27 | I/O Block I2C | |
28 | region SMBus Block proc. block | |
29 | Chip name PCI ID size PEC buffer call read | |
30 | ---------------------------------------------------------------------- | |
31 | 82801AA (ICH) 0x2413 16 no no no no | |
32 | 82801AB (ICH0) 0x2423 16 no no no no | |
33 | 82801BA (ICH2) 0x2443 16 no no no no | |
34 | 82801CA (ICH3) 0x2483 32 soft no no no | |
35 | 82801DB (ICH4) 0x24c3 32 hard yes no no | |
36 | 82801E (ICH5) 0x24d3 32 hard yes yes yes | |
37 | 6300ESB 0x25a4 32 hard yes yes yes | |
38 | 82801F (ICH6) 0x266a 32 hard yes yes yes | |
39 | 6310ESB/6320ESB 0x269b 32 hard yes yes yes | |
40 | 82801G (ICH7) 0x27da 32 hard yes yes yes | |
41 | 82801H (ICH8) 0x283e 32 hard yes yes yes | |
42 | 82801I (ICH9) 0x2930 32 hard yes yes yes | |
cb04e95b | 43 | EP80579 (Tolapai) 0x5032 32 hard yes yes yes |
d28dc711 GJ |
44 | ICH10 0x3a30 32 hard yes yes yes |
45 | ICH10 0x3a60 32 hard yes yes yes | |
cb04e95b | 46 | 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes |
662cda8a | 47 | 6 Series (PCH) 0x1c22 32 hard yes yes yes |
e30d9859 | 48 | Patsburg (PCH) 0x1d22 32 hard yes yes yes |
55fee8d7 DW |
49 | Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes |
50 | Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes | |
51 | Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes | |
662cda8a | 52 | DH89xxCC (PCH) 0x2330 32 hard yes yes yes |
6e2a851e | 53 | Panther Point (PCH) 0x1e22 32 hard yes yes yes |
062737fb | 54 | Lynx Point (PCH) 0x8c22 32 hard yes yes yes |
ae7b0497 JD |
55 | |
56 | Features supported by this driver: | |
57 | Software PEC no | |
58 | Hardware PEC yes | |
59 | Block buffer yes | |
60 | Block process call transaction no | |
6342064c | 61 | I2C block read transaction yes (doesn't use the block buffer) |
55fee8d7 | 62 | Slave mode no |
ae7b0497 JD |
63 | |
64 | See the file Documentation/i2c/busses/i2c-i801 for details. | |
1da177e4 LT |
65 | */ |
66 | ||
1da177e4 LT |
67 | #include <linux/module.h> |
68 | #include <linux/pci.h> | |
69 | #include <linux/kernel.h> | |
70 | #include <linux/stddef.h> | |
71 | #include <linux/delay.h> | |
1da177e4 LT |
72 | #include <linux/ioport.h> |
73 | #include <linux/init.h> | |
74 | #include <linux/i2c.h> | |
54fb4a05 | 75 | #include <linux/acpi.h> |
1561bfe5 | 76 | #include <linux/io.h> |
fa5bfab7 | 77 | #include <linux/dmi.h> |
665a96b7 | 78 | #include <linux/slab.h> |
1da177e4 | 79 | |
1da177e4 | 80 | /* I801 SMBus address offsets */ |
0cd96eb0 DW |
81 | #define SMBHSTSTS(p) (0 + (p)->smba) |
82 | #define SMBHSTCNT(p) (2 + (p)->smba) | |
83 | #define SMBHSTCMD(p) (3 + (p)->smba) | |
84 | #define SMBHSTADD(p) (4 + (p)->smba) | |
85 | #define SMBHSTDAT0(p) (5 + (p)->smba) | |
86 | #define SMBHSTDAT1(p) (6 + (p)->smba) | |
87 | #define SMBBLKDAT(p) (7 + (p)->smba) | |
88 | #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ | |
89 | #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ | |
90 | #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ | |
1da177e4 LT |
91 | |
92 | /* PCI Address Constants */ | |
6dcc19df | 93 | #define SMBBAR 4 |
1da177e4 | 94 | #define SMBHSTCFG 0x040 |
1da177e4 LT |
95 | |
96 | /* Host configuration bits for SMBHSTCFG */ | |
97 | #define SMBHSTCFG_HST_EN 1 | |
98 | #define SMBHSTCFG_SMB_SMI_EN 2 | |
99 | #define SMBHSTCFG_I2C_EN 4 | |
100 | ||
25985edc | 101 | /* Auxiliary control register bits, ICH4+ only */ |
ca8b9e32 OR |
102 | #define SMBAUXCTL_CRC 1 |
103 | #define SMBAUXCTL_E32B 2 | |
104 | ||
1da177e4 | 105 | /* Other settings */ |
84c1af4c | 106 | #define MAX_RETRIES 400 |
1da177e4 LT |
107 | #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */ |
108 | ||
109 | /* I801 command constants */ | |
110 | #define I801_QUICK 0x00 | |
111 | #define I801_BYTE 0x04 | |
112 | #define I801_BYTE_DATA 0x08 | |
113 | #define I801_WORD_DATA 0x0C | |
ae7b0497 | 114 | #define I801_PROC_CALL 0x10 /* unimplemented */ |
1da177e4 | 115 | #define I801_BLOCK_DATA 0x14 |
6342064c | 116 | #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ |
edbeea63 DK |
117 | |
118 | /* I801 Host Control register bits */ | |
119 | #define SMBHSTCNT_INTREN 0x01 | |
120 | #define SMBHSTCNT_KILL 0x02 | |
121 | #define SMBHSTCNT_LAST_BYTE 0x20 | |
122 | #define SMBHSTCNT_START 0x40 | |
123 | #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */ | |
1da177e4 | 124 | |
ca8b9e32 OR |
125 | /* I801 Hosts Status register bits */ |
126 | #define SMBHSTSTS_BYTE_DONE 0x80 | |
127 | #define SMBHSTSTS_INUSE_STS 0x40 | |
128 | #define SMBHSTSTS_SMBALERT_STS 0x20 | |
129 | #define SMBHSTSTS_FAILED 0x10 | |
130 | #define SMBHSTSTS_BUS_ERR 0x08 | |
131 | #define SMBHSTSTS_DEV_ERR 0x04 | |
132 | #define SMBHSTSTS_INTR 0x02 | |
133 | #define SMBHSTSTS_HOST_BUSY 0x01 | |
1da177e4 | 134 | |
70a1cc19 DK |
135 | #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ |
136 | SMBHSTSTS_DEV_ERR) | |
137 | ||
138 | #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ | |
139 | STATUS_ERROR_FLAGS) | |
cf898dc5 | 140 | |
a6e5e2be JD |
141 | /* Older devices have their ID defined in <linux/pci_ids.h> */ |
142 | #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 | |
143 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 | |
55fee8d7 DW |
144 | /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ |
145 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 | |
146 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 | |
147 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 | |
6e2a851e | 148 | #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 |
a6e5e2be JD |
149 | #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 |
150 | #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 | |
062737fb | 151 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 |
55fee8d7 | 152 | |
0cd96eb0 DW |
153 | struct i801_priv { |
154 | struct i2c_adapter adapter; | |
155 | unsigned long smba; | |
156 | unsigned char original_hstcfg; | |
157 | struct pci_dev *pci_dev; | |
158 | unsigned int features; | |
159 | }; | |
160 | ||
d6072f84 | 161 | static struct pci_driver i801_driver; |
369f6f4a JD |
162 | |
163 | #define FEATURE_SMBUS_PEC (1 << 0) | |
164 | #define FEATURE_BLOCK_BUFFER (1 << 1) | |
165 | #define FEATURE_BLOCK_PROC (1 << 2) | |
166 | #define FEATURE_I2C_BLOCK_READ (1 << 3) | |
e7198fbf JD |
167 | /* Not really a feature, but it's convenient to handle it as such */ |
168 | #define FEATURE_IDF (1 << 15) | |
1da177e4 | 169 | |
adff687d JD |
170 | static const char *i801_feature_names[] = { |
171 | "SMBus PEC", | |
172 | "Block buffer", | |
173 | "Block process call", | |
174 | "I2C block read", | |
175 | }; | |
176 | ||
177 | static unsigned int disable_features; | |
178 | module_param(disable_features, uint, S_IRUGO | S_IWUSR); | |
179 | MODULE_PARM_DESC(disable_features, "Disable selected driver features"); | |
180 | ||
cf898dc5 JD |
181 | /* Make sure the SMBus host is ready to start transmitting. |
182 | Return 0 if it is, -EBUSY if it is not. */ | |
0cd96eb0 | 183 | static int i801_check_pre(struct i801_priv *priv) |
1da177e4 | 184 | { |
2b73809d | 185 | int status; |
1da177e4 | 186 | |
0cd96eb0 | 187 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 | 188 | if (status & SMBHSTSTS_HOST_BUSY) { |
0cd96eb0 | 189 | dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); |
cf898dc5 JD |
190 | return -EBUSY; |
191 | } | |
192 | ||
193 | status &= STATUS_FLAGS; | |
194 | if (status) { | |
0cd96eb0 | 195 | dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", |
2b73809d | 196 | status); |
0cd96eb0 DW |
197 | outb_p(status, SMBHSTSTS(priv)); |
198 | status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; | |
cf898dc5 | 199 | if (status) { |
0cd96eb0 | 200 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
201 | "Failed clearing status flags (%02x)\n", |
202 | status); | |
97140342 | 203 | return -EBUSY; |
1da177e4 LT |
204 | } |
205 | } | |
206 | ||
cf898dc5 JD |
207 | return 0; |
208 | } | |
1da177e4 | 209 | |
cf898dc5 | 210 | /* Convert the status register to an error code, and clear it. */ |
0cd96eb0 | 211 | static int i801_check_post(struct i801_priv *priv, int status, int timeout) |
cf898dc5 JD |
212 | { |
213 | int result = 0; | |
1da177e4 LT |
214 | |
215 | /* If the SMBus is still busy, we give up */ | |
cf898dc5 | 216 | if (timeout) { |
0cd96eb0 | 217 | dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); |
ca8b9e32 | 218 | /* try to stop the current command */ |
0cd96eb0 DW |
219 | dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); |
220 | outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, | |
221 | SMBHSTCNT(priv)); | |
84c1af4c | 222 | usleep_range(1000, 2000); |
0cd96eb0 DW |
223 | outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), |
224 | SMBHSTCNT(priv)); | |
cf898dc5 JD |
225 | |
226 | /* Check if it worked */ | |
0cd96eb0 | 227 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 JD |
228 | if ((status & SMBHSTSTS_HOST_BUSY) || |
229 | !(status & SMBHSTSTS_FAILED)) | |
0cd96eb0 | 230 | dev_err(&priv->pci_dev->dev, |
cf898dc5 | 231 | "Failed terminating the transaction\n"); |
0cd96eb0 | 232 | outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); |
cf898dc5 | 233 | return -ETIMEDOUT; |
1da177e4 LT |
234 | } |
235 | ||
2b73809d | 236 | if (status & SMBHSTSTS_FAILED) { |
97140342 | 237 | result = -EIO; |
0cd96eb0 | 238 | dev_err(&priv->pci_dev->dev, "Transaction failed\n"); |
cf898dc5 JD |
239 | } |
240 | if (status & SMBHSTSTS_DEV_ERR) { | |
241 | result = -ENXIO; | |
0cd96eb0 | 242 | dev_dbg(&priv->pci_dev->dev, "No response\n"); |
1da177e4 | 243 | } |
2b73809d | 244 | if (status & SMBHSTSTS_BUS_ERR) { |
dcb5c923 | 245 | result = -EAGAIN; |
0cd96eb0 | 246 | dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); |
1da177e4 LT |
247 | } |
248 | ||
cf898dc5 JD |
249 | if (result) { |
250 | /* Clear error flags */ | |
0cd96eb0 DW |
251 | outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv)); |
252 | status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; | |
cf898dc5 | 253 | if (status) { |
0cd96eb0 | 254 | dev_warn(&priv->pci_dev->dev, "Failed clearing status " |
cf898dc5 JD |
255 | "flags at end of transaction (%02x)\n", |
256 | status); | |
257 | } | |
1da177e4 LT |
258 | } |
259 | ||
1da177e4 LT |
260 | return result; |
261 | } | |
262 | ||
0cd96eb0 | 263 | static int i801_transaction(struct i801_priv *priv, int xact) |
cf898dc5 JD |
264 | { |
265 | int status; | |
266 | int result; | |
267 | int timeout = 0; | |
268 | ||
0cd96eb0 | 269 | result = i801_check_pre(priv); |
cf898dc5 JD |
270 | if (result < 0) |
271 | return result; | |
272 | ||
273 | /* the current contents of SMBHSTCNT can be overwritten, since PEC, | |
274 | * INTREN, SMBSCMD are passed in xact */ | |
edbeea63 | 275 | outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); |
cf898dc5 JD |
276 | |
277 | /* We will always wait for a fraction of a second! */ | |
278 | do { | |
84c1af4c | 279 | usleep_range(250, 500); |
0cd96eb0 | 280 | status = inb_p(SMBHSTSTS(priv)); |
84c1af4c | 281 | } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_RETRIES)); |
cf898dc5 | 282 | |
84c1af4c | 283 | result = i801_check_post(priv, status, timeout > MAX_RETRIES); |
cf898dc5 JD |
284 | if (result < 0) |
285 | return result; | |
286 | ||
0cd96eb0 | 287 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); |
cf898dc5 JD |
288 | return 0; |
289 | } | |
290 | ||
ca8b9e32 | 291 | /* wait for INTR bit as advised by Intel */ |
0cd96eb0 | 292 | static void i801_wait_hwpec(struct i801_priv *priv) |
ca8b9e32 OR |
293 | { |
294 | int timeout = 0; | |
2b73809d | 295 | int status; |
ca8b9e32 OR |
296 | |
297 | do { | |
84c1af4c | 298 | usleep_range(250, 500); |
0cd96eb0 | 299 | status = inb_p(SMBHSTSTS(priv)); |
2b73809d | 300 | } while ((!(status & SMBHSTSTS_INTR)) |
84c1af4c | 301 | && (timeout++ < MAX_RETRIES)); |
ca8b9e32 | 302 | |
84c1af4c | 303 | if (timeout > MAX_RETRIES) |
0cd96eb0 | 304 | dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n"); |
4ccc28f7 | 305 | |
0ba8b8bf | 306 | outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv)); |
ca8b9e32 OR |
307 | } |
308 | ||
0cd96eb0 DW |
309 | static int i801_block_transaction_by_block(struct i801_priv *priv, |
310 | union i2c_smbus_data *data, | |
7edcb9ab OR |
311 | char read_write, int hwpec) |
312 | { | |
313 | int i, len; | |
97140342 | 314 | int status; |
7edcb9ab | 315 | |
0cd96eb0 | 316 | inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ |
7edcb9ab OR |
317 | |
318 | /* Use 32-byte buffer to process this transaction */ | |
319 | if (read_write == I2C_SMBUS_WRITE) { | |
320 | len = data->block[0]; | |
0cd96eb0 | 321 | outb_p(len, SMBHSTDAT0(priv)); |
7edcb9ab | 322 | for (i = 0; i < len; i++) |
0cd96eb0 | 323 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
7edcb9ab OR |
324 | } |
325 | ||
0cd96eb0 | 326 | status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 | |
edbeea63 | 327 | (hwpec ? SMBHSTCNT_PEC_EN : 0)); |
97140342 DB |
328 | if (status) |
329 | return status; | |
7edcb9ab OR |
330 | |
331 | if (read_write == I2C_SMBUS_READ) { | |
0cd96eb0 | 332 | len = inb_p(SMBHSTDAT0(priv)); |
7edcb9ab | 333 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) |
97140342 | 334 | return -EPROTO; |
7edcb9ab OR |
335 | |
336 | data->block[0] = len; | |
337 | for (i = 0; i < len; i++) | |
0cd96eb0 | 338 | data->block[i + 1] = inb_p(SMBBLKDAT(priv)); |
7edcb9ab OR |
339 | } |
340 | return 0; | |
341 | } | |
342 | ||
efa3cb15 DK |
343 | /* |
344 | * For "byte-by-byte" block transactions: | |
345 | * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 | |
346 | * I2C read uses cmd=I801_I2C_BLOCK_DATA | |
347 | */ | |
0cd96eb0 DW |
348 | static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, |
349 | union i2c_smbus_data *data, | |
6342064c JD |
350 | char read_write, int command, |
351 | int hwpec) | |
1da177e4 LT |
352 | { |
353 | int i, len; | |
354 | int smbcmd; | |
2b73809d | 355 | int status; |
cf898dc5 | 356 | int result; |
1da177e4 | 357 | int timeout; |
cf898dc5 | 358 | |
0cd96eb0 | 359 | result = i801_check_pre(priv); |
cf898dc5 JD |
360 | if (result < 0) |
361 | return result; | |
1da177e4 | 362 | |
7edcb9ab | 363 | len = data->block[0]; |
1da177e4 LT |
364 | |
365 | if (read_write == I2C_SMBUS_WRITE) { | |
0cd96eb0 DW |
366 | outb_p(len, SMBHSTDAT0(priv)); |
367 | outb_p(data->block[1], SMBBLKDAT(priv)); | |
1da177e4 LT |
368 | } |
369 | ||
efa3cb15 DK |
370 | if (command == I2C_SMBUS_I2C_BLOCK_DATA && |
371 | read_write == I2C_SMBUS_READ) | |
372 | smbcmd = I801_I2C_BLOCK_DATA; | |
373 | else | |
374 | smbcmd = I801_BLOCK_DATA; | |
375 | ||
1da177e4 | 376 | for (i = 1; i <= len; i++) { |
efa3cb15 | 377 | if (i == len && read_write == I2C_SMBUS_READ) |
edbeea63 | 378 | smbcmd |= SMBHSTCNT_LAST_BYTE; |
0cd96eb0 | 379 | outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv)); |
1da177e4 | 380 | |
1da177e4 | 381 | if (i == 1) |
edbeea63 | 382 | outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, |
0cd96eb0 | 383 | SMBHSTCNT(priv)); |
1da177e4 LT |
384 | |
385 | /* We will always wait for a fraction of a second! */ | |
386 | timeout = 0; | |
387 | do { | |
84c1af4c | 388 | usleep_range(250, 500); |
0cd96eb0 | 389 | status = inb_p(SMBHSTSTS(priv)); |
70a1cc19 | 390 | } while (!(status & (SMBHSTSTS_BYTE_DONE | STATUS_ERROR_FLAGS)) |
84c1af4c | 391 | && (timeout++ < MAX_RETRIES)); |
1da177e4 | 392 | |
84c1af4c | 393 | result = i801_check_post(priv, status, timeout > MAX_RETRIES); |
cf898dc5 JD |
394 | if (result < 0) |
395 | return result; | |
1da177e4 | 396 | |
6342064c JD |
397 | if (i == 1 && read_write == I2C_SMBUS_READ |
398 | && command != I2C_SMBUS_I2C_BLOCK_DATA) { | |
0cd96eb0 | 399 | len = inb_p(SMBHSTDAT0(priv)); |
cf898dc5 | 400 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { |
0cd96eb0 | 401 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
402 | "Illegal SMBus block read size %d\n", |
403 | len); | |
404 | /* Recover */ | |
0cd96eb0 DW |
405 | while (inb_p(SMBHSTSTS(priv)) & |
406 | SMBHSTSTS_HOST_BUSY) | |
407 | outb_p(SMBHSTSTS_BYTE_DONE, | |
408 | SMBHSTSTS(priv)); | |
409 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); | |
97140342 | 410 | return -EPROTO; |
cf898dc5 | 411 | } |
1da177e4 LT |
412 | data->block[0] = len; |
413 | } | |
414 | ||
415 | /* Retrieve/store value in SMBBLKDAT */ | |
416 | if (read_write == I2C_SMBUS_READ) | |
0cd96eb0 | 417 | data->block[i] = inb_p(SMBBLKDAT(priv)); |
1da177e4 | 418 | if (read_write == I2C_SMBUS_WRITE && i+1 <= len) |
0cd96eb0 | 419 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
1da177e4 | 420 | |
cf898dc5 | 421 | /* signals SMBBLKDAT ready */ |
0cd96eb0 | 422 | outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv)); |
1da177e4 | 423 | } |
cf898dc5 JD |
424 | |
425 | return 0; | |
7edcb9ab | 426 | } |
1da177e4 | 427 | |
0cd96eb0 | 428 | static int i801_set_block_buffer_mode(struct i801_priv *priv) |
7edcb9ab | 429 | { |
0cd96eb0 DW |
430 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); |
431 | if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) | |
97140342 | 432 | return -EIO; |
7edcb9ab OR |
433 | return 0; |
434 | } | |
435 | ||
436 | /* Block transaction function */ | |
0cd96eb0 DW |
437 | static int i801_block_transaction(struct i801_priv *priv, |
438 | union i2c_smbus_data *data, char read_write, | |
7edcb9ab OR |
439 | int command, int hwpec) |
440 | { | |
441 | int result = 0; | |
442 | unsigned char hostc; | |
443 | ||
444 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
445 | if (read_write == I2C_SMBUS_WRITE) { | |
446 | /* set I2C_EN bit in configuration register */ | |
0cd96eb0 DW |
447 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); |
448 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, | |
7edcb9ab | 449 | hostc | SMBHSTCFG_I2C_EN); |
0cd96eb0 DW |
450 | } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { |
451 | dev_err(&priv->pci_dev->dev, | |
6342064c | 452 | "I2C block read is unsupported!\n"); |
97140342 | 453 | return -EOPNOTSUPP; |
7edcb9ab OR |
454 | } |
455 | } | |
456 | ||
6342064c JD |
457 | if (read_write == I2C_SMBUS_WRITE |
458 | || command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
7edcb9ab OR |
459 | if (data->block[0] < 1) |
460 | data->block[0] = 1; | |
461 | if (data->block[0] > I2C_SMBUS_BLOCK_MAX) | |
462 | data->block[0] = I2C_SMBUS_BLOCK_MAX; | |
463 | } else { | |
6342064c | 464 | data->block[0] = 32; /* max for SMBus block reads */ |
7edcb9ab OR |
465 | } |
466 | ||
c074c39d JD |
467 | /* Experience has shown that the block buffer can only be used for |
468 | SMBus (not I2C) block transactions, even though the datasheet | |
469 | doesn't mention this limitation. */ | |
0cd96eb0 | 470 | if ((priv->features & FEATURE_BLOCK_BUFFER) |
c074c39d | 471 | && command != I2C_SMBUS_I2C_BLOCK_DATA |
0cd96eb0 DW |
472 | && i801_set_block_buffer_mode(priv) == 0) |
473 | result = i801_block_transaction_by_block(priv, data, | |
474 | read_write, hwpec); | |
7edcb9ab | 475 | else |
0cd96eb0 DW |
476 | result = i801_block_transaction_byte_by_byte(priv, data, |
477 | read_write, | |
6342064c | 478 | command, hwpec); |
7edcb9ab OR |
479 | |
480 | if (result == 0 && hwpec) | |
0cd96eb0 | 481 | i801_wait_hwpec(priv); |
1da177e4 | 482 | |
6342064c JD |
483 | if (command == I2C_SMBUS_I2C_BLOCK_DATA |
484 | && read_write == I2C_SMBUS_WRITE) { | |
1da177e4 | 485 | /* restore saved configuration register value */ |
0cd96eb0 | 486 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); |
1da177e4 LT |
487 | } |
488 | return result; | |
489 | } | |
490 | ||
97140342 | 491 | /* Return negative errno on error. */ |
3fb21c64 | 492 | static s32 i801_access(struct i2c_adapter *adap, u16 addr, |
1da177e4 | 493 | unsigned short flags, char read_write, u8 command, |
3fb21c64 | 494 | int size, union i2c_smbus_data *data) |
1da177e4 | 495 | { |
e8aac4a9 | 496 | int hwpec; |
1da177e4 LT |
497 | int block = 0; |
498 | int ret, xact = 0; | |
0cd96eb0 | 499 | struct i801_priv *priv = i2c_get_adapdata(adap); |
1da177e4 | 500 | |
0cd96eb0 | 501 | hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) |
e8aac4a9 JD |
502 | && size != I2C_SMBUS_QUICK |
503 | && size != I2C_SMBUS_I2C_BLOCK_DATA; | |
1da177e4 LT |
504 | |
505 | switch (size) { | |
506 | case I2C_SMBUS_QUICK: | |
507 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 508 | SMBHSTADD(priv)); |
1da177e4 LT |
509 | xact = I801_QUICK; |
510 | break; | |
511 | case I2C_SMBUS_BYTE: | |
512 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 513 | SMBHSTADD(priv)); |
1da177e4 | 514 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 515 | outb_p(command, SMBHSTCMD(priv)); |
1da177e4 LT |
516 | xact = I801_BYTE; |
517 | break; | |
518 | case I2C_SMBUS_BYTE_DATA: | |
519 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
520 | SMBHSTADD(priv)); |
521 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 522 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 523 | outb_p(data->byte, SMBHSTDAT0(priv)); |
1da177e4 LT |
524 | xact = I801_BYTE_DATA; |
525 | break; | |
526 | case I2C_SMBUS_WORD_DATA: | |
527 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
528 | SMBHSTADD(priv)); |
529 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 530 | if (read_write == I2C_SMBUS_WRITE) { |
0cd96eb0 DW |
531 | outb_p(data->word & 0xff, SMBHSTDAT0(priv)); |
532 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); | |
1da177e4 LT |
533 | } |
534 | xact = I801_WORD_DATA; | |
535 | break; | |
536 | case I2C_SMBUS_BLOCK_DATA: | |
1da177e4 | 537 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), |
0cd96eb0 DW |
538 | SMBHSTADD(priv)); |
539 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 LT |
540 | block = 1; |
541 | break; | |
6342064c JD |
542 | case I2C_SMBUS_I2C_BLOCK_DATA: |
543 | /* NB: page 240 of ICH5 datasheet shows that the R/#W | |
544 | * bit should be cleared here, even when reading */ | |
0cd96eb0 | 545 | outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); |
6342064c JD |
546 | if (read_write == I2C_SMBUS_READ) { |
547 | /* NB: page 240 of ICH5 datasheet also shows | |
548 | * that DATA1 is the cmd field when reading */ | |
0cd96eb0 | 549 | outb_p(command, SMBHSTDAT1(priv)); |
6342064c | 550 | } else |
0cd96eb0 | 551 | outb_p(command, SMBHSTCMD(priv)); |
6342064c JD |
552 | block = 1; |
553 | break; | |
1da177e4 | 554 | default: |
0cd96eb0 DW |
555 | dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", |
556 | size); | |
97140342 | 557 | return -EOPNOTSUPP; |
1da177e4 LT |
558 | } |
559 | ||
ca8b9e32 | 560 | if (hwpec) /* enable/disable hardware PEC */ |
0cd96eb0 | 561 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); |
ca8b9e32 | 562 | else |
0cd96eb0 DW |
563 | outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), |
564 | SMBAUXCTL(priv)); | |
e8aac4a9 | 565 | |
3fb21c64 | 566 | if (block) |
0cd96eb0 DW |
567 | ret = i801_block_transaction(priv, data, read_write, size, |
568 | hwpec); | |
7edcb9ab | 569 | else |
0cd96eb0 | 570 | ret = i801_transaction(priv, xact | ENABLE_INT9); |
1da177e4 | 571 | |
c79cfbac | 572 | /* Some BIOSes don't like it when PEC is enabled at reboot or resume |
7edcb9ab OR |
573 | time, so we forcibly disable it after every transaction. Turn off |
574 | E32B for the same reason. */ | |
a0921b6c | 575 | if (hwpec || block) |
0cd96eb0 DW |
576 | outb_p(inb_p(SMBAUXCTL(priv)) & |
577 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
c79cfbac | 578 | |
3fb21c64 | 579 | if (block) |
1da177e4 | 580 | return ret; |
3fb21c64 | 581 | if (ret) |
97140342 | 582 | return ret; |
1da177e4 LT |
583 | if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) |
584 | return 0; | |
585 | ||
586 | switch (xact & 0x7f) { | |
587 | case I801_BYTE: /* Result put in SMBHSTDAT0 */ | |
588 | case I801_BYTE_DATA: | |
0cd96eb0 | 589 | data->byte = inb_p(SMBHSTDAT0(priv)); |
1da177e4 LT |
590 | break; |
591 | case I801_WORD_DATA: | |
0cd96eb0 DW |
592 | data->word = inb_p(SMBHSTDAT0(priv)) + |
593 | (inb_p(SMBHSTDAT1(priv)) << 8); | |
1da177e4 LT |
594 | break; |
595 | } | |
596 | return 0; | |
597 | } | |
598 | ||
599 | ||
600 | static u32 i801_func(struct i2c_adapter *adapter) | |
601 | { | |
0cd96eb0 DW |
602 | struct i801_priv *priv = i2c_get_adapdata(adapter); |
603 | ||
1da177e4 | 604 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | |
369f6f4a JD |
605 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | |
606 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | | |
0cd96eb0 DW |
607 | ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | |
608 | ((priv->features & FEATURE_I2C_BLOCK_READ) ? | |
6342064c | 609 | I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0); |
1da177e4 LT |
610 | } |
611 | ||
8f9082c5 | 612 | static const struct i2c_algorithm smbus_algorithm = { |
1da177e4 LT |
613 | .smbus_xfer = i801_access, |
614 | .functionality = i801_func, | |
615 | }; | |
616 | ||
3527bd50 | 617 | static DEFINE_PCI_DEVICE_TABLE(i801_ids) = { |
1da177e4 LT |
618 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, |
619 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, | |
620 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, | |
621 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, | |
622 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, | |
623 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, | |
624 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, | |
625 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, | |
626 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, | |
b0a70b57 | 627 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, |
8254fc4a | 628 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, |
adbc2a10 | 629 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, |
cb04e95b | 630 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, |
d28dc711 GJ |
631 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, |
632 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, | |
cb04e95b SH |
633 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, |
634 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, | |
e30d9859 | 635 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, |
55fee8d7 DW |
636 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, |
637 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, | |
638 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, | |
662cda8a | 639 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, |
6e2a851e | 640 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, |
062737fb | 641 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, |
1da177e4 LT |
642 | { 0, } |
643 | }; | |
644 | ||
3fb21c64 | 645 | MODULE_DEVICE_TABLE(pci, i801_ids); |
1da177e4 | 646 | |
8eacfceb | 647 | #if defined CONFIG_X86 && defined CONFIG_DMI |
1561bfe5 JD |
648 | static unsigned char apanel_addr; |
649 | ||
650 | /* Scan the system ROM for the signature "FJKEYINF" */ | |
651 | static __init const void __iomem *bios_signature(const void __iomem *bios) | |
652 | { | |
653 | ssize_t offset; | |
654 | const unsigned char signature[] = "FJKEYINF"; | |
655 | ||
656 | for (offset = 0; offset < 0x10000; offset += 0x10) { | |
657 | if (check_signature(bios + offset, signature, | |
658 | sizeof(signature)-1)) | |
659 | return bios + offset; | |
660 | } | |
661 | return NULL; | |
662 | } | |
663 | ||
664 | static void __init input_apanel_init(void) | |
665 | { | |
666 | void __iomem *bios; | |
667 | const void __iomem *p; | |
668 | ||
669 | bios = ioremap(0xF0000, 0x10000); /* Can't fail */ | |
670 | p = bios_signature(bios); | |
671 | if (p) { | |
672 | /* just use the first address */ | |
673 | apanel_addr = readb(p + 8 + 3) >> 1; | |
674 | } | |
675 | iounmap(bios); | |
676 | } | |
1561bfe5 | 677 | |
fa5bfab7 HG |
678 | struct dmi_onboard_device_info { |
679 | const char *name; | |
680 | u8 type; | |
681 | unsigned short i2c_addr; | |
682 | const char *i2c_type; | |
683 | }; | |
684 | ||
685 | static struct dmi_onboard_device_info __devinitdata dmi_devices[] = { | |
686 | { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, | |
687 | { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, | |
688 | { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, | |
689 | }; | |
690 | ||
691 | static void __devinit dmi_check_onboard_device(u8 type, const char *name, | |
692 | struct i2c_adapter *adap) | |
693 | { | |
694 | int i; | |
695 | struct i2c_board_info info; | |
696 | ||
697 | for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { | |
698 | /* & ~0x80, ignore enabled/disabled bit */ | |
699 | if ((type & ~0x80) != dmi_devices[i].type) | |
700 | continue; | |
faabd47f | 701 | if (strcasecmp(name, dmi_devices[i].name)) |
fa5bfab7 HG |
702 | continue; |
703 | ||
704 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
705 | info.addr = dmi_devices[i].i2c_addr; | |
706 | strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); | |
707 | i2c_new_device(adap, &info); | |
708 | break; | |
709 | } | |
710 | } | |
711 | ||
712 | /* We use our own function to check for onboard devices instead of | |
713 | dmi_find_device() as some buggy BIOS's have the devices we are interested | |
714 | in marked as disabled */ | |
715 | static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm, | |
716 | void *adap) | |
717 | { | |
718 | int i, count; | |
719 | ||
720 | if (dm->type != 10) | |
721 | return; | |
722 | ||
723 | count = (dm->length - sizeof(struct dmi_header)) / 2; | |
724 | for (i = 0; i < count; i++) { | |
725 | const u8 *d = (char *)(dm + 1) + (i * 2); | |
726 | const char *name = ((char *) dm) + dm->length; | |
727 | u8 type = d[0]; | |
728 | u8 s = d[1]; | |
729 | ||
730 | if (!s) | |
731 | continue; | |
732 | s--; | |
733 | while (s > 0 && name[0]) { | |
734 | name += strlen(name) + 1; | |
735 | s--; | |
736 | } | |
737 | if (name[0] == 0) /* Bogus string reference */ | |
738 | continue; | |
739 | ||
740 | dmi_check_onboard_device(type, name, adap); | |
741 | } | |
742 | } | |
fa5bfab7 | 743 | |
e7198fbf JD |
744 | /* Register optional slaves */ |
745 | static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) | |
746 | { | |
747 | /* Only register slaves on main SMBus channel */ | |
748 | if (priv->features & FEATURE_IDF) | |
749 | return; | |
750 | ||
e7198fbf JD |
751 | if (apanel_addr) { |
752 | struct i2c_board_info info; | |
753 | ||
754 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
755 | info.addr = apanel_addr; | |
756 | strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); | |
757 | i2c_new_device(&priv->adapter, &info); | |
758 | } | |
8eacfceb | 759 | |
e7198fbf JD |
760 | if (dmi_name_in_vendors("FUJITSU")) |
761 | dmi_walk(dmi_check_onboard_devices, &priv->adapter); | |
e7198fbf | 762 | } |
8eacfceb JD |
763 | #else |
764 | static void __init input_apanel_init(void) {} | |
765 | static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {} | |
766 | #endif /* CONFIG_X86 && CONFIG_DMI */ | |
e7198fbf | 767 | |
3fb21c64 IM |
768 | static int __devinit i801_probe(struct pci_dev *dev, |
769 | const struct pci_device_id *id) | |
1da177e4 | 770 | { |
02dd7ae2 | 771 | unsigned char temp; |
adff687d | 772 | int err, i; |
0cd96eb0 DW |
773 | struct i801_priv *priv; |
774 | ||
775 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
776 | if (!priv) | |
777 | return -ENOMEM; | |
778 | ||
779 | i2c_set_adapdata(&priv->adapter, priv); | |
780 | priv->adapter.owner = THIS_MODULE; | |
781 | priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
782 | priv->adapter.algo = &smbus_algorithm; | |
1da177e4 | 783 | |
0cd96eb0 | 784 | priv->pci_dev = dev; |
250d1bd3 | 785 | switch (dev->device) { |
e7198fbf JD |
786 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: |
787 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: | |
788 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: | |
789 | priv->features |= FEATURE_IDF; | |
790 | /* fall through */ | |
e0e8398c | 791 | default: |
0cd96eb0 | 792 | priv->features |= FEATURE_I2C_BLOCK_READ; |
6342064c JD |
793 | /* fall through */ |
794 | case PCI_DEVICE_ID_INTEL_82801DB_3: | |
0cd96eb0 DW |
795 | priv->features |= FEATURE_SMBUS_PEC; |
796 | priv->features |= FEATURE_BLOCK_BUFFER; | |
e0e8398c JD |
797 | /* fall through */ |
798 | case PCI_DEVICE_ID_INTEL_82801CA_3: | |
799 | case PCI_DEVICE_ID_INTEL_82801BA_2: | |
800 | case PCI_DEVICE_ID_INTEL_82801AB_3: | |
801 | case PCI_DEVICE_ID_INTEL_82801AA_3: | |
250d1bd3 | 802 | break; |
250d1bd3 | 803 | } |
02dd7ae2 | 804 | |
adff687d JD |
805 | /* Disable features on user request */ |
806 | for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { | |
0cd96eb0 | 807 | if (priv->features & disable_features & (1 << i)) |
adff687d JD |
808 | dev_notice(&dev->dev, "%s disabled by user\n", |
809 | i801_feature_names[i]); | |
810 | } | |
0cd96eb0 | 811 | priv->features &= ~disable_features; |
adff687d | 812 | |
02dd7ae2 JD |
813 | err = pci_enable_device(dev); |
814 | if (err) { | |
815 | dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", | |
816 | err); | |
817 | goto exit; | |
818 | } | |
819 | ||
820 | /* Determine the address of the SMBus area */ | |
0cd96eb0 DW |
821 | priv->smba = pci_resource_start(dev, SMBBAR); |
822 | if (!priv->smba) { | |
02dd7ae2 JD |
823 | dev_err(&dev->dev, "SMBus base address uninitialized, " |
824 | "upgrade BIOS\n"); | |
825 | err = -ENODEV; | |
d6fcb3b9 | 826 | goto exit; |
02dd7ae2 JD |
827 | } |
828 | ||
54fb4a05 | 829 | err = acpi_check_resource_conflict(&dev->resource[SMBBAR]); |
18669eab JD |
830 | if (err) { |
831 | err = -ENODEV; | |
54fb4a05 | 832 | goto exit; |
18669eab | 833 | } |
54fb4a05 | 834 | |
02dd7ae2 JD |
835 | err = pci_request_region(dev, SMBBAR, i801_driver.name); |
836 | if (err) { | |
837 | dev_err(&dev->dev, "Failed to request SMBus region " | |
0cd96eb0 | 838 | "0x%lx-0x%Lx\n", priv->smba, |
598736c5 | 839 | (unsigned long long)pci_resource_end(dev, SMBBAR)); |
d6fcb3b9 | 840 | goto exit; |
02dd7ae2 JD |
841 | } |
842 | ||
0cd96eb0 DW |
843 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); |
844 | priv->original_hstcfg = temp; | |
02dd7ae2 JD |
845 | temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ |
846 | if (!(temp & SMBHSTCFG_HST_EN)) { | |
847 | dev_info(&dev->dev, "Enabling SMBus device\n"); | |
848 | temp |= SMBHSTCFG_HST_EN; | |
849 | } | |
0cd96eb0 | 850 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); |
02dd7ae2 JD |
851 | |
852 | if (temp & SMBHSTCFG_SMB_SMI_EN) | |
853 | dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); | |
854 | else | |
855 | dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n"); | |
1da177e4 | 856 | |
a0921b6c | 857 | /* Clear special mode bits */ |
0cd96eb0 DW |
858 | if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) |
859 | outb_p(inb_p(SMBAUXCTL(priv)) & | |
860 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
a0921b6c | 861 | |
405ae7d3 | 862 | /* set up the sysfs linkage to our parent device */ |
0cd96eb0 | 863 | priv->adapter.dev.parent = &dev->dev; |
1da177e4 | 864 | |
7e2193a8 | 865 | /* Retry up to 3 times on lost arbitration */ |
0cd96eb0 | 866 | priv->adapter.retries = 3; |
7e2193a8 | 867 | |
0cd96eb0 DW |
868 | snprintf(priv->adapter.name, sizeof(priv->adapter.name), |
869 | "SMBus I801 adapter at %04lx", priv->smba); | |
870 | err = i2c_add_adapter(&priv->adapter); | |
02dd7ae2 JD |
871 | if (err) { |
872 | dev_err(&dev->dev, "Failed to add SMBus adapter\n"); | |
d6fcb3b9 | 873 | goto exit_release; |
02dd7ae2 | 874 | } |
1561bfe5 | 875 | |
e7198fbf | 876 | i801_probe_optional_slaves(priv); |
1561bfe5 | 877 | |
0cd96eb0 | 878 | pci_set_drvdata(dev, priv); |
d6fcb3b9 | 879 | return 0; |
02dd7ae2 | 880 | |
d6fcb3b9 DR |
881 | exit_release: |
882 | pci_release_region(dev, SMBBAR); | |
02dd7ae2 | 883 | exit: |
0cd96eb0 | 884 | kfree(priv); |
02dd7ae2 | 885 | return err; |
1da177e4 LT |
886 | } |
887 | ||
888 | static void __devexit i801_remove(struct pci_dev *dev) | |
889 | { | |
0cd96eb0 DW |
890 | struct i801_priv *priv = pci_get_drvdata(dev); |
891 | ||
892 | i2c_del_adapter(&priv->adapter); | |
893 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); | |
6dcc19df | 894 | pci_release_region(dev, SMBBAR); |
0cd96eb0 DW |
895 | pci_set_drvdata(dev, NULL); |
896 | kfree(priv); | |
d6fcb3b9 DR |
897 | /* |
898 | * do not call pci_disable_device(dev) since it can cause hard hangs on | |
899 | * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) | |
900 | */ | |
1da177e4 LT |
901 | } |
902 | ||
a5aaea37 JD |
903 | #ifdef CONFIG_PM |
904 | static int i801_suspend(struct pci_dev *dev, pm_message_t mesg) | |
905 | { | |
0cd96eb0 DW |
906 | struct i801_priv *priv = pci_get_drvdata(dev); |
907 | ||
a5aaea37 | 908 | pci_save_state(dev); |
0cd96eb0 | 909 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); |
a5aaea37 JD |
910 | pci_set_power_state(dev, pci_choose_state(dev, mesg)); |
911 | return 0; | |
912 | } | |
913 | ||
914 | static int i801_resume(struct pci_dev *dev) | |
915 | { | |
916 | pci_set_power_state(dev, PCI_D0); | |
917 | pci_restore_state(dev); | |
918 | return pci_enable_device(dev); | |
919 | } | |
920 | #else | |
921 | #define i801_suspend NULL | |
922 | #define i801_resume NULL | |
923 | #endif | |
924 | ||
1da177e4 LT |
925 | static struct pci_driver i801_driver = { |
926 | .name = "i801_smbus", | |
927 | .id_table = i801_ids, | |
928 | .probe = i801_probe, | |
929 | .remove = __devexit_p(i801_remove), | |
a5aaea37 JD |
930 | .suspend = i801_suspend, |
931 | .resume = i801_resume, | |
1da177e4 LT |
932 | }; |
933 | ||
934 | static int __init i2c_i801_init(void) | |
935 | { | |
6aa1464d JD |
936 | if (dmi_name_in_vendors("FUJITSU")) |
937 | input_apanel_init(); | |
1da177e4 LT |
938 | return pci_register_driver(&i801_driver); |
939 | } | |
940 | ||
941 | static void __exit i2c_i801_exit(void) | |
942 | { | |
943 | pci_unregister_driver(&i801_driver); | |
944 | } | |
945 | ||
6342064c JD |
946 | MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, " |
947 | "Jean Delvare <khali@linux-fr.org>"); | |
1da177e4 LT |
948 | MODULE_DESCRIPTION("I801 SMBus driver"); |
949 | MODULE_LICENSE("GPL"); | |
950 | ||
951 | module_init(i2c_i801_init); | |
952 | module_exit(i2c_i801_exit); |