Commit | Line | Data |
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27bce457 JH |
1 | /* |
2 | * I2C adapter for the IMG Serial Control Bus (SCB) IP block. | |
3 | * | |
4 | * Copyright (C) 2009, 2010, 2012, 2014 Imagination Technologies Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * There are three ways that this I2C controller can be driven: | |
11 | * | |
12 | * - Raw control of the SDA and SCK signals. | |
13 | * | |
14 | * This corresponds to MODE_RAW, which takes control of the signals | |
15 | * directly for a certain number of clock cycles (the INT_TIMING | |
16 | * interrupt can be used for timing). | |
17 | * | |
18 | * - Atomic commands. A low level I2C symbol (such as generate | |
19 | * start/stop/ack/nack bit, generate byte, receive byte, and receive | |
20 | * ACK) is given to the hardware, with detection of completion by bits | |
21 | * in the LINESTAT register. | |
22 | * | |
23 | * This mode of operation is used by MODE_ATOMIC, which uses an I2C | |
24 | * state machine in the interrupt handler to compose/react to I2C | |
25 | * transactions using atomic mode commands, and also by MODE_SEQUENCE, | |
26 | * which emits a simple fixed sequence of atomic mode commands. | |
27 | * | |
28 | * Due to software control, the use of atomic commands usually results | |
29 | * in suboptimal use of the bus, with gaps between the I2C symbols while | |
30 | * the driver decides what to do next. | |
31 | * | |
32 | * - Automatic mode. A bus address, and whether to read/write is | |
33 | * specified, and the hardware takes care of the I2C state machine, | |
34 | * using a FIFO to send/receive bytes of data to an I2C slave. The | |
35 | * driver just has to keep the FIFO drained or filled in response to the | |
36 | * appropriate FIFO interrupts. | |
37 | * | |
38 | * This corresponds to MODE_AUTOMATIC, which manages the FIFOs and deals | |
39 | * with control of repeated start bits between I2C messages. | |
40 | * | |
41 | * Use of automatic mode and the FIFO can make much more efficient use | |
42 | * of the bus compared to individual atomic commands, with potentially | |
43 | * no wasted time between I2C symbols or I2C messages. | |
44 | * | |
45 | * In most cases MODE_AUTOMATIC is used, however if any of the messages in | |
46 | * a transaction are zero byte writes (e.g. used by i2cdetect for probing | |
47 | * the bus), MODE_ATOMIC must be used since automatic mode is normally | |
48 | * started by the writing of data into the FIFO. | |
49 | * | |
50 | * The other modes are used in specific circumstances where MODE_ATOMIC and | |
51 | * MODE_AUTOMATIC aren't appropriate. MODE_RAW is used to implement a bus | |
52 | * recovery routine. MODE_SEQUENCE is used to reset the bus and make sure | |
53 | * it is in a sane state. | |
54 | * | |
55 | * Notice that the driver implements a timer-based timeout mechanism. | |
56 | * The reason for this mechanism is to reduce the number of interrupts | |
57 | * received in automatic mode. | |
58 | * | |
59 | * The driver would get a slave event and transaction done interrupts for | |
60 | * each atomic mode command that gets completed. However, these events are | |
61 | * not needed in automatic mode, becase those atomic mode commands are | |
62 | * managed automatically by the hardware. | |
63 | * | |
64 | * In practice, normal I2C transactions will be complete well before you | |
65 | * get the timer interrupt, as the timer is re-scheduled during FIFO | |
66 | * maintenance and disabled after the transaction is complete. | |
67 | * | |
68 | * In this way normal automatic mode operation isn't impacted by | |
69 | * unnecessary interrupts, but the exceptional abort condition can still be | |
70 | * detected (with a slight delay). | |
71 | */ | |
72 | ||
73 | #include <linux/bitops.h> | |
74 | #include <linux/clk.h> | |
75 | #include <linux/completion.h> | |
76 | #include <linux/err.h> | |
77 | #include <linux/i2c.h> | |
78 | #include <linux/init.h> | |
79 | #include <linux/interrupt.h> | |
80 | #include <linux/io.h> | |
81 | #include <linux/kernel.h> | |
82 | #include <linux/module.h> | |
83 | #include <linux/of_platform.h> | |
84 | #include <linux/platform_device.h> | |
85 | #include <linux/slab.h> | |
86 | #include <linux/timer.h> | |
87 | ||
88 | /* Register offsets */ | |
89 | ||
90 | #define SCB_STATUS_REG 0x00 | |
91 | #define SCB_OVERRIDE_REG 0x04 | |
92 | #define SCB_READ_ADDR_REG 0x08 | |
93 | #define SCB_READ_COUNT_REG 0x0c | |
94 | #define SCB_WRITE_ADDR_REG 0x10 | |
95 | #define SCB_READ_DATA_REG 0x14 | |
96 | #define SCB_WRITE_DATA_REG 0x18 | |
97 | #define SCB_FIFO_STATUS_REG 0x1c | |
98 | #define SCB_CONTROL_SOFT_RESET 0x1f | |
99 | #define SCB_CLK_SET_REG 0x3c | |
100 | #define SCB_INT_STATUS_REG 0x40 | |
101 | #define SCB_INT_CLEAR_REG 0x44 | |
102 | #define SCB_INT_MASK_REG 0x48 | |
103 | #define SCB_CONTROL_REG 0x4c | |
104 | #define SCB_TIME_TPL_REG 0x50 | |
105 | #define SCB_TIME_TPH_REG 0x54 | |
106 | #define SCB_TIME_TP2S_REG 0x58 | |
107 | #define SCB_TIME_TBI_REG 0x60 | |
108 | #define SCB_TIME_TSL_REG 0x64 | |
109 | #define SCB_TIME_TDL_REG 0x68 | |
110 | #define SCB_TIME_TSDL_REG 0x6c | |
111 | #define SCB_TIME_TSDH_REG 0x70 | |
112 | #define SCB_READ_XADDR_REG 0x74 | |
113 | #define SCB_WRITE_XADDR_REG 0x78 | |
114 | #define SCB_WRITE_COUNT_REG 0x7c | |
115 | #define SCB_CORE_REV_REG 0x80 | |
116 | #define SCB_TIME_TCKH_REG 0x84 | |
117 | #define SCB_TIME_TCKL_REG 0x88 | |
118 | #define SCB_FIFO_FLUSH_REG 0x8c | |
119 | #define SCB_READ_FIFO_REG 0x94 | |
120 | #define SCB_CLEAR_REG 0x98 | |
121 | ||
122 | /* SCB_CONTROL_REG bits */ | |
123 | ||
124 | #define SCB_CONTROL_CLK_ENABLE 0x1e0 | |
125 | #define SCB_CONTROL_TRANSACTION_HALT 0x200 | |
126 | ||
127 | #define FIFO_READ_FULL BIT(0) | |
128 | #define FIFO_READ_EMPTY BIT(1) | |
129 | #define FIFO_WRITE_FULL BIT(2) | |
130 | #define FIFO_WRITE_EMPTY BIT(3) | |
131 | ||
132 | /* SCB_CLK_SET_REG bits */ | |
133 | #define SCB_FILT_DISABLE BIT(31) | |
134 | #define SCB_FILT_BYPASS BIT(30) | |
135 | #define SCB_FILT_INC_MASK 0x7f | |
136 | #define SCB_FILT_INC_SHIFT 16 | |
137 | #define SCB_INC_MASK 0x7f | |
138 | #define SCB_INC_SHIFT 8 | |
139 | ||
140 | /* SCB_INT_*_REG bits */ | |
141 | ||
142 | #define INT_BUS_INACTIVE BIT(0) | |
143 | #define INT_UNEXPECTED_START BIT(1) | |
144 | #define INT_SCLK_LOW_TIMEOUT BIT(2) | |
145 | #define INT_SDAT_LOW_TIMEOUT BIT(3) | |
146 | #define INT_WRITE_ACK_ERR BIT(4) | |
147 | #define INT_ADDR_ACK_ERR BIT(5) | |
148 | #define INT_FIFO_FULL BIT(9) | |
149 | #define INT_FIFO_FILLING BIT(10) | |
150 | #define INT_FIFO_EMPTY BIT(11) | |
151 | #define INT_FIFO_EMPTYING BIT(12) | |
152 | #define INT_TRANSACTION_DONE BIT(15) | |
153 | #define INT_SLAVE_EVENT BIT(16) | |
154 | #define INT_TIMING BIT(18) | |
155 | ||
156 | #define INT_FIFO_FULL_FILLING (INT_FIFO_FULL | INT_FIFO_FILLING) | |
157 | #define INT_FIFO_EMPTY_EMPTYING (INT_FIFO_EMPTY | INT_FIFO_EMPTYING) | |
158 | ||
159 | /* Level interrupts need clearing after handling instead of before */ | |
160 | #define INT_LEVEL 0x01e00 | |
161 | ||
162 | /* Don't allow any interrupts while the clock may be off */ | |
163 | #define INT_ENABLE_MASK_INACTIVE 0x00000 | |
164 | ||
165 | /* Interrupt masks for the different driver modes */ | |
166 | ||
167 | #define INT_ENABLE_MASK_RAW INT_TIMING | |
168 | ||
169 | #define INT_ENABLE_MASK_ATOMIC (INT_TRANSACTION_DONE | \ | |
170 | INT_SLAVE_EVENT | \ | |
171 | INT_ADDR_ACK_ERR | \ | |
172 | INT_WRITE_ACK_ERR) | |
173 | ||
174 | #define INT_ENABLE_MASK_AUTOMATIC (INT_SCLK_LOW_TIMEOUT | \ | |
175 | INT_ADDR_ACK_ERR | \ | |
176 | INT_WRITE_ACK_ERR | \ | |
177 | INT_FIFO_FULL | \ | |
178 | INT_FIFO_FILLING | \ | |
179 | INT_FIFO_EMPTY | \ | |
180 | INT_FIFO_EMPTYING) | |
181 | ||
182 | #define INT_ENABLE_MASK_WAITSTOP (INT_SLAVE_EVENT | \ | |
183 | INT_ADDR_ACK_ERR | \ | |
184 | INT_WRITE_ACK_ERR) | |
185 | ||
186 | /* SCB_STATUS_REG fields */ | |
187 | ||
188 | #define LINESTAT_SCLK_LINE_STATUS BIT(0) | |
189 | #define LINESTAT_SCLK_EN BIT(1) | |
190 | #define LINESTAT_SDAT_LINE_STATUS BIT(2) | |
191 | #define LINESTAT_SDAT_EN BIT(3) | |
192 | #define LINESTAT_DET_START_STATUS BIT(4) | |
193 | #define LINESTAT_DET_STOP_STATUS BIT(5) | |
194 | #define LINESTAT_DET_ACK_STATUS BIT(6) | |
195 | #define LINESTAT_DET_NACK_STATUS BIT(7) | |
196 | #define LINESTAT_BUS_IDLE BIT(8) | |
197 | #define LINESTAT_T_DONE_STATUS BIT(9) | |
198 | #define LINESTAT_SCLK_OUT_STATUS BIT(10) | |
199 | #define LINESTAT_SDAT_OUT_STATUS BIT(11) | |
200 | #define LINESTAT_GEN_LINE_MASK_STATUS BIT(12) | |
201 | #define LINESTAT_START_BIT_DET BIT(13) | |
202 | #define LINESTAT_STOP_BIT_DET BIT(14) | |
203 | #define LINESTAT_ACK_DET BIT(15) | |
204 | #define LINESTAT_NACK_DET BIT(16) | |
205 | #define LINESTAT_INPUT_HELD_V BIT(17) | |
206 | #define LINESTAT_ABORT_DET BIT(18) | |
207 | #define LINESTAT_ACK_OR_NACK_DET (LINESTAT_ACK_DET | LINESTAT_NACK_DET) | |
208 | #define LINESTAT_INPUT_DATA 0xff000000 | |
209 | #define LINESTAT_INPUT_DATA_SHIFT 24 | |
210 | ||
211 | #define LINESTAT_CLEAR_SHIFT 13 | |
212 | #define LINESTAT_LATCHED (0x3f << LINESTAT_CLEAR_SHIFT) | |
213 | ||
214 | /* SCB_OVERRIDE_REG fields */ | |
215 | ||
216 | #define OVERRIDE_SCLK_OVR BIT(0) | |
217 | #define OVERRIDE_SCLKEN_OVR BIT(1) | |
218 | #define OVERRIDE_SDAT_OVR BIT(2) | |
219 | #define OVERRIDE_SDATEN_OVR BIT(3) | |
220 | #define OVERRIDE_MASTER BIT(9) | |
221 | #define OVERRIDE_LINE_OVR_EN BIT(10) | |
222 | #define OVERRIDE_DIRECT BIT(11) | |
223 | #define OVERRIDE_CMD_SHIFT 4 | |
224 | #define OVERRIDE_CMD_MASK 0x1f | |
225 | #define OVERRIDE_DATA_SHIFT 24 | |
226 | ||
227 | #define OVERRIDE_SCLK_DOWN (OVERRIDE_LINE_OVR_EN | \ | |
228 | OVERRIDE_SCLKEN_OVR) | |
229 | #define OVERRIDE_SCLK_UP (OVERRIDE_LINE_OVR_EN | \ | |
230 | OVERRIDE_SCLKEN_OVR | \ | |
231 | OVERRIDE_SCLK_OVR) | |
232 | #define OVERRIDE_SDAT_DOWN (OVERRIDE_LINE_OVR_EN | \ | |
233 | OVERRIDE_SDATEN_OVR) | |
234 | #define OVERRIDE_SDAT_UP (OVERRIDE_LINE_OVR_EN | \ | |
235 | OVERRIDE_SDATEN_OVR | \ | |
236 | OVERRIDE_SDAT_OVR) | |
237 | ||
238 | /* OVERRIDE_CMD values */ | |
239 | ||
240 | #define CMD_PAUSE 0x00 | |
241 | #define CMD_GEN_DATA 0x01 | |
242 | #define CMD_GEN_START 0x02 | |
243 | #define CMD_GEN_STOP 0x03 | |
244 | #define CMD_GEN_ACK 0x04 | |
245 | #define CMD_GEN_NACK 0x05 | |
246 | #define CMD_RET_DATA 0x08 | |
247 | #define CMD_RET_ACK 0x09 | |
248 | ||
249 | /* Fixed timing values */ | |
250 | ||
251 | #define TIMEOUT_TBI 0x0 | |
252 | #define TIMEOUT_TSL 0xffff | |
253 | #define TIMEOUT_TDL 0x0 | |
254 | ||
255 | /* Transaction timeout */ | |
256 | ||
257 | #define IMG_I2C_TIMEOUT (msecs_to_jiffies(1000)) | |
258 | ||
259 | /* | |
260 | * Worst incs are 1 (innacurate) and 16*256 (irregular). | |
261 | * So a sensible inc is the logarithmic mean: 64 (2^6), which is | |
262 | * in the middle of the valid range (0-127). | |
263 | */ | |
264 | #define SCB_OPT_INC 64 | |
265 | ||
266 | /* Setup the clock enable filtering for 25 ns */ | |
267 | #define SCB_FILT_GLITCH 25 | |
268 | ||
269 | /* | |
270 | * Bits to return from interrupt handler functions for different modes. | |
271 | * This delays completion until we've finished with the registers, so that the | |
272 | * function waiting for completion can safely disable the clock to save power. | |
273 | */ | |
274 | #define ISR_COMPLETE_M BIT(31) | |
275 | #define ISR_FATAL_M BIT(30) | |
276 | #define ISR_WAITSTOP BIT(29) | |
277 | #define ISR_STATUS_M 0x0000ffff /* contains +ve errno */ | |
278 | #define ISR_COMPLETE(err) (ISR_COMPLETE_M | (ISR_STATUS_M & (err))) | |
279 | #define ISR_FATAL(err) (ISR_COMPLETE(err) | ISR_FATAL_M) | |
280 | ||
27bce457 JH |
281 | enum img_i2c_mode { |
282 | MODE_INACTIVE, | |
283 | MODE_RAW, | |
284 | MODE_ATOMIC, | |
285 | MODE_AUTOMATIC, | |
286 | MODE_SEQUENCE, | |
287 | MODE_FATAL, | |
288 | MODE_WAITSTOP, | |
289 | MODE_SUSPEND, | |
290 | }; | |
291 | ||
292 | /* Timing parameters for i2c modes (in ns) */ | |
293 | struct img_i2c_timings { | |
294 | const char *name; | |
295 | unsigned int max_bitrate; | |
296 | unsigned int tckh, tckl, tsdh, tsdl; | |
297 | unsigned int tp2s, tpl, tph; | |
298 | }; | |
299 | ||
300 | /* The timings array must be ordered from slower to faster */ | |
301 | static struct img_i2c_timings timings[] = { | |
302 | /* Standard mode */ | |
303 | { | |
304 | .name = "standard", | |
305 | .max_bitrate = 100000, | |
306 | .tckh = 4000, | |
307 | .tckl = 4700, | |
308 | .tsdh = 4700, | |
309 | .tsdl = 8700, | |
310 | .tp2s = 4700, | |
311 | .tpl = 4700, | |
312 | .tph = 4000, | |
313 | }, | |
314 | /* Fast mode */ | |
315 | { | |
316 | .name = "fast", | |
317 | .max_bitrate = 400000, | |
318 | .tckh = 600, | |
319 | .tckl = 1300, | |
320 | .tsdh = 600, | |
321 | .tsdl = 1200, | |
322 | .tp2s = 1300, | |
323 | .tpl = 600, | |
324 | .tph = 600, | |
325 | }, | |
326 | }; | |
327 | ||
328 | /* Reset dance */ | |
329 | static u8 img_i2c_reset_seq[] = { CMD_GEN_START, | |
330 | CMD_GEN_DATA, 0xff, | |
331 | CMD_RET_ACK, | |
332 | CMD_GEN_START, | |
333 | CMD_GEN_STOP, | |
334 | 0 }; | |
335 | /* Just issue a stop (after an abort condition) */ | |
336 | static u8 img_i2c_stop_seq[] = { CMD_GEN_STOP, | |
337 | 0 }; | |
338 | ||
339 | /* We're interested in different interrupts depending on the mode */ | |
340 | static unsigned int img_i2c_int_enable_by_mode[] = { | |
341 | [MODE_INACTIVE] = INT_ENABLE_MASK_INACTIVE, | |
342 | [MODE_RAW] = INT_ENABLE_MASK_RAW, | |
343 | [MODE_ATOMIC] = INT_ENABLE_MASK_ATOMIC, | |
344 | [MODE_AUTOMATIC] = INT_ENABLE_MASK_AUTOMATIC, | |
345 | [MODE_SEQUENCE] = INT_ENABLE_MASK_ATOMIC, | |
346 | [MODE_FATAL] = 0, | |
347 | [MODE_WAITSTOP] = INT_ENABLE_MASK_WAITSTOP, | |
348 | [MODE_SUSPEND] = 0, | |
349 | }; | |
350 | ||
351 | /* Atomic command names */ | |
352 | static const char * const img_i2c_atomic_cmd_names[] = { | |
353 | [CMD_PAUSE] = "PAUSE", | |
354 | [CMD_GEN_DATA] = "GEN_DATA", | |
355 | [CMD_GEN_START] = "GEN_START", | |
356 | [CMD_GEN_STOP] = "GEN_STOP", | |
357 | [CMD_GEN_ACK] = "GEN_ACK", | |
358 | [CMD_GEN_NACK] = "GEN_NACK", | |
359 | [CMD_RET_DATA] = "RET_DATA", | |
360 | [CMD_RET_ACK] = "RET_ACK", | |
361 | }; | |
362 | ||
363 | struct img_i2c { | |
364 | struct i2c_adapter adap; | |
365 | ||
366 | void __iomem *base; | |
367 | ||
368 | /* | |
369 | * The scb core clock is used to get the input frequency, and to disable | |
370 | * it after every set of transactions to save some power. | |
371 | */ | |
372 | struct clk *scb_clk, *sys_clk; | |
373 | unsigned int bitrate; | |
374 | bool need_wr_rd_fence; | |
375 | ||
376 | /* state */ | |
377 | struct completion msg_complete; | |
378 | spinlock_t lock; /* lock before doing anything with the state */ | |
379 | struct i2c_msg msg; | |
380 | ||
381 | /* After the last transaction, wait for a stop bit */ | |
382 | bool last_msg; | |
383 | int msg_status; | |
384 | ||
385 | enum img_i2c_mode mode; | |
386 | u32 int_enable; /* depends on mode */ | |
387 | u32 line_status; /* line status over command */ | |
388 | ||
389 | /* | |
390 | * To avoid slave event interrupts in automatic mode, use a timer to | |
391 | * poll the abort condition if we don't get an interrupt for too long. | |
392 | */ | |
393 | struct timer_list check_timer; | |
394 | bool t_halt; | |
395 | ||
396 | /* atomic mode state */ | |
397 | bool at_t_done; | |
398 | bool at_slave_event; | |
399 | int at_cur_cmd; | |
400 | u8 at_cur_data; | |
401 | ||
402 | /* Sequence: either reset or stop. See img_i2c_sequence. */ | |
403 | u8 *seq; | |
404 | ||
405 | /* raw mode */ | |
406 | unsigned int raw_timeout; | |
407 | }; | |
408 | ||
409 | static void img_i2c_writel(struct img_i2c *i2c, u32 offset, u32 value) | |
410 | { | |
411 | writel(value, i2c->base + offset); | |
412 | } | |
413 | ||
414 | static u32 img_i2c_readl(struct img_i2c *i2c, u32 offset) | |
415 | { | |
416 | return readl(i2c->base + offset); | |
417 | } | |
418 | ||
419 | /* | |
420 | * The code to read from the master read fifo, and write to the master | |
421 | * write fifo, checks a bit in an SCB register before every byte to | |
422 | * ensure that the fifo is not full (write fifo) or empty (read fifo). | |
423 | * Due to clock domain crossing inside the SCB block the updated value | |
424 | * of this bit is only visible after 2 cycles. | |
425 | * | |
426 | * The scb_wr_rd_fence() function does 2 dummy writes (to the read-only | |
427 | * revision register), and it's called after reading from or writing to the | |
428 | * fifos to ensure that subsequent reads of the fifo status bits do not read | |
429 | * stale values. | |
430 | */ | |
431 | static void img_i2c_wr_rd_fence(struct img_i2c *i2c) | |
432 | { | |
433 | if (i2c->need_wr_rd_fence) { | |
434 | img_i2c_writel(i2c, SCB_CORE_REV_REG, 0); | |
435 | img_i2c_writel(i2c, SCB_CORE_REV_REG, 0); | |
436 | } | |
437 | } | |
438 | ||
439 | static void img_i2c_switch_mode(struct img_i2c *i2c, enum img_i2c_mode mode) | |
440 | { | |
441 | i2c->mode = mode; | |
442 | i2c->int_enable = img_i2c_int_enable_by_mode[mode]; | |
443 | i2c->line_status = 0; | |
444 | } | |
445 | ||
446 | static void img_i2c_raw_op(struct img_i2c *i2c) | |
447 | { | |
448 | i2c->raw_timeout = 0; | |
449 | img_i2c_writel(i2c, SCB_OVERRIDE_REG, | |
450 | OVERRIDE_SCLKEN_OVR | | |
451 | OVERRIDE_SDATEN_OVR | | |
452 | OVERRIDE_MASTER | | |
453 | OVERRIDE_LINE_OVR_EN | | |
454 | OVERRIDE_DIRECT | | |
455 | ((i2c->at_cur_cmd & OVERRIDE_CMD_MASK) << OVERRIDE_CMD_SHIFT) | | |
456 | (i2c->at_cur_data << OVERRIDE_DATA_SHIFT)); | |
457 | } | |
458 | ||
459 | static const char *img_i2c_atomic_op_name(unsigned int cmd) | |
460 | { | |
461 | if (unlikely(cmd >= ARRAY_SIZE(img_i2c_atomic_cmd_names))) | |
462 | return "UNKNOWN"; | |
463 | return img_i2c_atomic_cmd_names[cmd]; | |
464 | } | |
465 | ||
466 | /* Send a single atomic mode command to the hardware */ | |
467 | static void img_i2c_atomic_op(struct img_i2c *i2c, int cmd, u8 data) | |
468 | { | |
469 | i2c->at_cur_cmd = cmd; | |
470 | i2c->at_cur_data = data; | |
471 | ||
472 | /* work around lack of data setup time when generating data */ | |
473 | if (cmd == CMD_GEN_DATA && i2c->mode == MODE_ATOMIC) { | |
474 | u32 line_status = img_i2c_readl(i2c, SCB_STATUS_REG); | |
475 | ||
476 | if (line_status & LINESTAT_SDAT_LINE_STATUS && !(data & 0x80)) { | |
477 | /* hold the data line down for a moment */ | |
478 | img_i2c_switch_mode(i2c, MODE_RAW); | |
479 | img_i2c_raw_op(i2c); | |
480 | return; | |
481 | } | |
482 | } | |
483 | ||
484 | dev_dbg(i2c->adap.dev.parent, | |
485 | "atomic cmd=%s (%d) data=%#x\n", | |
486 | img_i2c_atomic_op_name(cmd), cmd, data); | |
487 | i2c->at_t_done = (cmd == CMD_RET_DATA || cmd == CMD_RET_ACK); | |
488 | i2c->at_slave_event = false; | |
489 | i2c->line_status = 0; | |
490 | ||
491 | img_i2c_writel(i2c, SCB_OVERRIDE_REG, | |
492 | ((cmd & OVERRIDE_CMD_MASK) << OVERRIDE_CMD_SHIFT) | | |
493 | OVERRIDE_MASTER | | |
494 | OVERRIDE_DIRECT | | |
495 | (data << OVERRIDE_DATA_SHIFT)); | |
496 | } | |
497 | ||
498 | /* Start a transaction in atomic mode */ | |
499 | static void img_i2c_atomic_start(struct img_i2c *i2c) | |
500 | { | |
501 | img_i2c_switch_mode(i2c, MODE_ATOMIC); | |
502 | img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); | |
503 | img_i2c_atomic_op(i2c, CMD_GEN_START, 0x00); | |
504 | } | |
505 | ||
506 | static void img_i2c_soft_reset(struct img_i2c *i2c) | |
507 | { | |
508 | i2c->t_halt = false; | |
509 | img_i2c_writel(i2c, SCB_CONTROL_REG, 0); | |
510 | img_i2c_writel(i2c, SCB_CONTROL_REG, | |
511 | SCB_CONTROL_CLK_ENABLE | SCB_CONTROL_SOFT_RESET); | |
512 | } | |
513 | ||
514 | /* enable or release transaction halt for control of repeated starts */ | |
515 | static void img_i2c_transaction_halt(struct img_i2c *i2c, bool t_halt) | |
516 | { | |
517 | u32 val; | |
518 | ||
519 | if (i2c->t_halt == t_halt) | |
520 | return; | |
521 | i2c->t_halt = t_halt; | |
522 | val = img_i2c_readl(i2c, SCB_CONTROL_REG); | |
523 | if (t_halt) | |
524 | val |= SCB_CONTROL_TRANSACTION_HALT; | |
525 | else | |
526 | val &= ~SCB_CONTROL_TRANSACTION_HALT; | |
527 | img_i2c_writel(i2c, SCB_CONTROL_REG, val); | |
528 | } | |
529 | ||
530 | /* Drain data from the FIFO into the buffer (automatic mode) */ | |
531 | static void img_i2c_read_fifo(struct img_i2c *i2c) | |
532 | { | |
533 | while (i2c->msg.len) { | |
534 | u32 fifo_status; | |
535 | u8 data; | |
536 | ||
2aefb1bd | 537 | img_i2c_wr_rd_fence(i2c); |
27bce457 JH |
538 | fifo_status = img_i2c_readl(i2c, SCB_FIFO_STATUS_REG); |
539 | if (fifo_status & FIFO_READ_EMPTY) | |
540 | break; | |
541 | ||
542 | data = img_i2c_readl(i2c, SCB_READ_DATA_REG); | |
543 | *i2c->msg.buf = data; | |
544 | ||
545 | img_i2c_writel(i2c, SCB_READ_FIFO_REG, 0xff); | |
27bce457 JH |
546 | i2c->msg.len--; |
547 | i2c->msg.buf++; | |
548 | } | |
549 | } | |
550 | ||
551 | /* Fill the FIFO with data from the buffer (automatic mode) */ | |
552 | static void img_i2c_write_fifo(struct img_i2c *i2c) | |
553 | { | |
554 | while (i2c->msg.len) { | |
555 | u32 fifo_status; | |
556 | ||
2aefb1bd | 557 | img_i2c_wr_rd_fence(i2c); |
27bce457 JH |
558 | fifo_status = img_i2c_readl(i2c, SCB_FIFO_STATUS_REG); |
559 | if (fifo_status & FIFO_WRITE_FULL) | |
560 | break; | |
561 | ||
562 | img_i2c_writel(i2c, SCB_WRITE_DATA_REG, *i2c->msg.buf); | |
27bce457 JH |
563 | i2c->msg.len--; |
564 | i2c->msg.buf++; | |
565 | } | |
566 | ||
567 | /* Disable fifo emptying interrupt if nothing more to write */ | |
568 | if (!i2c->msg.len) | |
569 | i2c->int_enable &= ~INT_FIFO_EMPTYING; | |
570 | } | |
571 | ||
572 | /* Start a read transaction in automatic mode */ | |
573 | static void img_i2c_read(struct img_i2c *i2c) | |
574 | { | |
575 | img_i2c_switch_mode(i2c, MODE_AUTOMATIC); | |
576 | if (!i2c->last_msg) | |
577 | i2c->int_enable |= INT_SLAVE_EVENT; | |
578 | ||
579 | img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); | |
580 | img_i2c_writel(i2c, SCB_READ_ADDR_REG, i2c->msg.addr); | |
581 | img_i2c_writel(i2c, SCB_READ_COUNT_REG, i2c->msg.len); | |
582 | ||
583 | img_i2c_transaction_halt(i2c, false); | |
584 | mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1)); | |
585 | } | |
586 | ||
587 | /* Start a write transaction in automatic mode */ | |
588 | static void img_i2c_write(struct img_i2c *i2c) | |
589 | { | |
590 | img_i2c_switch_mode(i2c, MODE_AUTOMATIC); | |
591 | if (!i2c->last_msg) | |
592 | i2c->int_enable |= INT_SLAVE_EVENT; | |
593 | ||
594 | img_i2c_writel(i2c, SCB_WRITE_ADDR_REG, i2c->msg.addr); | |
595 | img_i2c_writel(i2c, SCB_WRITE_COUNT_REG, i2c->msg.len); | |
596 | ||
597 | img_i2c_transaction_halt(i2c, false); | |
598 | mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1)); | |
599 | img_i2c_write_fifo(i2c); | |
600 | ||
601 | /* img_i2c_write_fifo() may modify int_enable */ | |
602 | img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); | |
603 | } | |
604 | ||
605 | /* | |
606 | * Indicate that the transaction is complete. This is called from the | |
607 | * ISR to wake up the waiting thread, after which the ISR must not | |
608 | * access any more SCB registers. | |
609 | */ | |
610 | static void img_i2c_complete_transaction(struct img_i2c *i2c, int status) | |
611 | { | |
612 | img_i2c_switch_mode(i2c, MODE_INACTIVE); | |
613 | if (status) { | |
614 | i2c->msg_status = status; | |
615 | img_i2c_transaction_halt(i2c, false); | |
616 | } | |
617 | complete(&i2c->msg_complete); | |
618 | } | |
619 | ||
620 | static unsigned int img_i2c_raw_atomic_delay_handler(struct img_i2c *i2c, | |
621 | u32 int_status, u32 line_status) | |
622 | { | |
623 | /* Stay in raw mode for this, so we don't just loop infinitely */ | |
624 | img_i2c_atomic_op(i2c, i2c->at_cur_cmd, i2c->at_cur_data); | |
625 | img_i2c_switch_mode(i2c, MODE_ATOMIC); | |
626 | return 0; | |
627 | } | |
628 | ||
629 | static unsigned int img_i2c_raw(struct img_i2c *i2c, u32 int_status, | |
630 | u32 line_status) | |
631 | { | |
632 | if (int_status & INT_TIMING) { | |
633 | if (i2c->raw_timeout == 0) | |
634 | return img_i2c_raw_atomic_delay_handler(i2c, | |
635 | int_status, line_status); | |
636 | --i2c->raw_timeout; | |
637 | } | |
638 | return 0; | |
639 | } | |
640 | ||
641 | static unsigned int img_i2c_sequence(struct img_i2c *i2c, u32 int_status) | |
642 | { | |
643 | static const unsigned int continue_bits[] = { | |
644 | [CMD_GEN_START] = LINESTAT_START_BIT_DET, | |
645 | [CMD_GEN_DATA] = LINESTAT_INPUT_HELD_V, | |
646 | [CMD_RET_ACK] = LINESTAT_ACK_DET | LINESTAT_NACK_DET, | |
647 | [CMD_RET_DATA] = LINESTAT_INPUT_HELD_V, | |
648 | [CMD_GEN_STOP] = LINESTAT_STOP_BIT_DET, | |
649 | }; | |
650 | int next_cmd = -1; | |
651 | u8 next_data = 0x00; | |
652 | ||
653 | if (int_status & INT_SLAVE_EVENT) | |
654 | i2c->at_slave_event = true; | |
655 | if (int_status & INT_TRANSACTION_DONE) | |
656 | i2c->at_t_done = true; | |
657 | ||
658 | if (!i2c->at_slave_event || !i2c->at_t_done) | |
659 | return 0; | |
660 | ||
661 | /* wait if no continue bits are set */ | |
662 | if (i2c->at_cur_cmd >= 0 && | |
663 | i2c->at_cur_cmd < ARRAY_SIZE(continue_bits)) { | |
664 | unsigned int cont_bits = continue_bits[i2c->at_cur_cmd]; | |
665 | ||
666 | if (cont_bits) { | |
667 | cont_bits |= LINESTAT_ABORT_DET; | |
668 | if (!(i2c->line_status & cont_bits)) | |
669 | return 0; | |
670 | } | |
671 | } | |
672 | ||
673 | /* follow the sequence of commands in i2c->seq */ | |
674 | next_cmd = *i2c->seq; | |
675 | /* stop on a nil */ | |
676 | if (!next_cmd) { | |
677 | img_i2c_writel(i2c, SCB_OVERRIDE_REG, 0); | |
678 | return ISR_COMPLETE(0); | |
679 | } | |
680 | /* when generating data, the next byte is the data */ | |
681 | if (next_cmd == CMD_GEN_DATA) { | |
682 | ++i2c->seq; | |
683 | next_data = *i2c->seq; | |
684 | } | |
685 | ++i2c->seq; | |
686 | img_i2c_atomic_op(i2c, next_cmd, next_data); | |
687 | ||
688 | return 0; | |
689 | } | |
690 | ||
691 | static void img_i2c_reset_start(struct img_i2c *i2c) | |
692 | { | |
693 | /* Initiate the magic dance */ | |
694 | img_i2c_switch_mode(i2c, MODE_SEQUENCE); | |
695 | img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); | |
696 | i2c->seq = img_i2c_reset_seq; | |
697 | i2c->at_slave_event = true; | |
698 | i2c->at_t_done = true; | |
699 | i2c->at_cur_cmd = -1; | |
700 | ||
701 | /* img_i2c_reset_seq isn't empty so the following won't fail */ | |
702 | img_i2c_sequence(i2c, 0); | |
703 | } | |
704 | ||
705 | static void img_i2c_stop_start(struct img_i2c *i2c) | |
706 | { | |
707 | /* Initiate a stop bit sequence */ | |
708 | img_i2c_switch_mode(i2c, MODE_SEQUENCE); | |
709 | img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); | |
710 | i2c->seq = img_i2c_stop_seq; | |
711 | i2c->at_slave_event = true; | |
712 | i2c->at_t_done = true; | |
713 | i2c->at_cur_cmd = -1; | |
714 | ||
715 | /* img_i2c_stop_seq isn't empty so the following won't fail */ | |
716 | img_i2c_sequence(i2c, 0); | |
717 | } | |
718 | ||
719 | static unsigned int img_i2c_atomic(struct img_i2c *i2c, | |
720 | u32 int_status, | |
721 | u32 line_status) | |
722 | { | |
723 | int next_cmd = -1; | |
724 | u8 next_data = 0x00; | |
725 | ||
726 | if (int_status & INT_SLAVE_EVENT) | |
727 | i2c->at_slave_event = true; | |
728 | if (int_status & INT_TRANSACTION_DONE) | |
729 | i2c->at_t_done = true; | |
730 | ||
731 | if (!i2c->at_slave_event || !i2c->at_t_done) | |
732 | goto next_atomic_cmd; | |
733 | if (i2c->line_status & LINESTAT_ABORT_DET) { | |
734 | dev_dbg(i2c->adap.dev.parent, "abort condition detected\n"); | |
735 | next_cmd = CMD_GEN_STOP; | |
736 | i2c->msg_status = -EIO; | |
737 | goto next_atomic_cmd; | |
738 | } | |
739 | ||
740 | /* i2c->at_cur_cmd may have completed */ | |
741 | switch (i2c->at_cur_cmd) { | |
742 | case CMD_GEN_START: | |
743 | next_cmd = CMD_GEN_DATA; | |
744 | next_data = (i2c->msg.addr << 1); | |
745 | if (i2c->msg.flags & I2C_M_RD) | |
746 | next_data |= 0x1; | |
747 | break; | |
748 | case CMD_GEN_DATA: | |
749 | if (i2c->line_status & LINESTAT_INPUT_HELD_V) | |
750 | next_cmd = CMD_RET_ACK; | |
751 | break; | |
752 | case CMD_RET_ACK: | |
753 | if (i2c->line_status & LINESTAT_ACK_DET) { | |
754 | if (i2c->msg.len == 0) { | |
755 | next_cmd = CMD_GEN_STOP; | |
756 | } else if (i2c->msg.flags & I2C_M_RD) { | |
757 | next_cmd = CMD_RET_DATA; | |
758 | } else { | |
759 | next_cmd = CMD_GEN_DATA; | |
760 | next_data = *i2c->msg.buf; | |
761 | --i2c->msg.len; | |
762 | ++i2c->msg.buf; | |
763 | } | |
764 | } else if (i2c->line_status & LINESTAT_NACK_DET) { | |
765 | i2c->msg_status = -EIO; | |
766 | next_cmd = CMD_GEN_STOP; | |
767 | } | |
768 | break; | |
769 | case CMD_RET_DATA: | |
770 | if (i2c->line_status & LINESTAT_INPUT_HELD_V) { | |
771 | *i2c->msg.buf = (i2c->line_status & | |
772 | LINESTAT_INPUT_DATA) | |
773 | >> LINESTAT_INPUT_DATA_SHIFT; | |
774 | --i2c->msg.len; | |
775 | ++i2c->msg.buf; | |
776 | if (i2c->msg.len) | |
777 | next_cmd = CMD_GEN_ACK; | |
778 | else | |
779 | next_cmd = CMD_GEN_NACK; | |
780 | } | |
781 | break; | |
782 | case CMD_GEN_ACK: | |
783 | if (i2c->line_status & LINESTAT_ACK_DET) { | |
784 | next_cmd = CMD_RET_DATA; | |
785 | } else { | |
786 | i2c->msg_status = -EIO; | |
787 | next_cmd = CMD_GEN_STOP; | |
788 | } | |
789 | break; | |
790 | case CMD_GEN_NACK: | |
791 | next_cmd = CMD_GEN_STOP; | |
792 | break; | |
793 | case CMD_GEN_STOP: | |
794 | img_i2c_writel(i2c, SCB_OVERRIDE_REG, 0); | |
795 | return ISR_COMPLETE(0); | |
796 | default: | |
797 | dev_err(i2c->adap.dev.parent, "bad atomic command %d\n", | |
798 | i2c->at_cur_cmd); | |
799 | i2c->msg_status = -EIO; | |
800 | next_cmd = CMD_GEN_STOP; | |
801 | break; | |
802 | } | |
803 | ||
804 | next_atomic_cmd: | |
805 | if (next_cmd != -1) { | |
806 | /* don't actually stop unless we're the last transaction */ | |
807 | if (next_cmd == CMD_GEN_STOP && !i2c->msg_status && | |
808 | !i2c->last_msg) | |
809 | return ISR_COMPLETE(0); | |
810 | img_i2c_atomic_op(i2c, next_cmd, next_data); | |
811 | } | |
812 | return 0; | |
813 | } | |
814 | ||
815 | /* | |
816 | * Timer function to check if something has gone wrong in automatic mode (so we | |
817 | * don't have to handle so many interrupts just to catch an exception). | |
818 | */ | |
819 | static void img_i2c_check_timer(unsigned long arg) | |
820 | { | |
821 | struct img_i2c *i2c = (struct img_i2c *)arg; | |
822 | unsigned long flags; | |
823 | unsigned int line_status; | |
824 | ||
825 | spin_lock_irqsave(&i2c->lock, flags); | |
826 | line_status = img_i2c_readl(i2c, SCB_STATUS_REG); | |
827 | ||
828 | /* check for an abort condition */ | |
829 | if (line_status & LINESTAT_ABORT_DET) { | |
830 | dev_dbg(i2c->adap.dev.parent, | |
831 | "abort condition detected by check timer\n"); | |
832 | /* enable slave event interrupt mask to trigger irq */ | |
833 | img_i2c_writel(i2c, SCB_INT_MASK_REG, | |
834 | i2c->int_enable | INT_SLAVE_EVENT); | |
835 | } | |
836 | ||
837 | spin_unlock_irqrestore(&i2c->lock, flags); | |
838 | } | |
839 | ||
840 | static unsigned int img_i2c_auto(struct img_i2c *i2c, | |
841 | unsigned int int_status, | |
842 | unsigned int line_status) | |
843 | { | |
844 | if (int_status & (INT_WRITE_ACK_ERR | INT_ADDR_ACK_ERR)) | |
845 | return ISR_COMPLETE(EIO); | |
846 | ||
847 | if (line_status & LINESTAT_ABORT_DET) { | |
848 | dev_dbg(i2c->adap.dev.parent, "abort condition detected\n"); | |
849 | /* empty the read fifo */ | |
850 | if ((i2c->msg.flags & I2C_M_RD) && | |
851 | (int_status & INT_FIFO_FULL_FILLING)) | |
852 | img_i2c_read_fifo(i2c); | |
853 | /* use atomic mode and try to force a stop bit */ | |
854 | i2c->msg_status = -EIO; | |
855 | img_i2c_stop_start(i2c); | |
856 | return 0; | |
857 | } | |
858 | ||
859 | /* Enable transaction halt on start bit */ | |
860 | if (!i2c->last_msg && i2c->line_status & LINESTAT_START_BIT_DET) { | |
861 | img_i2c_transaction_halt(i2c, true); | |
862 | /* we're no longer interested in the slave event */ | |
863 | i2c->int_enable &= ~INT_SLAVE_EVENT; | |
864 | } | |
865 | ||
866 | mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1)); | |
867 | ||
868 | if (i2c->msg.flags & I2C_M_RD) { | |
869 | if (int_status & INT_FIFO_FULL_FILLING) { | |
870 | img_i2c_read_fifo(i2c); | |
871 | if (i2c->msg.len == 0) | |
872 | return ISR_WAITSTOP; | |
873 | } | |
874 | } else { | |
875 | if (int_status & INT_FIFO_EMPTY_EMPTYING) { | |
876 | /* | |
877 | * The write fifo empty indicates that we're in the | |
878 | * last byte so it's safe to start a new write | |
879 | * transaction without losing any bytes from the | |
880 | * previous one. | |
881 | * see 2.3.7 Repeated Start Transactions. | |
882 | */ | |
883 | if ((int_status & INT_FIFO_EMPTY) && | |
884 | i2c->msg.len == 0) | |
885 | return ISR_WAITSTOP; | |
886 | img_i2c_write_fifo(i2c); | |
887 | } | |
888 | } | |
889 | ||
890 | return 0; | |
891 | } | |
892 | ||
893 | static irqreturn_t img_i2c_isr(int irq, void *dev_id) | |
894 | { | |
895 | struct img_i2c *i2c = (struct img_i2c *)dev_id; | |
896 | u32 int_status, line_status; | |
897 | /* We handle transaction completion AFTER accessing registers */ | |
898 | unsigned int hret; | |
899 | ||
900 | /* Read interrupt status register. */ | |
901 | int_status = img_i2c_readl(i2c, SCB_INT_STATUS_REG); | |
902 | /* Clear detected interrupts. */ | |
903 | img_i2c_writel(i2c, SCB_INT_CLEAR_REG, int_status); | |
904 | ||
905 | /* | |
906 | * Read line status and clear it until it actually is clear. We have | |
907 | * to be careful not to lose any line status bits that get latched. | |
908 | */ | |
909 | line_status = img_i2c_readl(i2c, SCB_STATUS_REG); | |
910 | if (line_status & LINESTAT_LATCHED) { | |
911 | img_i2c_writel(i2c, SCB_CLEAR_REG, | |
912 | (line_status & LINESTAT_LATCHED) | |
913 | >> LINESTAT_CLEAR_SHIFT); | |
914 | img_i2c_wr_rd_fence(i2c); | |
915 | } | |
916 | ||
917 | spin_lock(&i2c->lock); | |
918 | ||
919 | /* Keep track of line status bits received */ | |
920 | i2c->line_status &= ~LINESTAT_INPUT_DATA; | |
921 | i2c->line_status |= line_status; | |
922 | ||
923 | /* | |
924 | * Certain interrupts indicate that sclk low timeout is not | |
925 | * a problem. If any of these are set, just continue. | |
926 | */ | |
927 | if ((int_status & INT_SCLK_LOW_TIMEOUT) && | |
928 | !(int_status & (INT_SLAVE_EVENT | | |
929 | INT_FIFO_EMPTY | | |
930 | INT_FIFO_FULL))) { | |
931 | dev_crit(i2c->adap.dev.parent, | |
932 | "fatal: clock low timeout occurred %s addr 0x%02x\n", | |
933 | (i2c->msg.flags & I2C_M_RD) ? "reading" : "writing", | |
934 | i2c->msg.addr); | |
935 | hret = ISR_FATAL(EIO); | |
936 | goto out; | |
937 | } | |
938 | ||
939 | if (i2c->mode == MODE_ATOMIC) | |
940 | hret = img_i2c_atomic(i2c, int_status, line_status); | |
941 | else if (i2c->mode == MODE_AUTOMATIC) | |
942 | hret = img_i2c_auto(i2c, int_status, line_status); | |
943 | else if (i2c->mode == MODE_SEQUENCE) | |
944 | hret = img_i2c_sequence(i2c, int_status); | |
945 | else if (i2c->mode == MODE_WAITSTOP && (int_status & INT_SLAVE_EVENT) && | |
946 | (line_status & LINESTAT_STOP_BIT_DET)) | |
947 | hret = ISR_COMPLETE(0); | |
948 | else if (i2c->mode == MODE_RAW) | |
949 | hret = img_i2c_raw(i2c, int_status, line_status); | |
950 | else | |
951 | hret = 0; | |
952 | ||
953 | /* Clear detected level interrupts. */ | |
954 | img_i2c_writel(i2c, SCB_INT_CLEAR_REG, int_status & INT_LEVEL); | |
955 | ||
956 | out: | |
957 | if (hret & ISR_WAITSTOP) { | |
958 | /* | |
959 | * Only wait for stop on last message. | |
960 | * Also we may already have detected the stop bit. | |
961 | */ | |
962 | if (!i2c->last_msg || i2c->line_status & LINESTAT_STOP_BIT_DET) | |
963 | hret = ISR_COMPLETE(0); | |
964 | else | |
965 | img_i2c_switch_mode(i2c, MODE_WAITSTOP); | |
966 | } | |
967 | ||
968 | /* now we've finished using regs, handle transaction completion */ | |
969 | if (hret & ISR_COMPLETE_M) { | |
970 | int status = -(hret & ISR_STATUS_M); | |
971 | ||
972 | img_i2c_complete_transaction(i2c, status); | |
973 | if (hret & ISR_FATAL_M) | |
974 | img_i2c_switch_mode(i2c, MODE_FATAL); | |
975 | } | |
976 | ||
977 | /* Enable interrupts (int_enable may be altered by changing mode) */ | |
978 | img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); | |
979 | ||
980 | spin_unlock(&i2c->lock); | |
981 | ||
982 | return IRQ_HANDLED; | |
983 | } | |
984 | ||
985 | /* Force a bus reset sequence and wait for it to complete */ | |
986 | static int img_i2c_reset_bus(struct img_i2c *i2c) | |
987 | { | |
988 | unsigned long flags; | |
913b1d85 | 989 | unsigned long time_left; |
27bce457 JH |
990 | |
991 | spin_lock_irqsave(&i2c->lock, flags); | |
992 | reinit_completion(&i2c->msg_complete); | |
993 | img_i2c_reset_start(i2c); | |
994 | spin_unlock_irqrestore(&i2c->lock, flags); | |
995 | ||
913b1d85 NMG |
996 | time_left = wait_for_completion_timeout(&i2c->msg_complete, |
997 | IMG_I2C_TIMEOUT); | |
998 | if (time_left == 0) | |
27bce457 JH |
999 | return -ETIMEDOUT; |
1000 | return 0; | |
1001 | } | |
1002 | ||
1003 | static int img_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, | |
1004 | int num) | |
1005 | { | |
1006 | struct img_i2c *i2c = i2c_get_adapdata(adap); | |
1007 | bool atomic = false; | |
1008 | int i, ret; | |
913b1d85 | 1009 | unsigned long time_left; |
27bce457 JH |
1010 | |
1011 | if (i2c->mode == MODE_SUSPEND) { | |
1012 | WARN(1, "refusing to service transaction in suspended state\n"); | |
1013 | return -EIO; | |
1014 | } | |
1015 | ||
1016 | if (i2c->mode == MODE_FATAL) | |
1017 | return -EIO; | |
1018 | ||
1019 | for (i = 0; i < num; i++) { | |
1020 | if (likely(msgs[i].len)) | |
1021 | continue; | |
1022 | /* | |
1023 | * 0 byte reads are not possible because the slave could try | |
1024 | * and pull the data line low, preventing a stop bit. | |
1025 | */ | |
1026 | if (unlikely(msgs[i].flags & I2C_M_RD)) | |
1027 | return -EIO; | |
1028 | /* | |
1029 | * 0 byte writes are possible and used for probing, but we | |
1030 | * cannot do them in automatic mode, so use atomic mode | |
1031 | * instead. | |
1032 | */ | |
1033 | atomic = true; | |
1034 | } | |
1035 | ||
1036 | ret = clk_prepare_enable(i2c->scb_clk); | |
1037 | if (ret) | |
1038 | return ret; | |
1039 | ||
1040 | for (i = 0; i < num; i++) { | |
1041 | struct i2c_msg *msg = &msgs[i]; | |
1042 | unsigned long flags; | |
1043 | ||
1044 | spin_lock_irqsave(&i2c->lock, flags); | |
1045 | ||
1046 | /* | |
1047 | * Make a copy of the message struct. We mustn't modify the | |
1048 | * original or we'll confuse drivers and i2c-dev. | |
1049 | */ | |
1050 | i2c->msg = *msg; | |
1051 | i2c->msg_status = 0; | |
1052 | ||
1053 | /* | |
1054 | * After the last message we must have waited for a stop bit. | |
1055 | * Not waiting can cause problems when the clock is disabled | |
1056 | * before the stop bit is sent, and the linux I2C interface | |
1057 | * requires separate transfers not to joined with repeated | |
1058 | * start. | |
1059 | */ | |
1060 | i2c->last_msg = (i == num - 1); | |
1061 | reinit_completion(&i2c->msg_complete); | |
1062 | ||
1063 | if (atomic) | |
1064 | img_i2c_atomic_start(i2c); | |
1065 | else if (msg->flags & I2C_M_RD) | |
1066 | img_i2c_read(i2c); | |
1067 | else | |
1068 | img_i2c_write(i2c); | |
1069 | spin_unlock_irqrestore(&i2c->lock, flags); | |
1070 | ||
913b1d85 NMG |
1071 | time_left = wait_for_completion_timeout(&i2c->msg_complete, |
1072 | IMG_I2C_TIMEOUT); | |
27bce457 JH |
1073 | del_timer_sync(&i2c->check_timer); |
1074 | ||
913b1d85 | 1075 | if (time_left == 0) { |
27bce457 JH |
1076 | dev_err(adap->dev.parent, "i2c transfer timed out\n"); |
1077 | i2c->msg_status = -ETIMEDOUT; | |
1078 | break; | |
1079 | } | |
1080 | ||
1081 | if (i2c->msg_status) | |
1082 | break; | |
1083 | } | |
1084 | ||
1085 | clk_disable_unprepare(i2c->scb_clk); | |
1086 | ||
1087 | return i2c->msg_status ? i2c->msg_status : num; | |
1088 | } | |
1089 | ||
1090 | static u32 img_i2c_func(struct i2c_adapter *adap) | |
1091 | { | |
1092 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
1093 | } | |
1094 | ||
1095 | static const struct i2c_algorithm img_i2c_algo = { | |
1096 | .master_xfer = img_i2c_xfer, | |
1097 | .functionality = img_i2c_func, | |
1098 | }; | |
1099 | ||
1100 | static int img_i2c_init(struct img_i2c *i2c) | |
1101 | { | |
1102 | unsigned int clk_khz, bitrate_khz, clk_period, tckh, tckl, tsdh; | |
1103 | unsigned int i, ret, data, prescale, inc, int_bitrate, filt; | |
1104 | struct img_i2c_timings timing; | |
1105 | u32 rev; | |
1106 | ||
1107 | ret = clk_prepare_enable(i2c->scb_clk); | |
1108 | if (ret) | |
1109 | return ret; | |
1110 | ||
1111 | rev = img_i2c_readl(i2c, SCB_CORE_REV_REG); | |
1112 | if ((rev & 0x00ffffff) < 0x00020200) { | |
1113 | dev_info(i2c->adap.dev.parent, | |
1114 | "Unknown hardware revision (%d.%d.%d.%d)\n", | |
1115 | (rev >> 24) & 0xff, (rev >> 16) & 0xff, | |
1116 | (rev >> 8) & 0xff, rev & 0xff); | |
1117 | clk_disable_unprepare(i2c->scb_clk); | |
1118 | return -EINVAL; | |
1119 | } | |
1120 | ||
0e59378b SN |
1121 | /* Fencing enabled by default. */ |
1122 | i2c->need_wr_rd_fence = true; | |
27bce457 JH |
1123 | |
1124 | bitrate_khz = i2c->bitrate / 1000; | |
1125 | clk_khz = clk_get_rate(i2c->scb_clk) / 1000; | |
1126 | ||
1127 | /* Determine what mode we're in from the bitrate */ | |
1128 | timing = timings[0]; | |
1129 | for (i = 0; i < ARRAY_SIZE(timings); i++) { | |
1130 | if (i2c->bitrate <= timings[i].max_bitrate) { | |
1131 | timing = timings[i]; | |
1132 | break; | |
1133 | } | |
1134 | } | |
1135 | ||
1136 | /* Find the prescale that would give us that inc (approx delay = 0) */ | |
1137 | prescale = SCB_OPT_INC * clk_khz / (256 * 16 * bitrate_khz); | |
1138 | prescale = clamp_t(unsigned int, prescale, 1, 8); | |
1139 | clk_khz /= prescale; | |
1140 | ||
1141 | /* Setup the clock increment value */ | |
1142 | inc = (256 * 16 * bitrate_khz) / clk_khz; | |
1143 | ||
1144 | /* | |
1145 | * The clock generation logic allows to filter glitches on the bus. | |
1146 | * This filter is able to remove bus glitches shorter than 50ns. | |
1147 | * If the clock enable rate is greater than 20 MHz, no filtering | |
1148 | * is required, so we need to disable it. | |
1149 | * If it's between the 20-40 MHz range, there's no need to divide | |
1150 | * the clock to get a filter. | |
1151 | */ | |
1152 | if (clk_khz < 20000) { | |
1153 | filt = SCB_FILT_DISABLE; | |
1154 | } else if (clk_khz < 40000) { | |
1155 | filt = SCB_FILT_BYPASS; | |
1156 | } else { | |
1157 | /* Calculate filter clock */ | |
1158 | filt = (64000 / ((clk_khz / 1000) * SCB_FILT_GLITCH)); | |
1159 | ||
1160 | /* Scale up if needed */ | |
1161 | if (64000 % ((clk_khz / 1000) * SCB_FILT_GLITCH)) | |
1162 | inc++; | |
1163 | ||
1164 | if (filt > SCB_FILT_INC_MASK) | |
1165 | filt = SCB_FILT_INC_MASK; | |
1166 | ||
1167 | filt = (filt & SCB_FILT_INC_MASK) << SCB_FILT_INC_SHIFT; | |
1168 | } | |
1169 | data = filt | ((inc & SCB_INC_MASK) << SCB_INC_SHIFT) | (prescale - 1); | |
1170 | img_i2c_writel(i2c, SCB_CLK_SET_REG, data); | |
1171 | ||
1172 | /* Obtain the clock period of the fx16 clock in ns */ | |
1173 | clk_period = (256 * 1000000) / (clk_khz * inc); | |
1174 | ||
1175 | /* Calculate the bitrate in terms of internal clock pulses */ | |
1176 | int_bitrate = 1000000 / (bitrate_khz * clk_period); | |
1177 | if ((1000000 % (bitrate_khz * clk_period)) >= | |
1178 | ((bitrate_khz * clk_period) / 2)) | |
1179 | int_bitrate++; | |
1180 | ||
1181 | /* Setup TCKH value */ | |
5728d95f | 1182 | tckh = DIV_ROUND_UP(timing.tckh, clk_period); |
27bce457 JH |
1183 | |
1184 | if (tckh > 0) | |
1185 | data = tckh - 1; | |
1186 | else | |
1187 | data = 0; | |
1188 | ||
1189 | img_i2c_writel(i2c, SCB_TIME_TCKH_REG, data); | |
1190 | ||
1191 | /* Setup TCKL value */ | |
1192 | tckl = int_bitrate - tckh; | |
1193 | ||
1194 | if (tckl > 0) | |
1195 | data = tckl - 1; | |
1196 | else | |
1197 | data = 0; | |
1198 | ||
1199 | img_i2c_writel(i2c, SCB_TIME_TCKL_REG, data); | |
1200 | ||
1201 | /* Setup TSDH value */ | |
5728d95f | 1202 | tsdh = DIV_ROUND_UP(timing.tsdh, clk_period); |
27bce457 JH |
1203 | |
1204 | if (tsdh > 1) | |
1205 | data = tsdh - 1; | |
1206 | else | |
1207 | data = 0x01; | |
1208 | img_i2c_writel(i2c, SCB_TIME_TSDH_REG, data); | |
1209 | ||
1210 | /* This value is used later */ | |
1211 | tsdh = data; | |
1212 | ||
1213 | /* Setup TPL value */ | |
1214 | data = timing.tpl / clk_period; | |
1215 | if (data > 0) | |
1216 | --data; | |
1217 | img_i2c_writel(i2c, SCB_TIME_TPL_REG, data); | |
1218 | ||
1219 | /* Setup TPH value */ | |
1220 | data = timing.tph / clk_period; | |
1221 | if (data > 0) | |
1222 | --data; | |
1223 | img_i2c_writel(i2c, SCB_TIME_TPH_REG, data); | |
1224 | ||
1225 | /* Setup TSDL value to TPL + TSDH + 2 */ | |
1226 | img_i2c_writel(i2c, SCB_TIME_TSDL_REG, data + tsdh + 2); | |
1227 | ||
1228 | /* Setup TP2S value */ | |
1229 | data = timing.tp2s / clk_period; | |
1230 | if (data > 0) | |
1231 | --data; | |
1232 | img_i2c_writel(i2c, SCB_TIME_TP2S_REG, data); | |
1233 | ||
1234 | img_i2c_writel(i2c, SCB_TIME_TBI_REG, TIMEOUT_TBI); | |
1235 | img_i2c_writel(i2c, SCB_TIME_TSL_REG, TIMEOUT_TSL); | |
1236 | img_i2c_writel(i2c, SCB_TIME_TDL_REG, TIMEOUT_TDL); | |
1237 | ||
1238 | /* Take module out of soft reset and enable clocks */ | |
1239 | img_i2c_soft_reset(i2c); | |
1240 | ||
1241 | /* Disable all interrupts */ | |
1242 | img_i2c_writel(i2c, SCB_INT_MASK_REG, 0); | |
1243 | ||
1244 | /* Clear all interrupts */ | |
1245 | img_i2c_writel(i2c, SCB_INT_CLEAR_REG, ~0); | |
1246 | ||
1247 | /* Clear the scb_line_status events */ | |
1248 | img_i2c_writel(i2c, SCB_CLEAR_REG, ~0); | |
1249 | ||
1250 | /* Enable interrupts */ | |
1251 | img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); | |
1252 | ||
1253 | /* Perform a synchronous sequence to reset the bus */ | |
1254 | ret = img_i2c_reset_bus(i2c); | |
1255 | ||
1256 | clk_disable_unprepare(i2c->scb_clk); | |
1257 | ||
1258 | return ret; | |
1259 | } | |
1260 | ||
1261 | static int img_i2c_probe(struct platform_device *pdev) | |
1262 | { | |
1263 | struct device_node *node = pdev->dev.of_node; | |
1264 | struct img_i2c *i2c; | |
1265 | struct resource *res; | |
1266 | int irq, ret; | |
1267 | u32 val; | |
1268 | ||
1269 | i2c = devm_kzalloc(&pdev->dev, sizeof(struct img_i2c), GFP_KERNEL); | |
1270 | if (!i2c) | |
1271 | return -ENOMEM; | |
1272 | ||
1273 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1274 | i2c->base = devm_ioremap_resource(&pdev->dev, res); | |
1275 | if (IS_ERR(i2c->base)) | |
1276 | return PTR_ERR(i2c->base); | |
1277 | ||
1278 | irq = platform_get_irq(pdev, 0); | |
1279 | if (irq < 0) { | |
1280 | dev_err(&pdev->dev, "can't get irq number\n"); | |
1281 | return irq; | |
1282 | } | |
1283 | ||
1284 | i2c->sys_clk = devm_clk_get(&pdev->dev, "sys"); | |
1285 | if (IS_ERR(i2c->sys_clk)) { | |
1286 | dev_err(&pdev->dev, "can't get system clock\n"); | |
1287 | return PTR_ERR(i2c->sys_clk); | |
1288 | } | |
1289 | ||
1290 | i2c->scb_clk = devm_clk_get(&pdev->dev, "scb"); | |
1291 | if (IS_ERR(i2c->scb_clk)) { | |
1292 | dev_err(&pdev->dev, "can't get core clock\n"); | |
1293 | return PTR_ERR(i2c->scb_clk); | |
1294 | } | |
1295 | ||
1296 | ret = devm_request_irq(&pdev->dev, irq, img_i2c_isr, 0, | |
1297 | pdev->name, i2c); | |
1298 | if (ret) { | |
1299 | dev_err(&pdev->dev, "can't request irq %d\n", irq); | |
1300 | return ret; | |
1301 | } | |
1302 | ||
1303 | /* Set up the exception check timer */ | |
1304 | init_timer(&i2c->check_timer); | |
1305 | i2c->check_timer.function = img_i2c_check_timer; | |
1306 | i2c->check_timer.data = (unsigned long)i2c; | |
1307 | ||
1308 | i2c->bitrate = timings[0].max_bitrate; | |
1309 | if (!of_property_read_u32(node, "clock-frequency", &val)) | |
1310 | i2c->bitrate = val; | |
1311 | ||
1312 | i2c_set_adapdata(&i2c->adap, i2c); | |
1313 | i2c->adap.dev.parent = &pdev->dev; | |
1314 | i2c->adap.dev.of_node = node; | |
1315 | i2c->adap.owner = THIS_MODULE; | |
1316 | i2c->adap.algo = &img_i2c_algo; | |
1317 | i2c->adap.retries = 5; | |
1318 | i2c->adap.nr = pdev->id; | |
1319 | snprintf(i2c->adap.name, sizeof(i2c->adap.name), "IMG SCB I2C"); | |
1320 | ||
1321 | img_i2c_switch_mode(i2c, MODE_INACTIVE); | |
1322 | spin_lock_init(&i2c->lock); | |
1323 | init_completion(&i2c->msg_complete); | |
1324 | ||
1325 | platform_set_drvdata(pdev, i2c); | |
1326 | ||
1327 | ret = clk_prepare_enable(i2c->sys_clk); | |
1328 | if (ret) | |
1329 | return ret; | |
1330 | ||
1331 | ret = img_i2c_init(i2c); | |
1332 | if (ret) | |
1333 | goto disable_clk; | |
1334 | ||
1335 | ret = i2c_add_numbered_adapter(&i2c->adap); | |
1336 | if (ret < 0) { | |
1337 | dev_err(&pdev->dev, "failed to add adapter\n"); | |
1338 | goto disable_clk; | |
1339 | } | |
1340 | ||
1341 | return 0; | |
1342 | ||
1343 | disable_clk: | |
1344 | clk_disable_unprepare(i2c->sys_clk); | |
1345 | return ret; | |
1346 | } | |
1347 | ||
1348 | static int img_i2c_remove(struct platform_device *dev) | |
1349 | { | |
1350 | struct img_i2c *i2c = platform_get_drvdata(dev); | |
1351 | ||
1352 | i2c_del_adapter(&i2c->adap); | |
1353 | clk_disable_unprepare(i2c->sys_clk); | |
1354 | ||
1355 | return 0; | |
1356 | } | |
1357 | ||
1358 | #ifdef CONFIG_PM_SLEEP | |
1359 | static int img_i2c_suspend(struct device *dev) | |
1360 | { | |
1361 | struct img_i2c *i2c = dev_get_drvdata(dev); | |
1362 | ||
1363 | img_i2c_switch_mode(i2c, MODE_SUSPEND); | |
1364 | ||
1365 | clk_disable_unprepare(i2c->sys_clk); | |
1366 | ||
1367 | return 0; | |
1368 | } | |
1369 | ||
1370 | static int img_i2c_resume(struct device *dev) | |
1371 | { | |
1372 | struct img_i2c *i2c = dev_get_drvdata(dev); | |
1373 | int ret; | |
1374 | ||
1375 | ret = clk_prepare_enable(i2c->sys_clk); | |
1376 | if (ret) | |
1377 | return ret; | |
1378 | ||
1379 | img_i2c_init(i2c); | |
1380 | ||
1381 | return 0; | |
1382 | } | |
1383 | #endif /* CONFIG_PM_SLEEP */ | |
1384 | ||
1385 | static SIMPLE_DEV_PM_OPS(img_i2c_pm, img_i2c_suspend, img_i2c_resume); | |
1386 | ||
1387 | static const struct of_device_id img_scb_i2c_match[] = { | |
1388 | { .compatible = "img,scb-i2c" }, | |
1389 | { } | |
1390 | }; | |
1391 | MODULE_DEVICE_TABLE(of, img_scb_i2c_match); | |
1392 | ||
1393 | static struct platform_driver img_scb_i2c_driver = { | |
1394 | .driver = { | |
1395 | .name = "img-i2c-scb", | |
1396 | .of_match_table = img_scb_i2c_match, | |
1397 | .pm = &img_i2c_pm, | |
1398 | }, | |
1399 | .probe = img_i2c_probe, | |
1400 | .remove = img_i2c_remove, | |
1401 | }; | |
1402 | module_platform_driver(img_scb_i2c_driver); | |
1403 | ||
1404 | MODULE_AUTHOR("James Hogan <james.hogan@imgtec.com>"); | |
1405 | MODULE_DESCRIPTION("IMG host I2C driver"); | |
1406 | MODULE_LICENSE("GPL v2"); |